Macros
FLEXSPI Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » FLEXSPI Peripheral Access Layer
Collaboration diagram for FLEXSPI Register Masks:

Macros

#define FLEXSPI_AHBRXBUFCR0_COUNT   (4U)
 
#define FLEXSPI_DLLCR_COUNT   (2U)
 
#define FLEXSPI_FLSHCR0_COUNT   (4U)
 
#define FLEXSPI_FLSHCR1_COUNT   (4U)
 
#define FLEXSPI_FLSHCR2_COUNT   (4U)
 
#define FLEXSPI_LUT_COUNT   (64U)
 
#define FLEXSPI_RFDR_COUNT   (32U)
 
#define FLEXSPI_TFDR_COUNT   (32U)
 

MCR0 - Module Control Register 0

#define FLEXSPI_MCR0_SWRESET_MASK   (0x1U)
 
#define FLEXSPI_MCR0_SWRESET_SHIFT   (0U)
 
#define FLEXSPI_MCR0_SWRESET(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
 
#define FLEXSPI_MCR0_MDIS_MASK   (0x2U)
 
#define FLEXSPI_MCR0_MDIS_SHIFT   (1U)
 
#define FLEXSPI_MCR0_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
 
#define FLEXSPI_MCR0_RXCLKSRC_MASK   (0x30U)
 
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT   (4U)
 
#define FLEXSPI_MCR0_RXCLKSRC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
 
#define FLEXSPI_MCR0_ARDFEN_MASK   (0x40U)
 
#define FLEXSPI_MCR0_ARDFEN_SHIFT   (6U)
 
#define FLEXSPI_MCR0_ARDFEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
 
#define FLEXSPI_MCR0_ATDFEN_MASK   (0x80U)
 
#define FLEXSPI_MCR0_ATDFEN_SHIFT   (7U)
 
#define FLEXSPI_MCR0_ATDFEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
 
#define FLEXSPI_MCR0_HSEN_MASK   (0x800U)
 
#define FLEXSPI_MCR0_HSEN_SHIFT   (11U)
 
#define FLEXSPI_MCR0_HSEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
 
#define FLEXSPI_MCR0_DOZEEN_MASK   (0x1000U)
 
#define FLEXSPI_MCR0_DOZEEN_SHIFT   (12U)
 
#define FLEXSPI_MCR0_DOZEEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
 
#define FLEXSPI_MCR0_COMBINATIONEN_MASK   (0x2000U)
 
#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT   (13U)
 
#define FLEXSPI_MCR0_COMBINATIONEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
 
#define FLEXSPI_MCR0_SCKFREERUNEN_MASK   (0x4000U)
 
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT   (14U)
 
#define FLEXSPI_MCR0_SCKFREERUNEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
 
#define FLEXSPI_MCR0_IPGRANTWAIT_MASK   (0xFF0000U)
 
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT   (16U)
 
#define FLEXSPI_MCR0_IPGRANTWAIT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
 
#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK   (0xFF000000U)
 
#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT   (24U)
 
#define FLEXSPI_MCR0_AHBGRANTWAIT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
 

MCR1 - Module Control Register 1

#define FLEXSPI_MCR1_AHBBUSWAIT_MASK   (0xFFFFU)
 
#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT   (0U)
 
#define FLEXSPI_MCR1_AHBBUSWAIT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
 
#define FLEXSPI_MCR1_SEQWAIT_MASK   (0xFFFF0000U)
 
#define FLEXSPI_MCR1_SEQWAIT_SHIFT   (16U)
 
#define FLEXSPI_MCR1_SEQWAIT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
 

MCR2 - Module Control Register 2

#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK   (0x800U)
 
#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT   (11U)
 
#define FLEXSPI_MCR2_CLRAHBBUFOPT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
 
#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK   (0x4000U)
 
#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT   (14U)
 
#define FLEXSPI_MCR2_CLRLEARNPHASE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
 
#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK   (0x8000U)
 
#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT   (15U)
 
#define FLEXSPI_MCR2_SAMEDEVICEEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
 
#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK   (0x80000U)
 
#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT   (19U)
 
#define FLEXSPI_MCR2_SCKBDIFFOPT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
 
#define FLEXSPI_MCR2_RESUMEWAIT_MASK   (0xFF000000U)
 
#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT   (24U)
 
#define FLEXSPI_MCR2_RESUMEWAIT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
 

AHBCR - AHB Bus Control Register

#define FLEXSPI_AHBCR_APAREN_MASK   (0x1U)
 
#define FLEXSPI_AHBCR_APAREN_SHIFT   (0U)
 
#define FLEXSPI_AHBCR_APAREN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
 
#define FLEXSPI_AHBCR_CACHABLEEN_MASK   (0x8U)
 
#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT   (3U)
 
#define FLEXSPI_AHBCR_CACHABLEEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
 
#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK   (0x10U)
 
#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT   (4U)
 
#define FLEXSPI_AHBCR_BUFFERABLEEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
 
#define FLEXSPI_AHBCR_PREFETCHEN_MASK   (0x20U)
 
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT   (5U)
 
#define FLEXSPI_AHBCR_PREFETCHEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
 
#define FLEXSPI_AHBCR_READADDROPT_MASK   (0x40U)
 
#define FLEXSPI_AHBCR_READADDROPT_SHIFT   (6U)
 
#define FLEXSPI_AHBCR_READADDROPT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
 

INTEN - Interrupt Enable Register

#define FLEXSPI_INTEN_IPCMDDONEEN_MASK   (0x1U)
 
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT   (0U)
 
#define FLEXSPI_INTEN_IPCMDDONEEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
 
#define FLEXSPI_INTEN_IPCMDGEEN_MASK   (0x2U)
 
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT   (1U)
 
#define FLEXSPI_INTEN_IPCMDGEEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
 
#define FLEXSPI_INTEN_AHBCMDGEEN_MASK   (0x4U)
 
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT   (2U)
 
#define FLEXSPI_INTEN_AHBCMDGEEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
 
#define FLEXSPI_INTEN_IPCMDERREN_MASK   (0x8U)
 
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT   (3U)
 
#define FLEXSPI_INTEN_IPCMDERREN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
 
#define FLEXSPI_INTEN_AHBCMDERREN_MASK   (0x10U)
 
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT   (4U)
 
#define FLEXSPI_INTEN_AHBCMDERREN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
 
#define FLEXSPI_INTEN_IPRXWAEN_MASK   (0x20U)
 
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT   (5U)
 
#define FLEXSPI_INTEN_IPRXWAEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
 
#define FLEXSPI_INTEN_IPTXWEEN_MASK   (0x40U)
 
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT   (6U)
 
#define FLEXSPI_INTEN_IPTXWEEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
 
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK   (0x100U)
 
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT   (8U)
 
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
 
#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK   (0x200U)
 
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT   (9U)
 
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
 
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK   (0x400U)
 
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT   (10U)
 
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
 
#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK   (0x800U)
 
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT   (11U)
 
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
 
#define PWM_INTEN_CMPIE_MASK   (0x3FU)
 
#define PWM_INTEN_CMPIE_SHIFT   (0U)
 
#define PWM_INTEN_CMPIE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
 
#define PWM_INTEN_CX0IE_MASK   (0x40U)
 
#define PWM_INTEN_CX0IE_SHIFT   (6U)
 
#define PWM_INTEN_CX0IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
 
#define PWM_INTEN_CX1IE_MASK   (0x80U)
 
#define PWM_INTEN_CX1IE_SHIFT   (7U)
 
#define PWM_INTEN_CX1IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
 
#define PWM_INTEN_CB0IE_MASK   (0x100U)
 
#define PWM_INTEN_CB0IE_SHIFT   (8U)
 
#define PWM_INTEN_CB0IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
 
#define PWM_INTEN_CB1IE_MASK   (0x200U)
 
#define PWM_INTEN_CB1IE_SHIFT   (9U)
 
#define PWM_INTEN_CB1IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
 
#define PWM_INTEN_CA0IE_MASK   (0x400U)
 
#define PWM_INTEN_CA0IE_SHIFT   (10U)
 
#define PWM_INTEN_CA0IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
 
#define PWM_INTEN_CA1IE_MASK   (0x800U)
 
#define PWM_INTEN_CA1IE_SHIFT   (11U)
 
#define PWM_INTEN_CA1IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
 
#define PWM_INTEN_RIE_MASK   (0x1000U)
 
#define PWM_INTEN_RIE_SHIFT   (12U)
 
#define PWM_INTEN_RIE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
 
#define PWM_INTEN_REIE_MASK   (0x2000U)
 
#define PWM_INTEN_REIE_SHIFT   (13U)
 
#define PWM_INTEN_REIE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
 
#define SEMC_INTEN_IPCMDDONEEN_MASK   (0x1U)
 
#define SEMC_INTEN_IPCMDDONEEN_SHIFT   (0U)
 
#define SEMC_INTEN_IPCMDDONEEN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
 
#define SEMC_INTEN_IPCMDERREN_MASK   (0x2U)
 
#define SEMC_INTEN_IPCMDERREN_SHIFT   (1U)
 
#define SEMC_INTEN_IPCMDERREN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
 
#define SEMC_INTEN_AXICMDERREN_MASK   (0x4U)
 
#define SEMC_INTEN_AXICMDERREN_SHIFT   (2U)
 
#define SEMC_INTEN_AXICMDERREN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
 
#define SEMC_INTEN_AXIBUSERREN_MASK   (0x8U)
 
#define SEMC_INTEN_AXIBUSERREN_SHIFT   (3U)
 
#define SEMC_INTEN_AXIBUSERREN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
 
#define SEMC_INTEN_NDPAGEENDEN_MASK   (0x10U)
 
#define SEMC_INTEN_NDPAGEENDEN_SHIFT   (4U)
 
#define SEMC_INTEN_NDPAGEENDEN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
 
#define SEMC_INTEN_NDNOPENDEN_MASK   (0x20U)
 
#define SEMC_INTEN_NDNOPENDEN_SHIFT   (5U)
 
#define SEMC_INTEN_NDNOPENDEN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
 

INTR - Interrupt Register

#define FLEXSPI_INTR_IPCMDDONE_MASK   (0x1U)
 
#define FLEXSPI_INTR_IPCMDDONE_SHIFT   (0U)
 
#define FLEXSPI_INTR_IPCMDDONE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
 
#define FLEXSPI_INTR_IPCMDGE_MASK   (0x2U)
 
#define FLEXSPI_INTR_IPCMDGE_SHIFT   (1U)
 
#define FLEXSPI_INTR_IPCMDGE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
 
#define FLEXSPI_INTR_AHBCMDGE_MASK   (0x4U)
 
#define FLEXSPI_INTR_AHBCMDGE_SHIFT   (2U)
 
#define FLEXSPI_INTR_AHBCMDGE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
 
#define FLEXSPI_INTR_IPCMDERR_MASK   (0x8U)
 
#define FLEXSPI_INTR_IPCMDERR_SHIFT   (3U)
 
#define FLEXSPI_INTR_IPCMDERR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
 
#define FLEXSPI_INTR_AHBCMDERR_MASK   (0x10U)
 
#define FLEXSPI_INTR_AHBCMDERR_SHIFT   (4U)
 
#define FLEXSPI_INTR_AHBCMDERR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
 
#define FLEXSPI_INTR_IPRXWA_MASK   (0x20U)
 
#define FLEXSPI_INTR_IPRXWA_SHIFT   (5U)
 
#define FLEXSPI_INTR_IPRXWA(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
 
#define FLEXSPI_INTR_IPTXWE_MASK   (0x40U)
 
#define FLEXSPI_INTR_IPTXWE_SHIFT   (6U)
 
#define FLEXSPI_INTR_IPTXWE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
 
#define FLEXSPI_INTR_SCKSTOPBYRD_MASK   (0x100U)
 
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT   (8U)
 
#define FLEXSPI_INTR_SCKSTOPBYRD(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
 
#define FLEXSPI_INTR_SCKSTOPBYWR_MASK   (0x200U)
 
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT   (9U)
 
#define FLEXSPI_INTR_SCKSTOPBYWR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
 
#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK   (0x400U)
 
#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT   (10U)
 
#define FLEXSPI_INTR_AHBBUSTIMEOUT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
 
#define FLEXSPI_INTR_SEQTIMEOUT_MASK   (0x800U)
 
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT   (11U)
 
#define FLEXSPI_INTR_SEQTIMEOUT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
 

LUTKEY - LUT Key Register

#define FLEXSPI_LUTKEY_KEY_MASK   (0xFFFFFFFFU)
 
#define FLEXSPI_LUTKEY_KEY_SHIFT   (0U)
 
#define FLEXSPI_LUTKEY_KEY(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
 

LUTCR - LUT Control Register

#define FLEXSPI_LUTCR_LOCK_MASK   (0x1U)
 
#define FLEXSPI_LUTCR_LOCK_SHIFT   (0U)
 
#define FLEXSPI_LUTCR_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
 
#define FLEXSPI_LUTCR_UNLOCK_MASK   (0x2U)
 
#define FLEXSPI_LUTCR_UNLOCK_SHIFT   (1U)
 
#define FLEXSPI_LUTCR_UNLOCK(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
 

AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0

#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK   (0xFFU)
 
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT   (0U)
 
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
 
#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK   (0xF0000U)
 
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT   (16U)
 
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
 
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK   (0x3000000U)
 
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT   (24U)
 
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
 
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK   (0x80000000U)
 
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT   (31U)
 
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
 

FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0

#define FLEXSPI_FLSHCR0_FLSHSZ_MASK   (0x7FFFFFU)
 
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT   (0U)
 
#define FLEXSPI_FLSHCR0_FLSHSZ(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
 

FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1

#define FLEXSPI_FLSHCR1_TCSS_MASK   (0x1FU)
 
#define FLEXSPI_FLSHCR1_TCSS_SHIFT   (0U)
 
#define FLEXSPI_FLSHCR1_TCSS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
 
#define FLEXSPI_FLSHCR1_TCSH_MASK   (0x3E0U)
 
#define FLEXSPI_FLSHCR1_TCSH_SHIFT   (5U)
 
#define FLEXSPI_FLSHCR1_TCSH(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
 
#define FLEXSPI_FLSHCR1_WA_MASK   (0x400U)
 
#define FLEXSPI_FLSHCR1_WA_SHIFT   (10U)
 
#define FLEXSPI_FLSHCR1_WA(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
 
#define FLEXSPI_FLSHCR1_CAS_MASK   (0x7800U)
 
#define FLEXSPI_FLSHCR1_CAS_SHIFT   (11U)
 
#define FLEXSPI_FLSHCR1_CAS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
 
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK   (0x8000U)
 
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT   (15U)
 
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
 
#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK   (0xFFFF0000U)
 
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT   (16U)
 
#define FLEXSPI_FLSHCR1_CSINTERVAL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
 

FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2

#define FLEXSPI_FLSHCR2_ARDSEQID_MASK   (0xFU)
 
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT   (0U)
 
#define FLEXSPI_FLSHCR2_ARDSEQID(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
 
#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK   (0xE0U)
 
#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT   (5U)
 
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
 
#define FLEXSPI_FLSHCR2_AWRSEQID_MASK   (0xF00U)
 
#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT   (8U)
 
#define FLEXSPI_FLSHCR2_AWRSEQID(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
 
#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK   (0xE000U)
 
#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT   (13U)
 
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
 
#define FLEXSPI_FLSHCR2_AWRWAIT_MASK   (0xFFF0000U)
 
#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT   (16U)
 
#define FLEXSPI_FLSHCR2_AWRWAIT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
 
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK   (0x70000000U)
 
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT   (28U)
 
#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
 
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK   (0x80000000U)
 
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT   (31U)
 
#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
 

FLSHCR4 - Flash Control Register 4

#define FLEXSPI_FLSHCR4_WMOPT1_MASK   (0x1U)
 
#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT   (0U)
 
#define FLEXSPI_FLSHCR4_WMOPT1(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
 
#define FLEXSPI_FLSHCR4_WMENA_MASK   (0x4U)
 
#define FLEXSPI_FLSHCR4_WMENA_SHIFT   (2U)
 
#define FLEXSPI_FLSHCR4_WMENA(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
 
#define FLEXSPI_FLSHCR4_WMENB_MASK   (0x8U)
 
#define FLEXSPI_FLSHCR4_WMENB_SHIFT   (3U)
 
#define FLEXSPI_FLSHCR4_WMENB(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
 

IPCR0 - IP Control Register 0

#define FLEXSPI_IPCR0_SFAR_MASK   (0xFFFFFFFFU)
 
#define FLEXSPI_IPCR0_SFAR_SHIFT   (0U)
 
#define FLEXSPI_IPCR0_SFAR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
 

IPCR1 - IP Control Register 1

#define FLEXSPI_IPCR1_IDATSZ_MASK   (0xFFFFU)
 
#define FLEXSPI_IPCR1_IDATSZ_SHIFT   (0U)
 
#define FLEXSPI_IPCR1_IDATSZ(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
 
#define FLEXSPI_IPCR1_ISEQID_MASK   (0xF0000U)
 
#define FLEXSPI_IPCR1_ISEQID_SHIFT   (16U)
 
#define FLEXSPI_IPCR1_ISEQID(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
 
#define FLEXSPI_IPCR1_ISEQNUM_MASK   (0x7000000U)
 
#define FLEXSPI_IPCR1_ISEQNUM_SHIFT   (24U)
 
#define FLEXSPI_IPCR1_ISEQNUM(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
 
#define FLEXSPI_IPCR1_IPAREN_MASK   (0x80000000U)
 
#define FLEXSPI_IPCR1_IPAREN_SHIFT   (31U)
 
#define FLEXSPI_IPCR1_IPAREN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
 

IPCMD - IP Command register

#define FLEXSPI_IPCMD_TRG_MASK   (0x1U)
 
#define FLEXSPI_IPCMD_TRG_SHIFT   (0U)
 
#define FLEXSPI_IPCMD_TRG(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
 
#define SEMC_IPCMD_CMD_MASK   (0xFFFFU)
 
#define SEMC_IPCMD_CMD_SHIFT   (0U)
 
#define SEMC_IPCMD_CMD(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
 
#define SEMC_IPCMD_KEY_MASK   (0xFFFF0000U)
 
#define SEMC_IPCMD_KEY_SHIFT   (16U)
 
#define SEMC_IPCMD_KEY(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
 

IPRXFCR - IP RX FIFO Control Register

#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK   (0x1U)
 
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT   (0U)
 
#define FLEXSPI_IPRXFCR_CLRIPRXF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
 
#define FLEXSPI_IPRXFCR_RXDMAEN_MASK   (0x2U)
 
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT   (1U)
 
#define FLEXSPI_IPRXFCR_RXDMAEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
 
#define FLEXSPI_IPRXFCR_RXWMRK_MASK   (0x3CU)
 
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT   (2U)
 
#define FLEXSPI_IPRXFCR_RXWMRK(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
 

IPTXFCR - IP TX FIFO Control Register

#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK   (0x1U)
 
#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT   (0U)
 
#define FLEXSPI_IPTXFCR_CLRIPTXF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
 
#define FLEXSPI_IPTXFCR_TXDMAEN_MASK   (0x2U)
 
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT   (1U)
 
#define FLEXSPI_IPTXFCR_TXDMAEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
 
#define FLEXSPI_IPTXFCR_TXWMRK_MASK   (0x3CU)
 
#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT   (2U)
 
#define FLEXSPI_IPTXFCR_TXWMRK(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
 

DLLCR - DLL Control Register 0

#define FLEXSPI_DLLCR_DLLEN_MASK   (0x1U)
 
#define FLEXSPI_DLLCR_DLLEN_SHIFT   (0U)
 
#define FLEXSPI_DLLCR_DLLEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
 
#define FLEXSPI_DLLCR_DLLRESET_MASK   (0x2U)
 
#define FLEXSPI_DLLCR_DLLRESET_SHIFT   (1U)
 
#define FLEXSPI_DLLCR_DLLRESET(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
 
#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK   (0x78U)
 
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT   (3U)
 
#define FLEXSPI_DLLCR_SLVDLYTARGET(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
 
#define FLEXSPI_DLLCR_OVRDEN_MASK   (0x100U)
 
#define FLEXSPI_DLLCR_OVRDEN_SHIFT   (8U)
 
#define FLEXSPI_DLLCR_OVRDEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
 
#define FLEXSPI_DLLCR_OVRDVAL_MASK   (0x7E00U)
 
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT   (9U)
 
#define FLEXSPI_DLLCR_OVRDVAL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
 

STS0 - Status register 0

#define FLEXSPI_STS0_SEQIDLE_MASK   (0x1U)
 
#define FLEXSPI_STS0_SEQIDLE_SHIFT   (0U)
 
#define FLEXSPI_STS0_SEQIDLE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
 
#define FLEXSPI_STS0_ARBIDLE_MASK   (0x2U)
 
#define FLEXSPI_STS0_ARBIDLE_SHIFT   (1U)
 
#define FLEXSPI_STS0_ARBIDLE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
 
#define FLEXSPI_STS0_ARBCMDSRC_MASK   (0xCU)
 
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT   (2U)
 
#define FLEXSPI_STS0_ARBCMDSRC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
 
#define SEMC_STS0_IDLE_MASK   (0x1U)
 
#define SEMC_STS0_IDLE_SHIFT   (0U)
 
#define SEMC_STS0_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
 
#define SEMC_STS0_NARDY_MASK   (0x2U)
 
#define SEMC_STS0_NARDY_SHIFT   (1U)
 
#define SEMC_STS0_NARDY(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
 

STS1 - Status Register 1

#define FLEXSPI_STS1_AHBCMDERRID_MASK   (0xFU)
 
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT   (0U)
 
#define FLEXSPI_STS1_AHBCMDERRID(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
 
#define FLEXSPI_STS1_AHBCMDERRCODE_MASK   (0xF00U)
 
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT   (8U)
 
#define FLEXSPI_STS1_AHBCMDERRCODE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
 
#define FLEXSPI_STS1_IPCMDERRID_MASK   (0xF0000U)
 
#define FLEXSPI_STS1_IPCMDERRID_SHIFT   (16U)
 
#define FLEXSPI_STS1_IPCMDERRID(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
 
#define FLEXSPI_STS1_IPCMDERRCODE_MASK   (0xF000000U)
 
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT   (24U)
 
#define FLEXSPI_STS1_IPCMDERRCODE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
 

STS2 - Status register 2

#define FLEXSPI_STS2_ASLVLOCK_MASK   (0x1U)
 
#define FLEXSPI_STS2_ASLVLOCK_SHIFT   (0U)
 
#define FLEXSPI_STS2_ASLVLOCK(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
 
#define FLEXSPI_STS2_AREFLOCK_MASK   (0x2U)
 
#define FLEXSPI_STS2_AREFLOCK_SHIFT   (1U)
 
#define FLEXSPI_STS2_AREFLOCK(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
 
#define FLEXSPI_STS2_ASLVSEL_MASK   (0xFCU)
 
#define FLEXSPI_STS2_ASLVSEL_SHIFT   (2U)
 
#define FLEXSPI_STS2_ASLVSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
 
#define FLEXSPI_STS2_AREFSEL_MASK   (0x3F00U)
 
#define FLEXSPI_STS2_AREFSEL_SHIFT   (8U)
 
#define FLEXSPI_STS2_AREFSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
 
#define FLEXSPI_STS2_BSLVLOCK_MASK   (0x10000U)
 
#define FLEXSPI_STS2_BSLVLOCK_SHIFT   (16U)
 
#define FLEXSPI_STS2_BSLVLOCK(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
 
#define FLEXSPI_STS2_BREFLOCK_MASK   (0x20000U)
 
#define FLEXSPI_STS2_BREFLOCK_SHIFT   (17U)
 
#define FLEXSPI_STS2_BREFLOCK(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
 
#define FLEXSPI_STS2_BSLVSEL_MASK   (0xFC0000U)
 
#define FLEXSPI_STS2_BSLVSEL_SHIFT   (18U)
 
#define FLEXSPI_STS2_BSLVSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
 
#define FLEXSPI_STS2_BREFSEL_MASK   (0x3F000000U)
 
#define FLEXSPI_STS2_BREFSEL_SHIFT   (24U)
 
#define FLEXSPI_STS2_BREFSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
 
#define SEMC_STS2_NDWRPEND_MASK   (0x8U)
 
#define SEMC_STS2_NDWRPEND_SHIFT   (3U)
 
#define SEMC_STS2_NDWRPEND(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
 

AHBSPNDSTS - AHB Suspend Status Register

#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK   (0x1U)
 
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT   (0U)
 
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
 
#define FLEXSPI_AHBSPNDSTS_BUFID_MASK   (0xEU)
 
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT   (1U)
 
#define FLEXSPI_AHBSPNDSTS_BUFID(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
 
#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK   (0xFFFF0000U)
 
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT   (16U)
 
#define FLEXSPI_AHBSPNDSTS_DATLFT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
 

IPRXFSTS - IP RX FIFO Status Register

#define FLEXSPI_IPRXFSTS_FILL_MASK   (0xFFU)
 
#define FLEXSPI_IPRXFSTS_FILL_SHIFT   (0U)
 
#define FLEXSPI_IPRXFSTS_FILL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
 
#define FLEXSPI_IPRXFSTS_RDCNTR_MASK   (0xFFFF0000U)
 
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT   (16U)
 
#define FLEXSPI_IPRXFSTS_RDCNTR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
 

IPTXFSTS - IP TX FIFO Status Register

#define FLEXSPI_IPTXFSTS_FILL_MASK   (0xFFU)
 
#define FLEXSPI_IPTXFSTS_FILL_SHIFT   (0U)
 
#define FLEXSPI_IPTXFSTS_FILL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
 
#define FLEXSPI_IPTXFSTS_WRCNTR_MASK   (0xFFFF0000U)
 
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT   (16U)
 
#define FLEXSPI_IPTXFSTS_WRCNTR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
 

RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31

#define FLEXSPI_RFDR_RXDATA_MASK   (0xFFFFFFFFU)
 
#define FLEXSPI_RFDR_RXDATA_SHIFT   (0U)
 
#define FLEXSPI_RFDR_RXDATA(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
 

TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31

#define FLEXSPI_TFDR_TXDATA_MASK   (0xFFFFFFFFU)
 
#define FLEXSPI_TFDR_TXDATA_SHIFT   (0U)
 
#define FLEXSPI_TFDR_TXDATA(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
 

LUT - LUT 0..LUT 63

#define FLEXSPI_LUT_OPERAND0_MASK   (0xFFU)
 
#define FLEXSPI_LUT_OPERAND0_SHIFT   (0U)
 
#define FLEXSPI_LUT_OPERAND0(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
 
#define FLEXSPI_LUT_NUM_PADS0_MASK   (0x300U)
 
#define FLEXSPI_LUT_NUM_PADS0_SHIFT   (8U)
 
#define FLEXSPI_LUT_NUM_PADS0(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
 
#define FLEXSPI_LUT_OPCODE0_MASK   (0xFC00U)
 
#define FLEXSPI_LUT_OPCODE0_SHIFT   (10U)
 
#define FLEXSPI_LUT_OPCODE0(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
 
#define FLEXSPI_LUT_OPERAND1_MASK   (0xFF0000U)
 
#define FLEXSPI_LUT_OPERAND1_SHIFT   (16U)
 
#define FLEXSPI_LUT_OPERAND1(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
 
#define FLEXSPI_LUT_NUM_PADS1_MASK   (0x3000000U)
 
#define FLEXSPI_LUT_NUM_PADS1_SHIFT   (24U)
 
#define FLEXSPI_LUT_NUM_PADS1(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
 
#define FLEXSPI_LUT_OPCODE1_MASK   (0xFC000000U)
 
#define FLEXSPI_LUT_OPCODE1_SHIFT   (26U)
 
#define FLEXSPI_LUT_OPCODE1(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
 

Detailed Description

Macro Definition Documentation

◆ FLEXSPI_AHBCR_APAREN

#define FLEXSPI_AHBCR_APAREN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)

APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . 0b0..Flash will be accessed in Individual mode. 0b1..Flash will be accessed in Parallel mode.

Definition at line 18275 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_APAREN_MASK

#define FLEXSPI_AHBCR_APAREN_MASK   (0x1U)

Definition at line 18269 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_APAREN_SHIFT

#define FLEXSPI_AHBCR_APAREN_SHIFT   (0U)

Definition at line 18270 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_BUFFERABLEEN

#define FLEXSPI_AHBCR_BUFFERABLEEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)

BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.

Definition at line 18292 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_BUFFERABLEEN_MASK

#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK   (0x10U)

Definition at line 18283 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT

#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT   (4U)

Definition at line 18284 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_CACHABLEEN

#define FLEXSPI_AHBCR_CACHABLEEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)

CACHABLEEN - Enable AHB bus cachable read access support. 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.

Definition at line 18282 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_CACHABLEEN_MASK

#define FLEXSPI_AHBCR_CACHABLEEN_MASK   (0x8U)

Definition at line 18276 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_CACHABLEEN_SHIFT

#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT   (3U)

Definition at line 18277 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_PREFETCHEN

#define FLEXSPI_AHBCR_PREFETCHEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)

PREFETCHEN - AHB Read Prefetch Enable.

Definition at line 18297 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_PREFETCHEN_MASK

#define FLEXSPI_AHBCR_PREFETCHEN_MASK   (0x20U)

Definition at line 18293 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_PREFETCHEN_SHIFT

#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT   (5U)

Definition at line 18294 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_READADDROPT

#define FLEXSPI_AHBCR_READADDROPT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)

READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement.

Definition at line 18305 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_READADDROPT_MASK

#define FLEXSPI_AHBCR_READADDROPT_MASK   (0x40U)

Definition at line 18298 of file MIMXRT1052.h.

◆ FLEXSPI_AHBCR_READADDROPT_SHIFT

#define FLEXSPI_AHBCR_READADDROPT_SHIFT   (6U)

Definition at line 18299 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_BUFSZ

#define FLEXSPI_AHBRXBUFCR0_BUFSZ (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)

BUFSZ - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

Definition at line 18458 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK

#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK   (0xFFU)

Definition at line 18454 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT

#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT   (0U)

Definition at line 18455 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_COUNT

#define FLEXSPI_AHBRXBUFCR0_COUNT   (4U)

Definition at line 18477 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_MSTRID

#define FLEXSPI_AHBRXBUFCR0_MSTRID (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)

MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

Definition at line 18463 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_MSTRID_MASK

#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK   (0xF0000U)

Definition at line 18459 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT

#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT   (16U)

Definition at line 18460 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_PREFETCHEN

#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)

PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

Definition at line 18473 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK

#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK   (0x80000000U)

Definition at line 18469 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT

#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT   (31U)

Definition at line 18470 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_PRIORITY

#define FLEXSPI_AHBRXBUFCR0_PRIORITY (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)

PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

Definition at line 18468 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK

#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK   (0x3000000U)

Definition at line 18464 of file MIMXRT1052.h.

◆ FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT

#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT   (24U)

Definition at line 18465 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_ACTIVE

#define FLEXSPI_AHBSPNDSTS_ACTIVE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)

ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.

Definition at line 18852 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_ACTIVE_MASK

#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK   (0x1U)

Definition at line 18848 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT

#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT   (0U)

Definition at line 18849 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_BUFID

#define FLEXSPI_AHBSPNDSTS_BUFID (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)

BUFID - AHB RX BUF ID for suspended command sequence.

Definition at line 18857 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_BUFID_MASK

#define FLEXSPI_AHBSPNDSTS_BUFID_MASK   (0xEU)

Definition at line 18853 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_BUFID_SHIFT

#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT   (1U)

Definition at line 18854 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_DATLFT

#define FLEXSPI_AHBSPNDSTS_DATLFT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)

DATLFT - Left Data size for suspended command sequence (in byte).

Definition at line 18862 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_DATLFT_MASK

#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK   (0xFFFF0000U)

Definition at line 18858 of file MIMXRT1052.h.

◆ FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT

#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT   (16U)

Definition at line 18859 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_COUNT

#define FLEXSPI_DLLCR_COUNT   (2U)

Definition at line 18730 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_DLLEN

#define FLEXSPI_DLLCR_DLLEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)

DLLEN - DLL calibration enable.

Definition at line 18703 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_DLLEN_MASK

#define FLEXSPI_DLLCR_DLLEN_MASK   (0x1U)

Definition at line 18699 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_DLLEN_SHIFT

#define FLEXSPI_DLLCR_DLLEN_SHIFT   (0U)

Definition at line 18700 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_DLLRESET

#define FLEXSPI_DLLCR_DLLRESET (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)

DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).

Definition at line 18711 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_DLLRESET_MASK

#define FLEXSPI_DLLCR_DLLRESET_MASK   (0x2U)

Definition at line 18704 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_DLLRESET_SHIFT

#define FLEXSPI_DLLCR_DLLRESET_SHIFT   (1U)

Definition at line 18705 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_OVRDEN

#define FLEXSPI_DLLCR_OVRDEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)

OVRDEN - Slave clock delay line delay cell number selection override enable.

Definition at line 18721 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_OVRDEN_MASK

#define FLEXSPI_DLLCR_OVRDEN_MASK   (0x100U)

Definition at line 18717 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_OVRDEN_SHIFT

#define FLEXSPI_DLLCR_OVRDEN_SHIFT   (8U)

Definition at line 18718 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_OVRDVAL

#define FLEXSPI_DLLCR_OVRDVAL (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)

OVRDVAL - Slave clock delay line delay cell number selection override value.

Definition at line 18726 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_OVRDVAL_MASK

#define FLEXSPI_DLLCR_OVRDVAL_MASK   (0x7E00U)

Definition at line 18722 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_OVRDVAL_SHIFT

#define FLEXSPI_DLLCR_OVRDVAL_SHIFT   (9U)

Definition at line 18723 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_SLVDLYTARGET

#define FLEXSPI_DLLCR_SLVDLYTARGET (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)

SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock).

Definition at line 18716 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_SLVDLYTARGET_MASK

#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK   (0x78U)

Definition at line 18712 of file MIMXRT1052.h.

◆ FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT

#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT   (3U)

Definition at line 18713 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR0_COUNT

#define FLEXSPI_FLSHCR0_COUNT   (4U)

Definition at line 18489 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR0_FLSHSZ

#define FLEXSPI_FLSHCR0_FLSHSZ (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)

FLSHSZ - Flash Size in KByte.

Definition at line 18485 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR0_FLSHSZ_MASK

#define FLEXSPI_FLSHCR0_FLSHSZ_MASK   (0x7FFFFFU)

Definition at line 18481 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR0_FLSHSZ_SHIFT

#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT   (0U)

Definition at line 18482 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CAS

#define FLEXSPI_FLSHCR1_CAS (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)

CAS - Column Address Size.

Definition at line 18512 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CAS_MASK

#define FLEXSPI_FLSHCR1_CAS_MASK   (0x7800U)

Definition at line 18508 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CAS_SHIFT

#define FLEXSPI_FLSHCR1_CAS_SHIFT   (11U)

Definition at line 18509 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_COUNT

#define FLEXSPI_FLSHCR1_COUNT   (4U)

Definition at line 18531 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CSINTERVAL

#define FLEXSPI_FLSHCR1_CSINTERVAL (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)

CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.

Definition at line 18527 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CSINTERVAL_MASK

#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK   (0xFFFF0000U)

Definition at line 18520 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT

#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT   (16U)

Definition at line 18521 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CSINTERVALUNIT

#define FLEXSPI_FLSHCR1_CSINTERVALUNIT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)

CSINTERVALUNIT - CS interval unit 0b0..The CS interval unit is 1 serial clock cycle 0b1..The CS interval unit is 256 serial clock cycle

Definition at line 18519 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK

#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK   (0x8000U)

Definition at line 18513 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT

#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT   (15U)

Definition at line 18514 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_TCSH

#define FLEXSPI_FLSHCR1_TCSH (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)

TCSH - Serial Flash CS Hold time.

Definition at line 18502 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_TCSH_MASK

#define FLEXSPI_FLSHCR1_TCSH_MASK   (0x3E0U)

Definition at line 18498 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_TCSH_SHIFT

#define FLEXSPI_FLSHCR1_TCSH_SHIFT   (5U)

Definition at line 18499 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_TCSS

#define FLEXSPI_FLSHCR1_TCSS (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)

TCSS - Serial Flash CS setup time.

Definition at line 18497 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_TCSS_MASK

#define FLEXSPI_FLSHCR1_TCSS_MASK   (0x1FU)

Definition at line 18493 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_TCSS_SHIFT

#define FLEXSPI_FLSHCR1_TCSS_SHIFT   (0U)

Definition at line 18494 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_WA

#define FLEXSPI_FLSHCR1_WA (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)

WA - Word Addressable.

Definition at line 18507 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_WA_MASK

#define FLEXSPI_FLSHCR1_WA_MASK   (0x400U)

Definition at line 18503 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR1_WA_SHIFT

#define FLEXSPI_FLSHCR1_WA_SHIFT   (10U)

Definition at line 18504 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_ARDSEQID

#define FLEXSPI_FLSHCR2_ARDSEQID (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)

ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.

Definition at line 18539 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_ARDSEQID_MASK

#define FLEXSPI_FLSHCR2_ARDSEQID_MASK   (0xFU)

Definition at line 18535 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_ARDSEQID_SHIFT

#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT   (0U)

Definition at line 18536 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_ARDSEQNUM

#define FLEXSPI_FLSHCR2_ARDSEQNUM (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)

ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.

Definition at line 18544 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_ARDSEQNUM_MASK

#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK   (0xE0U)

Definition at line 18540 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT

#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT   (5U)

Definition at line 18541 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRSEQID

#define FLEXSPI_FLSHCR2_AWRSEQID (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)

AWRSEQID - Sequence Index for AHB Write triggered Command.

Definition at line 18549 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRSEQID_MASK

#define FLEXSPI_FLSHCR2_AWRSEQID_MASK   (0xF00U)

Definition at line 18545 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRSEQID_SHIFT

#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT   (8U)

Definition at line 18546 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRSEQNUM

#define FLEXSPI_FLSHCR2_AWRSEQNUM (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)

AWRSEQNUM - Sequence Number for AHB Write triggered Command.

Definition at line 18554 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRSEQNUM_MASK

#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK   (0xE000U)

Definition at line 18550 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT

#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT   (13U)

Definition at line 18551 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRWAIT

#define FLEXSPI_FLSHCR2_AWRWAIT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)

Definition at line 18557 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRWAIT_MASK

#define FLEXSPI_FLSHCR2_AWRWAIT_MASK   (0xFFF0000U)

Definition at line 18555 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRWAIT_SHIFT

#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT   (16U)

Definition at line 18556 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRWAITUNIT

#define FLEXSPI_FLSHCR2_AWRWAITUNIT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)

AWRWAITUNIT - AWRWAIT unit 0b000..The AWRWAIT unit is 2 ahb clock cycle 0b001..The AWRWAIT unit is 8 ahb clock cycle 0b010..The AWRWAIT unit is 32 ahb clock cycle 0b011..The AWRWAIT unit is 128 ahb clock cycle 0b100..The AWRWAIT unit is 512 ahb clock cycle 0b101..The AWRWAIT unit is 2048 ahb clock cycle 0b110..The AWRWAIT unit is 8192 ahb clock cycle 0b111..The AWRWAIT unit is 32768 ahb clock cycle

Definition at line 18570 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK

#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK   (0x70000000U)

Definition at line 18558 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT

#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT   (28U)

Definition at line 18559 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_CLRINSTRPTR

#define FLEXSPI_FLSHCR2_CLRINSTRPTR (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)

CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.

Definition at line 18576 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK

#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK   (0x80000000U)

Definition at line 18571 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT

#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT   (31U)

Definition at line 18572 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR2_COUNT

#define FLEXSPI_FLSHCR2_COUNT   (4U)

Definition at line 18580 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMENA

#define FLEXSPI_FLSHCR4_WMENA (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)

WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.

Definition at line 18600 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMENA_MASK

#define FLEXSPI_FLSHCR4_WMENA_MASK   (0x4U)

Definition at line 18593 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMENA_SHIFT

#define FLEXSPI_FLSHCR4_WMENA_SHIFT   (2U)

Definition at line 18594 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMENB

#define FLEXSPI_FLSHCR4_WMENB (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)

WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.

Definition at line 18608 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMENB_MASK

#define FLEXSPI_FLSHCR4_WMENB_MASK   (0x8U)

Definition at line 18601 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMENB_SHIFT

#define FLEXSPI_FLSHCR4_WMENB_SHIFT   (3U)

Definition at line 18602 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMOPT1

#define FLEXSPI_FLSHCR4_WMOPT1 (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)

WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.

Definition at line 18592 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMOPT1_MASK

#define FLEXSPI_FLSHCR4_WMOPT1_MASK   (0x1U)

Definition at line 18584 of file MIMXRT1052.h.

◆ FLEXSPI_FLSHCR4_WMOPT1_SHIFT

#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT   (0U)

Definition at line 18585 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBBUSTIMEOUTEN

#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)

AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.

Definition at line 18359 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK

#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK   (0x400U)

Definition at line 18355 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT

#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT   (10U)

Definition at line 18356 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBCMDERREN

#define FLEXSPI_INTEN_AHBCMDERREN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)

AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.

Definition at line 18334 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBCMDERREN_MASK

#define FLEXSPI_INTEN_AHBCMDERREN_MASK   (0x10U)

Definition at line 18330 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBCMDERREN_SHIFT

#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT   (4U)

Definition at line 18331 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBCMDGEEN

#define FLEXSPI_INTEN_AHBCMDGEEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)

AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.

Definition at line 18324 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBCMDGEEN_MASK

#define FLEXSPI_INTEN_AHBCMDGEEN_MASK   (0x4U)

Definition at line 18320 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_AHBCMDGEEN_SHIFT

#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT   (2U)

Definition at line 18321 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDDONEEN

#define FLEXSPI_INTEN_IPCMDDONEEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)

IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.

Definition at line 18314 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDDONEEN_MASK

#define FLEXSPI_INTEN_IPCMDDONEEN_MASK   (0x1U)

Definition at line 18310 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDDONEEN_SHIFT

#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT   (0U)

Definition at line 18311 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDERREN

#define FLEXSPI_INTEN_IPCMDERREN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)

IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.

Definition at line 18329 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDERREN_MASK

#define FLEXSPI_INTEN_IPCMDERREN_MASK   (0x8U)

Definition at line 18325 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDERREN_SHIFT

#define FLEXSPI_INTEN_IPCMDERREN_SHIFT   (3U)

Definition at line 18326 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDGEEN

#define FLEXSPI_INTEN_IPCMDGEEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)

IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.

Definition at line 18319 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDGEEN_MASK

#define FLEXSPI_INTEN_IPCMDGEEN_MASK   (0x2U)

Definition at line 18315 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPCMDGEEN_SHIFT

#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT   (1U)

Definition at line 18316 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPRXWAEN

#define FLEXSPI_INTEN_IPRXWAEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)

IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.

Definition at line 18339 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPRXWAEN_MASK

#define FLEXSPI_INTEN_IPRXWAEN_MASK   (0x20U)

Definition at line 18335 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPRXWAEN_SHIFT

#define FLEXSPI_INTEN_IPRXWAEN_SHIFT   (5U)

Definition at line 18336 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPTXWEEN

#define FLEXSPI_INTEN_IPTXWEEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)

IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.

Definition at line 18344 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPTXWEEN_MASK

#define FLEXSPI_INTEN_IPTXWEEN_MASK   (0x40U)

Definition at line 18340 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_IPTXWEEN_SHIFT

#define FLEXSPI_INTEN_IPTXWEEN_SHIFT   (6U)

Definition at line 18341 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SCKSTOPBYRDEN

#define FLEXSPI_INTEN_SCKSTOPBYRDEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)

SCKSTOPBYRDEN - SCK is stopped during command sequence because Async RX FIFO full interrupt enable.

Definition at line 18349 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK

#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK   (0x100U)

Definition at line 18345 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT

#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT   (8U)

Definition at line 18346 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SCKSTOPBYWREN

#define FLEXSPI_INTEN_SCKSTOPBYWREN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)

SCKSTOPBYWREN - SCK is stopped during command sequence because Async TX FIFO empty interrupt enable.

Definition at line 18354 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SCKSTOPBYWREN_MASK

#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK   (0x200U)

Definition at line 18350 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT

#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT   (9U)

Definition at line 18351 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SEQTIMEOUTEN

#define FLEXSPI_INTEN_SEQTIMEOUTEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)

SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.

Definition at line 18364 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SEQTIMEOUTEN_MASK

#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK   (0x800U)

Definition at line 18360 of file MIMXRT1052.h.

◆ FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT

#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT   (11U)

Definition at line 18361 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBBUSTIMEOUT

#define FLEXSPI_INTR_AHBBUSTIMEOUT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)

AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.

Definition at line 18421 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBBUSTIMEOUT_MASK

#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK   (0x400U)

Definition at line 18417 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT

#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT   (10U)

Definition at line 18418 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBCMDERR

#define FLEXSPI_INTR_AHBCMDERR (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)

AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all.

Definition at line 18396 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBCMDERR_MASK

#define FLEXSPI_INTR_AHBCMDERR_MASK   (0x10U)

Definition at line 18391 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBCMDERR_SHIFT

#define FLEXSPI_INTR_AHBCMDERR_SHIFT   (4U)

Definition at line 18392 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBCMDGE

#define FLEXSPI_INTR_AHBCMDGE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)

AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.

Definition at line 18384 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBCMDGE_MASK

#define FLEXSPI_INTR_AHBCMDGE_MASK   (0x4U)

Definition at line 18380 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_AHBCMDGE_SHIFT

#define FLEXSPI_INTR_AHBCMDGE_SHIFT   (2U)

Definition at line 18381 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDDONE

#define FLEXSPI_INTR_IPCMDDONE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)

IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated.

Definition at line 18374 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDDONE_MASK

#define FLEXSPI_INTR_IPCMDDONE_MASK   (0x1U)

Definition at line 18369 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDDONE_SHIFT

#define FLEXSPI_INTR_IPCMDDONE_SHIFT   (0U)

Definition at line 18370 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDERR

#define FLEXSPI_INTR_IPCMDERR (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)

IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all.

Definition at line 18390 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDERR_MASK

#define FLEXSPI_INTR_IPCMDERR_MASK   (0x8U)

Definition at line 18385 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDERR_SHIFT

#define FLEXSPI_INTR_IPCMDERR_SHIFT   (3U)

Definition at line 18386 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDGE

#define FLEXSPI_INTR_IPCMDGE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)

IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.

Definition at line 18379 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDGE_MASK

#define FLEXSPI_INTR_IPCMDGE_MASK   (0x2U)

Definition at line 18375 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPCMDGE_SHIFT

#define FLEXSPI_INTR_IPCMDGE_SHIFT   (1U)

Definition at line 18376 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPRXWA

#define FLEXSPI_INTR_IPRXWA (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)

IPRXWA - IP RX FIFO watermark available interrupt.

Definition at line 18401 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPRXWA_MASK

#define FLEXSPI_INTR_IPRXWA_MASK   (0x20U)

Definition at line 18397 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPRXWA_SHIFT

#define FLEXSPI_INTR_IPRXWA_SHIFT   (5U)

Definition at line 18398 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPTXWE

#define FLEXSPI_INTR_IPTXWE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)

IPTXWE - IP TX FIFO watermark empty interrupt.

Definition at line 18406 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPTXWE_MASK

#define FLEXSPI_INTR_IPTXWE_MASK   (0x40U)

Definition at line 18402 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_IPTXWE_SHIFT

#define FLEXSPI_INTR_IPTXWE_SHIFT   (6U)

Definition at line 18403 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SCKSTOPBYRD

#define FLEXSPI_INTR_SCKSTOPBYRD (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)

SCKSTOPBYRD - SCK is stopped during command sequence because Async RX FIFO full interrupt.

Definition at line 18411 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SCKSTOPBYRD_MASK

#define FLEXSPI_INTR_SCKSTOPBYRD_MASK   (0x100U)

Definition at line 18407 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SCKSTOPBYRD_SHIFT

#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT   (8U)

Definition at line 18408 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SCKSTOPBYWR

#define FLEXSPI_INTR_SCKSTOPBYWR (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)

SCKSTOPBYWR - SCK is stopped during command sequence because Async TX FIFO empty interrupt.

Definition at line 18416 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SCKSTOPBYWR_MASK

#define FLEXSPI_INTR_SCKSTOPBYWR_MASK   (0x200U)

Definition at line 18412 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SCKSTOPBYWR_SHIFT

#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT   (9U)

Definition at line 18413 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SEQTIMEOUT

#define FLEXSPI_INTR_SEQTIMEOUT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)

SEQTIMEOUT - Sequence execution timeout interrupt.

Definition at line 18426 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SEQTIMEOUT_MASK

#define FLEXSPI_INTR_SEQTIMEOUT_MASK   (0x800U)

Definition at line 18422 of file MIMXRT1052.h.

◆ FLEXSPI_INTR_SEQTIMEOUT_SHIFT

#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT   (11U)

Definition at line 18423 of file MIMXRT1052.h.

◆ FLEXSPI_IPCMD_TRG

#define FLEXSPI_IPCMD_TRG (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)

TRG - Setting this bit will trigger an IP Command.

Definition at line 18652 of file MIMXRT1052.h.

◆ FLEXSPI_IPCMD_TRG_MASK

#define FLEXSPI_IPCMD_TRG_MASK   (0x1U)

Definition at line 18648 of file MIMXRT1052.h.

◆ FLEXSPI_IPCMD_TRG_SHIFT

#define FLEXSPI_IPCMD_TRG_SHIFT   (0U)

Definition at line 18649 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR0_SFAR

#define FLEXSPI_IPCR0_SFAR (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)

SFAR - Serial Flash Address for IP command.

Definition at line 18617 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR0_SFAR_MASK

#define FLEXSPI_IPCR0_SFAR_MASK   (0xFFFFFFFFU)

Definition at line 18613 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR0_SFAR_SHIFT

#define FLEXSPI_IPCR0_SFAR_SHIFT   (0U)

Definition at line 18614 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_IDATSZ

#define FLEXSPI_IPCR1_IDATSZ (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)

IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.

Definition at line 18626 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_IDATSZ_MASK

#define FLEXSPI_IPCR1_IDATSZ_MASK   (0xFFFFU)

Definition at line 18622 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_IDATSZ_SHIFT

#define FLEXSPI_IPCR1_IDATSZ_SHIFT   (0U)

Definition at line 18623 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_IPAREN

#define FLEXSPI_IPCR1_IPAREN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)

IPAREN - Parallel mode Enabled for IP command. 0b0..Flash will be accessed in Individual mode. 0b1..Flash will be accessed in Parallel mode.

Definition at line 18643 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_IPAREN_MASK

#define FLEXSPI_IPCR1_IPAREN_MASK   (0x80000000U)

Definition at line 18637 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_IPAREN_SHIFT

#define FLEXSPI_IPCR1_IPAREN_SHIFT   (31U)

Definition at line 18638 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_ISEQID

#define FLEXSPI_IPCR1_ISEQID (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)

ISEQID - Sequence Index in LUT for IP command.

Definition at line 18631 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_ISEQID_MASK

#define FLEXSPI_IPCR1_ISEQID_MASK   (0xF0000U)

Definition at line 18627 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_ISEQID_SHIFT

#define FLEXSPI_IPCR1_ISEQID_SHIFT   (16U)

Definition at line 18628 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_ISEQNUM

#define FLEXSPI_IPCR1_ISEQNUM (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)

ISEQNUM - Sequence Number for IP command: ISEQNUM+1.

Definition at line 18636 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_ISEQNUM_MASK

#define FLEXSPI_IPCR1_ISEQNUM_MASK   (0x7000000U)

Definition at line 18632 of file MIMXRT1052.h.

◆ FLEXSPI_IPCR1_ISEQNUM_SHIFT

#define FLEXSPI_IPCR1_ISEQNUM_SHIFT   (24U)

Definition at line 18633 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_CLRIPRXF

#define FLEXSPI_IPRXFCR_CLRIPRXF (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)

CLRIPRXF - Clear all valid data entries in IP RX FIFO.

Definition at line 18661 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_CLRIPRXF_MASK

#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK   (0x1U)

Definition at line 18657 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT

#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT   (0U)

Definition at line 18658 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_RXDMAEN

#define FLEXSPI_IPRXFCR_RXDMAEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)

RXDMAEN - IP RX FIFO reading by DMA enabled. 0b0..IP RX FIFO would be read by processor. 0b1..IP RX FIFO would be read by DMA.

Definition at line 18668 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_RXDMAEN_MASK

#define FLEXSPI_IPRXFCR_RXDMAEN_MASK   (0x2U)

Definition at line 18662 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_RXDMAEN_SHIFT

#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT   (1U)

Definition at line 18663 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_RXWMRK

#define FLEXSPI_IPRXFCR_RXWMRK (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)

RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.

Definition at line 18673 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_RXWMRK_MASK

#define FLEXSPI_IPRXFCR_RXWMRK_MASK   (0x3CU)

Definition at line 18669 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFCR_RXWMRK_SHIFT

#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT   (2U)

Definition at line 18670 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFSTS_FILL

#define FLEXSPI_IPRXFSTS_FILL (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)

FILL - Fill level of IP RX FIFO.

Definition at line 18871 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFSTS_FILL_MASK

#define FLEXSPI_IPRXFSTS_FILL_MASK   (0xFFU)

Definition at line 18867 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFSTS_FILL_SHIFT

#define FLEXSPI_IPRXFSTS_FILL_SHIFT   (0U)

Definition at line 18868 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFSTS_RDCNTR

#define FLEXSPI_IPRXFSTS_RDCNTR (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)

RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.

Definition at line 18876 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFSTS_RDCNTR_MASK

#define FLEXSPI_IPRXFSTS_RDCNTR_MASK   (0xFFFF0000U)

Definition at line 18872 of file MIMXRT1052.h.

◆ FLEXSPI_IPRXFSTS_RDCNTR_SHIFT

#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT   (16U)

Definition at line 18873 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_CLRIPTXF

#define FLEXSPI_IPTXFCR_CLRIPTXF (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)

CLRIPTXF - Clear all valid data entries in IP TX FIFO.

Definition at line 18682 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_CLRIPTXF_MASK

#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK   (0x1U)

Definition at line 18678 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT

#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT   (0U)

Definition at line 18679 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_TXDMAEN

#define FLEXSPI_IPTXFCR_TXDMAEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)

TXDMAEN - IP TX FIFO filling by DMA enabled. 0b0..IP TX FIFO would be filled by processor. 0b1..IP TX FIFO would be filled by DMA.

Definition at line 18689 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_TXDMAEN_MASK

#define FLEXSPI_IPTXFCR_TXDMAEN_MASK   (0x2U)

Definition at line 18683 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_TXDMAEN_SHIFT

#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT   (1U)

Definition at line 18684 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_TXWMRK

#define FLEXSPI_IPTXFCR_TXWMRK (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)

TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.

Definition at line 18694 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_TXWMRK_MASK

#define FLEXSPI_IPTXFCR_TXWMRK_MASK   (0x3CU)

Definition at line 18690 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFCR_TXWMRK_SHIFT

#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT   (2U)

Definition at line 18691 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFSTS_FILL

#define FLEXSPI_IPTXFSTS_FILL (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)

FILL - Fill level of IP TX FIFO.

Definition at line 18885 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFSTS_FILL_MASK

#define FLEXSPI_IPTXFSTS_FILL_MASK   (0xFFU)

Definition at line 18881 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFSTS_FILL_SHIFT

#define FLEXSPI_IPTXFSTS_FILL_SHIFT   (0U)

Definition at line 18882 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFSTS_WRCNTR

#define FLEXSPI_IPTXFSTS_WRCNTR (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)

WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.

Definition at line 18890 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFSTS_WRCNTR_MASK

#define FLEXSPI_IPTXFSTS_WRCNTR_MASK   (0xFFFF0000U)

Definition at line 18886 of file MIMXRT1052.h.

◆ FLEXSPI_IPTXFSTS_WRCNTR_SHIFT

#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT   (16U)

Definition at line 18887 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_COUNT

#define FLEXSPI_LUT_COUNT   (64U)

Definition at line 18952 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_NUM_PADS0

#define FLEXSPI_LUT_NUM_PADS0 (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)

NUM_PADS0 - NUM_PADS0

Definition at line 18928 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_NUM_PADS0_MASK

#define FLEXSPI_LUT_NUM_PADS0_MASK   (0x300U)

Definition at line 18924 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_NUM_PADS0_SHIFT

#define FLEXSPI_LUT_NUM_PADS0_SHIFT   (8U)

Definition at line 18925 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_NUM_PADS1

#define FLEXSPI_LUT_NUM_PADS1 (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)

NUM_PADS1 - NUM_PADS1

Definition at line 18943 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_NUM_PADS1_MASK

#define FLEXSPI_LUT_NUM_PADS1_MASK   (0x3000000U)

Definition at line 18939 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_NUM_PADS1_SHIFT

#define FLEXSPI_LUT_NUM_PADS1_SHIFT   (24U)

Definition at line 18940 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPCODE0

#define FLEXSPI_LUT_OPCODE0 (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)

OPCODE0 - OPCODE

Definition at line 18933 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPCODE0_MASK

#define FLEXSPI_LUT_OPCODE0_MASK   (0xFC00U)

Definition at line 18929 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPCODE0_SHIFT

#define FLEXSPI_LUT_OPCODE0_SHIFT   (10U)

Definition at line 18930 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPCODE1

#define FLEXSPI_LUT_OPCODE1 (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)

OPCODE1 - OPCODE1

Definition at line 18948 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPCODE1_MASK

#define FLEXSPI_LUT_OPCODE1_MASK   (0xFC000000U)

Definition at line 18944 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPCODE1_SHIFT

#define FLEXSPI_LUT_OPCODE1_SHIFT   (26U)

Definition at line 18945 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPERAND0

#define FLEXSPI_LUT_OPERAND0 (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)

OPERAND0 - OPERAND0

Definition at line 18923 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPERAND0_MASK

#define FLEXSPI_LUT_OPERAND0_MASK   (0xFFU)

Definition at line 18919 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPERAND0_SHIFT

#define FLEXSPI_LUT_OPERAND0_SHIFT   (0U)

Definition at line 18920 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPERAND1

#define FLEXSPI_LUT_OPERAND1 (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)

OPERAND1 - OPERAND1

Definition at line 18938 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPERAND1_MASK

#define FLEXSPI_LUT_OPERAND1_MASK   (0xFF0000U)

Definition at line 18934 of file MIMXRT1052.h.

◆ FLEXSPI_LUT_OPERAND1_SHIFT

#define FLEXSPI_LUT_OPERAND1_SHIFT   (16U)

Definition at line 18935 of file MIMXRT1052.h.

◆ FLEXSPI_LUTCR_LOCK

#define FLEXSPI_LUTCR_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)

LOCK - Lock LUT

Definition at line 18444 of file MIMXRT1052.h.

◆ FLEXSPI_LUTCR_LOCK_MASK

#define FLEXSPI_LUTCR_LOCK_MASK   (0x1U)

Definition at line 18440 of file MIMXRT1052.h.

◆ FLEXSPI_LUTCR_LOCK_SHIFT

#define FLEXSPI_LUTCR_LOCK_SHIFT   (0U)

Definition at line 18441 of file MIMXRT1052.h.

◆ FLEXSPI_LUTCR_UNLOCK

#define FLEXSPI_LUTCR_UNLOCK (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)

UNLOCK - Unlock LUT

Definition at line 18449 of file MIMXRT1052.h.

◆ FLEXSPI_LUTCR_UNLOCK_MASK

#define FLEXSPI_LUTCR_UNLOCK_MASK   (0x2U)

Definition at line 18445 of file MIMXRT1052.h.

◆ FLEXSPI_LUTCR_UNLOCK_SHIFT

#define FLEXSPI_LUTCR_UNLOCK_SHIFT   (1U)

Definition at line 18446 of file MIMXRT1052.h.

◆ FLEXSPI_LUTKEY_KEY

#define FLEXSPI_LUTKEY_KEY (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)

KEY - The Key to lock or unlock LUT.

Definition at line 18435 of file MIMXRT1052.h.

◆ FLEXSPI_LUTKEY_KEY_MASK

#define FLEXSPI_LUTKEY_KEY_MASK   (0xFFFFFFFFU)

Definition at line 18431 of file MIMXRT1052.h.

◆ FLEXSPI_LUTKEY_KEY_SHIFT

#define FLEXSPI_LUTKEY_KEY_SHIFT   (0U)

Definition at line 18432 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_AHBGRANTWAIT

#define FLEXSPI_MCR0_AHBGRANTWAIT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)

AHBGRANTWAIT - Timeout wait cycle for AHB command grant.

Definition at line 18210 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_AHBGRANTWAIT_MASK

#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK   (0xFF000000U)

Definition at line 18206 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT

#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT   (24U)

Definition at line 18207 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_ARDFEN

#define FLEXSPI_MCR0_ARDFEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)

ARDFEN - Enable AHB bus Read Access to IP RX FIFO. 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.

Definition at line 18163 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_ARDFEN_MASK

#define FLEXSPI_MCR0_ARDFEN_MASK   (0x40U)

Definition at line 18157 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_ARDFEN_SHIFT

#define FLEXSPI_MCR0_ARDFEN_SHIFT   (6U)

Definition at line 18158 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_ATDFEN

#define FLEXSPI_MCR0_ATDFEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)

ATDFEN - Enable AHB bus Write Access to IP TX FIFO. 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.

Definition at line 18170 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_ATDFEN_MASK

#define FLEXSPI_MCR0_ATDFEN_MASK   (0x80U)

Definition at line 18164 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_ATDFEN_SHIFT

#define FLEXSPI_MCR0_ATDFEN_SHIFT   (7U)

Definition at line 18165 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_COMBINATIONEN

#define FLEXSPI_MCR0_COMBINATIONEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)

COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). 0b0..Disable. 0b1..Enable.

Definition at line 18191 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_COMBINATIONEN_MASK

#define FLEXSPI_MCR0_COMBINATIONEN_MASK   (0x2000U)

Definition at line 18185 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_COMBINATIONEN_SHIFT

#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT   (13U)

Definition at line 18186 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_DOZEEN

#define FLEXSPI_MCR0_DOZEEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)

DOZEEN - Doze mode enable bit 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.

Definition at line 18184 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_DOZEEN_MASK

#define FLEXSPI_MCR0_DOZEEN_MASK   (0x1000U)

Definition at line 18178 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_DOZEEN_SHIFT

#define FLEXSPI_MCR0_DOZEEN_SHIFT   (12U)

Definition at line 18179 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_HSEN

#define FLEXSPI_MCR0_HSEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)

HSEN - Half Speed Serial Flash access Enable. 0b0..Disable divide by 2 of serial flash clock for half speed commands. 0b1..Enable divide by 2 of serial flash clock for half speed commands.

Definition at line 18177 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_HSEN_MASK

#define FLEXSPI_MCR0_HSEN_MASK   (0x800U)

Definition at line 18171 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_HSEN_SHIFT

#define FLEXSPI_MCR0_HSEN_SHIFT   (11U)

Definition at line 18172 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_IPGRANTWAIT

#define FLEXSPI_MCR0_IPGRANTWAIT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)

IPGRANTWAIT - Time out wait cycle for IP command grant.

Definition at line 18205 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_IPGRANTWAIT_MASK

#define FLEXSPI_MCR0_IPGRANTWAIT_MASK   (0xFF0000U)

Definition at line 18201 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_IPGRANTWAIT_SHIFT

#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT   (16U)

Definition at line 18202 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_MDIS

#define FLEXSPI_MCR0_MDIS (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)

MDIS - Module Disable

Definition at line 18147 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_MDIS_MASK

#define FLEXSPI_MCR0_MDIS_MASK   (0x2U)

Definition at line 18143 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_MDIS_SHIFT

#define FLEXSPI_MCR0_MDIS_SHIFT   (1U)

Definition at line 18144 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_RXCLKSRC

#define FLEXSPI_MCR0_RXCLKSRC (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)

RXCLKSRC - Sample Clock source selection for Flash Reading 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. 0b10..Reserved 0b11..Flash provided Read strobe and input from DQS pad

Definition at line 18156 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_RXCLKSRC_MASK

#define FLEXSPI_MCR0_RXCLKSRC_MASK   (0x30U)

Definition at line 18148 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_RXCLKSRC_SHIFT

#define FLEXSPI_MCR0_RXCLKSRC_SHIFT   (4U)

Definition at line 18149 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_SCKFREERUNEN

#define FLEXSPI_MCR0_SCKFREERUNEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)

SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). 0b0..Disable. 0b1..Enable.

Definition at line 18200 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_SCKFREERUNEN_MASK

#define FLEXSPI_MCR0_SCKFREERUNEN_MASK   (0x4000U)

Definition at line 18192 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_SCKFREERUNEN_SHIFT

#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT   (14U)

Definition at line 18193 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_SWRESET

#define FLEXSPI_MCR0_SWRESET (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)

SWRESET - Software Reset

Definition at line 18142 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_SWRESET_MASK

#define FLEXSPI_MCR0_SWRESET_MASK   (0x1U)

Definition at line 18138 of file MIMXRT1052.h.

◆ FLEXSPI_MCR0_SWRESET_SHIFT

#define FLEXSPI_MCR0_SWRESET_SHIFT   (0U)

Definition at line 18139 of file MIMXRT1052.h.

◆ FLEXSPI_MCR1_AHBBUSWAIT

#define FLEXSPI_MCR1_AHBBUSWAIT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)

Definition at line 18217 of file MIMXRT1052.h.

◆ FLEXSPI_MCR1_AHBBUSWAIT_MASK

#define FLEXSPI_MCR1_AHBBUSWAIT_MASK   (0xFFFFU)

Definition at line 18215 of file MIMXRT1052.h.

◆ FLEXSPI_MCR1_AHBBUSWAIT_SHIFT

#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT   (0U)

Definition at line 18216 of file MIMXRT1052.h.

◆ FLEXSPI_MCR1_SEQWAIT

#define FLEXSPI_MCR1_SEQWAIT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)

Definition at line 18220 of file MIMXRT1052.h.

◆ FLEXSPI_MCR1_SEQWAIT_MASK

#define FLEXSPI_MCR1_SEQWAIT_MASK   (0xFFFF0000U)

Definition at line 18218 of file MIMXRT1052.h.

◆ FLEXSPI_MCR1_SEQWAIT_SHIFT

#define FLEXSPI_MCR1_SEQWAIT_SHIFT   (16U)

Definition at line 18219 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_CLRAHBBUFOPT

#define FLEXSPI_MCR2_CLRAHBBUFOPT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)

CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.

Definition at line 18234 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_CLRAHBBUFOPT_MASK

#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK   (0x800U)

Definition at line 18225 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT

#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT   (11U)

Definition at line 18226 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_CLRLEARNPHASE

#define FLEXSPI_MCR2_CLRLEARNPHASE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)

CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.

Definition at line 18240 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_CLRLEARNPHASE_MASK

#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK   (0x4000U)

Definition at line 18235 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT

#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT   (14U)

Definition at line 18236 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_RESUMEWAIT

#define FLEXSPI_MCR2_RESUMEWAIT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)

RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.

Definition at line 18264 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_RESUMEWAIT_MASK

#define FLEXSPI_MCR2_RESUMEWAIT_MASK   (0xFF000000U)

Definition at line 18260 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_RESUMEWAIT_SHIFT

#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT   (24U)

Definition at line 18261 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_SAMEDEVICEEN

#define FLEXSPI_MCR2_SAMEDEVICEEN (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)

SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.

Definition at line 18250 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_SAMEDEVICEEN_MASK

#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK   (0x8000U)

Definition at line 18241 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT

#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT   (15U)

Definition at line 18242 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_SCKBDIFFOPT

#define FLEXSPI_MCR2_SCKBDIFFOPT (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)

SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available.

Definition at line 18259 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_SCKBDIFFOPT_MASK

#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK   (0x80000U)

Definition at line 18251 of file MIMXRT1052.h.

◆ FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT

#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT   (19U)

Definition at line 18252 of file MIMXRT1052.h.

◆ FLEXSPI_RFDR_COUNT

#define FLEXSPI_RFDR_COUNT   (32U)

Definition at line 18903 of file MIMXRT1052.h.

◆ FLEXSPI_RFDR_RXDATA

#define FLEXSPI_RFDR_RXDATA (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)

RXDATA - RX Data

Definition at line 18899 of file MIMXRT1052.h.

◆ FLEXSPI_RFDR_RXDATA_MASK

#define FLEXSPI_RFDR_RXDATA_MASK   (0xFFFFFFFFU)

Definition at line 18895 of file MIMXRT1052.h.

◆ FLEXSPI_RFDR_RXDATA_SHIFT

#define FLEXSPI_RFDR_RXDATA_SHIFT   (0U)

Definition at line 18896 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_ARBCMDSRC

#define FLEXSPI_STS0_ARBCMDSRC (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)

ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). 0b00..Triggered by AHB read command (triggered by AHB read). 0b01..Triggered by AHB write command (triggered by AHB Write). 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). 0b11..Triggered by suspended command (resumed).

Definition at line 18757 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_ARBCMDSRC_MASK

#define FLEXSPI_STS0_ARBCMDSRC_MASK   (0xCU)

Definition at line 18748 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_ARBCMDSRC_SHIFT

#define FLEXSPI_STS0_ARBCMDSRC_SHIFT   (2U)

Definition at line 18749 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_ARBIDLE

#define FLEXSPI_STS0_ARBIDLE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)

ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.

Definition at line 18747 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_ARBIDLE_MASK

#define FLEXSPI_STS0_ARBIDLE_MASK   (0x2U)

Definition at line 18740 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_ARBIDLE_SHIFT

#define FLEXSPI_STS0_ARBIDLE_SHIFT   (1U)

Definition at line 18741 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_SEQIDLE

#define FLEXSPI_STS0_SEQIDLE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)

SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.

Definition at line 18739 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_SEQIDLE_MASK

#define FLEXSPI_STS0_SEQIDLE_MASK   (0x1U)

Definition at line 18734 of file MIMXRT1052.h.

◆ FLEXSPI_STS0_SEQIDLE_SHIFT

#define FLEXSPI_STS0_SEQIDLE_SHIFT   (0U)

Definition at line 18735 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_AHBCMDERRCODE

#define FLEXSPI_STS1_AHBCMDERRCODE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)

AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). 0b0000..No error. 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. 0b0011..There is unknown instruction opcode in the sequence. 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0b1110..Sequence execution timeout.

Definition at line 18779 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_AHBCMDERRCODE_MASK

#define FLEXSPI_STS1_AHBCMDERRCODE_MASK   (0xF00U)

Definition at line 18768 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_AHBCMDERRCODE_SHIFT

#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT   (8U)

Definition at line 18769 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_AHBCMDERRID

#define FLEXSPI_STS1_AHBCMDERRID (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)

AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).

Definition at line 18767 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_AHBCMDERRID_MASK

#define FLEXSPI_STS1_AHBCMDERRID_MASK   (0xFU)

Definition at line 18762 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_AHBCMDERRID_SHIFT

#define FLEXSPI_STS1_AHBCMDERRID_SHIFT   (0U)

Definition at line 18763 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_IPCMDERRCODE

#define FLEXSPI_STS1_IPCMDERRCODE (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)

IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). 0b0000..No error. 0b0010..IP command with JMP_ON_CS instruction used in the sequence. 0b0011..There is unknown instruction opcode in the sequence. 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). 0b1110..Sequence execution timeout. 0b1111..Flash boundary crossed.

Definition at line 18799 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_IPCMDERRCODE_MASK

#define FLEXSPI_STS1_IPCMDERRCODE_MASK   (0xF000000U)

Definition at line 18786 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_IPCMDERRCODE_SHIFT

#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT   (24U)

Definition at line 18787 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_IPCMDERRID

#define FLEXSPI_STS1_IPCMDERRID (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)

IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).

Definition at line 18785 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_IPCMDERRID_MASK

#define FLEXSPI_STS1_IPCMDERRID_MASK   (0xF0000U)

Definition at line 18780 of file MIMXRT1052.h.

◆ FLEXSPI_STS1_IPCMDERRID_SHIFT

#define FLEXSPI_STS1_IPCMDERRID_SHIFT   (16U)

Definition at line 18781 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_AREFLOCK

#define FLEXSPI_STS2_AREFLOCK (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)

AREFLOCK - Flash A sample clock reference delay line locked.

Definition at line 18813 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_AREFLOCK_MASK

#define FLEXSPI_STS2_AREFLOCK_MASK   (0x2U)

Definition at line 18809 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_AREFLOCK_SHIFT

#define FLEXSPI_STS2_AREFLOCK_SHIFT   (1U)

Definition at line 18810 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_AREFSEL

#define FLEXSPI_STS2_AREFSEL (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)

AREFSEL - Flash A sample clock reference delay line delay cell number selection.

Definition at line 18823 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_AREFSEL_MASK

#define FLEXSPI_STS2_AREFSEL_MASK   (0x3F00U)

Definition at line 18819 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_AREFSEL_SHIFT

#define FLEXSPI_STS2_AREFSEL_SHIFT   (8U)

Definition at line 18820 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_ASLVLOCK

#define FLEXSPI_STS2_ASLVLOCK (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)

ASLVLOCK - Flash A sample clock slave delay line locked.

Definition at line 18808 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_ASLVLOCK_MASK

#define FLEXSPI_STS2_ASLVLOCK_MASK   (0x1U)

Definition at line 18804 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_ASLVLOCK_SHIFT

#define FLEXSPI_STS2_ASLVLOCK_SHIFT   (0U)

Definition at line 18805 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_ASLVSEL

#define FLEXSPI_STS2_ASLVSEL (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)

ASLVSEL - Flash A sample clock slave delay line delay cell number selection .

Definition at line 18818 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_ASLVSEL_MASK

#define FLEXSPI_STS2_ASLVSEL_MASK   (0xFCU)

Definition at line 18814 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_ASLVSEL_SHIFT

#define FLEXSPI_STS2_ASLVSEL_SHIFT   (2U)

Definition at line 18815 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BREFLOCK

#define FLEXSPI_STS2_BREFLOCK (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)

BREFLOCK - Flash B sample clock reference delay line locked.

Definition at line 18833 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BREFLOCK_MASK

#define FLEXSPI_STS2_BREFLOCK_MASK   (0x20000U)

Definition at line 18829 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BREFLOCK_SHIFT

#define FLEXSPI_STS2_BREFLOCK_SHIFT   (17U)

Definition at line 18830 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BREFSEL

#define FLEXSPI_STS2_BREFSEL (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)

BREFSEL - Flash B sample clock reference delay line delay cell number selection.

Definition at line 18843 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BREFSEL_MASK

#define FLEXSPI_STS2_BREFSEL_MASK   (0x3F000000U)

Definition at line 18839 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BREFSEL_SHIFT

#define FLEXSPI_STS2_BREFSEL_SHIFT   (24U)

Definition at line 18840 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BSLVLOCK

#define FLEXSPI_STS2_BSLVLOCK (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)

BSLVLOCK - Flash B sample clock slave delay line locked.

Definition at line 18828 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BSLVLOCK_MASK

#define FLEXSPI_STS2_BSLVLOCK_MASK   (0x10000U)

Definition at line 18824 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BSLVLOCK_SHIFT

#define FLEXSPI_STS2_BSLVLOCK_SHIFT   (16U)

Definition at line 18825 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BSLVSEL

#define FLEXSPI_STS2_BSLVSEL (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)

BSLVSEL - Flash B sample clock slave delay line delay cell number selection.

Definition at line 18838 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BSLVSEL_MASK

#define FLEXSPI_STS2_BSLVSEL_MASK   (0xFC0000U)

Definition at line 18834 of file MIMXRT1052.h.

◆ FLEXSPI_STS2_BSLVSEL_SHIFT

#define FLEXSPI_STS2_BSLVSEL_SHIFT   (18U)

Definition at line 18835 of file MIMXRT1052.h.

◆ FLEXSPI_TFDR_COUNT

#define FLEXSPI_TFDR_COUNT   (32U)

Definition at line 18915 of file MIMXRT1052.h.

◆ FLEXSPI_TFDR_TXDATA

#define FLEXSPI_TFDR_TXDATA (   x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)

TXDATA - TX Data

Definition at line 18911 of file MIMXRT1052.h.

◆ FLEXSPI_TFDR_TXDATA_MASK

#define FLEXSPI_TFDR_TXDATA_MASK   (0xFFFFFFFFU)

Definition at line 18907 of file MIMXRT1052.h.

◆ FLEXSPI_TFDR_TXDATA_SHIFT

#define FLEXSPI_TFDR_TXDATA_SHIFT   (0U)

Definition at line 18908 of file MIMXRT1052.h.

◆ PWM_INTEN_CA0IE

#define PWM_INTEN_CA0IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)

CA0IE - Capture A 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA0]. 0b1..Interrupt request enabled for STS[CFA0].

Definition at line 31485 of file MIMXRT1052.h.

◆ PWM_INTEN_CA0IE_MASK

#define PWM_INTEN_CA0IE_MASK   (0x400U)

Definition at line 31479 of file MIMXRT1052.h.

◆ PWM_INTEN_CA0IE_SHIFT

#define PWM_INTEN_CA0IE_SHIFT   (10U)

Definition at line 31480 of file MIMXRT1052.h.

◆ PWM_INTEN_CA1IE

#define PWM_INTEN_CA1IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)

CA1IE - Capture A 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA1]. 0b1..Interrupt request enabled for STS[CFA1].

Definition at line 31492 of file MIMXRT1052.h.

◆ PWM_INTEN_CA1IE_MASK

#define PWM_INTEN_CA1IE_MASK   (0x800U)

Definition at line 31486 of file MIMXRT1052.h.

◆ PWM_INTEN_CA1IE_SHIFT

#define PWM_INTEN_CA1IE_SHIFT   (11U)

Definition at line 31487 of file MIMXRT1052.h.

◆ PWM_INTEN_CB0IE

#define PWM_INTEN_CB0IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)

CB0IE - Capture B 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB0]. 0b1..Interrupt request enabled for STS[CFB0].

Definition at line 31471 of file MIMXRT1052.h.

◆ PWM_INTEN_CB0IE_MASK

#define PWM_INTEN_CB0IE_MASK   (0x100U)

Definition at line 31465 of file MIMXRT1052.h.

◆ PWM_INTEN_CB0IE_SHIFT

#define PWM_INTEN_CB0IE_SHIFT   (8U)

Definition at line 31466 of file MIMXRT1052.h.

◆ PWM_INTEN_CB1IE

#define PWM_INTEN_CB1IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)

CB1IE - Capture B 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB1]. 0b1..Interrupt request enabled for STS[CFB1].

Definition at line 31478 of file MIMXRT1052.h.

◆ PWM_INTEN_CB1IE_MASK

#define PWM_INTEN_CB1IE_MASK   (0x200U)

Definition at line 31472 of file MIMXRT1052.h.

◆ PWM_INTEN_CB1IE_SHIFT

#define PWM_INTEN_CB1IE_SHIFT   (9U)

Definition at line 31473 of file MIMXRT1052.h.

◆ PWM_INTEN_CMPIE

#define PWM_INTEN_CMPIE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)

CMPIE - Compare Interrupt Enables 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.

Definition at line 31450 of file MIMXRT1052.h.

◆ PWM_INTEN_CMPIE_MASK

#define PWM_INTEN_CMPIE_MASK   (0x3FU)

Definition at line 31444 of file MIMXRT1052.h.

◆ PWM_INTEN_CMPIE_SHIFT

#define PWM_INTEN_CMPIE_SHIFT   (0U)

Definition at line 31445 of file MIMXRT1052.h.

◆ PWM_INTEN_CX0IE

#define PWM_INTEN_CX0IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)

CX0IE - Capture X 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX0]. 0b1..Interrupt request enabled for STS[CFX0].

Definition at line 31457 of file MIMXRT1052.h.

◆ PWM_INTEN_CX0IE_MASK

#define PWM_INTEN_CX0IE_MASK   (0x40U)

Definition at line 31451 of file MIMXRT1052.h.

◆ PWM_INTEN_CX0IE_SHIFT

#define PWM_INTEN_CX0IE_SHIFT   (6U)

Definition at line 31452 of file MIMXRT1052.h.

◆ PWM_INTEN_CX1IE

#define PWM_INTEN_CX1IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)

CX1IE - Capture X 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX1]. 0b1..Interrupt request enabled for STS[CFX1].

Definition at line 31464 of file MIMXRT1052.h.

◆ PWM_INTEN_CX1IE_MASK

#define PWM_INTEN_CX1IE_MASK   (0x80U)

Definition at line 31458 of file MIMXRT1052.h.

◆ PWM_INTEN_CX1IE_SHIFT

#define PWM_INTEN_CX1IE_SHIFT   (7U)

Definition at line 31459 of file MIMXRT1052.h.

◆ PWM_INTEN_REIE

#define PWM_INTEN_REIE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)

REIE - Reload Error Interrupt Enable 0b0..STS[REF] CPU interrupt requests disabled 0b1..STS[REF] CPU interrupt requests enabled

Definition at line 31506 of file MIMXRT1052.h.

◆ PWM_INTEN_REIE_MASK

#define PWM_INTEN_REIE_MASK   (0x2000U)

Definition at line 31500 of file MIMXRT1052.h.

◆ PWM_INTEN_REIE_SHIFT

#define PWM_INTEN_REIE_SHIFT   (13U)

Definition at line 31501 of file MIMXRT1052.h.

◆ PWM_INTEN_RIE

#define PWM_INTEN_RIE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)

RIE - Reload Interrupt Enable 0b0..STS[RF] CPU interrupt requests disabled 0b1..STS[RF] CPU interrupt requests enabled

Definition at line 31499 of file MIMXRT1052.h.

◆ PWM_INTEN_RIE_MASK

#define PWM_INTEN_RIE_MASK   (0x1000U)

Definition at line 31493 of file MIMXRT1052.h.

◆ PWM_INTEN_RIE_SHIFT

#define PWM_INTEN_RIE_SHIFT   (12U)

Definition at line 31494 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXIBUSERREN

#define SEMC_INTEN_AXIBUSERREN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)

AXIBUSERREN - AXI bus error interrupt enable

Definition at line 34452 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXIBUSERREN_MASK

#define SEMC_INTEN_AXIBUSERREN_MASK   (0x8U)

Definition at line 34448 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXIBUSERREN_SHIFT

#define SEMC_INTEN_AXIBUSERREN_SHIFT   (3U)

Definition at line 34449 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXICMDERREN

#define SEMC_INTEN_AXICMDERREN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)

AXICMDERREN - AXI command error interrupt enable

Definition at line 34447 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXICMDERREN_MASK

#define SEMC_INTEN_AXICMDERREN_MASK   (0x4U)

Definition at line 34443 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXICMDERREN_SHIFT

#define SEMC_INTEN_AXICMDERREN_SHIFT   (2U)

Definition at line 34444 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDDONEEN

#define SEMC_INTEN_IPCMDDONEEN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)

IPCMDDONEEN - IP command done interrupt enable

Definition at line 34437 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDDONEEN_MASK

#define SEMC_INTEN_IPCMDDONEEN_MASK   (0x1U)

Definition at line 34433 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDDONEEN_SHIFT

#define SEMC_INTEN_IPCMDDONEEN_SHIFT   (0U)

Definition at line 34434 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDERREN

#define SEMC_INTEN_IPCMDERREN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)

IPCMDERREN - IP command error interrupt enable

Definition at line 34442 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDERREN_MASK

#define SEMC_INTEN_IPCMDERREN_MASK   (0x2U)

Definition at line 34438 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDERREN_SHIFT

#define SEMC_INTEN_IPCMDERREN_SHIFT   (1U)

Definition at line 34439 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDNOPENDEN

#define SEMC_INTEN_NDNOPENDEN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)

NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation. 0b0..Disable 0b1..Enable

Definition at line 34466 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDNOPENDEN_MASK

#define SEMC_INTEN_NDNOPENDEN_MASK   (0x20U)

Definition at line 34460 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDNOPENDEN_SHIFT

#define SEMC_INTEN_NDNOPENDEN_SHIFT   (5U)

Definition at line 34461 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDPAGEENDEN

#define SEMC_INTEN_NDPAGEENDEN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)

NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation. 0b0..Disable 0b1..Enable

Definition at line 34459 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDPAGEENDEN_MASK

#define SEMC_INTEN_NDPAGEENDEN_MASK   (0x10U)

Definition at line 34453 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDPAGEENDEN_SHIFT

#define SEMC_INTEN_NDPAGEENDEN_SHIFT   (4U)

Definition at line 34454 of file MIMXRT1052.h.

◆ SEMC_IPCMD_CMD

#define SEMC_IPCMD_CMD (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)

Definition at line 35228 of file MIMXRT1052.h.

◆ SEMC_IPCMD_CMD_MASK

#define SEMC_IPCMD_CMD_MASK   (0xFFFFU)

Definition at line 35226 of file MIMXRT1052.h.

◆ SEMC_IPCMD_CMD_SHIFT

#define SEMC_IPCMD_CMD_SHIFT   (0U)

Definition at line 35227 of file MIMXRT1052.h.

◆ SEMC_IPCMD_KEY

#define SEMC_IPCMD_KEY (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)

KEY - This field should be written with 0xA55A when trigging an IP command.

Definition at line 35233 of file MIMXRT1052.h.

◆ SEMC_IPCMD_KEY_MASK

#define SEMC_IPCMD_KEY_MASK   (0xFFFF0000U)

Definition at line 35229 of file MIMXRT1052.h.

◆ SEMC_IPCMD_KEY_SHIFT

#define SEMC_IPCMD_KEY_SHIFT   (16U)

Definition at line 35230 of file MIMXRT1052.h.

◆ SEMC_STS0_IDLE

#define SEMC_STS0_IDLE (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)

IDLE - Indicating whether SEMC is in IDLE state.

Definition at line 35256 of file MIMXRT1052.h.

◆ SEMC_STS0_IDLE_MASK

#define SEMC_STS0_IDLE_MASK   (0x1U)

Definition at line 35252 of file MIMXRT1052.h.

◆ SEMC_STS0_IDLE_SHIFT

#define SEMC_STS0_IDLE_SHIFT   (0U)

Definition at line 35253 of file MIMXRT1052.h.

◆ SEMC_STS0_NARDY

#define SEMC_STS0_NARDY (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)

NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready

Definition at line 35263 of file MIMXRT1052.h.

◆ SEMC_STS0_NARDY_MASK

#define SEMC_STS0_NARDY_MASK   (0x2U)

Definition at line 35257 of file MIMXRT1052.h.

◆ SEMC_STS0_NARDY_SHIFT

#define SEMC_STS0_NARDY_SHIFT   (1U)

Definition at line 35258 of file MIMXRT1052.h.

◆ SEMC_STS2_NDWRPEND

#define SEMC_STS2_NDWRPEND (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)

NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending

Definition at line 35274 of file MIMXRT1052.h.

◆ SEMC_STS2_NDWRPEND_MASK

#define SEMC_STS2_NDWRPEND_MASK   (0x8U)

Definition at line 35268 of file MIMXRT1052.h.

◆ SEMC_STS2_NDWRPEND_SHIFT

#define SEMC_STS2_NDWRPEND_SHIFT   (3U)

Definition at line 35269 of file MIMXRT1052.h.


picovoice_driver
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autogenerated on Fri Apr 1 2022 02:15:10