Collaboration diagram for PMU Register Masks:

MISC0 - Miscellaneous Register 0
#define	PMU_MISC0_REFTOP_PWD_MASK (0x1U)

#define	PMU_MISC0_REFTOP_PWD_SHIFT (0U)

#define	PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)

#define	PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)

#define	PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)

#define	PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)

#define	PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)

#define	PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)

#define	PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)

#define	PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)

#define	PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)

#define	PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)

#define	PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)

#define	PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)

#define	PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)

#define	PMU_MISC0_OSC_I_MASK (0x6000U)

#define	PMU_MISC0_OSC_I_SHIFT (13U)

#define	PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)

#define	PMU_MISC0_OSC_XTALOK_MASK (0x8000U)

#define	PMU_MISC0_OSC_XTALOK_SHIFT (15U)

#define	PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)

#define	PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)

#define	PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)

#define	PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)

#define	PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)

#define	PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)

#define	PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)

#define	PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)

#define	PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)

#define	PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)

#define	PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)

#define	PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)

#define	PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)

#define	PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)

#define	PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)

#define	PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)

#define	PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)

MISC0_SET - Miscellaneous Register 0
#define	PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)

#define	PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)

#define	PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)

#define	PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

#define	PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)

#define	PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)

#define	PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)

#define	PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)

#define	PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)

#define	PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)

#define	PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)

#define	PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)

#define	PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)

#define	PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)

#define	PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)

#define	PMU_MISC0_SET_OSC_I_MASK (0x6000U)

#define	PMU_MISC0_SET_OSC_I_SHIFT (13U)

#define	PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)

#define	PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)

#define	PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)

#define	PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)

#define	PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)

#define	PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)

#define	PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)

#define	PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)

#define	PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)

#define	PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)

#define	PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)

#define	PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)

#define	PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)

#define	PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)

#define	PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)

#define	PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)

#define	PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)

#define	PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)

#define	PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)

#define	PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)

MISC0_CLR - Miscellaneous Register 0
#define	PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)

#define	PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)

#define	PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)

#define	PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

#define	PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)

#define	PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)

#define	PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)

#define	PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)

#define	PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)

#define	PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)

#define	PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)

#define	PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)

#define	PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)

#define	PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)

#define	PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

#define	PMU_MISC0_CLR_OSC_I_MASK (0x6000U)

#define	PMU_MISC0_CLR_OSC_I_SHIFT (13U)

#define	PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)

#define	PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)

#define	PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)

#define	PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)

#define	PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)

#define	PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)

#define	PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)

#define	PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)

#define	PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)

#define	PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)

#define	PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)

#define	PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)

#define	PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)

#define	PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)

#define	PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

#define	PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)

#define	PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)

#define	PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)

#define	PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)

#define	PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)

MISC0_TOG - Miscellaneous Register 0
#define	PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)

#define	PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)

#define	PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)

#define	PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

#define	PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)

#define	PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)

#define	PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)

#define	PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)

#define	PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)

#define	PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)

#define	PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)

#define	PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)

#define	PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)

#define	PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)

#define	PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

#define	PMU_MISC0_TOG_OSC_I_MASK (0x6000U)

#define	PMU_MISC0_TOG_OSC_I_SHIFT (13U)

#define	PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)

#define	PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)

#define	PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)

#define	PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)

#define	PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)

#define	PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)

#define	PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)

#define	PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)

#define	PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)

#define	PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)

#define	PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)

#define	PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)

#define	PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)

#define	PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)

#define	PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

#define	PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)

#define	PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)

#define	PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)

#define	PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)

#define	PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)

MISC1 - Miscellaneous Register 1
#define	PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)

#define	PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)

#define	PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)

#define	PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)

#define	PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)

#define	PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)

#define	PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)

#define	PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)

#define	PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)

#define	PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)

#define	PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)

#define	PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)

#define	PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)

#define	PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)

#define	PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)

#define	PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)

#define	PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)

#define	PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)

#define	PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)

#define	PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)

#define	PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)

#define	PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)

#define	PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)

#define	PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)

#define	PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)

#define	PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)

#define	PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)

#define	PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)

#define	PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)

#define	PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)

#define	PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)

#define	PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)

#define	PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)

MISC1_SET - Miscellaneous Register 1
#define	PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)

#define	PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)

#define	PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)

#define	PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)

#define	PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)

#define	PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)

#define	PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)

#define	PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)

#define	PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)

#define	PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)

#define	PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)

#define	PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)

#define	PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)

#define	PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)

#define	PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)

#define	PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)

#define	PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)

#define	PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)

#define	PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)

#define	PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)

#define	PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)

#define	PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)

#define	PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)

#define	PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)

#define	PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)

#define	PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)

#define	PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)

#define	PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)

#define	PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)

#define	PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)

#define	PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)

#define	PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)

#define	PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)

MISC1_CLR - Miscellaneous Register 1
#define	PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)

#define	PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)

#define	PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)

#define	PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)

#define	PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)

#define	PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)

#define	PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)

#define	PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)

#define	PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)

#define	PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)

#define	PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)

#define	PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)

#define	PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)

#define	PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)

#define	PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)

#define	PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)

#define	PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)

#define	PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)

#define	PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)

#define	PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)

#define	PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)

#define	PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)

#define	PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)

#define	PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)

#define	PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)

#define	PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)

#define	PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)

#define	PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)

#define	PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)

#define	PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)

#define	PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)

#define	PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)

#define	PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)

MISC1_TOG - Miscellaneous Register 1
#define	PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)

#define	PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)

#define	PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)

#define	PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)

#define	PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)

#define	PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)

#define	PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)

#define	PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)

#define	PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)

#define	PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)

#define	PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)

#define	PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)

#define	PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)

#define	PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)

#define	PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)

#define	PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)

#define	PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)

#define	PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)

#define	PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)

#define	PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)

#define	PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)

#define	PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)

#define	PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)

#define	PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)

#define	PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)

#define	PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)

#define	PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)

#define	PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)

#define	PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)

#define	PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)

#define	PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)

#define	PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)

#define	PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)

REG_1P1 - Regulator 1P1 Register
#define	PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)

#define	PMU_REG_1P1_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_1P1_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)

#define	PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)

#define	PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)

#define	PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)

#define	PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)

#define	PMU_REG_1P1_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_1P1_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)

#define	PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)

#define	PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)

#define	PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)

#define	PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)

#define	PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)

#define	PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)

#define	PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)

#define	PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)

#define	PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)

#define	PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)

#define	PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)

#define	PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)

#define	PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)

REG_1P1_SET - Regulator 1P1 Register
#define	PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)

#define	PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)

#define	PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)

#define	PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)

#define	PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)

#define	PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)

#define	PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)

#define	PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)

#define	PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)

#define	PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)

#define	PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)

#define	PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)

#define	PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)

#define	PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)

#define	PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)

#define	PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)

#define	PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)

#define	PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)

#define	PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)

#define	PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)

REG_1P1_CLR - Regulator 1P1 Register
#define	PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)

#define	PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)

#define	PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)

#define	PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)

#define	PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)

#define	PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)

#define	PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)

#define	PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)

#define	PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)

#define	PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)

#define	PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)

#define	PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)

#define	PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)

#define	PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)

#define	PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)

#define	PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)

#define	PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)

#define	PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)

#define	PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)

#define	PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)

REG_1P1_TOG - Regulator 1P1 Register
#define	PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)

#define	PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)

#define	PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)

#define	PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)

#define	PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)

#define	PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)

#define	PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)

#define	PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)

#define	PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)

#define	PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)

#define	PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)

#define	PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)

#define	PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)

#define	PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)

#define	PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)

#define	PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)

#define	PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)

#define	PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)

#define	PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)

#define	PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)

REG_3P0 - Regulator 3P0 Register
#define	PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)

#define	PMU_REG_3P0_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_3P0_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)

#define	PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)

#define	PMU_REG_3P0_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_3P0_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)

#define	PMU_REG_3P0_VBUS_SEL_MASK (0x80U)

#define	PMU_REG_3P0_VBUS_SEL_SHIFT (7U)

#define	PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)

#define	PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)

#define	PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)

#define	PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)

#define	PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)

#define	PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)

#define	PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)

#define	PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)

REG_3P0_SET - Regulator 3P0 Register
#define	PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)

#define	PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)

#define	PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)

#define	PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)

#define	PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)

#define	PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)

#define	PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)

#define	PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)

#define	PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)

#define	PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)

#define	PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)

#define	PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)

#define	PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)

#define	PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)

REG_3P0_CLR - Regulator 3P0 Register
#define	PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)

#define	PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)

#define	PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)

#define	PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)

#define	PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)

#define	PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)

#define	PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)

#define	PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)

#define	PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)

#define	PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)

#define	PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)

#define	PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)

#define	PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)

#define	PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)

REG_3P0_TOG - Regulator 3P0 Register
#define	PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)

#define	PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)

#define	PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)

#define	PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)

#define	PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)

#define	PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)

#define	PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)

#define	PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)

#define	PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)

#define	PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)

#define	PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)

#define	PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)

#define	PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)

#define	PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)

REG_2P5 - Regulator 2P5 Register
#define	PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)

#define	PMU_REG_2P5_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_2P5_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)

#define	PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)

#define	PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)

#define	PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)

#define	PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)

#define	PMU_REG_2P5_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_2P5_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)

#define	PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)

#define	PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)

#define	PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)

#define	PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)

#define	PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)

#define	PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)

#define	PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)

#define	PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)

#define	PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)

#define	PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)

REG_2P5_SET - Regulator 2P5 Register
#define	PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)

#define	PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)

#define	PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)

#define	PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)

#define	PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)

#define	PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)

#define	PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)

#define	PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)

#define	PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)

#define	PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)

#define	PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)

#define	PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)

#define	PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)

#define	PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)

#define	PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)

#define	PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)

#define	PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)

REG_2P5_CLR - Regulator 2P5 Register
#define	PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)

#define	PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)

#define	PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)

#define	PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)

#define	PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)

#define	PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)

#define	PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)

#define	PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)

#define	PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)

#define	PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)

#define	PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)

#define	PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)

#define	PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)

#define	PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)

#define	PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)

#define	PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)

#define	PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)

REG_2P5_TOG - Regulator 2P5 Register
#define	PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)

#define	PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)

#define	PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)

#define	PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)

#define	PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)

#define	PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)

#define	PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)

#define	PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)

#define	PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)

#define	PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)

#define	PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)

#define	PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)

#define	PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)

#define	PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)

#define	PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)

#define	PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)

#define	PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)

#define	PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)

#define	PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)

#define	PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)

#define	PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)

#define	PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)

#define	PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)

#define	PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)

#define	PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)

#define	PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)

#define	PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)

REG_CORE - Digital Regulator Core Register
#define	PMU_REG_CORE_REG0_TARG_MASK (0x1FU)

#define	PMU_REG_CORE_REG0_TARG_SHIFT (0U)

#define	PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)

#define	PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)

#define	PMU_REG_CORE_REG0_ADJ_SHIFT (5U)

#define	PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)

#define	PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)

#define	PMU_REG_CORE_REG1_TARG_SHIFT (9U)

#define	PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)

#define	PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)

#define	PMU_REG_CORE_REG1_ADJ_SHIFT (14U)

#define	PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)

#define	PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)

#define	PMU_REG_CORE_REG2_TARG_SHIFT (18U)

#define	PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)

#define	PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)

#define	PMU_REG_CORE_REG2_ADJ_SHIFT (23U)

#define	PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)

#define	PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)

#define	PMU_REG_CORE_RAMP_RATE_SHIFT (27U)

#define	PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)

#define	PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)

#define	PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)

#define	PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)

REG_CORE_SET - Digital Regulator Core Register
#define	PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)

#define	PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)

#define	PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)

#define	PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)

#define	PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)

#define	PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)

#define	PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)

#define	PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)

#define	PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)

#define	PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)

#define	PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)

#define	PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)

#define	PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)

#define	PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)

#define	PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)

#define	PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)

#define	PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)

#define	PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)

#define	PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)

#define	PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)

#define	PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)

#define	PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)

#define	PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)

#define	PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)

REG_CORE_CLR - Digital Regulator Core Register
#define	PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)

#define	PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)

#define	PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)

#define	PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)

#define	PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)

#define	PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)

#define	PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)

#define	PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)

#define	PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)

#define	PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)

#define	PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)

#define	PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)

#define	PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)

#define	PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)

#define	PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)

#define	PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)

#define	PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)

#define	PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)

#define	PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)

#define	PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)

#define	PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)

#define	PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)

#define	PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)

#define	PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)

REG_CORE_TOG - Digital Regulator Core Register
#define	PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)

#define	PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)

#define	PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)

#define	PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)

#define	PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)

#define	PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)

#define	PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)

#define	PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)

#define	PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)

#define	PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)

#define	PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)

#define	PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)

#define	PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)

#define	PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)

#define	PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)

#define	PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)

#define	PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)

#define	PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)

#define	PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)

#define	PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)

#define	PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)

#define	PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)

#define	PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)

#define	PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)

MISC2 - Miscellaneous Control Register
#define	PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)

#define	PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)

#define	PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)

#define	PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)

#define	PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)

#define	PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)

#define	PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)

#define	PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)

#define	PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)

#define	PMU_MISC2_PLL3_disable_MASK (0x80U)

#define	PMU_MISC2_PLL3_disable_SHIFT (7U)

#define	PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)

#define	PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)

#define	PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)

#define	PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)

#define	PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)

#define	PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)

#define	PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)

#define	PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)

#define	PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)

#define	PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)

#define	PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)

#define	PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)

#define	PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)

#define	PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)

#define	PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)

#define	PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)

#define	PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)

#define	PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)

#define	PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)

#define	PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)

#define	PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)

#define	PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)

#define	PMU_MISC2_REG2_OK_MASK (0x400000U)

#define	PMU_MISC2_REG2_OK_SHIFT (22U)

#define	PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)

#define	PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)

#define	PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)

#define	PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)

#define	PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)

#define	PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)

#define	PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)

#define	PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)

#define	PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)

#define	PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)

#define	PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)

#define	PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)

#define	PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)

#define	PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)

#define	PMU_MISC2_VIDEO_DIV_SHIFT (30U)

#define	PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)

MISC2_SET - Miscellaneous Control Register
#define	PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)

#define	PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)

#define	PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)

#define	PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)

#define	PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)

#define	PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)

#define	PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)

#define	PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)

#define	PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)

#define	PMU_MISC2_SET_PLL3_disable_MASK (0x80U)

#define	PMU_MISC2_SET_PLL3_disable_SHIFT (7U)

#define	PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)

#define	PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)

#define	PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)

#define	PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)

#define	PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)

#define	PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)

#define	PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)

#define	PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)

#define	PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)

#define	PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)

#define	PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)

#define	PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)

#define	PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)

#define	PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)

#define	PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)

#define	PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)

#define	PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)

#define	PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)

#define	PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)

#define	PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)

#define	PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)

#define	PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)

#define	PMU_MISC2_SET_REG2_OK_MASK (0x400000U)

#define	PMU_MISC2_SET_REG2_OK_SHIFT (22U)

#define	PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)

#define	PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)

#define	PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)

#define	PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)

#define	PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)

#define	PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)

#define	PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)

#define	PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)

#define	PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)

#define	PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)

#define	PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)

#define	PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)

#define	PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)

#define	PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)

#define	PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)

#define	PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)

MISC2_CLR - Miscellaneous Control Register
#define	PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)

#define	PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)

#define	PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)

#define	PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)

#define	PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)

#define	PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)

#define	PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)

#define	PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)

#define	PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)

#define	PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)

#define	PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)

#define	PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)

#define	PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)

#define	PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)

#define	PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)

#define	PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)

#define	PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)

#define	PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)

#define	PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)

#define	PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)

#define	PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)

#define	PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)

#define	PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)

#define	PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)

#define	PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)

#define	PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)

#define	PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)

#define	PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)

#define	PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)

#define	PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)

#define	PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)

#define	PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)

#define	PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)

#define	PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)

#define	PMU_MISC2_CLR_REG2_OK_SHIFT (22U)

#define	PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)

#define	PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)

#define	PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)

#define	PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)

#define	PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)

#define	PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)

#define	PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)

#define	PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)

#define	PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)

#define	PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)

#define	PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)

#define	PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)

#define	PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)

#define	PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)

#define	PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)

#define	PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)

MISC2_TOG - Miscellaneous Control Register
#define	PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)

#define	PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)

#define	PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)

#define	PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)

#define	PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)

#define	PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)

#define	PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)

#define	PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)

#define	PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)

#define	PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)

#define	PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)

#define	PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)

#define	PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)

#define	PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)

#define	PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)

#define	PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)

#define	PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)

#define	PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)

#define	PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)

#define	PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)

#define	PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)

#define	PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)

#define	PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)

#define	PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)

#define	PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)

#define	PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)

#define	PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)

#define	PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)

#define	PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)

#define	PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)

#define	PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)

#define	PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)

#define	PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)

#define	PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)

#define	PMU_MISC2_TOG_REG2_OK_SHIFT (22U)

#define	PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)

#define	PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)

#define	PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)

#define	PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)

#define	PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)

#define	PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)

#define	PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)

#define	PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)

#define	PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)

#define	PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)

#define	PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)

#define	PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)

#define	PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)

#define	PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)

#define	PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)

#define	PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)

Detailed Description

Macro Definition Documentation

◆ PMU_MISC0_CLKGATE_CTRL

#define PMU_MISC0_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

Definition at line 29729 of file MIMXRT1052.h.

◆ PMU_MISC0_CLKGATE_CTRL_MASK

#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)

Definition at line 29723 of file MIMXRT1052.h.

◆ PMU_MISC0_CLKGATE_CTRL_SHIFT

#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)

Definition at line 29724 of file MIMXRT1052.h.

◆ PMU_MISC0_CLKGATE_DELAY

#define PMU_MISC0_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

Definition at line 29742 of file MIMXRT1052.h.

◆ PMU_MISC0_CLKGATE_DELAY_MASK

#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)

Definition at line 29730 of file MIMXRT1052.h.

◆ PMU_MISC0_CLKGATE_DELAY_SHIFT

#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)

Definition at line 29731 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_CLKGATE_CTRL

#define PMU_MISC0_CLR_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

Definition at line 29925 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_CLKGATE_CTRL_MASK

#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)

Definition at line 29919 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT

#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)

Definition at line 29920 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_CLKGATE_DELAY

#define PMU_MISC0_CLR_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

Definition at line 29938 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_CLKGATE_DELAY_MASK

#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)

Definition at line 29926 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT

#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)

Definition at line 29927 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS

#define PMU_MISC0_CLR_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

Definition at line 29903 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK

#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)

Definition at line 29897 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT

#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)

Definition at line 29898 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_I

#define PMU_MISC0_CLR_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

Definition at line 29912 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_I_MASK

#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)

Definition at line 29904 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_I_SHIFT

#define PMU_MISC0_CLR_OSC_I_SHIFT (13U)

Definition at line 29905 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_XTALOK

#define PMU_MISC0_CLR_OSC_XTALOK ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)

Definition at line 29915 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_XTALOK_EN

#define PMU_MISC0_CLR_OSC_XTALOK_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)

Definition at line 29918 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_XTALOK_EN_MASK

#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)

Definition at line 29916 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT

#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)

Definition at line 29917 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_XTALOK_MASK

#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)

Definition at line 29913 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_OSC_XTALOK_SHIFT

#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)

Definition at line 29914 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_PWD

#define PMU_MISC0_CLR_REFTOP_PWD ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)

Definition at line 29864 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_PWD_MASK

#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)

Definition at line 29862 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_PWD_SHIFT

#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)

Definition at line 29863 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF

#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

Definition at line 29871 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK

#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)

Definition at line 29865 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT

#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)

Definition at line 29866 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_VBGADJ

#define PMU_MISC0_CLR_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

Definition at line 29884 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_VBGADJ_MASK

#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)

Definition at line 29872 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT

#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)

Definition at line 29873 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_VBGUP

#define PMU_MISC0_CLR_REFTOP_VBGUP ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)

Definition at line 29887 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_VBGUP_MASK

#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)

Definition at line 29885 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT

#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)

Definition at line 29886 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE

#define PMU_MISC0_CLR_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

Definition at line 29945 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK

#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)

Definition at line 29939 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT

#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)

Definition at line 29940 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_STOP_MODE_CONFIG

#define PMU_MISC0_CLR_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

Definition at line 29896 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK

#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)

Definition at line 29888 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT

#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)

Definition at line 29889 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_VID_PLL_PREDIV

#define PMU_MISC0_CLR_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

Definition at line 29955 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_VID_PLL_PREDIV_MASK

#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)

Definition at line 29949 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT

#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)

Definition at line 29950 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_XTAL_24M_PWD

#define PMU_MISC0_CLR_XTAL_24M_PWD ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)

Definition at line 29948 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_XTAL_24M_PWD_MASK

#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)

Definition at line 29946 of file MIMXRT1052.h.

◆ PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT

#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)

Definition at line 29947 of file MIMXRT1052.h.

◆ PMU_MISC0_DISCON_HIGH_SNVS

#define PMU_MISC0_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

Definition at line 29707 of file MIMXRT1052.h.

◆ PMU_MISC0_DISCON_HIGH_SNVS_MASK

#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)

Definition at line 29701 of file MIMXRT1052.h.

◆ PMU_MISC0_DISCON_HIGH_SNVS_SHIFT

#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)

Definition at line 29702 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_I

#define PMU_MISC0_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

Definition at line 29716 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_I_MASK

#define PMU_MISC0_OSC_I_MASK (0x6000U)

Definition at line 29708 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_I_SHIFT

#define PMU_MISC0_OSC_I_SHIFT (13U)

Definition at line 29709 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_XTALOK

#define PMU_MISC0_OSC_XTALOK ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)

Definition at line 29719 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_XTALOK_EN

#define PMU_MISC0_OSC_XTALOK_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)

Definition at line 29722 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_XTALOK_EN_MASK

#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)

Definition at line 29720 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_XTALOK_EN_SHIFT

#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)

Definition at line 29721 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_XTALOK_MASK

#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)

Definition at line 29717 of file MIMXRT1052.h.

◆ PMU_MISC0_OSC_XTALOK_SHIFT

#define PMU_MISC0_OSC_XTALOK_SHIFT (15U)

Definition at line 29718 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_PWD

#define PMU_MISC0_REFTOP_PWD ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)

Definition at line 29668 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_PWD_MASK

#define PMU_MISC0_REFTOP_PWD_MASK (0x1U)

Definition at line 29666 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_PWD_SHIFT

#define PMU_MISC0_REFTOP_PWD_SHIFT (0U)

Definition at line 29667 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_SELFBIASOFF

#define PMU_MISC0_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

Definition at line 29675 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_SELFBIASOFF_MASK

#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)

Definition at line 29669 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT

#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)

Definition at line 29670 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_VBGADJ

#define PMU_MISC0_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

Definition at line 29688 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_VBGADJ_MASK

#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)

Definition at line 29676 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_VBGADJ_SHIFT

#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)

Definition at line 29677 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_VBGUP

#define PMU_MISC0_REFTOP_VBGUP ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)

Definition at line 29691 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_VBGUP_MASK

#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)

Definition at line 29689 of file MIMXRT1052.h.

◆ PMU_MISC0_REFTOP_VBGUP_SHIFT

#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)

Definition at line 29690 of file MIMXRT1052.h.

◆ PMU_MISC0_RTC_XTAL_SOURCE

#define PMU_MISC0_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

Definition at line 29749 of file MIMXRT1052.h.

◆ PMU_MISC0_RTC_XTAL_SOURCE_MASK

#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)

Definition at line 29743 of file MIMXRT1052.h.

◆ PMU_MISC0_RTC_XTAL_SOURCE_SHIFT

#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)

Definition at line 29744 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_CLKGATE_CTRL

#define PMU_MISC0_SET_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

Definition at line 29827 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_CLKGATE_CTRL_MASK

#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)

Definition at line 29821 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_CLKGATE_CTRL_SHIFT

#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)

Definition at line 29822 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_CLKGATE_DELAY

#define PMU_MISC0_SET_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

Definition at line 29840 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_CLKGATE_DELAY_MASK

#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)

Definition at line 29828 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_CLKGATE_DELAY_SHIFT

#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)

Definition at line 29829 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_DISCON_HIGH_SNVS

#define PMU_MISC0_SET_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

Definition at line 29805 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK

#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)

Definition at line 29799 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT

#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)

Definition at line 29800 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_I

#define PMU_MISC0_SET_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

Definition at line 29814 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_I_MASK

#define PMU_MISC0_SET_OSC_I_MASK (0x6000U)

Definition at line 29806 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_I_SHIFT

#define PMU_MISC0_SET_OSC_I_SHIFT (13U)

Definition at line 29807 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_XTALOK

#define PMU_MISC0_SET_OSC_XTALOK ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)

Definition at line 29817 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_XTALOK_EN

#define PMU_MISC0_SET_OSC_XTALOK_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)

Definition at line 29820 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_XTALOK_EN_MASK

#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)

Definition at line 29818 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT

#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)

Definition at line 29819 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_XTALOK_MASK

#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)

Definition at line 29815 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_OSC_XTALOK_SHIFT

#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)

Definition at line 29816 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_PWD

#define PMU_MISC0_SET_REFTOP_PWD ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)

Definition at line 29766 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_PWD_MASK

#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)

Definition at line 29764 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_PWD_SHIFT

#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)

Definition at line 29765 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_SELFBIASOFF

#define PMU_MISC0_SET_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

Definition at line 29773 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK

#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)

Definition at line 29767 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT

#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)

Definition at line 29768 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_VBGADJ

#define PMU_MISC0_SET_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

Definition at line 29786 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_VBGADJ_MASK

#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)

Definition at line 29774 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT

#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)

Definition at line 29775 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_VBGUP

#define PMU_MISC0_SET_REFTOP_VBGUP ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)

Definition at line 29789 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_VBGUP_MASK

#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)

Definition at line 29787 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_REFTOP_VBGUP_SHIFT

#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)

Definition at line 29788 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_RTC_XTAL_SOURCE

#define PMU_MISC0_SET_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

Definition at line 29847 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK

#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)

Definition at line 29841 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT

#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)

Definition at line 29842 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_STOP_MODE_CONFIG

#define PMU_MISC0_SET_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

Definition at line 29798 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_STOP_MODE_CONFIG_MASK

#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)

Definition at line 29790 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT

#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)

Definition at line 29791 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_VID_PLL_PREDIV

#define PMU_MISC0_SET_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

Definition at line 29857 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_VID_PLL_PREDIV_MASK

#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)

Definition at line 29851 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT

#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)

Definition at line 29852 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_XTAL_24M_PWD

#define PMU_MISC0_SET_XTAL_24M_PWD ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)

Definition at line 29850 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_XTAL_24M_PWD_MASK

#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)

Definition at line 29848 of file MIMXRT1052.h.

◆ PMU_MISC0_SET_XTAL_24M_PWD_SHIFT

#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)

Definition at line 29849 of file MIMXRT1052.h.

◆ PMU_MISC0_STOP_MODE_CONFIG

#define PMU_MISC0_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

Definition at line 29700 of file MIMXRT1052.h.

◆ PMU_MISC0_STOP_MODE_CONFIG_MASK

#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)

Definition at line 29692 of file MIMXRT1052.h.

◆ PMU_MISC0_STOP_MODE_CONFIG_SHIFT

#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)

Definition at line 29693 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_CLKGATE_CTRL

#define PMU_MISC0_TOG_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

Definition at line 30023 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_CLKGATE_CTRL_MASK

#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)

Definition at line 30017 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT

#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)

Definition at line 30018 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_CLKGATE_DELAY

#define PMU_MISC0_TOG_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

Definition at line 30036 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_CLKGATE_DELAY_MASK

#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)

Definition at line 30024 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT

#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)

Definition at line 30025 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_DISCON_HIGH_SNVS

#define PMU_MISC0_TOG_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

Definition at line 30001 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK

#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)

Definition at line 29995 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT

#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)

Definition at line 29996 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_I

#define PMU_MISC0_TOG_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

Definition at line 30010 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_I_MASK

#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)

Definition at line 30002 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_I_SHIFT

#define PMU_MISC0_TOG_OSC_I_SHIFT (13U)

Definition at line 30003 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_XTALOK

#define PMU_MISC0_TOG_OSC_XTALOK ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)

Definition at line 30013 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_XTALOK_EN

#define PMU_MISC0_TOG_OSC_XTALOK_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)

Definition at line 30016 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_XTALOK_EN_MASK

#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)

Definition at line 30014 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT

#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)

Definition at line 30015 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_XTALOK_MASK

#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)

Definition at line 30011 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_OSC_XTALOK_SHIFT

#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)

Definition at line 30012 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_PWD

#define PMU_MISC0_TOG_REFTOP_PWD ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)

Definition at line 29962 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_PWD_MASK

#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)

Definition at line 29960 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_PWD_SHIFT

#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)

Definition at line 29961 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_SELFBIASOFF

#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

Definition at line 29969 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK

#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)

Definition at line 29963 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT

#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)

Definition at line 29964 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_VBGADJ

#define PMU_MISC0_TOG_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

Definition at line 29982 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_VBGADJ_MASK

#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)

Definition at line 29970 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT

#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)

Definition at line 29971 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_VBGUP

#define PMU_MISC0_TOG_REFTOP_VBGUP ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)

Definition at line 29985 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_VBGUP_MASK

#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)

Definition at line 29983 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT

#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)

Definition at line 29984 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_RTC_XTAL_SOURCE

#define PMU_MISC0_TOG_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

Definition at line 30043 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK

#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)

Definition at line 30037 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT

#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)

Definition at line 30038 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_STOP_MODE_CONFIG

#define PMU_MISC0_TOG_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

Definition at line 29994 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK

#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)

Definition at line 29986 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT

#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)

Definition at line 29987 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_VID_PLL_PREDIV

#define PMU_MISC0_TOG_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

Definition at line 30053 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_VID_PLL_PREDIV_MASK

#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)

Definition at line 30047 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT

#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)

Definition at line 30048 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_XTAL_24M_PWD

#define PMU_MISC0_TOG_XTAL_24M_PWD ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)

Definition at line 30046 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_XTAL_24M_PWD_MASK

#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)

Definition at line 30044 of file MIMXRT1052.h.

◆ PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT

#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)

Definition at line 30045 of file MIMXRT1052.h.

◆ PMU_MISC0_VID_PLL_PREDIV

#define PMU_MISC0_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

Definition at line 29759 of file MIMXRT1052.h.

◆ PMU_MISC0_VID_PLL_PREDIV_MASK

#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)

Definition at line 29753 of file MIMXRT1052.h.

◆ PMU_MISC0_VID_PLL_PREDIV_SHIFT

#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)

Definition at line 29754 of file MIMXRT1052.h.

◆ PMU_MISC0_XTAL_24M_PWD

#define PMU_MISC0_XTAL_24M_PWD ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)

Definition at line 29752 of file MIMXRT1052.h.

◆ PMU_MISC0_XTAL_24M_PWD_MASK

#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)

Definition at line 29750 of file MIMXRT1052.h.

◆ PMU_MISC0_XTAL_24M_PWD_SHIFT

#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)

Definition at line 29751 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_ANA_BO

#define PMU_MISC1_CLR_IRQ_ANA_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)

Definition at line 30302 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_ANA_BO_MASK

#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)

Definition at line 30300 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT

#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)

Definition at line 30301 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_DIG_BO

#define PMU_MISC1_CLR_IRQ_DIG_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)

Definition at line 30305 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_DIG_BO_MASK

#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)

Definition at line 30303 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT

#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)

Definition at line 30304 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPHIGH

#define PMU_MISC1_CLR_IRQ_TEMPHIGH ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)

Definition at line 30299 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK

#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)

Definition at line 30297 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT

#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)

Definition at line 30298 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPLOW

#define PMU_MISC1_CLR_IRQ_TEMPLOW ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)

Definition at line 30296 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPLOW_MASK

#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)

Definition at line 30294 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT

#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)

Definition at line 30295 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPPANIC

#define PMU_MISC1_CLR_IRQ_TEMPPANIC ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)

Definition at line 30293 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK

#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)

Definition at line 30291 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT

#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)

Definition at line 30292 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDS1_CLK_SEL

#define PMU_MISC1_CLR_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

Definition at line 30246 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK

#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)

Definition at line 30226 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT

#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)

Definition at line 30227 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDS2_CLK_SEL

#define PMU_MISC1_CLR_LVDS2_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

Definition at line 30272 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK

#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)

Definition at line 30247 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT

#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)

Definition at line 30248 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK1_IBEN

#define PMU_MISC1_CLR_LVDSCLK1_IBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)

Definition at line 30281 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK

#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)

Definition at line 30279 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT

#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)

Definition at line 30280 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK1_OBEN

#define PMU_MISC1_CLR_LVDSCLK1_OBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)

Definition at line 30275 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK

#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)

Definition at line 30273 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT

#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)

Definition at line 30274 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK2_IBEN

#define PMU_MISC1_CLR_LVDSCLK2_IBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)

Definition at line 30284 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK

#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)

Definition at line 30282 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT

#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)

Definition at line 30283 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK2_OBEN

#define PMU_MISC1_CLR_LVDSCLK2_OBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)

Definition at line 30278 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK

#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)

Definition at line 30276 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT

#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)

Definition at line 30277 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_PFD_480_AUTOGATE_EN

#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)

Definition at line 30287 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK

#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)

Definition at line 30285 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT

#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)

Definition at line 30286 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_PFD_528_AUTOGATE_EN

#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)

Definition at line 30290 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK

#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)

Definition at line 30288 of file MIMXRT1052.h.

◆ PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT

#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)

Definition at line 30289 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_ANA_BO

#define PMU_MISC1_IRQ_ANA_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)

Definition at line 30134 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_ANA_BO_MASK

#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)

Definition at line 30132 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_ANA_BO_SHIFT

#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)

Definition at line 30133 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_DIG_BO

#define PMU_MISC1_IRQ_DIG_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)

Definition at line 30137 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_DIG_BO_MASK

#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)

Definition at line 30135 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_DIG_BO_SHIFT

#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)

Definition at line 30136 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPHIGH

#define PMU_MISC1_IRQ_TEMPHIGH ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)

Definition at line 30131 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPHIGH_MASK

#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)

Definition at line 30129 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPHIGH_SHIFT

#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)

Definition at line 30130 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPLOW

#define PMU_MISC1_IRQ_TEMPLOW ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)

Definition at line 30128 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPLOW_MASK

#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)

Definition at line 30126 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPLOW_SHIFT

#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)

Definition at line 30127 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPPANIC

#define PMU_MISC1_IRQ_TEMPPANIC ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)

Definition at line 30125 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPPANIC_MASK

#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)

Definition at line 30123 of file MIMXRT1052.h.

◆ PMU_MISC1_IRQ_TEMPPANIC_SHIFT

#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)

Definition at line 30124 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDS1_CLK_SEL

#define PMU_MISC1_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

Definition at line 30078 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDS1_CLK_SEL_MASK

#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)

Definition at line 30058 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDS1_CLK_SEL_SHIFT

#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)

Definition at line 30059 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDS2_CLK_SEL

#define PMU_MISC1_LVDS2_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

Definition at line 30104 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDS2_CLK_SEL_MASK

#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)

Definition at line 30079 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDS2_CLK_SEL_SHIFT

#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)

Definition at line 30080 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK1_IBEN

#define PMU_MISC1_LVDSCLK1_IBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)

Definition at line 30113 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK1_IBEN_MASK

#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)

Definition at line 30111 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK1_IBEN_SHIFT

#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)

Definition at line 30112 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK1_OBEN

#define PMU_MISC1_LVDSCLK1_OBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)

Definition at line 30107 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK1_OBEN_MASK

#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)

Definition at line 30105 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK1_OBEN_SHIFT

#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)

Definition at line 30106 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK2_IBEN

#define PMU_MISC1_LVDSCLK2_IBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)

Definition at line 30116 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK2_IBEN_MASK

#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)

Definition at line 30114 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK2_IBEN_SHIFT

#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)

Definition at line 30115 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK2_OBEN

#define PMU_MISC1_LVDSCLK2_OBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)

Definition at line 30110 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK2_OBEN_MASK

#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)

Definition at line 30108 of file MIMXRT1052.h.

◆ PMU_MISC1_LVDSCLK2_OBEN_SHIFT

#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)

Definition at line 30109 of file MIMXRT1052.h.

◆ PMU_MISC1_PFD_480_AUTOGATE_EN

#define PMU_MISC1_PFD_480_AUTOGATE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)

Definition at line 30119 of file MIMXRT1052.h.

◆ PMU_MISC1_PFD_480_AUTOGATE_EN_MASK

#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)

Definition at line 30117 of file MIMXRT1052.h.

◆ PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT

#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)

Definition at line 30118 of file MIMXRT1052.h.

◆ PMU_MISC1_PFD_528_AUTOGATE_EN

#define PMU_MISC1_PFD_528_AUTOGATE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)

Definition at line 30122 of file MIMXRT1052.h.

◆ PMU_MISC1_PFD_528_AUTOGATE_EN_MASK

#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)

Definition at line 30120 of file MIMXRT1052.h.

◆ PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT

#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)

Definition at line 30121 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_ANA_BO

#define PMU_MISC1_SET_IRQ_ANA_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)

Definition at line 30218 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_ANA_BO_MASK

#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)

Definition at line 30216 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_ANA_BO_SHIFT

#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)

Definition at line 30217 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_DIG_BO

#define PMU_MISC1_SET_IRQ_DIG_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)

Definition at line 30221 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_DIG_BO_MASK

#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)

Definition at line 30219 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_DIG_BO_SHIFT

#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)

Definition at line 30220 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPHIGH

#define PMU_MISC1_SET_IRQ_TEMPHIGH ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)

Definition at line 30215 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPHIGH_MASK

#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)

Definition at line 30213 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT

#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)

Definition at line 30214 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPLOW

#define PMU_MISC1_SET_IRQ_TEMPLOW ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)

Definition at line 30212 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPLOW_MASK

#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)

Definition at line 30210 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT

#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)

Definition at line 30211 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPPANIC

#define PMU_MISC1_SET_IRQ_TEMPPANIC ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)

Definition at line 30209 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPPANIC_MASK

#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)

Definition at line 30207 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT

#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)

Definition at line 30208 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDS1_CLK_SEL

#define PMU_MISC1_SET_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

Definition at line 30162 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDS1_CLK_SEL_MASK

#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)

Definition at line 30142 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT

#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)

Definition at line 30143 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDS2_CLK_SEL

#define PMU_MISC1_SET_LVDS2_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

Definition at line 30188 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDS2_CLK_SEL_MASK

#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)

Definition at line 30163 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT

#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)

Definition at line 30164 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK1_IBEN

#define PMU_MISC1_SET_LVDSCLK1_IBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)

Definition at line 30197 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK1_IBEN_MASK

#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)

Definition at line 30195 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT

#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)

Definition at line 30196 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK1_OBEN

#define PMU_MISC1_SET_LVDSCLK1_OBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)

Definition at line 30191 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK1_OBEN_MASK

#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)

Definition at line 30189 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT

#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)

Definition at line 30190 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK2_IBEN

#define PMU_MISC1_SET_LVDSCLK2_IBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)

Definition at line 30200 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK2_IBEN_MASK

#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)

Definition at line 30198 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT

#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)

Definition at line 30199 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK2_OBEN

#define PMU_MISC1_SET_LVDSCLK2_OBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)

Definition at line 30194 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK2_OBEN_MASK

#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)

Definition at line 30192 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT

#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)

Definition at line 30193 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_PFD_480_AUTOGATE_EN

#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)

Definition at line 30203 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK

#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)

Definition at line 30201 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT

#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)

Definition at line 30202 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_PFD_528_AUTOGATE_EN

#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)

Definition at line 30206 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK

#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)

Definition at line 30204 of file MIMXRT1052.h.

◆ PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT

#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)

Definition at line 30205 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_ANA_BO

#define PMU_MISC1_TOG_IRQ_ANA_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)

Definition at line 30386 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_ANA_BO_MASK

#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)

Definition at line 30384 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT

#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)

Definition at line 30385 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_DIG_BO

#define PMU_MISC1_TOG_IRQ_DIG_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)

Definition at line 30389 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_DIG_BO_MASK

#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)

Definition at line 30387 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT

#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)

Definition at line 30388 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPHIGH

#define PMU_MISC1_TOG_IRQ_TEMPHIGH ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)

Definition at line 30383 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK

#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)

Definition at line 30381 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT

#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)

Definition at line 30382 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPLOW

#define PMU_MISC1_TOG_IRQ_TEMPLOW ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)

Definition at line 30380 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPLOW_MASK

#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)

Definition at line 30378 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT

#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)

Definition at line 30379 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPPANIC

#define PMU_MISC1_TOG_IRQ_TEMPPANIC ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)

Definition at line 30377 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK

#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)

Definition at line 30375 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT

#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)

Definition at line 30376 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDS1_CLK_SEL

#define PMU_MISC1_TOG_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

Definition at line 30330 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK

#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)

Definition at line 30310 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT

#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)

Definition at line 30311 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDS2_CLK_SEL

#define PMU_MISC1_TOG_LVDS2_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

Definition at line 30356 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK

#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)

Definition at line 30331 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT

#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)

Definition at line 30332 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK1_IBEN

#define PMU_MISC1_TOG_LVDSCLK1_IBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)

Definition at line 30365 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK

#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)

Definition at line 30363 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT

#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)

Definition at line 30364 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK1_OBEN

#define PMU_MISC1_TOG_LVDSCLK1_OBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)

Definition at line 30359 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK

#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)

Definition at line 30357 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT

#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)

Definition at line 30358 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK2_IBEN

#define PMU_MISC1_TOG_LVDSCLK2_IBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)

Definition at line 30368 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK

#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)

Definition at line 30366 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT

#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)

Definition at line 30367 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK2_OBEN

#define PMU_MISC1_TOG_LVDSCLK2_OBEN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)

Definition at line 30362 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK

#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)

Definition at line 30360 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT

#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)

Definition at line 30361 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_PFD_480_AUTOGATE_EN

#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)

Definition at line 30371 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK

#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)

Definition at line 30369 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT

#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)

Definition at line 30370 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_PFD_528_AUTOGATE_EN

#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)

Definition at line 30374 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK

#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)

Definition at line 30372 of file MIMXRT1052.h.

◆ PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT

#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)

Definition at line 30373 of file MIMXRT1052.h.

◆ PMU_MISC2_AUDIO_DIV_LSB

#define PMU_MISC2_AUDIO_DIV_LSB ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 30435 of file MIMXRT1052.h.

◆ PMU_MISC2_AUDIO_DIV_LSB_MASK

#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)

Definition at line 30429 of file MIMXRT1052.h.

◆ PMU_MISC2_AUDIO_DIV_LSB_SHIFT

#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)

Definition at line 30430 of file MIMXRT1052.h.

◆ PMU_MISC2_AUDIO_DIV_MSB

#define PMU_MISC2_AUDIO_DIV_MSB ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 30458 of file MIMXRT1052.h.

◆ PMU_MISC2_AUDIO_DIV_MSB_MASK

#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)

Definition at line 30452 of file MIMXRT1052.h.

◆ PMU_MISC2_AUDIO_DIV_MSB_SHIFT

#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)

Definition at line 30453 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_AUDIO_DIV_LSB

#define PMU_MISC2_CLR_AUDIO_DIV_LSB ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 30645 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK

#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)

Definition at line 30639 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT

#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)

Definition at line 30640 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_AUDIO_DIV_MSB

#define PMU_MISC2_CLR_AUDIO_DIV_MSB ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 30668 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK

#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)

Definition at line 30662 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT

#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)

Definition at line 30663 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_PLL3_disable

#define PMU_MISC2_CLR_PLL3_disable ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)

Definition at line 30622 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_PLL3_disable_MASK

#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)

Definition at line 30620 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_PLL3_disable_SHIFT

#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)

Definition at line 30621 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_BO_OFFSET

#define PMU_MISC2_CLR_REG0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30610 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_BO_OFFSET_MASK

#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)

Definition at line 30604 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT

#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)

Definition at line 30605 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_BO_STATUS

#define PMU_MISC2_CLR_REG0_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 30616 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_BO_STATUS_MASK

#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)

Definition at line 30611 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT

#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)

Definition at line 30612 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_ENABLE_BO

#define PMU_MISC2_CLR_REG0_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)

Definition at line 30619 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_ENABLE_BO_MASK

#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)

Definition at line 30617 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT

#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)

Definition at line 30618 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_STEP_TIME

#define PMU_MISC2_CLR_REG0_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30677 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_STEP_TIME_MASK

#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)

Definition at line 30669 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT

#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)

Definition at line 30670 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_BO_OFFSET

#define PMU_MISC2_CLR_REG1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30629 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_BO_OFFSET_MASK

#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)

Definition at line 30623 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT

#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)

Definition at line 30624 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_BO_STATUS

#define PMU_MISC2_CLR_REG1_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 30635 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_BO_STATUS_MASK

#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)

Definition at line 30630 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT

#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)

Definition at line 30631 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_ENABLE_BO

#define PMU_MISC2_CLR_REG1_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)

Definition at line 30638 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_ENABLE_BO_MASK

#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)

Definition at line 30636 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT

#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)

Definition at line 30637 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_STEP_TIME

#define PMU_MISC2_CLR_REG1_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30686 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_STEP_TIME_MASK

#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)

Definition at line 30678 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT

#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)

Definition at line 30679 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_BO_OFFSET

#define PMU_MISC2_CLR_REG2_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30652 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_BO_OFFSET_MASK

#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)

Definition at line 30646 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT

#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)

Definition at line 30647 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_BO_STATUS

#define PMU_MISC2_CLR_REG2_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)

Definition at line 30655 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_BO_STATUS_MASK

#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)

Definition at line 30653 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT

#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)

Definition at line 30654 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_ENABLE_BO

#define PMU_MISC2_CLR_REG2_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)

Definition at line 30658 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_ENABLE_BO_MASK

#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)

Definition at line 30656 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT

#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)

Definition at line 30657 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_OK

#define PMU_MISC2_CLR_REG2_OK ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)

Definition at line 30661 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_OK_MASK

#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)

Definition at line 30659 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_OK_SHIFT

#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)

Definition at line 30660 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_STEP_TIME

#define PMU_MISC2_CLR_REG2_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30695 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_STEP_TIME_MASK

#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)

Definition at line 30687 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT

#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)

Definition at line 30688 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_VIDEO_DIV

#define PMU_MISC2_CLR_VIDEO_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

Definition at line 30704 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_VIDEO_DIV_MASK

#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)

Definition at line 30696 of file MIMXRT1052.h.

◆ PMU_MISC2_CLR_VIDEO_DIV_SHIFT

#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)

Definition at line 30697 of file MIMXRT1052.h.

◆ PMU_MISC2_PLL3_disable

#define PMU_MISC2_PLL3_disable ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)

Definition at line 30412 of file MIMXRT1052.h.

◆ PMU_MISC2_PLL3_disable_MASK

#define PMU_MISC2_PLL3_disable_MASK (0x80U)

Definition at line 30410 of file MIMXRT1052.h.

◆ PMU_MISC2_PLL3_disable_SHIFT

#define PMU_MISC2_PLL3_disable_SHIFT (7U)

Definition at line 30411 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_BO_OFFSET

#define PMU_MISC2_REG0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30400 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_BO_OFFSET_MASK

#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)

Definition at line 30394 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_BO_OFFSET_SHIFT

#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)

Definition at line 30395 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_BO_STATUS

#define PMU_MISC2_REG0_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 30406 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_BO_STATUS_MASK

#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)

Definition at line 30401 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_BO_STATUS_SHIFT

#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)

Definition at line 30402 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_ENABLE_BO

#define PMU_MISC2_REG0_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)

Definition at line 30409 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_ENABLE_BO_MASK

#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)

Definition at line 30407 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_ENABLE_BO_SHIFT

#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)

Definition at line 30408 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_STEP_TIME

#define PMU_MISC2_REG0_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30467 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_STEP_TIME_MASK

#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)

Definition at line 30459 of file MIMXRT1052.h.

◆ PMU_MISC2_REG0_STEP_TIME_SHIFT

#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)

Definition at line 30460 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_BO_OFFSET

#define PMU_MISC2_REG1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30419 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_BO_OFFSET_MASK

#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)

Definition at line 30413 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_BO_OFFSET_SHIFT

#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)

Definition at line 30414 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_BO_STATUS

#define PMU_MISC2_REG1_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 30425 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_BO_STATUS_MASK

#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)

Definition at line 30420 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_BO_STATUS_SHIFT

#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)

Definition at line 30421 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_ENABLE_BO

#define PMU_MISC2_REG1_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)

Definition at line 30428 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_ENABLE_BO_MASK

#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)

Definition at line 30426 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_ENABLE_BO_SHIFT

#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)

Definition at line 30427 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_STEP_TIME

#define PMU_MISC2_REG1_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30476 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_STEP_TIME_MASK

#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)

Definition at line 30468 of file MIMXRT1052.h.

◆ PMU_MISC2_REG1_STEP_TIME_SHIFT

#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)

Definition at line 30469 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_BO_OFFSET

#define PMU_MISC2_REG2_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30442 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_BO_OFFSET_MASK

#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)

Definition at line 30436 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_BO_OFFSET_SHIFT

#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)

Definition at line 30437 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_BO_STATUS

#define PMU_MISC2_REG2_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)

Definition at line 30445 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_BO_STATUS_MASK

#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)

Definition at line 30443 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_BO_STATUS_SHIFT

#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)

Definition at line 30444 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_ENABLE_BO

#define PMU_MISC2_REG2_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)

Definition at line 30448 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_ENABLE_BO_MASK

#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)

Definition at line 30446 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_ENABLE_BO_SHIFT

#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)

Definition at line 30447 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_OK

#define PMU_MISC2_REG2_OK ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)

Definition at line 30451 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_OK_MASK

#define PMU_MISC2_REG2_OK_MASK (0x400000U)

Definition at line 30449 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_OK_SHIFT

#define PMU_MISC2_REG2_OK_SHIFT (22U)

Definition at line 30450 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_STEP_TIME

#define PMU_MISC2_REG2_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30485 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_STEP_TIME_MASK

#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)

Definition at line 30477 of file MIMXRT1052.h.

◆ PMU_MISC2_REG2_STEP_TIME_SHIFT

#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)

Definition at line 30478 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_AUDIO_DIV_LSB

#define PMU_MISC2_SET_AUDIO_DIV_LSB ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 30540 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_AUDIO_DIV_LSB_MASK

#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)

Definition at line 30534 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT

#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)

Definition at line 30535 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_AUDIO_DIV_MSB

#define PMU_MISC2_SET_AUDIO_DIV_MSB ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 30563 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_AUDIO_DIV_MSB_MASK

#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)

Definition at line 30557 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT

#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)

Definition at line 30558 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_PLL3_disable

#define PMU_MISC2_SET_PLL3_disable ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)

Definition at line 30517 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_PLL3_disable_MASK

#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)

Definition at line 30515 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_PLL3_disable_SHIFT

#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)

Definition at line 30516 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_BO_OFFSET

#define PMU_MISC2_SET_REG0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30505 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_BO_OFFSET_MASK

#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)

Definition at line 30499 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT

#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)

Definition at line 30500 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_BO_STATUS

#define PMU_MISC2_SET_REG0_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 30511 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_BO_STATUS_MASK

#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)

Definition at line 30506 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_BO_STATUS_SHIFT

#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)

Definition at line 30507 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_ENABLE_BO

#define PMU_MISC2_SET_REG0_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)

Definition at line 30514 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_ENABLE_BO_MASK

#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)

Definition at line 30512 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT

#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)

Definition at line 30513 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_STEP_TIME

#define PMU_MISC2_SET_REG0_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30572 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_STEP_TIME_MASK

#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)

Definition at line 30564 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG0_STEP_TIME_SHIFT

#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)

Definition at line 30565 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_BO_OFFSET

#define PMU_MISC2_SET_REG1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30524 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_BO_OFFSET_MASK

#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)

Definition at line 30518 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT

#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)

Definition at line 30519 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_BO_STATUS

#define PMU_MISC2_SET_REG1_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 30530 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_BO_STATUS_MASK

#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)

Definition at line 30525 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_BO_STATUS_SHIFT

#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)

Definition at line 30526 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_ENABLE_BO

#define PMU_MISC2_SET_REG1_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)

Definition at line 30533 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_ENABLE_BO_MASK

#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)

Definition at line 30531 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT

#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)

Definition at line 30532 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_STEP_TIME

#define PMU_MISC2_SET_REG1_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30581 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_STEP_TIME_MASK

#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)

Definition at line 30573 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG1_STEP_TIME_SHIFT

#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)

Definition at line 30574 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_BO_OFFSET

#define PMU_MISC2_SET_REG2_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30547 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_BO_OFFSET_MASK

#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)

Definition at line 30541 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT

#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)

Definition at line 30542 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_BO_STATUS

#define PMU_MISC2_SET_REG2_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)

Definition at line 30550 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_BO_STATUS_MASK

#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)

Definition at line 30548 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_BO_STATUS_SHIFT

#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)

Definition at line 30549 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_ENABLE_BO

#define PMU_MISC2_SET_REG2_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)

Definition at line 30553 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_ENABLE_BO_MASK

#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)

Definition at line 30551 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT

#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)

Definition at line 30552 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_OK

#define PMU_MISC2_SET_REG2_OK ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)

Definition at line 30556 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_OK_MASK

#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)

Definition at line 30554 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_OK_SHIFT

#define PMU_MISC2_SET_REG2_OK_SHIFT (22U)

Definition at line 30555 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_STEP_TIME

#define PMU_MISC2_SET_REG2_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30590 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_STEP_TIME_MASK

#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)

Definition at line 30582 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_REG2_STEP_TIME_SHIFT

#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)

Definition at line 30583 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_VIDEO_DIV

#define PMU_MISC2_SET_VIDEO_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

Definition at line 30599 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_VIDEO_DIV_MASK

#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)

Definition at line 30591 of file MIMXRT1052.h.

◆ PMU_MISC2_SET_VIDEO_DIV_SHIFT

#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)

Definition at line 30592 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_AUDIO_DIV_LSB

#define PMU_MISC2_TOG_AUDIO_DIV_LSB ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 30750 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK

#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)

Definition at line 30744 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT

#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)

Definition at line 30745 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_AUDIO_DIV_MSB

#define PMU_MISC2_TOG_AUDIO_DIV_MSB ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 30773 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK

#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)

Definition at line 30767 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT

#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)

Definition at line 30768 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_PLL3_disable

#define PMU_MISC2_TOG_PLL3_disable ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)

Definition at line 30727 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_PLL3_disable_MASK

#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)

Definition at line 30725 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_PLL3_disable_SHIFT

#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)

Definition at line 30726 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_BO_OFFSET

#define PMU_MISC2_TOG_REG0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30715 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_BO_OFFSET_MASK

#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)

Definition at line 30709 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT

#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)

Definition at line 30710 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_BO_STATUS

#define PMU_MISC2_TOG_REG0_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 30721 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_BO_STATUS_MASK

#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)

Definition at line 30716 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT

#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)

Definition at line 30717 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_ENABLE_BO

#define PMU_MISC2_TOG_REG0_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)

Definition at line 30724 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_ENABLE_BO_MASK

#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)

Definition at line 30722 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT

#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)

Definition at line 30723 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_STEP_TIME

#define PMU_MISC2_TOG_REG0_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30782 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_STEP_TIME_MASK

#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)

Definition at line 30774 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT

#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)

Definition at line 30775 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_BO_OFFSET

#define PMU_MISC2_TOG_REG1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30734 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_BO_OFFSET_MASK

#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)

Definition at line 30728 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT

#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)

Definition at line 30729 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_BO_STATUS

#define PMU_MISC2_TOG_REG1_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 30740 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_BO_STATUS_MASK

#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)

Definition at line 30735 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT

#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)

Definition at line 30736 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_ENABLE_BO

#define PMU_MISC2_TOG_REG1_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)

Definition at line 30743 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_ENABLE_BO_MASK

#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)

Definition at line 30741 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT

#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)

Definition at line 30742 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_STEP_TIME

#define PMU_MISC2_TOG_REG1_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30791 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_STEP_TIME_MASK

#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)

Definition at line 30783 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT

#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)

Definition at line 30784 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_BO_OFFSET

#define PMU_MISC2_TOG_REG2_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 30757 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_BO_OFFSET_MASK

#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)

Definition at line 30751 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT

#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)

Definition at line 30752 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_BO_STATUS

#define PMU_MISC2_TOG_REG2_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)

Definition at line 30760 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_BO_STATUS_MASK

#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)

Definition at line 30758 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT

#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)

Definition at line 30759 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_ENABLE_BO

#define PMU_MISC2_TOG_REG2_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)

Definition at line 30763 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_ENABLE_BO_MASK

#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)

Definition at line 30761 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT

#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)

Definition at line 30762 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_OK

#define PMU_MISC2_TOG_REG2_OK ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)

Definition at line 30766 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_OK_MASK

#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)

Definition at line 30764 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_OK_SHIFT

#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)

Definition at line 30765 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_STEP_TIME

#define PMU_MISC2_TOG_REG2_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 30800 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_STEP_TIME_MASK

#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)

Definition at line 30792 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT

#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)

Definition at line 30793 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_VIDEO_DIV

#define PMU_MISC2_TOG_VIDEO_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

Definition at line 30809 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_VIDEO_DIV_MASK

#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)

Definition at line 30801 of file MIMXRT1052.h.

◆ PMU_MISC2_TOG_VIDEO_DIV_SHIFT

#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)

Definition at line 30802 of file MIMXRT1052.h.

◆ PMU_MISC2_VIDEO_DIV

#define PMU_MISC2_VIDEO_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

Definition at line 30494 of file MIMXRT1052.h.

◆ PMU_MISC2_VIDEO_DIV_MASK

#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)

Definition at line 30486 of file MIMXRT1052.h.

◆ PMU_MISC2_VIDEO_DIV_SHIFT

#define PMU_MISC2_VIDEO_DIV_SHIFT (30U)

Definition at line 30487 of file MIMXRT1052.h.

◆ PMU_REG_1P1_BO_OFFSET

#define PMU_REG_1P1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)

Definition at line 28724 of file MIMXRT1052.h.

◆ PMU_REG_1P1_BO_OFFSET_MASK

#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)

Definition at line 28722 of file MIMXRT1052.h.

◆ PMU_REG_1P1_BO_OFFSET_SHIFT

#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)

Definition at line 28723 of file MIMXRT1052.h.

◆ PMU_REG_1P1_BO_VDD1P1

#define PMU_REG_1P1_BO_VDD1P1 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)

Definition at line 28735 of file MIMXRT1052.h.

◆ PMU_REG_1P1_BO_VDD1P1_MASK

#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)

Definition at line 28733 of file MIMXRT1052.h.

◆ PMU_REG_1P1_BO_VDD1P1_SHIFT

#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)

Definition at line 28734 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_BO_OFFSET

#define PMU_REG_1P1_CLR_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)

Definition at line 28810 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_BO_OFFSET_MASK

#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)

Definition at line 28808 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_BO_OFFSET_SHIFT

#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)

Definition at line 28809 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_BO_VDD1P1

#define PMU_REG_1P1_CLR_BO_VDD1P1 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)

Definition at line 28821 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_BO_VDD1P1_MASK

#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)

Definition at line 28819 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT

#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)

Definition at line 28820 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_BO

#define PMU_REG_1P1_CLR_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)

Definition at line 28801 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_BO_MASK

#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)

Definition at line 28799 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_BO_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)

Definition at line 28800 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_ILIMIT

#define PMU_REG_1P1_CLR_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)

Definition at line 28804 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK

#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 28802 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 28803 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_LINREG

#define PMU_REG_1P1_CLR_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)

Definition at line 28798 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_LINREG_MASK

#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)

Definition at line 28796 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)

Definition at line 28797 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_PULLDOWN

#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)

Definition at line 28807 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK

#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 28805 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 28806 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG

#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)

Definition at line 28827 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 28825 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 28826 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_OK_VDD1P1

#define PMU_REG_1P1_CLR_OK_VDD1P1 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)

Definition at line 28824 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_OK_VDD1P1_MASK

#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)

Definition at line 28822 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT

#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)

Definition at line 28823 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_OUTPUT_TRG

#define PMU_REG_1P1_CLR_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00100..0.8V 0b10000..1.1V 0b000x1..1.375V

Definition at line 28818 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_OUTPUT_TRG_MASK

#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 28811 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT

#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)

Definition at line 28812 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_SELREF_WEAK_LINREG

#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)

SELREF_WEAK_LINREG 0b0..Weak-linreg output tracks low-power-bandgap voltage 0b1..Weak-linreg output tracks VDD_SOC_IN voltage

Definition at line 28834 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK

#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)

Definition at line 28828 of file MIMXRT1052.h.

◆ PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)

Definition at line 28829 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_BO

#define PMU_REG_1P1_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)

Definition at line 28715 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_BO_MASK

#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)

Definition at line 28713 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_BO_SHIFT

#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)

Definition at line 28714 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_ILIMIT

#define PMU_REG_1P1_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)

Definition at line 28718 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_ILIMIT_MASK

#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 28716 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_ILIMIT_SHIFT

#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 28717 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_LINREG

#define PMU_REG_1P1_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)

Definition at line 28712 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_LINREG_MASK

#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)

Definition at line 28710 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_LINREG_SHIFT

#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)

Definition at line 28711 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_PULLDOWN

#define PMU_REG_1P1_ENABLE_PULLDOWN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)

Definition at line 28721 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_PULLDOWN_MASK

#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 28719 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 28720 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_WEAK_LINREG

#define PMU_REG_1P1_ENABLE_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)

Definition at line 28741 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 28739 of file MIMXRT1052.h.

◆ PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 28740 of file MIMXRT1052.h.

◆ PMU_REG_1P1_OK_VDD1P1

#define PMU_REG_1P1_OK_VDD1P1 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)

Definition at line 28738 of file MIMXRT1052.h.

◆ PMU_REG_1P1_OK_VDD1P1_MASK

#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)

Definition at line 28736 of file MIMXRT1052.h.

◆ PMU_REG_1P1_OK_VDD1P1_SHIFT

#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)

Definition at line 28737 of file MIMXRT1052.h.

◆ PMU_REG_1P1_OUTPUT_TRG

#define PMU_REG_1P1_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00100..0.8V 0b10000..1.1V 0b000x1..1.375V

Definition at line 28732 of file MIMXRT1052.h.

◆ PMU_REG_1P1_OUTPUT_TRG_MASK

#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 28725 of file MIMXRT1052.h.

◆ PMU_REG_1P1_OUTPUT_TRG_SHIFT

#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)

Definition at line 28726 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SELREF_WEAK_LINREG

#define PMU_REG_1P1_SELREF_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)

SELREF_WEAK_LINREG 0b0..Weak-linreg output tracks low-power-bandgap voltage 0b1..Weak-linreg output tracks VDD_SOC_IN voltage

Definition at line 28748 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SELREF_WEAK_LINREG_MASK

#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)

Definition at line 28742 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)

Definition at line 28743 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_BO_OFFSET

#define PMU_REG_1P1_SET_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)

Definition at line 28767 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_BO_OFFSET_MASK

#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)

Definition at line 28765 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_BO_OFFSET_SHIFT

#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)

Definition at line 28766 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_BO_VDD1P1

#define PMU_REG_1P1_SET_BO_VDD1P1 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)

Definition at line 28778 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_BO_VDD1P1_MASK

#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)

Definition at line 28776 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_BO_VDD1P1_SHIFT

#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)

Definition at line 28777 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_BO

#define PMU_REG_1P1_SET_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)

Definition at line 28758 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_BO_MASK

#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)

Definition at line 28756 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_BO_SHIFT

#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)

Definition at line 28757 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_ILIMIT

#define PMU_REG_1P1_SET_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)

Definition at line 28761 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK

#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 28759 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT

#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 28760 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_LINREG

#define PMU_REG_1P1_SET_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)

Definition at line 28755 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_LINREG_MASK

#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)

Definition at line 28753 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT

#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)

Definition at line 28754 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_PULLDOWN

#define PMU_REG_1P1_SET_ENABLE_PULLDOWN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)

Definition at line 28764 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK

#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 28762 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 28763 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_WEAK_LINREG

#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)

Definition at line 28784 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 28782 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 28783 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_OK_VDD1P1

#define PMU_REG_1P1_SET_OK_VDD1P1 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)

Definition at line 28781 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_OK_VDD1P1_MASK

#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)

Definition at line 28779 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_OK_VDD1P1_SHIFT

#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)

Definition at line 28780 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_OUTPUT_TRG

#define PMU_REG_1P1_SET_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00100..0.8V 0b10000..1.1V 0b000x1..1.375V

Definition at line 28775 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_OUTPUT_TRG_MASK

#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 28768 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT

#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)

Definition at line 28769 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_SELREF_WEAK_LINREG

#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)

SELREF_WEAK_LINREG 0b0..Weak-linreg output tracks low-power-bandgap voltage 0b1..Weak-linreg output tracks VDD_SOC_IN voltage

Definition at line 28791 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK

#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)

Definition at line 28785 of file MIMXRT1052.h.

◆ PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)

Definition at line 28786 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_BO_OFFSET

#define PMU_REG_1P1_TOG_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)

Definition at line 28853 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_BO_OFFSET_MASK

#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)

Definition at line 28851 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_BO_OFFSET_SHIFT

#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)

Definition at line 28852 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_BO_VDD1P1

#define PMU_REG_1P1_TOG_BO_VDD1P1 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)

Definition at line 28864 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_BO_VDD1P1_MASK

#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)

Definition at line 28862 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT

#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)

Definition at line 28863 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_BO

#define PMU_REG_1P1_TOG_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)

Definition at line 28844 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_BO_MASK

#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)

Definition at line 28842 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_BO_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)

Definition at line 28843 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_ILIMIT

#define PMU_REG_1P1_TOG_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)

Definition at line 28847 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK

#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 28845 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 28846 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_LINREG

#define PMU_REG_1P1_TOG_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)

Definition at line 28841 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_LINREG_MASK

#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)

Definition at line 28839 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)

Definition at line 28840 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_PULLDOWN

#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)

Definition at line 28850 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK

#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 28848 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 28849 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG

#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)

Definition at line 28870 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 28868 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 28869 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_OK_VDD1P1

#define PMU_REG_1P1_TOG_OK_VDD1P1 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)

Definition at line 28867 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_OK_VDD1P1_MASK

#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)

Definition at line 28865 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT

#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)

Definition at line 28866 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_OUTPUT_TRG

#define PMU_REG_1P1_TOG_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00100..0.8V 0b10000..1.1V 0b000x1..1.375V

Definition at line 28861 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_OUTPUT_TRG_MASK

#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 28854 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT

#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)

Definition at line 28855 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_SELREF_WEAK_LINREG

#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)

SELREF_WEAK_LINREG 0b0..Weak-linreg output tracks low-power-bandgap voltage 0b1..Weak-linreg output tracks VDD_SOC_IN voltage

Definition at line 28877 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK

#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)

Definition at line 28871 of file MIMXRT1052.h.

◆ PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)

Definition at line 28872 of file MIMXRT1052.h.

◆ PMU_REG_2P5_BO_OFFSET

#define PMU_REG_2P5_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)

Definition at line 29044 of file MIMXRT1052.h.

◆ PMU_REG_2P5_BO_OFFSET_MASK

#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)

Definition at line 29042 of file MIMXRT1052.h.

◆ PMU_REG_2P5_BO_OFFSET_SHIFT

#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)

Definition at line 29043 of file MIMXRT1052.h.

◆ PMU_REG_2P5_BO_VDD2P5

#define PMU_REG_2P5_BO_VDD2P5 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)

Definition at line 29055 of file MIMXRT1052.h.

◆ PMU_REG_2P5_BO_VDD2P5_MASK

#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)

Definition at line 29053 of file MIMXRT1052.h.

◆ PMU_REG_2P5_BO_VDD2P5_SHIFT

#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)

Definition at line 29054 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_BO_OFFSET

#define PMU_REG_2P5_CLR_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)

Definition at line 29116 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_BO_OFFSET_MASK

#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)

Definition at line 29114 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_BO_OFFSET_SHIFT

#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)

Definition at line 29115 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_BO_VDD2P5

#define PMU_REG_2P5_CLR_BO_VDD2P5 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)

Definition at line 29127 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_BO_VDD2P5_MASK

#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)

Definition at line 29125 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT

#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)

Definition at line 29126 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_BO

#define PMU_REG_2P5_CLR_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)

Definition at line 29107 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_BO_MASK

#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)

Definition at line 29105 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_BO_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)

Definition at line 29106 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_ILIMIT

#define PMU_REG_2P5_CLR_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)

Definition at line 29110 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK

#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 29108 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 29109 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_LINREG

#define PMU_REG_2P5_CLR_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)

Definition at line 29104 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_LINREG_MASK

#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)

Definition at line 29102 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)

Definition at line 29103 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_PULLDOWN

#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)

Definition at line 29113 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK

#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 29111 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 29112 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG

#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)

Definition at line 29133 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 29131 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 29132 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_OK_VDD2P5

#define PMU_REG_2P5_CLR_OK_VDD2P5 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)

Definition at line 29130 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_OK_VDD2P5_MASK

#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)

Definition at line 29128 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT

#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)

Definition at line 29129 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_OUTPUT_TRG

#define PMU_REG_2P5_CLR_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.10V 0b10000..2.50V 0b11111..2.875V

Definition at line 29124 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_OUTPUT_TRG_MASK

#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 29117 of file MIMXRT1052.h.

◆ PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT

#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)

Definition at line 29118 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_BO

#define PMU_REG_2P5_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)

Definition at line 29035 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_BO_MASK

#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)

Definition at line 29033 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_BO_SHIFT

#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)

Definition at line 29034 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_ILIMIT

#define PMU_REG_2P5_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)

Definition at line 29038 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_ILIMIT_MASK

#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 29036 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_ILIMIT_SHIFT

#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 29037 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_LINREG

#define PMU_REG_2P5_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)

Definition at line 29032 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_LINREG_MASK

#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)

Definition at line 29030 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_LINREG_SHIFT

#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)

Definition at line 29031 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_PULLDOWN

#define PMU_REG_2P5_ENABLE_PULLDOWN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)

Definition at line 29041 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_PULLDOWN_MASK

#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 29039 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 29040 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_WEAK_LINREG

#define PMU_REG_2P5_ENABLE_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)

Definition at line 29061 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 29059 of file MIMXRT1052.h.

◆ PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 29060 of file MIMXRT1052.h.

◆ PMU_REG_2P5_OK_VDD2P5

#define PMU_REG_2P5_OK_VDD2P5 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)

Definition at line 29058 of file MIMXRT1052.h.

◆ PMU_REG_2P5_OK_VDD2P5_MASK

#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)

Definition at line 29056 of file MIMXRT1052.h.

◆ PMU_REG_2P5_OK_VDD2P5_SHIFT

#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)

Definition at line 29057 of file MIMXRT1052.h.

◆ PMU_REG_2P5_OUTPUT_TRG

#define PMU_REG_2P5_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.10V 0b10000..2.50V 0b11111..2.875V

Definition at line 29052 of file MIMXRT1052.h.

◆ PMU_REG_2P5_OUTPUT_TRG_MASK

#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 29045 of file MIMXRT1052.h.

◆ PMU_REG_2P5_OUTPUT_TRG_SHIFT

#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)

Definition at line 29046 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_BO_OFFSET

#define PMU_REG_2P5_SET_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)

Definition at line 29080 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_BO_OFFSET_MASK

#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)

Definition at line 29078 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_BO_OFFSET_SHIFT

#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)

Definition at line 29079 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_BO_VDD2P5

#define PMU_REG_2P5_SET_BO_VDD2P5 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)

Definition at line 29091 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_BO_VDD2P5_MASK

#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)

Definition at line 29089 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_BO_VDD2P5_SHIFT

#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)

Definition at line 29090 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_BO

#define PMU_REG_2P5_SET_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)

Definition at line 29071 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_BO_MASK

#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)

Definition at line 29069 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_BO_SHIFT

#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)

Definition at line 29070 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_ILIMIT

#define PMU_REG_2P5_SET_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)

Definition at line 29074 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK

#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 29072 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT

#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 29073 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_LINREG

#define PMU_REG_2P5_SET_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)

Definition at line 29068 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_LINREG_MASK

#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)

Definition at line 29066 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT

#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)

Definition at line 29067 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_PULLDOWN

#define PMU_REG_2P5_SET_ENABLE_PULLDOWN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)

Definition at line 29077 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK

#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 29075 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 29076 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_WEAK_LINREG

#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)

Definition at line 29097 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 29095 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 29096 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_OK_VDD2P5

#define PMU_REG_2P5_SET_OK_VDD2P5 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)

Definition at line 29094 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_OK_VDD2P5_MASK

#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)

Definition at line 29092 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_OK_VDD2P5_SHIFT

#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)

Definition at line 29093 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_OUTPUT_TRG

#define PMU_REG_2P5_SET_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.10V 0b10000..2.50V 0b11111..2.875V

Definition at line 29088 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_OUTPUT_TRG_MASK

#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 29081 of file MIMXRT1052.h.

◆ PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT

#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)

Definition at line 29082 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_BO_OFFSET

#define PMU_REG_2P5_TOG_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)

Definition at line 29152 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_BO_OFFSET_MASK

#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)

Definition at line 29150 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_BO_OFFSET_SHIFT

#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)

Definition at line 29151 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_BO_VDD2P5

#define PMU_REG_2P5_TOG_BO_VDD2P5 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)

Definition at line 29163 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_BO_VDD2P5_MASK

#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)

Definition at line 29161 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT

#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)

Definition at line 29162 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_BO

#define PMU_REG_2P5_TOG_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)

Definition at line 29143 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_BO_MASK

#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)

Definition at line 29141 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_BO_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)

Definition at line 29142 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_ILIMIT

#define PMU_REG_2P5_TOG_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)

Definition at line 29146 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK

#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 29144 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 29145 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_LINREG

#define PMU_REG_2P5_TOG_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)

Definition at line 29140 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_LINREG_MASK

#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)

Definition at line 29138 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)

Definition at line 29139 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_PULLDOWN

#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)

Definition at line 29149 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK

#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 29147 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 29148 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG

#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)

Definition at line 29169 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 29167 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 29168 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_OK_VDD2P5

#define PMU_REG_2P5_TOG_OK_VDD2P5 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)

Definition at line 29166 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_OK_VDD2P5_MASK

#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)

Definition at line 29164 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT

#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)

Definition at line 29165 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_OUTPUT_TRG

#define PMU_REG_2P5_TOG_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.10V 0b10000..2.50V 0b11111..2.875V

Definition at line 29160 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_OUTPUT_TRG_MASK

#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 29153 of file MIMXRT1052.h.

◆ PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT

#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)

Definition at line 29154 of file MIMXRT1052.h.

◆ PMU_REG_3P0_BO_OFFSET

#define PMU_REG_3P0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)

Definition at line 28893 of file MIMXRT1052.h.

◆ PMU_REG_3P0_BO_OFFSET_MASK

#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)

Definition at line 28891 of file MIMXRT1052.h.

◆ PMU_REG_3P0_BO_OFFSET_SHIFT

#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)

Definition at line 28892 of file MIMXRT1052.h.

◆ PMU_REG_3P0_BO_VDD3P0

#define PMU_REG_3P0_BO_VDD3P0 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)

Definition at line 28911 of file MIMXRT1052.h.

◆ PMU_REG_3P0_BO_VDD3P0_MASK

#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)

Definition at line 28909 of file MIMXRT1052.h.

◆ PMU_REG_3P0_BO_VDD3P0_SHIFT

#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)

Definition at line 28910 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_BO_OFFSET

#define PMU_REG_3P0_CLR_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)

Definition at line 28967 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_BO_OFFSET_MASK

#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)

Definition at line 28965 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_BO_OFFSET_SHIFT

#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)

Definition at line 28966 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_BO_VDD3P0

#define PMU_REG_3P0_CLR_BO_VDD3P0 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)

Definition at line 28985 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_BO_VDD3P0_MASK

#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)

Definition at line 28983 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT

#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)

Definition at line 28984 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_BO

#define PMU_REG_3P0_CLR_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)

Definition at line 28961 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_BO_MASK

#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)

Definition at line 28959 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_BO_SHIFT

#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)

Definition at line 28960 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_ILIMIT

#define PMU_REG_3P0_CLR_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)

Definition at line 28964 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK

#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 28962 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT

#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 28963 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_LINREG

#define PMU_REG_3P0_CLR_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)

Definition at line 28958 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_LINREG_MASK

#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)

Definition at line 28956 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT

#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)

Definition at line 28957 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_OK_VDD3P0

#define PMU_REG_3P0_CLR_OK_VDD3P0 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)

Definition at line 28988 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_OK_VDD3P0_MASK

#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)

Definition at line 28986 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT

#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)

Definition at line 28987 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_OUTPUT_TRG

#define PMU_REG_3P0_CLR_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.625V 0b01111..3.000V 0b11111..3.400V

Definition at line 28982 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_OUTPUT_TRG_MASK

#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 28975 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT

#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)

Definition at line 28976 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_VBUS_SEL

#define PMU_REG_3P0_CLR_VBUS_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)

VBUS_SEL 0b1..Utilize VBUS OTG1 power 0b0..Utilize VBUS OTG2 power

Definition at line 28974 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_VBUS_SEL_MASK

#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)

Definition at line 28968 of file MIMXRT1052.h.

◆ PMU_REG_3P0_CLR_VBUS_SEL_SHIFT

#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)

Definition at line 28969 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_BO

#define PMU_REG_3P0_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)

Definition at line 28887 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_BO_MASK

#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)

Definition at line 28885 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_BO_SHIFT

#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)

Definition at line 28886 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_ILIMIT

#define PMU_REG_3P0_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)

Definition at line 28890 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_ILIMIT_MASK

#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 28888 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_ILIMIT_SHIFT

#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 28889 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_LINREG

#define PMU_REG_3P0_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)

Definition at line 28884 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_LINREG_MASK

#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)

Definition at line 28882 of file MIMXRT1052.h.

◆ PMU_REG_3P0_ENABLE_LINREG_SHIFT

#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)

Definition at line 28883 of file MIMXRT1052.h.

◆ PMU_REG_3P0_OK_VDD3P0

#define PMU_REG_3P0_OK_VDD3P0 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)

Definition at line 28914 of file MIMXRT1052.h.

◆ PMU_REG_3P0_OK_VDD3P0_MASK

#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)

Definition at line 28912 of file MIMXRT1052.h.

◆ PMU_REG_3P0_OK_VDD3P0_SHIFT

#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)

Definition at line 28913 of file MIMXRT1052.h.

◆ PMU_REG_3P0_OUTPUT_TRG

#define PMU_REG_3P0_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.625V 0b01111..3.000V 0b11111..3.400V

Definition at line 28908 of file MIMXRT1052.h.

◆ PMU_REG_3P0_OUTPUT_TRG_MASK

#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 28901 of file MIMXRT1052.h.

◆ PMU_REG_3P0_OUTPUT_TRG_SHIFT

#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)

Definition at line 28902 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_BO_OFFSET

#define PMU_REG_3P0_SET_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)

Definition at line 28930 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_BO_OFFSET_MASK

#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)

Definition at line 28928 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_BO_OFFSET_SHIFT

#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)

Definition at line 28929 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_BO_VDD3P0

#define PMU_REG_3P0_SET_BO_VDD3P0 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)

Definition at line 28948 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_BO_VDD3P0_MASK

#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)

Definition at line 28946 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_BO_VDD3P0_SHIFT

#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)

Definition at line 28947 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_BO

#define PMU_REG_3P0_SET_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)

Definition at line 28924 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_BO_MASK

#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)

Definition at line 28922 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_BO_SHIFT

#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)

Definition at line 28923 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_ILIMIT

#define PMU_REG_3P0_SET_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)

Definition at line 28927 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK

#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 28925 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT

#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 28926 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_LINREG

#define PMU_REG_3P0_SET_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)

Definition at line 28921 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_LINREG_MASK

#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)

Definition at line 28919 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT

#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)

Definition at line 28920 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_OK_VDD3P0

#define PMU_REG_3P0_SET_OK_VDD3P0 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)

Definition at line 28951 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_OK_VDD3P0_MASK

#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)

Definition at line 28949 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_OK_VDD3P0_SHIFT

#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)

Definition at line 28950 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_OUTPUT_TRG

#define PMU_REG_3P0_SET_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.625V 0b01111..3.000V 0b11111..3.400V

Definition at line 28945 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_OUTPUT_TRG_MASK

#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 28938 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT

#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)

Definition at line 28939 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_VBUS_SEL

#define PMU_REG_3P0_SET_VBUS_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)

VBUS_SEL 0b1..Utilize VBUS OTG1 power 0b0..Utilize VBUS OTG2 power

Definition at line 28937 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_VBUS_SEL_MASK

#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)

Definition at line 28931 of file MIMXRT1052.h.

◆ PMU_REG_3P0_SET_VBUS_SEL_SHIFT

#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)

Definition at line 28932 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_BO_OFFSET

#define PMU_REG_3P0_TOG_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)

Definition at line 29004 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_BO_OFFSET_MASK

#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)

Definition at line 29002 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_BO_OFFSET_SHIFT

#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)

Definition at line 29003 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_BO_VDD3P0

#define PMU_REG_3P0_TOG_BO_VDD3P0 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)

Definition at line 29022 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_BO_VDD3P0_MASK

#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)

Definition at line 29020 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT

#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)

Definition at line 29021 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_BO

#define PMU_REG_3P0_TOG_ENABLE_BO ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)

Definition at line 28998 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_BO_MASK

#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)

Definition at line 28996 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_BO_SHIFT

#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)

Definition at line 28997 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_ILIMIT

#define PMU_REG_3P0_TOG_ENABLE_ILIMIT ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)

Definition at line 29001 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK

#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 28999 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT

#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 29000 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_LINREG

#define PMU_REG_3P0_TOG_ENABLE_LINREG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)

Definition at line 28995 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_LINREG_MASK

#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)

Definition at line 28993 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT

#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)

Definition at line 28994 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_OK_VDD3P0

#define PMU_REG_3P0_TOG_OK_VDD3P0 ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)

Definition at line 29025 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_OK_VDD3P0_MASK

#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)

Definition at line 29023 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT

#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)

Definition at line 29024 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_OUTPUT_TRG

#define PMU_REG_3P0_TOG_OUTPUT_TRG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.625V 0b01111..3.000V 0b11111..3.400V

Definition at line 29019 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_OUTPUT_TRG_MASK

#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 29012 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT

#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)

Definition at line 29013 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_VBUS_SEL

#define PMU_REG_3P0_TOG_VBUS_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)

VBUS_SEL 0b1..Utilize VBUS OTG1 power 0b0..Utilize VBUS OTG2 power

Definition at line 29011 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_VBUS_SEL_MASK

#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)

Definition at line 29005 of file MIMXRT1052.h.

◆ PMU_REG_3P0_TOG_VBUS_SEL_SHIFT

#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)

Definition at line 29006 of file MIMXRT1052.h.

◆ PMU_REG_3P0_VBUS_SEL

#define PMU_REG_3P0_VBUS_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)

VBUS_SEL 0b1..Utilize VBUS OTG1 power 0b0..Utilize VBUS OTG2 power

Definition at line 28900 of file MIMXRT1052.h.

◆ PMU_REG_3P0_VBUS_SEL_MASK

#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)

Definition at line 28894 of file MIMXRT1052.h.

◆ PMU_REG_3P0_VBUS_SEL_SHIFT

#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)

Definition at line 28895 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_FET_ODRIVE

#define PMU_REG_CORE_CLR_FET_ODRIVE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)

Definition at line 29538 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_FET_ODRIVE_MASK

#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)

Definition at line 29536 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT

#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)

Definition at line 29537 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_RAMP_RATE

#define PMU_REG_CORE_CLR_RAMP_RATE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)

RAMP_RATE 0b00..Fast 0b01..Medium Fast 0b10..Medium Slow 0b11..Slow

Definition at line 29535 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_RAMP_RATE_MASK

#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)

Definition at line 29527 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_RAMP_RATE_SHIFT

#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)

Definition at line 29528 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG0_ADJ

#define PMU_REG_CORE_CLR_REG0_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)

REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29454 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG0_ADJ_MASK

#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)

Definition at line 29432 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG0_ADJ_SHIFT

#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)

Definition at line 29433 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG0_TARG

#define PMU_REG_CORE_CLR_REG0_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)

REG0_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29431 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG0_TARG_MASK

#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)

Definition at line 29420 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG0_TARG_SHIFT

#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)

Definition at line 29421 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG1_ADJ

#define PMU_REG_CORE_CLR_REG1_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)

REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29491 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG1_ADJ_MASK

#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)

Definition at line 29469 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG1_ADJ_SHIFT

#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)

Definition at line 29470 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG1_TARG

#define PMU_REG_CORE_CLR_REG1_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)

REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29468 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG1_TARG_MASK

#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)

Definition at line 29455 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG1_TARG_SHIFT

#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)

Definition at line 29456 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG2_ADJ

#define PMU_REG_CORE_CLR_REG2_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)

REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29526 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG2_ADJ_MASK

#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)

Definition at line 29504 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG2_ADJ_SHIFT

#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)

Definition at line 29505 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG2_TARG

#define PMU_REG_CORE_CLR_REG2_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)

REG2_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29503 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG2_TARG_MASK

#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)

Definition at line 29492 of file MIMXRT1052.h.

◆ PMU_REG_CORE_CLR_REG2_TARG_SHIFT

#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)

Definition at line 29493 of file MIMXRT1052.h.

◆ PMU_REG_CORE_FET_ODRIVE

#define PMU_REG_CORE_FET_ODRIVE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)

Definition at line 29292 of file MIMXRT1052.h.

◆ PMU_REG_CORE_FET_ODRIVE_MASK

#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)

Definition at line 29290 of file MIMXRT1052.h.

◆ PMU_REG_CORE_FET_ODRIVE_SHIFT

#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)

Definition at line 29291 of file MIMXRT1052.h.

◆ PMU_REG_CORE_RAMP_RATE

#define PMU_REG_CORE_RAMP_RATE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)

RAMP_RATE 0b00..Fast 0b01..Medium Fast 0b10..Medium Slow 0b11..Slow

Definition at line 29289 of file MIMXRT1052.h.

◆ PMU_REG_CORE_RAMP_RATE_MASK

#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)

Definition at line 29281 of file MIMXRT1052.h.

◆ PMU_REG_CORE_RAMP_RATE_SHIFT

#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)

Definition at line 29282 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG0_ADJ

#define PMU_REG_CORE_REG0_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)

REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29208 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG0_ADJ_MASK

#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)

Definition at line 29186 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG0_ADJ_SHIFT

#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)

Definition at line 29187 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG0_TARG

#define PMU_REG_CORE_REG0_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)

REG0_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29185 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG0_TARG_MASK

#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)

Definition at line 29174 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG0_TARG_SHIFT

#define PMU_REG_CORE_REG0_TARG_SHIFT (0U)

Definition at line 29175 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG1_ADJ

#define PMU_REG_CORE_REG1_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)

REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29245 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG1_ADJ_MASK

#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)

Definition at line 29223 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG1_ADJ_SHIFT

#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)

Definition at line 29224 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG1_TARG

#define PMU_REG_CORE_REG1_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)

REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29222 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG1_TARG_MASK

#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)

Definition at line 29209 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG1_TARG_SHIFT

#define PMU_REG_CORE_REG1_TARG_SHIFT (9U)

Definition at line 29210 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG2_ADJ

#define PMU_REG_CORE_REG2_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)

REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29280 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG2_ADJ_MASK

#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)

Definition at line 29258 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG2_ADJ_SHIFT

#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)

Definition at line 29259 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG2_TARG

#define PMU_REG_CORE_REG2_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)

REG2_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29257 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG2_TARG_MASK

#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)

Definition at line 29246 of file MIMXRT1052.h.

◆ PMU_REG_CORE_REG2_TARG_SHIFT

#define PMU_REG_CORE_REG2_TARG_SHIFT (18U)

Definition at line 29247 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_FET_ODRIVE

#define PMU_REG_CORE_SET_FET_ODRIVE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)

Definition at line 29415 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_FET_ODRIVE_MASK

#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)

Definition at line 29413 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_FET_ODRIVE_SHIFT

#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)

Definition at line 29414 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_RAMP_RATE

#define PMU_REG_CORE_SET_RAMP_RATE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)

RAMP_RATE 0b00..Fast 0b01..Medium Fast 0b10..Medium Slow 0b11..Slow

Definition at line 29412 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_RAMP_RATE_MASK

#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)

Definition at line 29404 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_RAMP_RATE_SHIFT

#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)

Definition at line 29405 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG0_ADJ

#define PMU_REG_CORE_SET_REG0_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)

REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29331 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG0_ADJ_MASK

#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)

Definition at line 29309 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG0_ADJ_SHIFT

#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)

Definition at line 29310 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG0_TARG

#define PMU_REG_CORE_SET_REG0_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)

REG0_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29308 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG0_TARG_MASK

#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)

Definition at line 29297 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG0_TARG_SHIFT

#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)

Definition at line 29298 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG1_ADJ

#define PMU_REG_CORE_SET_REG1_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)

REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29368 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG1_ADJ_MASK

#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)

Definition at line 29346 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG1_ADJ_SHIFT

#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)

Definition at line 29347 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG1_TARG

#define PMU_REG_CORE_SET_REG1_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)

REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29345 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG1_TARG_MASK

#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)

Definition at line 29332 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG1_TARG_SHIFT

#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)

Definition at line 29333 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG2_ADJ

#define PMU_REG_CORE_SET_REG2_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)

REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29403 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG2_ADJ_MASK

#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)

Definition at line 29381 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG2_ADJ_SHIFT

#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)

Definition at line 29382 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG2_TARG

#define PMU_REG_CORE_SET_REG2_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)

REG2_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29380 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG2_TARG_MASK

#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)

Definition at line 29369 of file MIMXRT1052.h.

◆ PMU_REG_CORE_SET_REG2_TARG_SHIFT

#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)

Definition at line 29370 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_FET_ODRIVE

#define PMU_REG_CORE_TOG_FET_ODRIVE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)

Definition at line 29661 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_FET_ODRIVE_MASK

#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)

Definition at line 29659 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT

#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)

Definition at line 29660 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_RAMP_RATE

#define PMU_REG_CORE_TOG_RAMP_RATE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)

RAMP_RATE 0b00..Fast 0b01..Medium Fast 0b10..Medium Slow 0b11..Slow

Definition at line 29658 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_RAMP_RATE_MASK

#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)

Definition at line 29650 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_RAMP_RATE_SHIFT

#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)

Definition at line 29651 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG0_ADJ

#define PMU_REG_CORE_TOG_REG0_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)

REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29577 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG0_ADJ_MASK

#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)

Definition at line 29555 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG0_ADJ_SHIFT

#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)

Definition at line 29556 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG0_TARG

#define PMU_REG_CORE_TOG_REG0_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)

REG0_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29554 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG0_TARG_MASK

#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)

Definition at line 29543 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG0_TARG_SHIFT

#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)

Definition at line 29544 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG1_ADJ

#define PMU_REG_CORE_TOG_REG1_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)

REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29614 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG1_ADJ_MASK

#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)

Definition at line 29592 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG1_ADJ_SHIFT

#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)

Definition at line 29593 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG1_TARG

#define PMU_REG_CORE_TOG_REG1_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)

REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29591 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG1_TARG_MASK

#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)

Definition at line 29578 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG1_TARG_SHIFT

#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)

Definition at line 29579 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG2_ADJ

#define PMU_REG_CORE_TOG_REG2_ADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)

REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 29649 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG2_ADJ_MASK

#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)

Definition at line 29627 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG2_ADJ_SHIFT

#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)

Definition at line 29628 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG2_TARG

#define PMU_REG_CORE_TOG_REG2_TARG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)

REG2_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 29626 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG2_TARG_MASK

#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)

Definition at line 29615 of file MIMXRT1052.h.

◆ PMU_REG_CORE_TOG_REG2_TARG_SHIFT

#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)

Definition at line 29616 of file MIMXRT1052.h.

MISC0 - Miscellaneous Register 0

MISC0_SET - Miscellaneous Register 0

MISC0_CLR - Miscellaneous Register 0

MISC0_TOG - Miscellaneous Register 0

MISC1 - Miscellaneous Register 1

MISC1_SET - Miscellaneous Register 1

MISC1_CLR - Miscellaneous Register 1

MISC1_TOG - Miscellaneous Register 1

REG_1P1 - Regulator 1P1 Register

REG_1P1_SET - Regulator 1P1 Register

REG_1P1_CLR - Regulator 1P1 Register

REG_1P1_TOG - Regulator 1P1 Register

REG_3P0 - Regulator 3P0 Register

REG_3P0_SET - Regulator 3P0 Register

REG_3P0_CLR - Regulator 3P0 Register

REG_3P0_TOG - Regulator 3P0 Register

REG_2P5 - Regulator 2P5 Register

REG_2P5_SET - Regulator 2P5 Register

REG_2P5_CLR - Regulator 2P5 Register

REG_2P5_TOG - Regulator 2P5 Register

REG_CORE - Digital Regulator Core Register

REG_CORE_SET - Digital Regulator Core Register

REG_CORE_CLR - Digital Regulator Core Register

REG_CORE_TOG - Digital Regulator Core Register

MISC2 - Miscellaneous Control Register

MISC2_SET - Miscellaneous Control Register

MISC2_CLR - Miscellaneous Control Register

MISC2_TOG - Miscellaneous Control Register

Detailed Description

Macro Definition Documentation

◆ PMU_MISC0_CLKGATE_CTRL

◆ PMU_MISC0_CLKGATE_CTRL_MASK

◆ PMU_MISC0_CLKGATE_CTRL_SHIFT

◆ PMU_MISC0_CLKGATE_DELAY

◆ PMU_MISC0_CLKGATE_DELAY_MASK

◆ PMU_MISC0_CLKGATE_DELAY_SHIFT

◆ PMU_MISC0_CLR_CLKGATE_CTRL

◆ PMU_MISC0_CLR_CLKGATE_CTRL_MASK

◆ PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT

◆ PMU_MISC0_CLR_CLKGATE_DELAY

◆ PMU_MISC0_CLR_CLKGATE_DELAY_MASK

◆ PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT

◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS

◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK

◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT

◆ PMU_MISC0_CLR_OSC_I

◆ PMU_MISC0_CLR_OSC_I_MASK

◆ PMU_MISC0_CLR_OSC_I_SHIFT

◆ PMU_MISC0_CLR_OSC_XTALOK

◆ PMU_MISC0_CLR_OSC_XTALOK_EN

◆ PMU_MISC0_CLR_OSC_XTALOK_EN_MASK

◆ PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT

◆ PMU_MISC0_CLR_OSC_XTALOK_MASK

◆ PMU_MISC0_CLR_OSC_XTALOK_SHIFT

◆ PMU_MISC0_CLR_REFTOP_PWD

◆ PMU_MISC0_CLR_REFTOP_PWD_MASK

◆ PMU_MISC0_CLR_REFTOP_PWD_SHIFT

◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF

◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK

◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT

◆ PMU_MISC0_CLR_REFTOP_VBGADJ

◆ PMU_MISC0_CLR_REFTOP_VBGADJ_MASK

◆ PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT

◆ PMU_MISC0_CLR_REFTOP_VBGUP

◆ PMU_MISC0_CLR_REFTOP_VBGUP_MASK

◆ PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT

◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE

◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK

◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT

◆ PMU_MISC0_CLR_STOP_MODE_CONFIG

◆ PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK

◆ PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT

◆ PMU_MISC0_CLR_VID_PLL_PREDIV

◆ PMU_MISC0_CLR_VID_PLL_PREDIV_MASK

◆ PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT

◆ PMU_MISC0_CLR_XTAL_24M_PWD

◆ PMU_MISC0_CLR_XTAL_24M_PWD_MASK

◆ PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT

◆ PMU_MISC0_DISCON_HIGH_SNVS

◆ PMU_MISC0_DISCON_HIGH_SNVS_MASK