WCR - Watchdog Control Register | |
| #define | WDOG_WCR_WDZST_MASK (0x1U) |
| #define | WDOG_WCR_WDZST_SHIFT (0U) |
| #define | WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
| #define | WDOG_WCR_WDBG_MASK (0x2U) |
| #define | WDOG_WCR_WDBG_SHIFT (1U) |
| #define | WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
| #define | WDOG_WCR_WDE_MASK (0x4U) |
| #define | WDOG_WCR_WDE_SHIFT (2U) |
| #define | WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
| #define | WDOG_WCR_WDT_MASK (0x8U) |
| #define | WDOG_WCR_WDT_SHIFT (3U) |
| #define | WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
| #define | WDOG_WCR_SRS_MASK (0x10U) |
| #define | WDOG_WCR_SRS_SHIFT (4U) |
| #define | WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
| #define | WDOG_WCR_WDA_MASK (0x20U) |
| #define | WDOG_WCR_WDA_SHIFT (5U) |
| #define | WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
| #define | WDOG_WCR_SRE_MASK (0x40U) |
| #define | WDOG_WCR_SRE_SHIFT (6U) |
| #define | WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
| #define | WDOG_WCR_WDW_MASK (0x80U) |
| #define | WDOG_WCR_WDW_SHIFT (7U) |
| #define | WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
| #define | WDOG_WCR_WT_MASK (0xFF00U) |
| #define | WDOG_WCR_WT_SHIFT (8U) |
| #define | WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WSR - Watchdog Service Register | |
| #define | WDOG_WSR_WSR_MASK (0xFFFFU) |
| #define | WDOG_WSR_WSR_SHIFT (0U) |
| #define | WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WRSR - Watchdog Reset Status Register | |
| #define | WDOG_WRSR_SFTW_MASK (0x1U) |
| #define | WDOG_WRSR_SFTW_SHIFT (0U) |
| #define | WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
| #define | WDOG_WRSR_TOUT_MASK (0x2U) |
| #define | WDOG_WRSR_TOUT_SHIFT (1U) |
| #define | WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
| #define | WDOG_WRSR_POR_MASK (0x10U) |
| #define | WDOG_WRSR_POR_SHIFT (4U) |
| #define | WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
WICR - Watchdog Interrupt Control Register | |
| #define | WDOG_WICR_WICT_MASK (0xFFU) |
| #define | WDOG_WICR_WICT_SHIFT (0U) |
| #define | WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
| #define | WDOG_WICR_WTIS_MASK (0x4000U) |
| #define | WDOG_WICR_WTIS_SHIFT (14U) |
| #define | WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
| #define | WDOG_WICR_WIE_MASK (0x8000U) |
| #define | WDOG_WICR_WIE_SHIFT (15U) |
| #define | WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WMCR - Watchdog Miscellaneous Control Register | |
| #define | WDOG_WMCR_PDE_MASK (0x1U) |
| #define | WDOG_WMCR_PDE_SHIFT (0U) |
| #define | WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
Detailed Description
Macro Definition Documentation
◆ WDOG_WCR_SRE
| #define WDOG_WCR_SRE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
SRE - software reset extension, an option way to generate software reset 0b0..using original way to generate software reset (default) 0b1..using new way to generate software reset.
Definition at line 44003 of file MIMXRT1052.h.
◆ WDOG_WCR_SRE_MASK
| #define WDOG_WCR_SRE_MASK (0x40U) |
Definition at line 43997 of file MIMXRT1052.h.
◆ WDOG_WCR_SRE_SHIFT
| #define WDOG_WCR_SRE_SHIFT (6U) |
Definition at line 43998 of file MIMXRT1052.h.
◆ WDOG_WCR_SRS
| #define WDOG_WCR_SRS | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
SRS - SRS 0b0..Assert system reset signal. 0b1..No effect on the system (Default).
Definition at line 43989 of file MIMXRT1052.h.
◆ WDOG_WCR_SRS_MASK
| #define WDOG_WCR_SRS_MASK (0x10U) |
Definition at line 43983 of file MIMXRT1052.h.
◆ WDOG_WCR_SRS_SHIFT
| #define WDOG_WCR_SRS_SHIFT (4U) |
Definition at line 43984 of file MIMXRT1052.h.
◆ WDOG_WCR_WDA
| #define WDOG_WCR_WDA | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
WDA - WDA 0b0..Assert WDOG_B output. 0b1..No effect on system (Default).
Definition at line 43996 of file MIMXRT1052.h.
◆ WDOG_WCR_WDA_MASK
| #define WDOG_WCR_WDA_MASK (0x20U) |
Definition at line 43990 of file MIMXRT1052.h.
◆ WDOG_WCR_WDA_SHIFT
| #define WDOG_WCR_WDA_SHIFT (5U) |
Definition at line 43991 of file MIMXRT1052.h.
◆ WDOG_WCR_WDBG
| #define WDOG_WCR_WDBG | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
WDBG - WDBG 0b0..Continue WDOG timer operation (Default). 0b1..Suspend the watchdog timer.
Definition at line 43968 of file MIMXRT1052.h.
◆ WDOG_WCR_WDBG_MASK
| #define WDOG_WCR_WDBG_MASK (0x2U) |
Definition at line 43962 of file MIMXRT1052.h.
◆ WDOG_WCR_WDBG_SHIFT
| #define WDOG_WCR_WDBG_SHIFT (1U) |
Definition at line 43963 of file MIMXRT1052.h.
◆ WDOG_WCR_WDE
| #define WDOG_WCR_WDE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
WDE - WDE 0b0..Disable the Watchdog (Default). 0b1..Enable the Watchdog.
Definition at line 43975 of file MIMXRT1052.h.
◆ WDOG_WCR_WDE_MASK
| #define WDOG_WCR_WDE_MASK (0x4U) |
Definition at line 43969 of file MIMXRT1052.h.
◆ WDOG_WCR_WDE_SHIFT
| #define WDOG_WCR_WDE_SHIFT (2U) |
Definition at line 43970 of file MIMXRT1052.h.
◆ WDOG_WCR_WDT
| #define WDOG_WCR_WDT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
WDT - WDT 0b0..No effect on WDOG_B (Default). 0b1..Assert WDOG_B upon a Watchdog Time-out event.
Definition at line 43982 of file MIMXRT1052.h.
◆ WDOG_WCR_WDT_MASK
| #define WDOG_WCR_WDT_MASK (0x8U) |
Definition at line 43976 of file MIMXRT1052.h.
◆ WDOG_WCR_WDT_SHIFT
| #define WDOG_WCR_WDT_SHIFT (3U) |
Definition at line 43977 of file MIMXRT1052.h.
◆ WDOG_WCR_WDW
| #define WDOG_WCR_WDW | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
WDW - WDW 0b0..Continue WDOG timer operation (Default). 0b1..Suspend WDOG timer operation.
Definition at line 44010 of file MIMXRT1052.h.
◆ WDOG_WCR_WDW_MASK
| #define WDOG_WCR_WDW_MASK (0x80U) |
Definition at line 44004 of file MIMXRT1052.h.
◆ WDOG_WCR_WDW_SHIFT
| #define WDOG_WCR_WDW_SHIFT (7U) |
Definition at line 44005 of file MIMXRT1052.h.
◆ WDOG_WCR_WDZST
| #define WDOG_WCR_WDZST | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
WDZST - WDZST 0b0..Continue timer operation (Default). 0b1..Suspend the watchdog timer.
Definition at line 43961 of file MIMXRT1052.h.
◆ WDOG_WCR_WDZST_MASK
| #define WDOG_WCR_WDZST_MASK (0x1U) |
Definition at line 43955 of file MIMXRT1052.h.
◆ WDOG_WCR_WDZST_SHIFT
| #define WDOG_WCR_WDZST_SHIFT (0U) |
Definition at line 43956 of file MIMXRT1052.h.
◆ WDOG_WCR_WT
| #define WDOG_WCR_WT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WT - WT 0b00000000..- 0.5 Seconds (Default). 0b00000001..- 1.0 Seconds. 0b00000010..- 1.5 Seconds. 0b00000011..- 2.0 Seconds. 0b11111111..- 128 Seconds.
Definition at line 44020 of file MIMXRT1052.h.
◆ WDOG_WCR_WT_MASK
| #define WDOG_WCR_WT_MASK (0xFF00U) |
Definition at line 44011 of file MIMXRT1052.h.
◆ WDOG_WCR_WT_SHIFT
| #define WDOG_WCR_WT_SHIFT (8U) |
Definition at line 44012 of file MIMXRT1052.h.
◆ WDOG_WICR_WICT
| #define WDOG_WICR_WICT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
WICT - WICT 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
Definition at line 44069 of file MIMXRT1052.h.
◆ WDOG_WICR_WICT_MASK
| #define WDOG_WICR_WICT_MASK (0xFFU) |
Definition at line 44061 of file MIMXRT1052.h.
◆ WDOG_WICR_WICT_SHIFT
| #define WDOG_WICR_WICT_SHIFT (0U) |
Definition at line 44062 of file MIMXRT1052.h.
◆ WDOG_WICR_WIE
| #define WDOG_WICR_WIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WIE - WIE 0b0..Disable Interrupt (Default). 0b1..Enable Interrupt.
Definition at line 44083 of file MIMXRT1052.h.
◆ WDOG_WICR_WIE_MASK
| #define WDOG_WICR_WIE_MASK (0x8000U) |
Definition at line 44077 of file MIMXRT1052.h.
◆ WDOG_WICR_WIE_SHIFT
| #define WDOG_WICR_WIE_SHIFT (15U) |
Definition at line 44078 of file MIMXRT1052.h.
◆ WDOG_WICR_WTIS
| #define WDOG_WICR_WTIS | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
WTIS - WTIS 0b0..No interrupt has occurred (Default). 0b1..Interrupt has occurred
Definition at line 44076 of file MIMXRT1052.h.
◆ WDOG_WICR_WTIS_MASK
| #define WDOG_WICR_WTIS_MASK (0x4000U) |
Definition at line 44070 of file MIMXRT1052.h.
◆ WDOG_WICR_WTIS_SHIFT
| #define WDOG_WICR_WTIS_SHIFT (14U) |
Definition at line 44071 of file MIMXRT1052.h.
◆ WDOG_WMCR_PDE
| #define WDOG_WMCR_PDE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
PDE - PDE 0b0..Power Down Counter of WDOG is disabled. 0b1..Power Down Counter of WDOG is enabled (Default).
Definition at line 44094 of file MIMXRT1052.h.
◆ WDOG_WMCR_PDE_MASK
| #define WDOG_WMCR_PDE_MASK (0x1U) |
Definition at line 44088 of file MIMXRT1052.h.
◆ WDOG_WMCR_PDE_SHIFT
| #define WDOG_WMCR_PDE_SHIFT (0U) |
Definition at line 44089 of file MIMXRT1052.h.
◆ WDOG_WRSR_POR
| #define WDOG_WRSR_POR | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
POR - POR 0b0..Reset is not the result of a power on reset. 0b1..Reset is the result of a power on reset.
Definition at line 44056 of file MIMXRT1052.h.
◆ WDOG_WRSR_POR_MASK
| #define WDOG_WRSR_POR_MASK (0x10U) |
Definition at line 44050 of file MIMXRT1052.h.
◆ WDOG_WRSR_POR_SHIFT
| #define WDOG_WRSR_POR_SHIFT (4U) |
Definition at line 44051 of file MIMXRT1052.h.
◆ WDOG_WRSR_SFTW
| #define WDOG_WRSR_SFTW | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
SFTW - SFTW 0b0..Reset is not the result of a software reset. 0b1..Reset is the result of a software reset.
Definition at line 44042 of file MIMXRT1052.h.
◆ WDOG_WRSR_SFTW_MASK
| #define WDOG_WRSR_SFTW_MASK (0x1U) |
Definition at line 44036 of file MIMXRT1052.h.
◆ WDOG_WRSR_SFTW_SHIFT
| #define WDOG_WRSR_SFTW_SHIFT (0U) |
Definition at line 44037 of file MIMXRT1052.h.
◆ WDOG_WRSR_TOUT
| #define WDOG_WRSR_TOUT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
TOUT - TOUT 0b0..Reset is not the result of a WDOG timeout. 0b1..Reset is the result of a WDOG timeout.
Definition at line 44049 of file MIMXRT1052.h.
◆ WDOG_WRSR_TOUT_MASK
| #define WDOG_WRSR_TOUT_MASK (0x2U) |
Definition at line 44043 of file MIMXRT1052.h.
◆ WDOG_WRSR_TOUT_SHIFT
| #define WDOG_WRSR_TOUT_SHIFT (1U) |
Definition at line 44044 of file MIMXRT1052.h.
◆ WDOG_WSR_WSR
| #define WDOG_WSR_WSR | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WSR - WSR 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
Definition at line 44031 of file MIMXRT1052.h.
◆ WDOG_WSR_WSR_MASK
| #define WDOG_WSR_WSR_MASK (0xFFFFU) |
Definition at line 44025 of file MIMXRT1052.h.
◆ WDOG_WSR_WSR_SHIFT
| #define WDOG_WSR_WSR_SHIFT (0U) |
Definition at line 44026 of file MIMXRT1052.h.