SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register | |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) |
SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register | |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) |
SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register | |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) |
| #define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) |
Detailed Description
Macro Definition Documentation
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) |
MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5
Definition at line 22842 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) |
Definition at line 22836 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) |
Definition at line 22837 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) |
SION - Software Input On Field. 0b1..Force input path of pad PMIC_ON_REQ 0b0..Input Path is determined by functionality
Definition at line 22849 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) |
Definition at line 22843 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) |
Definition at line 22844 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) |
MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5
Definition at line 22860 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) |
Definition at line 22854 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) |
Definition at line 22855 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) |
SION - Software Input On Field. 0b1..Force input path of pad PMIC_STBY_REQ 0b0..Input Path is determined by functionality
Definition at line 22867 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) |
Definition at line 22861 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) |
Definition at line 22862 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) |
MUX_MODE - MUX Mode Select Field. 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue
Definition at line 22824 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) |
Definition at line 22818 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) |
Definition at line 22819 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) |
SION - Software Input On Field. 0b1..Force input path of pad WAKEUP 0b0..Input Path is determined by functionality
Definition at line 22831 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) |
Definition at line 22825 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT
| #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) |
Definition at line 22826 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) |
DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7
Definition at line 23025 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) |
Definition at line 23013 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) |
Definition at line 23014 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) |
HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled
Definition at line 23068 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) |
Definition at line 23062 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) |
Definition at line 23063 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) |
ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled
Definition at line 23038 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) |
Definition at line 23032 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) |
Definition at line 23033 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) |
PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled
Definition at line 23045 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) |
Definition at line 23039 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) |
Definition at line 23040 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) |
PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull
Definition at line 23052 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) |
Definition at line 23046 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) |
Definition at line 23047 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) |
PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up
Definition at line 23061 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) |
Definition at line 23053 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) |
Definition at line 23054 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) |
SPEED - Speed Field 0b10..medium(100MHz)
Definition at line 23031 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) |
Definition at line 23026 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) |
Definition at line 23027 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) |
SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate
Definition at line 23012 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) |
Definition at line 23006 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) |
Definition at line 23007 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) |
DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7
Definition at line 23159 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) |
Definition at line 23147 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) |
Definition at line 23148 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) |
HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled
Definition at line 23202 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) |
Definition at line 23196 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) |
Definition at line 23197 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) |
ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled
Definition at line 23172 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) |
Definition at line 23166 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) |
Definition at line 23167 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) |
PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled
Definition at line 23179 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) |
Definition at line 23173 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) |
Definition at line 23174 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) |
PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull
Definition at line 23186 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) |
Definition at line 23180 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) |
Definition at line 23181 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) |
PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up
Definition at line 23195 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) |
Definition at line 23187 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) |
Definition at line 23188 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) |
SPEED - Speed Field 0b10..medium(100MHz)
Definition at line 23165 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) |
Definition at line 23160 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) |
Definition at line 23161 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) |
SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate
Definition at line 23146 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) |
Definition at line 23140 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) |
Definition at line 23141 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK) |
DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7
Definition at line 23226 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U) |
Definition at line 23214 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U) |
Definition at line 23215 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) |
HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled
Definition at line 23269 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) |
Definition at line 23263 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) |
Definition at line 23264 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK) |
ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled
Definition at line 23239 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U) |
Definition at line 23233 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U) |
Definition at line 23234 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK) |
PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled
Definition at line 23246 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U) |
Definition at line 23240 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U) |
Definition at line 23241 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK) |
PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull
Definition at line 23253 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U) |
Definition at line 23247 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U) |
Definition at line 23248 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK) |
PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up
Definition at line 23262 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U) |
Definition at line 23254 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U) |
Definition at line 23255 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK) |
SPEED - Speed Field 0b10..medium(100MHz)
Definition at line 23232 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U) |
Definition at line 23227 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U) |
Definition at line 23228 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) |
SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate
Definition at line 23213 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) |
Definition at line 23207 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) |
Definition at line 23208 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) |
DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7
Definition at line 22958 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) |
Definition at line 22946 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) |
Definition at line 22947 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) |
HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled
Definition at line 23001 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) |
Definition at line 22995 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) |
Definition at line 22996 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) |
ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled
Definition at line 22971 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) |
Definition at line 22965 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) |
Definition at line 22966 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) |
PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled
Definition at line 22978 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) |
Definition at line 22972 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) |
Definition at line 22973 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) |
PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull
Definition at line 22985 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) |
Definition at line 22979 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) |
Definition at line 22980 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) |
PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up
Definition at line 22994 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) |
Definition at line 22986 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) |
Definition at line 22987 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) |
SPEED - Speed Field 0b10..medium(100MHz)
Definition at line 22964 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) |
Definition at line 22959 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) |
Definition at line 22960 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) |
SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate
Definition at line 22945 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) |
Definition at line 22939 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) |
Definition at line 22940 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) |
DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7
Definition at line 22891 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) |
Definition at line 22879 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) |
Definition at line 22880 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) |
HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled
Definition at line 22934 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) |
Definition at line 22928 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) |
Definition at line 22929 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) |
ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled
Definition at line 22904 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) |
Definition at line 22898 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) |
Definition at line 22899 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) |
PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled
Definition at line 22911 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) |
Definition at line 22905 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) |
Definition at line 22906 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) |
PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull
Definition at line 22918 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) |
Definition at line 22912 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) |
Definition at line 22913 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) |
PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up
Definition at line 22927 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) |
Definition at line 22919 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) |
Definition at line 22920 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) |
SPEED - Speed Field 0b10..medium(100MHz)
Definition at line 22897 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) |
Definition at line 22892 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) |
Definition at line 22893 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) |
SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate
Definition at line 22878 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) |
Definition at line 22872 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) |
Definition at line 22873 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK) |
DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7
Definition at line 23092 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U) |
Definition at line 23080 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U) |
Definition at line 23081 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) |
HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled
Definition at line 23135 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) |
Definition at line 23129 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) |
Definition at line 23130 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK) |
ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled
Definition at line 23105 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U) |
Definition at line 23099 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U) |
Definition at line 23100 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK) |
PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled
Definition at line 23112 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U) |
Definition at line 23106 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U) |
Definition at line 23107 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK) |
PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull
Definition at line 23119 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U) |
Definition at line 23113 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U) |
Definition at line 23114 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK) |
PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up
Definition at line 23128 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U) |
Definition at line 23120 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U) |
Definition at line 23121 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK) |
SPEED - Speed Field 0b10..medium(100MHz)
Definition at line 23098 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U) |
Definition at line 23093 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U) |
Definition at line 23094 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) |
SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate
Definition at line 23079 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) |
Definition at line 23073 of file MIMXRT1052.h.
◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT
| #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) |
Definition at line 23074 of file MIMXRT1052.h.