imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_CM7_H_GENERIC
32 #define __CORE_CM7_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 /* CMSIS CM7 definitions */
66 #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB)
68 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
69  __CM7_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (7U)
76 #if defined ( __CC_ARM )
77  #if defined __TARGET_FPU_VFP
78  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79  #define __FPU_USED 1U
80  #else
81  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82  #define __FPU_USED 0U
83  #endif
84  #else
85  #define __FPU_USED 0U
86  #endif
87 
88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89  #if defined __ARM_FP
90  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91  #define __FPU_USED 1U
92  #else
93  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94  #define __FPU_USED 0U
95  #endif
96  #else
97  #define __FPU_USED 0U
98  #endif
99 
100 #elif defined ( __GNUC__ )
101  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103  #define __FPU_USED 1U
104  #else
105  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #define __FPU_USED 0U
107  #endif
108  #else
109  #define __FPU_USED 0U
110  #endif
111 
112 #elif defined ( __ICCARM__ )
113  #if defined __ARMVFP__
114  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115  #define __FPU_USED 1U
116  #else
117  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118  #define __FPU_USED 0U
119  #endif
120  #else
121  #define __FPU_USED 0U
122  #endif
123 
124 #elif defined ( __TI_ARM__ )
125  #if defined __TI_VFP_SUPPORT__
126  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127  #define __FPU_USED 1U
128  #else
129  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130  #define __FPU_USED 0U
131  #endif
132  #else
133  #define __FPU_USED 0U
134  #endif
135 
136 #elif defined ( __TASKING__ )
137  #if defined __FPU_VFP__
138  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139  #define __FPU_USED 1U
140  #else
141  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142  #define __FPU_USED 0U
143  #endif
144  #else
145  #define __FPU_USED 0U
146  #endif
147 
148 #elif defined ( __CSMC__ )
149  #if ( __CSMC__ & 0x400U)
150  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151  #define __FPU_USED 1U
152  #else
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #define __FPU_USED 0U
155  #endif
156  #else
157  #define __FPU_USED 0U
158  #endif
159 
160 #endif
161 
162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
163 
164 
165 #ifdef __cplusplus
166 }
167 #endif
168 
169 #endif /* __CORE_CM7_H_GENERIC */
170 
171 #ifndef __CMSIS_GENERIC
172 
173 #ifndef __CORE_CM7_H_DEPENDANT
174 #define __CORE_CM7_H_DEPENDANT
175 
176 #ifdef __cplusplus
177  extern "C" {
178 #endif
179 
180 /* check device defines and use defaults */
181 #if defined __CHECK_DEVICE_DEFINES
182  #ifndef __CM7_REV
183  #define __CM7_REV 0x0000U
184  #warning "__CM7_REV not defined in device header file; using default!"
185  #endif
186 
187  #ifndef __FPU_PRESENT
188  #define __FPU_PRESENT 0U
189  #warning "__FPU_PRESENT not defined in device header file; using default!"
190  #endif
191 
192  #ifndef __MPU_PRESENT
193  #define __MPU_PRESENT 0U
194  #warning "__MPU_PRESENT not defined in device header file; using default!"
195  #endif
196 
197  #ifndef __ICACHE_PRESENT
198  #define __ICACHE_PRESENT 0U
199  #warning "__ICACHE_PRESENT not defined in device header file; using default!"
200  #endif
201 
202  #ifndef __DCACHE_PRESENT
203  #define __DCACHE_PRESENT 0U
204  #warning "__DCACHE_PRESENT not defined in device header file; using default!"
205  #endif
206 
207  #ifndef __DTCM_PRESENT
208  #define __DTCM_PRESENT 0U
209  #warning "__DTCM_PRESENT not defined in device header file; using default!"
210  #endif
211 
212  #ifndef __NVIC_PRIO_BITS
213  #define __NVIC_PRIO_BITS 3U
214  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
215  #endif
216 
217  #ifndef __Vendor_SysTickConfig
218  #define __Vendor_SysTickConfig 0U
219  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
220  #endif
221 #endif
222 
223 /* IO definitions (access restrictions to peripheral registers) */
231 #ifdef __cplusplus
232  #define __I volatile
233 #else
234  #define __I volatile const
235 #endif
236 #define __O volatile
237 #define __IO volatile
239 /* following defines should be used for structure members */
240 #define __IM volatile const
241 #define __OM volatile
242 #define __IOM volatile
244 
248 /*******************************************************************************
249  * Register Abstraction
250  Core Register contain:
251  - Core Register
252  - Core NVIC Register
253  - Core SCB Register
254  - Core SysTick Register
255  - Core Debug Register
256  - Core MPU Register
257  - Core FPU Register
258  ******************************************************************************/
259 
274 typedef union
275 {
276  struct
277  {
278  uint32_t _reserved0:16;
279  uint32_t GE:4;
280  uint32_t _reserved1:7;
281  uint32_t Q:1;
282  uint32_t V:1;
283  uint32_t C:1;
284  uint32_t Z:1;
285  uint32_t N:1;
286  } b;
287  uint32_t w;
288 } APSR_Type;
289 
290 /* APSR Register Definitions */
291 #define APSR_N_Pos 31U
292 #define APSR_N_Msk (1UL << APSR_N_Pos)
294 #define APSR_Z_Pos 30U
295 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
297 #define APSR_C_Pos 29U
298 #define APSR_C_Msk (1UL << APSR_C_Pos)
300 #define APSR_V_Pos 28U
301 #define APSR_V_Msk (1UL << APSR_V_Pos)
303 #define APSR_Q_Pos 27U
304 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
306 #define APSR_GE_Pos 16U
307 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
313 typedef union
314 {
315  struct
316  {
317  uint32_t ISR:9;
318  uint32_t _reserved0:23;
319  } b;
320  uint32_t w;
321 } IPSR_Type;
322 
323 /* IPSR Register Definitions */
324 #define IPSR_ISR_Pos 0U
325 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
331 typedef union
332 {
333  struct
334  {
335  uint32_t ISR:9;
336  uint32_t _reserved0:1;
337  uint32_t ICI_IT_1:6;
338  uint32_t GE:4;
339  uint32_t _reserved1:4;
340  uint32_t T:1;
341  uint32_t ICI_IT_2:2;
342  uint32_t Q:1;
343  uint32_t V:1;
344  uint32_t C:1;
345  uint32_t Z:1;
346  uint32_t N:1;
347  } b;
348  uint32_t w;
349 } xPSR_Type;
350 
351 /* xPSR Register Definitions */
352 #define xPSR_N_Pos 31U
353 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
355 #define xPSR_Z_Pos 30U
356 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
358 #define xPSR_C_Pos 29U
359 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
361 #define xPSR_V_Pos 28U
362 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
364 #define xPSR_Q_Pos 27U
365 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
367 #define xPSR_ICI_IT_2_Pos 25U
368 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
370 #define xPSR_T_Pos 24U
371 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
373 #define xPSR_GE_Pos 16U
374 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
376 #define xPSR_ICI_IT_1_Pos 10U
377 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
379 #define xPSR_ISR_Pos 0U
380 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
386 typedef union
387 {
388  struct
389  {
390  uint32_t nPRIV:1;
391  uint32_t SPSEL:1;
392  uint32_t FPCA:1;
393  uint32_t _reserved0:29;
394  } b;
395  uint32_t w;
396 } CONTROL_Type;
397 
398 /* CONTROL Register Definitions */
399 #define CONTROL_FPCA_Pos 2U
400 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
402 #define CONTROL_SPSEL_Pos 1U
403 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
405 #define CONTROL_nPRIV_Pos 0U
406 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
408 
421 typedef struct
422 {
423  __IOM uint32_t ISER[8U];
424  uint32_t RESERVED0[24U];
425  __IOM uint32_t ICER[8U];
426  uint32_t RESERVED1[24U];
427  __IOM uint32_t ISPR[8U];
428  uint32_t RESERVED2[24U];
429  __IOM uint32_t ICPR[8U];
430  uint32_t RESERVED3[24U];
431  __IOM uint32_t IABR[8U];
432  uint32_t RESERVED4[56U];
433  __IOM uint8_t IP[240U];
434  uint32_t RESERVED5[644U];
435  __OM uint32_t STIR;
436 } NVIC_Type;
437 
438 /* Software Triggered Interrupt Register Definitions */
439 #define NVIC_STIR_INTID_Pos 0U
440 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
442 
455 typedef struct
456 {
457  __IM uint32_t CPUID;
458  __IOM uint32_t ICSR;
459  __IOM uint32_t VTOR;
460  __IOM uint32_t AIRCR;
461  __IOM uint32_t SCR;
462  __IOM uint32_t CCR;
463  __IOM uint8_t SHPR[12U];
464  __IOM uint32_t SHCSR;
465  __IOM uint32_t CFSR;
466  __IOM uint32_t HFSR;
467  __IOM uint32_t DFSR;
468  __IOM uint32_t MMFAR;
469  __IOM uint32_t BFAR;
470  __IOM uint32_t AFSR;
471  __IM uint32_t ID_PFR[2U];
472  __IM uint32_t ID_DFR;
473  __IM uint32_t ID_AFR;
474  __IM uint32_t ID_MFR[4U];
475  __IM uint32_t ID_ISAR[5U];
476  uint32_t RESERVED0[1U];
477  __IM uint32_t CLIDR;
478  __IM uint32_t CTR;
479  __IM uint32_t CCSIDR;
480  __IOM uint32_t CSSELR;
481  __IOM uint32_t CPACR;
482  uint32_t RESERVED3[93U];
483  __OM uint32_t STIR;
484  uint32_t RESERVED4[15U];
485  __IM uint32_t MVFR0;
486  __IM uint32_t MVFR1;
487  __IM uint32_t MVFR2;
488  uint32_t RESERVED5[1U];
489  __OM uint32_t ICIALLU;
490  uint32_t RESERVED6[1U];
491  __OM uint32_t ICIMVAU;
492  __OM uint32_t DCIMVAC;
493  __OM uint32_t DCISW;
494  __OM uint32_t DCCMVAU;
495  __OM uint32_t DCCMVAC;
496  __OM uint32_t DCCSW;
497  __OM uint32_t DCCIMVAC;
498  __OM uint32_t DCCISW;
499  uint32_t RESERVED7[6U];
500  __IOM uint32_t ITCMCR;
501  __IOM uint32_t DTCMCR;
502  __IOM uint32_t AHBPCR;
503  __IOM uint32_t CACR;
504  __IOM uint32_t AHBSCR;
505  uint32_t RESERVED8[1U];
506  __IOM uint32_t ABFSR;
507 } SCB_Type;
508 
509 /* SCB CPUID Register Definitions */
510 #define SCB_CPUID_IMPLEMENTER_Pos 24U
511 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
513 #define SCB_CPUID_VARIANT_Pos 20U
514 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
516 #define SCB_CPUID_ARCHITECTURE_Pos 16U
517 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
519 #define SCB_CPUID_PARTNO_Pos 4U
520 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
522 #define SCB_CPUID_REVISION_Pos 0U
523 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
525 /* SCB Interrupt Control State Register Definitions */
526 #define SCB_ICSR_NMIPENDSET_Pos 31U
527 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
529 #define SCB_ICSR_PENDSVSET_Pos 28U
530 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
532 #define SCB_ICSR_PENDSVCLR_Pos 27U
533 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
535 #define SCB_ICSR_PENDSTSET_Pos 26U
536 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
538 #define SCB_ICSR_PENDSTCLR_Pos 25U
539 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
541 #define SCB_ICSR_ISRPREEMPT_Pos 23U
542 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
544 #define SCB_ICSR_ISRPENDING_Pos 22U
545 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
547 #define SCB_ICSR_VECTPENDING_Pos 12U
548 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
550 #define SCB_ICSR_RETTOBASE_Pos 11U
551 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
553 #define SCB_ICSR_VECTACTIVE_Pos 0U
554 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
556 /* SCB Vector Table Offset Register Definitions */
557 #define SCB_VTOR_TBLOFF_Pos 7U
558 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
560 /* SCB Application Interrupt and Reset Control Register Definitions */
561 #define SCB_AIRCR_VECTKEY_Pos 16U
562 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
564 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
565 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
567 #define SCB_AIRCR_ENDIANESS_Pos 15U
568 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
570 #define SCB_AIRCR_PRIGROUP_Pos 8U
571 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
573 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
574 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
576 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
577 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
579 #define SCB_AIRCR_VECTRESET_Pos 0U
580 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
582 /* SCB System Control Register Definitions */
583 #define SCB_SCR_SEVONPEND_Pos 4U
584 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
586 #define SCB_SCR_SLEEPDEEP_Pos 2U
587 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
589 #define SCB_SCR_SLEEPONEXIT_Pos 1U
590 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
592 /* SCB Configuration Control Register Definitions */
593 #define SCB_CCR_BP_Pos 18U
594 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
596 #define SCB_CCR_IC_Pos 17U
597 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
599 #define SCB_CCR_DC_Pos 16U
600 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
602 #define SCB_CCR_STKALIGN_Pos 9U
603 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
605 #define SCB_CCR_BFHFNMIGN_Pos 8U
606 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
608 #define SCB_CCR_DIV_0_TRP_Pos 4U
609 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
611 #define SCB_CCR_UNALIGN_TRP_Pos 3U
612 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
614 #define SCB_CCR_USERSETMPEND_Pos 1U
615 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
617 #define SCB_CCR_NONBASETHRDENA_Pos 0U
618 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
620 /* SCB System Handler Control and State Register Definitions */
621 #define SCB_SHCSR_USGFAULTENA_Pos 18U
622 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
624 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
625 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
627 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
628 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
630 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
631 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
633 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
634 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
636 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
637 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
639 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
640 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
642 #define SCB_SHCSR_SYSTICKACT_Pos 11U
643 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
645 #define SCB_SHCSR_PENDSVACT_Pos 10U
646 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
648 #define SCB_SHCSR_MONITORACT_Pos 8U
649 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
651 #define SCB_SHCSR_SVCALLACT_Pos 7U
652 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
654 #define SCB_SHCSR_USGFAULTACT_Pos 3U
655 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
657 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
658 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
660 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
661 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
663 /* SCB Configurable Fault Status Register Definitions */
664 #define SCB_CFSR_USGFAULTSR_Pos 16U
665 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
667 #define SCB_CFSR_BUSFAULTSR_Pos 8U
668 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
670 #define SCB_CFSR_MEMFAULTSR_Pos 0U
671 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
673 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
674 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
675 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
677 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
678 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
680 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
681 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
683 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
684 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
686 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
687 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
689 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
690 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
692 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
693 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
694 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
696 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
697 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
699 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
700 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
702 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
703 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
705 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
706 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
708 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
709 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
711 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
712 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
714 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
715 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
716 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
718 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
719 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
721 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
722 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
724 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
725 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
727 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
728 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
730 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
731 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
733 /* SCB Hard Fault Status Register Definitions */
734 #define SCB_HFSR_DEBUGEVT_Pos 31U
735 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
737 #define SCB_HFSR_FORCED_Pos 30U
738 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
740 #define SCB_HFSR_VECTTBL_Pos 1U
741 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
743 /* SCB Debug Fault Status Register Definitions */
744 #define SCB_DFSR_EXTERNAL_Pos 4U
745 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
747 #define SCB_DFSR_VCATCH_Pos 3U
748 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
750 #define SCB_DFSR_DWTTRAP_Pos 2U
751 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
753 #define SCB_DFSR_BKPT_Pos 1U
754 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
756 #define SCB_DFSR_HALTED_Pos 0U
757 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
759 /* SCB Cache Level ID Register Definitions */
760 #define SCB_CLIDR_LOUU_Pos 27U
761 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
763 #define SCB_CLIDR_LOC_Pos 24U
764 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
766 /* SCB Cache Type Register Definitions */
767 #define SCB_CTR_FORMAT_Pos 29U
768 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
770 #define SCB_CTR_CWG_Pos 24U
771 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
773 #define SCB_CTR_ERG_Pos 20U
774 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
776 #define SCB_CTR_DMINLINE_Pos 16U
777 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
779 #define SCB_CTR_IMINLINE_Pos 0U
780 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
782 /* SCB Cache Size ID Register Definitions */
783 #define SCB_CCSIDR_WT_Pos 31U
784 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
786 #define SCB_CCSIDR_WB_Pos 30U
787 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
789 #define SCB_CCSIDR_RA_Pos 29U
790 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
792 #define SCB_CCSIDR_WA_Pos 28U
793 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
795 #define SCB_CCSIDR_NUMSETS_Pos 13U
796 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
798 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
799 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
801 #define SCB_CCSIDR_LINESIZE_Pos 0U
802 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
804 /* SCB Cache Size Selection Register Definitions */
805 #define SCB_CSSELR_LEVEL_Pos 1U
806 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
808 #define SCB_CSSELR_IND_Pos 0U
809 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
811 /* SCB Software Triggered Interrupt Register Definitions */
812 #define SCB_STIR_INTID_Pos 0U
813 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
815 /* SCB D-Cache Invalidate by Set-way Register Definitions */
816 #define SCB_DCISW_WAY_Pos 30U
817 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
819 #define SCB_DCISW_SET_Pos 5U
820 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
822 /* SCB D-Cache Clean by Set-way Register Definitions */
823 #define SCB_DCCSW_WAY_Pos 30U
824 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
826 #define SCB_DCCSW_SET_Pos 5U
827 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
829 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
830 #define SCB_DCCISW_WAY_Pos 30U
831 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
833 #define SCB_DCCISW_SET_Pos 5U
834 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
836 /* Instruction Tightly-Coupled Memory Control Register Definitions */
837 #define SCB_ITCMCR_SZ_Pos 3U
838 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
840 #define SCB_ITCMCR_RETEN_Pos 2U
841 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
843 #define SCB_ITCMCR_RMW_Pos 1U
844 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
846 #define SCB_ITCMCR_EN_Pos 0U
847 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
849 /* Data Tightly-Coupled Memory Control Register Definitions */
850 #define SCB_DTCMCR_SZ_Pos 3U
851 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
853 #define SCB_DTCMCR_RETEN_Pos 2U
854 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
856 #define SCB_DTCMCR_RMW_Pos 1U
857 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
859 #define SCB_DTCMCR_EN_Pos 0U
860 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
862 /* AHBP Control Register Definitions */
863 #define SCB_AHBPCR_SZ_Pos 1U
864 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
866 #define SCB_AHBPCR_EN_Pos 0U
867 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
869 /* L1 Cache Control Register Definitions */
870 #define SCB_CACR_FORCEWT_Pos 2U
871 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
873 #define SCB_CACR_ECCEN_Pos 1U
874 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
876 #define SCB_CACR_SIWT_Pos 0U
877 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
879 /* AHBS Control Register Definitions */
880 #define SCB_AHBSCR_INITCOUNT_Pos 11U
881 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
883 #define SCB_AHBSCR_TPRI_Pos 2U
884 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
886 #define SCB_AHBSCR_CTL_Pos 0U
887 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
889 /* Auxiliary Bus Fault Status Register Definitions */
890 #define SCB_ABFSR_AXIMTYPE_Pos 8U
891 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
893 #define SCB_ABFSR_EPPB_Pos 4U
894 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
896 #define SCB_ABFSR_AXIM_Pos 3U
897 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
899 #define SCB_ABFSR_AHBP_Pos 2U
900 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
902 #define SCB_ABFSR_DTCM_Pos 1U
903 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
905 #define SCB_ABFSR_ITCM_Pos 0U
906 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
908 
921 typedef struct
922 {
923  uint32_t RESERVED0[1U];
924  __IM uint32_t ICTR;
925  __IOM uint32_t ACTLR;
926 } SCnSCB_Type;
927 
928 /* Interrupt Controller Type Register Definitions */
929 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
930 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
932 /* Auxiliary Control Register Definitions */
933 #define SCnSCB_ACTLR_DISDYNADD_Pos 26U
934 #define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)
936 #define SCnSCB_ACTLR_DISISSCH1_Pos 21U
937 #define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)
939 #define SCnSCB_ACTLR_DISDI_Pos 16U
940 #define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)
942 #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U
943 #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)
945 #define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U
946 #define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)
948 #define SCnSCB_ACTLR_DISBTACREAD_Pos 13U
949 #define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)
951 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U
952 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)
954 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U
955 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)
957 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U
958 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)
960 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
961 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
963 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
964 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
966 
979 typedef struct
980 {
981  __IOM uint32_t CTRL;
982  __IOM uint32_t LOAD;
983  __IOM uint32_t VAL;
984  __IM uint32_t CALIB;
985 } SysTick_Type;
986 
987 /* SysTick Control / Status Register Definitions */
988 #define SysTick_CTRL_COUNTFLAG_Pos 16U
989 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
991 #define SysTick_CTRL_CLKSOURCE_Pos 2U
992 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
994 #define SysTick_CTRL_TICKINT_Pos 1U
995 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
997 #define SysTick_CTRL_ENABLE_Pos 0U
998 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1000 /* SysTick Reload Register Definitions */
1001 #define SysTick_LOAD_RELOAD_Pos 0U
1002 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1004 /* SysTick Current Register Definitions */
1005 #define SysTick_VAL_CURRENT_Pos 0U
1006 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1008 /* SysTick Calibration Register Definitions */
1009 #define SysTick_CALIB_NOREF_Pos 31U
1010 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1012 #define SysTick_CALIB_SKEW_Pos 30U
1013 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1015 #define SysTick_CALIB_TENMS_Pos 0U
1016 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1018 
1031 typedef struct
1032 {
1033  __OM union
1034  {
1035  __OM uint8_t u8;
1036  __OM uint16_t u16;
1037  __OM uint32_t u32;
1038  } PORT [32U];
1039  uint32_t RESERVED0[864U];
1040  __IOM uint32_t TER;
1041  uint32_t RESERVED1[15U];
1042  __IOM uint32_t TPR;
1043  uint32_t RESERVED2[15U];
1044  __IOM uint32_t TCR;
1045  uint32_t RESERVED3[32U];
1046  uint32_t RESERVED4[43U];
1047  __OM uint32_t LAR;
1048  __IM uint32_t LSR;
1049  uint32_t RESERVED5[6U];
1050  __IM uint32_t PID4;
1051  __IM uint32_t PID5;
1052  __IM uint32_t PID6;
1053  __IM uint32_t PID7;
1054  __IM uint32_t PID0;
1055  __IM uint32_t PID1;
1056  __IM uint32_t PID2;
1057  __IM uint32_t PID3;
1058  __IM uint32_t CID0;
1059  __IM uint32_t CID1;
1060  __IM uint32_t CID2;
1061  __IM uint32_t CID3;
1062 } ITM_Type;
1063 
1064 /* ITM Trace Privilege Register Definitions */
1065 #define ITM_TPR_PRIVMASK_Pos 0U
1066 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1068 /* ITM Trace Control Register Definitions */
1069 #define ITM_TCR_BUSY_Pos 23U
1070 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1072 #define ITM_TCR_TraceBusID_Pos 16U
1073 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
1075 #define ITM_TCR_GTSFREQ_Pos 10U
1076 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1078 #define ITM_TCR_TSPrescale_Pos 8U
1079 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
1081 #define ITM_TCR_SWOENA_Pos 4U
1082 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1084 #define ITM_TCR_DWTENA_Pos 3U
1085 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1087 #define ITM_TCR_SYNCENA_Pos 2U
1088 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1090 #define ITM_TCR_TSENA_Pos 1U
1091 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1093 #define ITM_TCR_ITMENA_Pos 0U
1094 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1096 /* ITM Lock Status Register Definitions */
1097 #define ITM_LSR_ByteAcc_Pos 2U
1098 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1100 #define ITM_LSR_Access_Pos 1U
1101 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1103 #define ITM_LSR_Present_Pos 0U
1104 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1106  /* end of group CMSIS_ITM */
1107 
1108 
1119 typedef struct
1120 {
1121  __IOM uint32_t CTRL;
1122  __IOM uint32_t CYCCNT;
1123  __IOM uint32_t CPICNT;
1124  __IOM uint32_t EXCCNT;
1125  __IOM uint32_t SLEEPCNT;
1126  __IOM uint32_t LSUCNT;
1127  __IOM uint32_t FOLDCNT;
1128  __IM uint32_t PCSR;
1129  __IOM uint32_t COMP0;
1130  __IOM uint32_t MASK0;
1131  __IOM uint32_t FUNCTION0;
1132  uint32_t RESERVED0[1U];
1133  __IOM uint32_t COMP1;
1134  __IOM uint32_t MASK1;
1135  __IOM uint32_t FUNCTION1;
1136  uint32_t RESERVED1[1U];
1137  __IOM uint32_t COMP2;
1138  __IOM uint32_t MASK2;
1139  __IOM uint32_t FUNCTION2;
1140  uint32_t RESERVED2[1U];
1141  __IOM uint32_t COMP3;
1142  __IOM uint32_t MASK3;
1143  __IOM uint32_t FUNCTION3;
1144  uint32_t RESERVED3[981U];
1145  __OM uint32_t LAR;
1146  __IM uint32_t LSR;
1147 } DWT_Type;
1148 
1149 /* DWT Control Register Definitions */
1150 #define DWT_CTRL_NUMCOMP_Pos 28U
1151 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1153 #define DWT_CTRL_NOTRCPKT_Pos 27U
1154 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1156 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1157 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1159 #define DWT_CTRL_NOCYCCNT_Pos 25U
1160 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1162 #define DWT_CTRL_NOPRFCNT_Pos 24U
1163 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1165 #define DWT_CTRL_CYCEVTENA_Pos 22U
1166 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1168 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1169 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1171 #define DWT_CTRL_LSUEVTENA_Pos 20U
1172 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1174 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1175 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1177 #define DWT_CTRL_EXCEVTENA_Pos 18U
1178 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1180 #define DWT_CTRL_CPIEVTENA_Pos 17U
1181 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1183 #define DWT_CTRL_EXCTRCENA_Pos 16U
1184 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1186 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1187 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1189 #define DWT_CTRL_SYNCTAP_Pos 10U
1190 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1192 #define DWT_CTRL_CYCTAP_Pos 9U
1193 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1195 #define DWT_CTRL_POSTINIT_Pos 5U
1196 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1198 #define DWT_CTRL_POSTPRESET_Pos 1U
1199 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1201 #define DWT_CTRL_CYCCNTENA_Pos 0U
1202 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1204 /* DWT CPI Count Register Definitions */
1205 #define DWT_CPICNT_CPICNT_Pos 0U
1206 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1208 /* DWT Exception Overhead Count Register Definitions */
1209 #define DWT_EXCCNT_EXCCNT_Pos 0U
1210 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1212 /* DWT Sleep Count Register Definitions */
1213 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1214 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1216 /* DWT LSU Count Register Definitions */
1217 #define DWT_LSUCNT_LSUCNT_Pos 0U
1218 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1220 /* DWT Folded-instruction Count Register Definitions */
1221 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1222 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1224 /* DWT Comparator Mask Register Definitions */
1225 #define DWT_MASK_MASK_Pos 0U
1226 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
1228 /* DWT Comparator Function Register Definitions */
1229 #define DWT_FUNCTION_MATCHED_Pos 24U
1230 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1232 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
1233 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1235 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
1236 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1238 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1239 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1241 #define DWT_FUNCTION_LNK1ENA_Pos 9U
1242 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1244 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
1245 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1247 #define DWT_FUNCTION_CYCMATCH_Pos 7U
1248 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1250 #define DWT_FUNCTION_EMITRANGE_Pos 5U
1251 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1253 #define DWT_FUNCTION_FUNCTION_Pos 0U
1254 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
1256  /* end of group CMSIS_DWT */
1257 
1258 
1269 typedef struct
1270 {
1271  __IM uint32_t SSPSR;
1272  __IOM uint32_t CSPSR;
1273  uint32_t RESERVED0[2U];
1274  __IOM uint32_t ACPR;
1275  uint32_t RESERVED1[55U];
1276  __IOM uint32_t SPPR;
1277  uint32_t RESERVED2[131U];
1278  __IM uint32_t FFSR;
1279  __IOM uint32_t FFCR;
1280  __IM uint32_t FSCR;
1281  uint32_t RESERVED3[759U];
1282  __IM uint32_t TRIGGER;
1283  __IM uint32_t FIFO0;
1284  __IM uint32_t ITATBCTR2;
1285  uint32_t RESERVED4[1U];
1286  __IM uint32_t ITATBCTR0;
1287  __IM uint32_t FIFO1;
1288  __IOM uint32_t ITCTRL;
1289  uint32_t RESERVED5[39U];
1290  __IOM uint32_t CLAIMSET;
1291  __IOM uint32_t CLAIMCLR;
1292  uint32_t RESERVED7[8U];
1293  __IM uint32_t DEVID;
1294  __IM uint32_t DEVTYPE;
1295 } TPI_Type;
1296 
1297 /* TPI Asynchronous Clock Prescaler Register Definitions */
1298 #define TPI_ACPR_PRESCALER_Pos 0U
1299 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1301 /* TPI Selected Pin Protocol Register Definitions */
1302 #define TPI_SPPR_TXMODE_Pos 0U
1303 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1305 /* TPI Formatter and Flush Status Register Definitions */
1306 #define TPI_FFSR_FtNonStop_Pos 3U
1307 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1309 #define TPI_FFSR_TCPresent_Pos 2U
1310 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1312 #define TPI_FFSR_FtStopped_Pos 1U
1313 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1315 #define TPI_FFSR_FlInProg_Pos 0U
1316 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1318 /* TPI Formatter and Flush Control Register Definitions */
1319 #define TPI_FFCR_TrigIn_Pos 8U
1320 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1322 #define TPI_FFCR_EnFCont_Pos 1U
1323 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1325 /* TPI TRIGGER Register Definitions */
1326 #define TPI_TRIGGER_TRIGGER_Pos 0U
1327 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1329 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1330 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1331 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
1333 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1334 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1336 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1337 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
1339 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1340 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1342 #define TPI_FIFO0_ETM2_Pos 16U
1343 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1345 #define TPI_FIFO0_ETM1_Pos 8U
1346 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1348 #define TPI_FIFO0_ETM0_Pos 0U
1349 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1351 /* TPI ITATBCTR2 Register Definitions */
1352 #define TPI_ITATBCTR2_ATREADY2_Pos 0U
1353 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
1355 #define TPI_ITATBCTR2_ATREADY1_Pos 0U
1356 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
1358 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1359 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1360 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
1362 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1363 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1365 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1366 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
1368 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1369 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1371 #define TPI_FIFO1_ITM2_Pos 16U
1372 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1374 #define TPI_FIFO1_ITM1_Pos 8U
1375 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1377 #define TPI_FIFO1_ITM0_Pos 0U
1378 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1380 /* TPI ITATBCTR0 Register Definitions */
1381 #define TPI_ITATBCTR0_ATREADY2_Pos 0U
1382 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
1384 #define TPI_ITATBCTR0_ATREADY1_Pos 0U
1385 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
1387 /* TPI Integration Mode Control Register Definitions */
1388 #define TPI_ITCTRL_Mode_Pos 0U
1389 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1391 /* TPI DEVID Register Definitions */
1392 #define TPI_DEVID_NRZVALID_Pos 11U
1393 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1395 #define TPI_DEVID_MANCVALID_Pos 10U
1396 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1398 #define TPI_DEVID_PTINVALID_Pos 9U
1399 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1401 #define TPI_DEVID_MinBufSz_Pos 6U
1402 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1404 #define TPI_DEVID_AsynClkIn_Pos 5U
1405 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1407 #define TPI_DEVID_NrTraceInput_Pos 0U
1408 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1410 /* TPI DEVTYPE Register Definitions */
1411 #define TPI_DEVTYPE_SubType_Pos 4U
1412 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1414 #define TPI_DEVTYPE_MajorType_Pos 0U
1415 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1417  /* end of group CMSIS_TPI */
1418 
1419 
1420 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1421 
1431 typedef struct
1432 {
1433  __IM uint32_t TYPE;
1434  __IOM uint32_t CTRL;
1435  __IOM uint32_t RNR;
1436  __IOM uint32_t RBAR;
1437  __IOM uint32_t RASR;
1438  __IOM uint32_t RBAR_A1;
1439  __IOM uint32_t RASR_A1;
1440  __IOM uint32_t RBAR_A2;
1441  __IOM uint32_t RASR_A2;
1442  __IOM uint32_t RBAR_A3;
1443  __IOM uint32_t RASR_A3;
1444 } MPU_Type;
1445 
1446 #define MPU_TYPE_RALIASES 4U
1447 
1448 /* MPU Type Register Definitions */
1449 #define MPU_TYPE_IREGION_Pos 16U
1450 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1452 #define MPU_TYPE_DREGION_Pos 8U
1453 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1455 #define MPU_TYPE_SEPARATE_Pos 0U
1456 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1458 /* MPU Control Register Definitions */
1459 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1460 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1462 #define MPU_CTRL_HFNMIENA_Pos 1U
1463 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1465 #define MPU_CTRL_ENABLE_Pos 0U
1466 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1468 /* MPU Region Number Register Definitions */
1469 #define MPU_RNR_REGION_Pos 0U
1470 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1472 /* MPU Region Base Address Register Definitions */
1473 #define MPU_RBAR_ADDR_Pos 5U
1474 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1476 #define MPU_RBAR_VALID_Pos 4U
1477 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1479 #define MPU_RBAR_REGION_Pos 0U
1480 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1482 /* MPU Region Attribute and Size Register Definitions */
1483 #define MPU_RASR_ATTRS_Pos 16U
1484 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1486 #define MPU_RASR_XN_Pos 28U
1487 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1489 #define MPU_RASR_AP_Pos 24U
1490 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1492 #define MPU_RASR_TEX_Pos 19U
1493 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1495 #define MPU_RASR_S_Pos 18U
1496 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1498 #define MPU_RASR_C_Pos 17U
1499 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1501 #define MPU_RASR_B_Pos 16U
1502 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1504 #define MPU_RASR_SRD_Pos 8U
1505 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1507 #define MPU_RASR_SIZE_Pos 1U
1508 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1510 #define MPU_RASR_ENABLE_Pos 0U
1511 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1513 
1514 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1515 
1516 
1527 typedef struct
1528 {
1529  uint32_t RESERVED0[1U];
1530  __IOM uint32_t FPCCR;
1531  __IOM uint32_t FPCAR;
1532  __IOM uint32_t FPDSCR;
1533  __IM uint32_t MVFR0;
1534  __IM uint32_t MVFR1;
1535  __IM uint32_t MVFR2;
1536 } FPU_Type;
1537 
1538 /* Floating-Point Context Control Register Definitions */
1539 #define FPU_FPCCR_ASPEN_Pos 31U
1540 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1542 #define FPU_FPCCR_LSPEN_Pos 30U
1543 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1545 #define FPU_FPCCR_MONRDY_Pos 8U
1546 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1548 #define FPU_FPCCR_BFRDY_Pos 6U
1549 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1551 #define FPU_FPCCR_MMRDY_Pos 5U
1552 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1554 #define FPU_FPCCR_HFRDY_Pos 4U
1555 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1557 #define FPU_FPCCR_THREAD_Pos 3U
1558 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1560 #define FPU_FPCCR_USER_Pos 1U
1561 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1563 #define FPU_FPCCR_LSPACT_Pos 0U
1564 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1566 /* Floating-Point Context Address Register Definitions */
1567 #define FPU_FPCAR_ADDRESS_Pos 3U
1568 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1570 /* Floating-Point Default Status Control Register Definitions */
1571 #define FPU_FPDSCR_AHP_Pos 26U
1572 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1574 #define FPU_FPDSCR_DN_Pos 25U
1575 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1577 #define FPU_FPDSCR_FZ_Pos 24U
1578 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1580 #define FPU_FPDSCR_RMode_Pos 22U
1581 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1583 /* Media and FP Feature Register 0 Definitions */
1584 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1585 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1587 #define FPU_MVFR0_Short_vectors_Pos 24U
1588 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1590 #define FPU_MVFR0_Square_root_Pos 20U
1591 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1593 #define FPU_MVFR0_Divide_Pos 16U
1594 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1596 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1597 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1599 #define FPU_MVFR0_Double_precision_Pos 8U
1600 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1602 #define FPU_MVFR0_Single_precision_Pos 4U
1603 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1605 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1606 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1608 /* Media and FP Feature Register 1 Definitions */
1609 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1610 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1612 #define FPU_MVFR1_FP_HPFP_Pos 24U
1613 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1615 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1616 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1618 #define FPU_MVFR1_FtZ_mode_Pos 0U
1619 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1621 /* Media and FP Feature Register 2 Definitions */
1622 
1623 #define FPU_MVFR2_VFP_Misc_Pos 4U
1624 #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
1626 
1639 typedef struct
1640 {
1641  __IOM uint32_t DHCSR;
1642  __OM uint32_t DCRSR;
1643  __IOM uint32_t DCRDR;
1644  __IOM uint32_t DEMCR;
1645 } CoreDebug_Type;
1646 
1647 /* Debug Halting Control and Status Register Definitions */
1648 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1649 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1651 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1652 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1654 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1655 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1657 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1658 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1660 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1661 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1663 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1664 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1666 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1667 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1669 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1670 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1672 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1673 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1675 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1676 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1678 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1679 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1681 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1682 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1684 /* Debug Core Register Selector Register Definitions */
1685 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1686 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1688 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1689 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1691 /* Debug Exception and Monitor Control Register Definitions */
1692 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1693 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1695 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1696 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1698 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1699 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1701 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1702 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1704 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1705 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1707 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1708 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1710 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1711 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1713 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1714 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1716 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1717 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1719 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1720 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1722 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1723 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1725 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1726 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1728 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1729 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1731 
1747 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1748 
1755 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1756 
1767 /* Memory mapping of Core Hardware */
1768 #define SCS_BASE (0xE000E000UL)
1769 #define ITM_BASE (0xE0000000UL)
1770 #define DWT_BASE (0xE0001000UL)
1771 #define TPI_BASE (0xE0040000UL)
1772 #define CoreDebug_BASE (0xE000EDF0UL)
1773 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1774 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1775 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1777 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1778 #define SCB ((SCB_Type *) SCB_BASE )
1779 #define SysTick ((SysTick_Type *) SysTick_BASE )
1780 #define NVIC ((NVIC_Type *) NVIC_BASE )
1781 #define ITM ((ITM_Type *) ITM_BASE )
1782 #define DWT ((DWT_Type *) DWT_BASE )
1783 #define TPI ((TPI_Type *) TPI_BASE )
1784 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1786 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1787  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1788  #define MPU ((MPU_Type *) MPU_BASE )
1789 #endif
1790 
1791 #define FPU_BASE (SCS_BASE + 0x0F30UL)
1792 #define FPU ((FPU_Type *) FPU_BASE )
1794 
1798 /*******************************************************************************
1799  * Hardware Abstraction Layer
1800  Core Function Interface contains:
1801  - Core NVIC Functions
1802  - Core SysTick Functions
1803  - Core Debug Functions
1804  - Core Register Access Functions
1805  ******************************************************************************/
1806 
1812 /* ########################## NVIC functions #################################### */
1820 #ifdef CMSIS_NVIC_VIRTUAL
1821  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1822  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1823  #endif
1824  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1825 #else
1826  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1827  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1828  #define NVIC_EnableIRQ __NVIC_EnableIRQ
1829  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1830  #define NVIC_DisableIRQ __NVIC_DisableIRQ
1831  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1832  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1833  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1834  #define NVIC_GetActive __NVIC_GetActive
1835  #define NVIC_SetPriority __NVIC_SetPriority
1836  #define NVIC_GetPriority __NVIC_GetPriority
1837  #define NVIC_SystemReset __NVIC_SystemReset
1838 #endif /* CMSIS_NVIC_VIRTUAL */
1839 
1840 #ifdef CMSIS_VECTAB_VIRTUAL
1841  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1842  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1843  #endif
1844  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1845 #else
1846  #define NVIC_SetVector __NVIC_SetVector
1847  #define NVIC_GetVector __NVIC_GetVector
1848 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1849 
1850 #define NVIC_USER_IRQ_OFFSET 16
1851 
1852 
1853 /* The following EXC_RETURN values are saved the LR on exception entry */
1854 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1855 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1856 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1857 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1858 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1859 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1860 
1861 
1871 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1872 {
1873  uint32_t reg_value;
1874  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1875 
1876  reg_value = SCB->AIRCR; /* read old register configuration */
1877  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1878  reg_value = (reg_value |
1879  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1880  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1881  SCB->AIRCR = reg_value;
1882 }
1883 
1884 
1890 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1891 {
1892  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1893 }
1894 
1895 
1902 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1903 {
1904  if ((int32_t)(IRQn) >= 0)
1905  {
1906  __COMPILER_BARRIER();
1907  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1908  __COMPILER_BARRIER();
1909  }
1910 }
1911 
1912 
1921 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1922 {
1923  if ((int32_t)(IRQn) >= 0)
1924  {
1925  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1926  }
1927  else
1928  {
1929  return(0U);
1930  }
1931 }
1932 
1933 
1940 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1941 {
1942  if ((int32_t)(IRQn) >= 0)
1943  {
1944  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1945  __DSB();
1946  __ISB();
1947  }
1948 }
1949 
1950 
1959 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1960 {
1961  if ((int32_t)(IRQn) >= 0)
1962  {
1963  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1964  }
1965  else
1966  {
1967  return(0U);
1968  }
1969 }
1970 
1971 
1978 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1979 {
1980  if ((int32_t)(IRQn) >= 0)
1981  {
1982  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1983  }
1984 }
1985 
1986 
1993 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1994 {
1995  if ((int32_t)(IRQn) >= 0)
1996  {
1997  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1998  }
1999 }
2000 
2001 
2010 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2011 {
2012  if ((int32_t)(IRQn) >= 0)
2013  {
2014  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2015  }
2016  else
2017  {
2018  return(0U);
2019  }
2020 }
2021 
2022 
2032 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2033 {
2034  if ((int32_t)(IRQn) >= 0)
2035  {
2036  NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2037  }
2038  else
2039  {
2040  SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2041  }
2042 }
2043 
2044 
2054 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2055 {
2056 
2057  if ((int32_t)(IRQn) >= 0)
2058  {
2059  return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2060  }
2061  else
2062  {
2063  return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2064  }
2065 }
2066 
2067 
2079 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2080 {
2081  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2082  uint32_t PreemptPriorityBits;
2083  uint32_t SubPriorityBits;
2084 
2085  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2086  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2087 
2088  return (
2089  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2090  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2091  );
2092 }
2093 
2094 
2106 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2107 {
2108  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2109  uint32_t PreemptPriorityBits;
2110  uint32_t SubPriorityBits;
2111 
2112  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2113  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2114 
2115  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2116  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2117 }
2118 
2119 
2129 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2130 {
2131  uint32_t vectors = (uint32_t )SCB->VTOR;
2132  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
2133  __DSB();
2134 }
2135 
2136 
2145 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2146 {
2147  uint32_t vectors = (uint32_t )SCB->VTOR;
2148  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
2149 }
2150 
2151 
2156 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2157 {
2158  __DSB(); /* Ensure all outstanding memory accesses included
2159  buffered write are completed before reset */
2160  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2161  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2162  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2163  __DSB(); /* Ensure completion of memory access */
2164 
2165  for(;;) /* wait until reset */
2166  {
2167  __NOP();
2168  }
2169 }
2170 
2174 /* ########################## MPU functions #################################### */
2175 
2176 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2177 
2178 #include "mpu_armv7.h"
2179 
2180 #endif
2181 
2182 
2183 /* ########################## FPU functions #################################### */
2199 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2200 {
2201  uint32_t mvfr0;
2202 
2203  mvfr0 = SCB->MVFR0;
2204  if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2205  {
2206  return 2U; /* Double + Single precision FPU */
2207  }
2208  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2209  {
2210  return 1U; /* Single precision FPU */
2211  }
2212  else
2213  {
2214  return 0U; /* No FPU */
2215  }
2216 }
2217 
2222 /* ########################## Cache functions #################################### */
2230 /* Cache Size ID Register Macros */
2231 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
2232 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
2233 
2234 #define __SCB_DCACHE_LINE_SIZE 32U
2235 #define __SCB_ICACHE_LINE_SIZE 32U
2241 __STATIC_FORCEINLINE void SCB_EnableICache (void)
2242 {
2243  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
2244  if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
2245 
2246  __DSB();
2247  __ISB();
2248  SCB->ICIALLU = 0UL; /* invalidate I-Cache */
2249  __DSB();
2250  __ISB();
2251  SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
2252  __DSB();
2253  __ISB();
2254  #endif
2255 }
2256 
2257 
2262 __STATIC_FORCEINLINE void SCB_DisableICache (void)
2263 {
2264  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
2265  __DSB();
2266  __ISB();
2267  SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
2268  SCB->ICIALLU = 0UL; /* invalidate I-Cache */
2269  __DSB();
2270  __ISB();
2271  #endif
2272 }
2273 
2274 
2279 __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
2280 {
2281  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
2282  __DSB();
2283  __ISB();
2284  SCB->ICIALLU = 0UL;
2285  __DSB();
2286  __ISB();
2287  #endif
2288 }
2289 
2290 
2299 __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
2300 {
2301  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
2302  if ( isize > 0 ) {
2303  int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
2304  uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
2305 
2306  __DSB();
2307 
2308  do {
2309  SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
2310  op_addr += __SCB_ICACHE_LINE_SIZE;
2311  op_size -= __SCB_ICACHE_LINE_SIZE;
2312  } while ( op_size > 0 );
2313 
2314  __DSB();
2315  __ISB();
2316  }
2317  #endif
2318 }
2319 
2320 
2325 __STATIC_FORCEINLINE void SCB_EnableDCache (void)
2326 {
2327  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2328  uint32_t ccsidr;
2329  uint32_t sets;
2330  uint32_t ways;
2331 
2332  if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
2333 
2334  SCB->CSSELR = 0U; /* select Level 1 data cache */
2335  __DSB();
2336 
2337  ccsidr = SCB->CCSIDR;
2338 
2339  /* invalidate D-Cache */
2340  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2341  do {
2342  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2343  do {
2344  SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
2345  ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
2346  #if defined ( __CC_ARM )
2347  __schedule_barrier();
2348  #endif
2349  } while (ways-- != 0U);
2350  } while(sets-- != 0U);
2351  __DSB();
2352 
2353  SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
2354 
2355  __DSB();
2356  __ISB();
2357  #endif
2358 }
2359 
2360 
2365 __STATIC_FORCEINLINE void SCB_DisableDCache (void)
2366 {
2367  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2368  register uint32_t ccsidr;
2369  register uint32_t sets;
2370  register uint32_t ways;
2371 
2372  SCB->CSSELR = 0U; /* select Level 1 data cache */
2373  __DSB();
2374 
2375  SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
2376  __DSB();
2377 
2378  ccsidr = SCB->CCSIDR;
2379 
2380  /* clean & invalidate D-Cache */
2381  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2382  do {
2383  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2384  do {
2385  SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
2386  ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
2387  #if defined ( __CC_ARM )
2388  __schedule_barrier();
2389  #endif
2390  } while (ways-- != 0U);
2391  } while(sets-- != 0U);
2392 
2393  __DSB();
2394  __ISB();
2395  #endif
2396 }
2397 
2398 
2403 __STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
2404 {
2405  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2406  uint32_t ccsidr;
2407  uint32_t sets;
2408  uint32_t ways;
2409 
2410  SCB->CSSELR = 0U; /* select Level 1 data cache */
2411  __DSB();
2412 
2413  ccsidr = SCB->CCSIDR;
2414 
2415  /* invalidate D-Cache */
2416  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2417  do {
2418  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2419  do {
2420  SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
2421  ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
2422  #if defined ( __CC_ARM )
2423  __schedule_barrier();
2424  #endif
2425  } while (ways-- != 0U);
2426  } while(sets-- != 0U);
2427 
2428  __DSB();
2429  __ISB();
2430  #endif
2431 }
2432 
2433 
2438 __STATIC_FORCEINLINE void SCB_CleanDCache (void)
2439 {
2440  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2441  uint32_t ccsidr;
2442  uint32_t sets;
2443  uint32_t ways;
2444 
2445  SCB->CSSELR = 0U; /* select Level 1 data cache */
2446  __DSB();
2447 
2448  ccsidr = SCB->CCSIDR;
2449 
2450  /* clean D-Cache */
2451  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2452  do {
2453  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2454  do {
2455  SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
2456  ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
2457  #if defined ( __CC_ARM )
2458  __schedule_barrier();
2459  #endif
2460  } while (ways-- != 0U);
2461  } while(sets-- != 0U);
2462 
2463  __DSB();
2464  __ISB();
2465  #endif
2466 }
2467 
2468 
2473 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
2474 {
2475  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2476  uint32_t ccsidr;
2477  uint32_t sets;
2478  uint32_t ways;
2479 
2480  SCB->CSSELR = 0U; /* select Level 1 data cache */
2481  __DSB();
2482 
2483  ccsidr = SCB->CCSIDR;
2484 
2485  /* clean & invalidate D-Cache */
2486  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2487  do {
2488  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2489  do {
2490  SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
2491  ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
2492  #if defined ( __CC_ARM )
2493  __schedule_barrier();
2494  #endif
2495  } while (ways-- != 0U);
2496  } while(sets-- != 0U);
2497 
2498  __DSB();
2499  __ISB();
2500  #endif
2501 }
2502 
2503 
2512 __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
2513 {
2514  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2515  if ( dsize > 0 ) {
2516  int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
2517  uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2518 
2519  __DSB();
2520 
2521  do {
2522  SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
2523  op_addr += __SCB_DCACHE_LINE_SIZE;
2524  op_size -= __SCB_DCACHE_LINE_SIZE;
2525  } while ( op_size > 0 );
2526 
2527  __DSB();
2528  __ISB();
2529  }
2530  #endif
2531 }
2532 
2533 
2542 __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
2543 {
2544  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2545  if ( dsize > 0 ) {
2546  int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
2547  uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2548 
2549  __DSB();
2550 
2551  do {
2552  SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
2553  op_addr += __SCB_DCACHE_LINE_SIZE;
2554  op_size -= __SCB_DCACHE_LINE_SIZE;
2555  } while ( op_size > 0 );
2556 
2557  __DSB();
2558  __ISB();
2559  }
2560  #endif
2561 }
2562 
2563 
2572 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2573 {
2574  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2575  if ( dsize > 0 ) {
2576  int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
2577  uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2578 
2579  __DSB();
2580 
2581  do {
2582  SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
2583  op_addr += __SCB_DCACHE_LINE_SIZE;
2584  op_size -= __SCB_DCACHE_LINE_SIZE;
2585  } while ( op_size > 0 );
2586 
2587  __DSB();
2588  __ISB();
2589  }
2590  #endif
2591 }
2592 
2597 /* ################################## SysTick function ############################################ */
2605 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2606 
2618 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2619 {
2620  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2621  {
2622  return (1UL); /* Reload value impossible */
2623  }
2624 
2625  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2626  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2627  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2628  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2629  SysTick_CTRL_TICKINT_Msk |
2630  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2631  return (0UL); /* Function successful */
2632 }
2633 
2634 #endif
2635 
2640 /* ##################################### Debug In/Output function ########################################### */
2648 extern volatile int32_t ITM_RxBuffer;
2649 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2660 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2661 {
2662  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2663  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2664  {
2665  while (ITM->PORT[0U].u32 == 0UL)
2666  {
2667  __NOP();
2668  }
2669  ITM->PORT[0U].u8 = (uint8_t)ch;
2670  }
2671  return (ch);
2672 }
2673 
2674 
2681 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2682 {
2683  int32_t ch = -1; /* no character available */
2684 
2685  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2686  {
2687  ch = ITM_RxBuffer;
2688  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2689  }
2690 
2691  return (ch);
2692 }
2693 
2694 
2701 __STATIC_INLINE int32_t ITM_CheckChar (void)
2702 {
2703 
2704  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2705  {
2706  return (0); /* no character available */
2707  }
2708  else
2709  {
2710  return (1); /* character available */
2711  }
2712 }
2713 
2719 #ifdef __cplusplus
2720 }
2721 #endif
2722 
2723 #endif /* __CORE_CM7_H_DEPENDANT */
2724 
2725 #endif /* __CMSIS_GENERIC */
CoreDebug_Type::DHCSR
__IOM uint32_t DHCSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1641
ITM_Type::TPR
__IOM uint32_t TPR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1042
SCB_CleanDCache_by_Addr
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean by address.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2542
SCB
#define SCB
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1778
ITM_Type::PID0
__IM uint32_t PID0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1054
__OM
#define __OM
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:241
__SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2234
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2054
TPI_Type::FFCR
__IOM uint32_t FFCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1279
ITM_Type::LAR
__OM uint32_t LAR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1047
APSR_Type::@294::N
uint32_t N
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:285
xPSR_Type::@296::ICI_IT_2
uint32_t ICI_IT_2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:341
SCB_InvalidateICache_by_Addr
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr(void *addr, int32_t isize)
I-Cache Invalidate by address.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2299
TPI_Type::ITCTRL
__IOM uint32_t ITCTRL
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1288
SCB_DCISW_WAY_Pos
#define SCB_DCISW_WAY_Pos
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:816
SCB_DisableICache
__STATIC_FORCEINLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2262
TPI_Type::DEVID
__IM uint32_t DEVID
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1293
DWT_Type::FUNCTION1
__IOM uint32_t FUNCTION1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1135
CCSIDR_SETS
#define CCSIDR_SETS(x)
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2232
DWT_Type::FUNCTION3
__IOM uint32_t FUNCTION3
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1143
NVIC_Type::STIR
__OM uint32_t STIR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:435
cmsis_version.h
CMSIS Core(M) Version definitions.
SCB_Type::CCR
__IOM uint32_t CCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:462
TPI_Type::SSPSR
__IM uint32_t SSPSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1271
IRQn
IRQn
Definition: MIMXRT1052.h:78
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2106
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:992
SCB_Type::DTCMCR
__IOM uint32_t DTCMCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:501
SCB_Type::CSSELR
__IOM uint32_t CSSELR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:480
SCB_Type::DCISW
__OM uint32_t DCISW
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:493
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:331
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:574
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:944
cmsis_compiler.h
CMSIS compiler generic header file.
DWT_Type::CTRL
__IOM uint32_t CTRL
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1121
DWT_Type::LSR
__IM uint32_t LSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1146
FPU_Type::MVFR2
__IM uint32_t MVFR2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1535
FPU_Type::MVFR1
__IM uint32_t MVFR1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1534
SCB_Type::CACR
__IOM uint32_t CACR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:503
TPI_Type::FFSR
__IM uint32_t FFSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1278
SCB_DCCSW_WAY_Msk
#define SCB_DCCSW_WAY_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:824
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1600
xPSR_Type::@296::_reserved1
uint32_t _reserved1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:339
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:274
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1031
xPSR_Type::@296::V
uint32_t V
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:343
SCnSCB_Type::ACTLR
__IOM uint32_t ACTLR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:925
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:933
SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:600
APSR_Type::@294::_reserved0
uint32_t _reserved0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:278
SCB_Type::AFSR
__IOM uint32_t AFSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:470
ITM_Type::TER
__IOM uint32_t TER
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1040
SCB_Type::ICSR
__IOM uint32_t ICSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:458
SCB_DCCSW_SET_Msk
#define SCB_DCCSW_SET_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:827
DWT_Type::COMP2
__IOM uint32_t COMP2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1137
SCB_Type::MVFR1
__IM uint32_t MVFR1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:486
SCB_Type::MVFR0
__IM uint32_t MVFR0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:485
ITM_Type::PID1
__IM uint32_t PID1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1055
SCB_Type::DCCIMVAC
__OM uint32_t DCCIMVAC
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:497
ITM_Type::CID3
__IM uint32_t CID3
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1061
xPSR_Type::@296::N
uint32_t N
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:346
SCB_DisableDCache
__STATIC_FORCEINLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2365
__SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2235
SCB_Type::SHCSR
__IOM uint32_t SHCSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:464
xPSR_Type::@296::ISR
uint32_t ISR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:335
APSR_Type::@294::Q
uint32_t Q
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:281
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1052.h:91
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2079
SCB_Type::CLIDR
__IM uint32_t CLIDR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:477
DWT_Type::EXCCNT
__IOM uint32_t EXCCNT
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1124
APSR_Type::@294::_reserved1
uint32_t _reserved1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:280
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2701
xPSR_Type::@296::ICI_IT_1
uint32_t ICI_IT_1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:337
CONTROL_Type::@297::SPSEL
uint32_t SPSEL
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:391
SCB_DCISW_SET_Pos
#define SCB_DCISW_SET_Pos
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:819
__STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:66
__NOP
#define __NOP
No Operation.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:416
SCB_DCCISW_SET_Pos
#define SCB_DCCISW_SET_Pos
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:833
DWT_Type::FUNCTION0
__IOM uint32_t FUNCTION0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1131
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2010
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1978
TPI_Type::FSCR
__IM uint32_t FSCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1280
SCB_CleanInvalidateDCache
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2473
DWT_Type::MASK1
__IOM uint32_t MASK1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1134
DWT_Type::FUNCTION2
__IOM uint32_t FUNCTION2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1139
SCB_Type::HFSR
__IOM uint32_t HFSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:466
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:455
CONTROL_Type::w
uint32_t w
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:395
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1094
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:995
TPI_Type::FIFO1
__IM uint32_t FIFO1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1287
IPSR_Type::w
uint32_t w
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:320
FPU_Type::FPCCR
__IOM uint32_t FPCCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1530
FPU_Type::FPDSCR
__IOM uint32_t FPDSCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1532
ITM_Type::PID5
__IM uint32_t PID5
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1051
SCB_DCISW_WAY_Msk
#define SCB_DCISW_WAY_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:817
ITM
#define ITM
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1781
SysTick_Type::CALIB
__IM uint32_t CALIB
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:984
SCB_Type::BFAR
__IOM uint32_t BFAR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:469
SCB_Type::CPACR
__IOM uint32_t CPACR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:481
DWT_Type::LSUCNT
__IOM uint32_t LSUCNT
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1126
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1119
ITM_Type::TCR
__IOM uint32_t TCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1044
ITM_Type::PID7
__IM uint32_t PID7
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1053
ITM_Type::PID2
__IM uint32_t PID2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1056
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1902
SCB_Type::VTOR
__IOM uint32_t VTOR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:459
CoreDebug_Type::DEMCR
__IOM uint32_t DEMCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1644
IPSR_Type::@295::ISR
uint32_t ISR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:317
CoreDebug_Type::DCRDR
__IOM uint32_t DCRDR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1643
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1993
__STATIC_INLINE
#define __STATIC_INLINE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:63
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
TPI_Type::SPPR
__IOM uint32_t SPPR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1276
xPSR_Type::@296::T
uint32_t T
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:340
SCB_Type::ICIMVAU
__OM uint32_t ICIMVAU
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:491
SCB_Type::ABFSR
__IOM uint32_t ABFSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:506
DWT_Type::MASK0
__IOM uint32_t MASK0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1130
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1002
DWT_Type::COMP3
__IOM uint32_t COMP3
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1141
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f407xx.h:66
APSR_Type::@294::V
uint32_t V
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:282
APSR_Type::w
uint32_t w
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:287
SCB_Type::CFSR
__IOM uint32_t CFSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:465
SCB_Type::MVFR2
__IM uint32_t MVFR2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:487
SCB_DCCSW_WAY_Pos
#define SCB_DCCSW_WAY_Pos
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:823
SCB_Type::STIR
__OM uint32_t STIR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:483
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:386
SCB_CleanInvalidateDCache_by_Addr
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2572
DWT_Type::MASK3
__IOM uint32_t MASK3
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1142
CONTROL_Type::@297::_reserved0
uint32_t _reserved0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:393
SCB_DCCSW_SET_Pos
#define SCB_DCCSW_SET_Pos
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:826
SCB_Type::ICIALLU
__OM uint32_t ICIALLU
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:489
CCSIDR_WAYS
#define CCSIDR_WAYS(x)
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2231
SCB_Type::DFSR
__IOM uint32_t DFSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:467
DWT_Type::CYCCNT
__IOM uint32_t CYCCNT
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1122
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2129
TPI_Type::TRIGGER
__IM uint32_t TRIGGER
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1282
TPI_Type::FIFO0
__IM uint32_t FIFO0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1283
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:561
SCB_InvalidateICache
__STATIC_FORCEINLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2279
DWT_Type::PCSR
__IM uint32_t PCSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1128
xPSR_Type::@296::Q
uint32_t Q
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:342
SysTick_Type::CTRL
__IOM uint32_t CTRL
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:981
SCB_Type::DCIMVAC
__OM uint32_t DCIMVAC
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:492
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1871
FPU_Type::MVFR0
__IM uint32_t MVFR0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1533
SCB_Type::AHBPCR
__IOM uint32_t AHBPCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:502
ITM_Type::CID0
__IM uint32_t CID0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1058
SCB_Type::DCCSW
__OM uint32_t DCCSW
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:496
SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:597
SCB_Type::ID_AFR
__IM uint32_t ID_AFR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:473
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1940
SCB_DCISW_SET_Msk
#define SCB_DCISW_SET_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:820
NVIC
#define NVIC
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1780
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2681
SCB_DCCISW_WAY_Msk
#define SCB_DCCISW_WAY_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:831
SysTick_Type::LOAD
__IOM uint32_t LOAD
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:982
SCB_InvalidateDCache
__STATIC_FORCEINLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2403
CONTROL_Type::@297::FPCA
uint32_t FPCA
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:392
FPU_Type::FPCAR
__IOM uint32_t FPCAR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1531
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2145
SCB_Type::AIRCR
__IOM uint32_t AIRCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:460
SCB_Type::AHBSCR
__IOM uint32_t AHBSCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:504
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2649
SCB_EnableDCache
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2325
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1639
SCB_Type::CCSIDR
__IM uint32_t CCSIDR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:479
SCB_Type::ITCMCR
__IOM uint32_t ITCMCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:500
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:570
SCB_Type::DCCISW
__OM uint32_t DCCISW
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:498
TPI_Type::DEVTYPE
__IM uint32_t DEVTYPE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1294
DWT_Type::FOLDCNT
__IOM uint32_t FOLDCNT
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1127
DWT_Type::COMP0
__IOM uint32_t COMP0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1129
NVIC_SetPriority
#define NVIC_SetPriority
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1835
__IM
#define __IM
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:240
ITM_Type::@298::u8
__OM uint8_t u8
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1035
ITM_Type::PID3
__IM uint32_t PID3
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1057
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1527
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1269
SCB_Type::SCR
__IOM uint32_t SCR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:461
__IOM
#define __IOM
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:242
TPI_Type::CSPSR
__IOM uint32_t CSPSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1272
DWT_Type::SLEEPCNT
__IOM uint32_t SLEEPCNT
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1125
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:998
xPSR_Type::@296::Z
uint32_t Z
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:345
CONTROL_Type::@297::nPRIV
uint32_t nPRIV
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:390
APSR_Type::@294::Z
uint32_t Z
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:284
__NO_RETURN
#define __NO_RETURN
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:69
SCB_Type::CPUID
__IM uint32_t CPUID
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:457
SCB_InvalidateDCache_by_Addr
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr(void *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2512
xPSR_Type::@296::C
uint32_t C
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:344
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:421
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1890
xPSR_Type::w
uint32_t w
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:348
xPSR_Type::@296::_reserved0
uint32_t _reserved0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:336
ITM_Type::PID4
__IM uint32_t PID4
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1050
SysTick
#define SysTick
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1779
DWT_Type::LAR
__OM uint32_t LAR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1145
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1850
SCB_Type::DCCMVAC
__OM uint32_t DCCMVAC
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:495
IPSR_Type::@295::_reserved0
uint32_t _reserved0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:318
SCB_Type::ID_DFR
__IM uint32_t ID_DFR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:472
SCB_Type::DCCMVAU
__OM uint32_t DCCMVAU
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:494
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:921
CoreDebug_Type::DCRSR
__OM uint32_t DCRSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1642
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:571
SCB_Type::MMFAR
__IOM uint32_t MMFAR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:468
ITM_Type::@298::u32
__OM uint32_t u32
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1037
SCB_CleanDCache
__STATIC_FORCEINLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2438
SCnSCB_Type::ICTR
__IM uint32_t ICTR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:924
TPI_Type::ITATBCTR0
__IM uint32_t ITATBCTR0
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1286
ITM_Type::CID2
__IM uint32_t CID2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1060
SCB_Type::CTR
__IM uint32_t CTR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:478
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2156
xPSR_Type::@296::GE
uint32_t GE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:338
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2032
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2199
DWT_Type::COMP1
__IOM uint32_t COMP1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1133
DWT_Type::MASK2
__IOM uint32_t MASK2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1138
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1959
ITM_Type::LSR
__IM uint32_t LSR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1048
TPI_Type::ITATBCTR2
__IM uint32_t ITATBCTR2
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1284
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1052.h:266
TPI_Type::CLAIMSET
__IOM uint32_t CLAIMSET
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1290
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:979
SysTick_Type::VAL
__IOM uint32_t VAL
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:983
APSR_Type::@294::GE
uint32_t GE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:279
SCB_DCCISW_WAY_Pos
#define SCB_DCCISW_WAY_Pos
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:830
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:313
ITM_Type::CID1
__IM uint32_t CID1
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1059
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:108
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1921
ITM_Type::@298::u16
__OM uint16_t u16
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1036
SCB_DCCISW_SET_Msk
#define SCB_DCCISW_SET_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:834
TPI_Type::CLAIMCLR
__IOM uint32_t CLAIMCLR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1291
DWT_Type::CPICNT
__IOM uint32_t CPICNT
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1123
ITM_Type::PID6
__IM uint32_t PID6
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1052
APSR_Type::@294::C
uint32_t C
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:283
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1603
TPI_Type::ACPR
__IOM uint32_t ACPR
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1274
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:562

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:13:48