Macros | |
| #define | DMAMUX_CHCFG_COUNT (32U) |
CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register | |
| #define | DMAMUX_CHCFG_SOURCE_MASK (0x7FU) |
| #define | DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
| #define | DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
| #define | DMAMUX_CHCFG_A_ON_MASK (0x20000000U) |
| #define | DMAMUX_CHCFG_A_ON_SHIFT (29U) |
| #define | DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) |
| #define | DMAMUX_CHCFG_TRIG_MASK (0x40000000U) |
| #define | DMAMUX_CHCFG_TRIG_SHIFT (30U) |
| #define | DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
| #define | DMAMUX_CHCFG_ENBL_MASK (0x80000000U) |
| #define | DMAMUX_CHCFG_ENBL_SHIFT (31U) |
| #define | DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
Detailed Description
Macro Definition Documentation
◆ DMAMUX_CHCFG_A_ON
| #define DMAMUX_CHCFG_A_ON | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) |
A_ON - DMA Channel Always Enable 0b0..DMA Channel Always ON function is disabled 0b1..DMA Channel Always ON function is enabled
Definition at line 15086 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_A_ON_MASK
| #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) |
Definition at line 15080 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_A_ON_SHIFT
| #define DMAMUX_CHCFG_A_ON_SHIFT (29U) |
Definition at line 15081 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_COUNT
| #define DMAMUX_CHCFG_COUNT (32U) |
Definition at line 15105 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_ENBL
| #define DMAMUX_CHCFG_ENBL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
ENBL - DMA Mux Channel Enable 0b0..DMA Mux channel is disabled 0b1..DMA Mux channel is enabled
Definition at line 15101 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_ENBL_MASK
| #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) |
Definition at line 15095 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_ENBL_SHIFT
| #define DMAMUX_CHCFG_ENBL_SHIFT (31U) |
Definition at line 15096 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_SOURCE
| #define DMAMUX_CHCFG_SOURCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
SOURCE - DMA Channel Source (Slot Number)
Definition at line 15079 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_SOURCE_MASK
| #define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) |
Definition at line 15075 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_SOURCE_SHIFT
| #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
Definition at line 15076 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_TRIG
| #define DMAMUX_CHCFG_TRIG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
TRIG - DMA Channel Trigger Enable 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
Definition at line 15094 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_TRIG_MASK
| #define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) |
Definition at line 15087 of file MIMXRT1052.h.
◆ DMAMUX_CHCFG_TRIG_SHIFT
| #define DMAMUX_CHCFG_TRIG_SHIFT (30U) |
Definition at line 15088 of file MIMXRT1052.h.