Collaboration diagram for DMA Register Masks:

Macros
#define	DMA_ATTR_COUNT (32U)

#define	DMA_BITER_ELINKNO_COUNT (32U)

#define	DMA_BITER_ELINKYES_COUNT (32U)

#define	DMA_CITER_ELINKNO_COUNT (32U)

#define	DMA_CITER_ELINKYES_COUNT (32U)

#define	DMA_CSR_COUNT (32U)

#define	DMA_DADDR_COUNT (32U)

#define	DMA_DLAST_SGA_COUNT (32U)

#define	DMA_DOFF_COUNT (32U)

#define	DMA_NBYTES_MLNO_COUNT (32U)

#define	DMA_NBYTES_MLOFFNO_COUNT (32U)

#define	DMA_NBYTES_MLOFFYES_COUNT (32U)

#define	DMA_SADDR_COUNT (32U)

#define	DMA_SLAST_COUNT (32U)

#define	DMA_SOFF_COUNT (32U)

CR - Control Register
#define	DMA_CR_EDBG_MASK (0x2U)

#define	DMA_CR_EDBG_SHIFT (1U)

#define	DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

#define	DMA_CR_ERCA_MASK (0x4U)

#define	DMA_CR_ERCA_SHIFT (2U)

#define	DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

#define	DMA_CR_ERGA_MASK (0x8U)

#define	DMA_CR_ERGA_SHIFT (3U)

#define	DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

#define	DMA_CR_HOE_MASK (0x10U)

#define	DMA_CR_HOE_SHIFT (4U)

#define	DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

#define	DMA_CR_HALT_MASK (0x20U)

#define	DMA_CR_HALT_SHIFT (5U)

#define	DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

#define	DMA_CR_CLM_MASK (0x40U)

#define	DMA_CR_CLM_SHIFT (6U)

#define	DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

#define	DMA_CR_EMLM_MASK (0x80U)

#define	DMA_CR_EMLM_SHIFT (7U)

#define	DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

#define	DMA_CR_GRP0PRI_MASK (0x100U)

#define	DMA_CR_GRP0PRI_SHIFT (8U)

#define	DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

#define	DMA_CR_GRP1PRI_MASK (0x400U)

#define	DMA_CR_GRP1PRI_SHIFT (10U)

#define	DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

#define	DMA_CR_ECX_MASK (0x10000U)

#define	DMA_CR_ECX_SHIFT (16U)

#define	DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

#define	DMA_CR_CX_MASK (0x20000U)

#define	DMA_CR_CX_SHIFT (17U)

#define	DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

#define	DMA_CR_ACTIVE_MASK (0x80000000U)

#define	DMA_CR_ACTIVE_SHIFT (31U)

#define	DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)

#define	LPSPI_CR_MEN_MASK (0x1U)

#define	LPSPI_CR_MEN_SHIFT (0U)

#define	LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

#define	LPSPI_CR_RST_MASK (0x2U)

#define	LPSPI_CR_RST_SHIFT (1U)

#define	LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

#define	LPSPI_CR_DOZEN_MASK (0x4U)

#define	LPSPI_CR_DOZEN_SHIFT (2U)

#define	LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

#define	LPSPI_CR_DBGEN_MASK (0x8U)

#define	LPSPI_CR_DBGEN_SHIFT (3U)

#define	LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

#define	LPSPI_CR_RTF_MASK (0x100U)

#define	LPSPI_CR_RTF_SHIFT (8U)

#define	LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

#define	LPSPI_CR_RRF_MASK (0x200U)

#define	LPSPI_CR_RRF_SHIFT (9U)

#define	LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

ES - Error Status Register
#define	DMA_ES_DBE_MASK (0x1U)

#define	DMA_ES_DBE_SHIFT (0U)

#define	DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

#define	DMA_ES_SBE_MASK (0x2U)

#define	DMA_ES_SBE_SHIFT (1U)

#define	DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

#define	DMA_ES_SGE_MASK (0x4U)

#define	DMA_ES_SGE_SHIFT (2U)

#define	DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

#define	DMA_ES_NCE_MASK (0x8U)

#define	DMA_ES_NCE_SHIFT (3U)

#define	DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

#define	DMA_ES_DOE_MASK (0x10U)

#define	DMA_ES_DOE_SHIFT (4U)

#define	DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

#define	DMA_ES_DAE_MASK (0x20U)

#define	DMA_ES_DAE_SHIFT (5U)

#define	DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

#define	DMA_ES_SOE_MASK (0x40U)

#define	DMA_ES_SOE_SHIFT (6U)

#define	DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

#define	DMA_ES_SAE_MASK (0x80U)

#define	DMA_ES_SAE_SHIFT (7U)

#define	DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

#define	DMA_ES_ERRCHN_MASK (0x1F00U)

#define	DMA_ES_ERRCHN_SHIFT (8U)

#define	DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

#define	DMA_ES_CPE_MASK (0x4000U)

#define	DMA_ES_CPE_SHIFT (14U)

#define	DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

#define	DMA_ES_GPE_MASK (0x8000U)

#define	DMA_ES_GPE_SHIFT (15U)

#define	DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

#define	DMA_ES_ECX_MASK (0x10000U)

#define	DMA_ES_ECX_SHIFT (16U)

#define	DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

#define	DMA_ES_VLD_MASK (0x80000000U)

#define	DMA_ES_VLD_SHIFT (31U)

#define	DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

ERQ - Enable Request Register
#define	DMA_ERQ_ERQ0_MASK (0x1U)

#define	DMA_ERQ_ERQ0_SHIFT (0U)

#define	DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

#define	DMA_ERQ_ERQ1_MASK (0x2U)

#define	DMA_ERQ_ERQ1_SHIFT (1U)

#define	DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

#define	DMA_ERQ_ERQ2_MASK (0x4U)

#define	DMA_ERQ_ERQ2_SHIFT (2U)

#define	DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

#define	DMA_ERQ_ERQ3_MASK (0x8U)

#define	DMA_ERQ_ERQ3_SHIFT (3U)

#define	DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

#define	DMA_ERQ_ERQ4_MASK (0x10U)

#define	DMA_ERQ_ERQ4_SHIFT (4U)

#define	DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

#define	DMA_ERQ_ERQ5_MASK (0x20U)

#define	DMA_ERQ_ERQ5_SHIFT (5U)

#define	DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

#define	DMA_ERQ_ERQ6_MASK (0x40U)

#define	DMA_ERQ_ERQ6_SHIFT (6U)

#define	DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

#define	DMA_ERQ_ERQ7_MASK (0x80U)

#define	DMA_ERQ_ERQ7_SHIFT (7U)

#define	DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

#define	DMA_ERQ_ERQ8_MASK (0x100U)

#define	DMA_ERQ_ERQ8_SHIFT (8U)

#define	DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

#define	DMA_ERQ_ERQ9_MASK (0x200U)

#define	DMA_ERQ_ERQ9_SHIFT (9U)

#define	DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

#define	DMA_ERQ_ERQ10_MASK (0x400U)

#define	DMA_ERQ_ERQ10_SHIFT (10U)

#define	DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

#define	DMA_ERQ_ERQ11_MASK (0x800U)

#define	DMA_ERQ_ERQ11_SHIFT (11U)

#define	DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

#define	DMA_ERQ_ERQ12_MASK (0x1000U)

#define	DMA_ERQ_ERQ12_SHIFT (12U)

#define	DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

#define	DMA_ERQ_ERQ13_MASK (0x2000U)

#define	DMA_ERQ_ERQ13_SHIFT (13U)

#define	DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

#define	DMA_ERQ_ERQ14_MASK (0x4000U)

#define	DMA_ERQ_ERQ14_SHIFT (14U)

#define	DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

#define	DMA_ERQ_ERQ15_MASK (0x8000U)

#define	DMA_ERQ_ERQ15_SHIFT (15U)

#define	DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

#define	DMA_ERQ_ERQ16_MASK (0x10000U)

#define	DMA_ERQ_ERQ16_SHIFT (16U)

#define	DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

#define	DMA_ERQ_ERQ17_MASK (0x20000U)

#define	DMA_ERQ_ERQ17_SHIFT (17U)

#define	DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

#define	DMA_ERQ_ERQ18_MASK (0x40000U)

#define	DMA_ERQ_ERQ18_SHIFT (18U)

#define	DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

#define	DMA_ERQ_ERQ19_MASK (0x80000U)

#define	DMA_ERQ_ERQ19_SHIFT (19U)

#define	DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

#define	DMA_ERQ_ERQ20_MASK (0x100000U)

#define	DMA_ERQ_ERQ20_SHIFT (20U)

#define	DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

#define	DMA_ERQ_ERQ21_MASK (0x200000U)

#define	DMA_ERQ_ERQ21_SHIFT (21U)

#define	DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

#define	DMA_ERQ_ERQ22_MASK (0x400000U)

#define	DMA_ERQ_ERQ22_SHIFT (22U)

#define	DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

#define	DMA_ERQ_ERQ23_MASK (0x800000U)

#define	DMA_ERQ_ERQ23_SHIFT (23U)

#define	DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

#define	DMA_ERQ_ERQ24_MASK (0x1000000U)

#define	DMA_ERQ_ERQ24_SHIFT (24U)

#define	DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

#define	DMA_ERQ_ERQ25_MASK (0x2000000U)

#define	DMA_ERQ_ERQ25_SHIFT (25U)

#define	DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

#define	DMA_ERQ_ERQ26_MASK (0x4000000U)

#define	DMA_ERQ_ERQ26_SHIFT (26U)

#define	DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

#define	DMA_ERQ_ERQ27_MASK (0x8000000U)

#define	DMA_ERQ_ERQ27_SHIFT (27U)

#define	DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

#define	DMA_ERQ_ERQ28_MASK (0x10000000U)

#define	DMA_ERQ_ERQ28_SHIFT (28U)

#define	DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

#define	DMA_ERQ_ERQ29_MASK (0x20000000U)

#define	DMA_ERQ_ERQ29_SHIFT (29U)

#define	DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

#define	DMA_ERQ_ERQ30_MASK (0x40000000U)

#define	DMA_ERQ_ERQ30_SHIFT (30U)

#define	DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

#define	DMA_ERQ_ERQ31_MASK (0x80000000U)

#define	DMA_ERQ_ERQ31_SHIFT (31U)

#define	DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

EEI - Enable Error Interrupt Register
#define	DMA_EEI_EEI0_MASK (0x1U)

#define	DMA_EEI_EEI0_SHIFT (0U)

#define	DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

#define	DMA_EEI_EEI1_MASK (0x2U)

#define	DMA_EEI_EEI1_SHIFT (1U)

#define	DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

#define	DMA_EEI_EEI2_MASK (0x4U)

#define	DMA_EEI_EEI2_SHIFT (2U)

#define	DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

#define	DMA_EEI_EEI3_MASK (0x8U)

#define	DMA_EEI_EEI3_SHIFT (3U)

#define	DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

#define	DMA_EEI_EEI4_MASK (0x10U)

#define	DMA_EEI_EEI4_SHIFT (4U)

#define	DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

#define	DMA_EEI_EEI5_MASK (0x20U)

#define	DMA_EEI_EEI5_SHIFT (5U)

#define	DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

#define	DMA_EEI_EEI6_MASK (0x40U)

#define	DMA_EEI_EEI6_SHIFT (6U)

#define	DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

#define	DMA_EEI_EEI7_MASK (0x80U)

#define	DMA_EEI_EEI7_SHIFT (7U)

#define	DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

#define	DMA_EEI_EEI8_MASK (0x100U)

#define	DMA_EEI_EEI8_SHIFT (8U)

#define	DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

#define	DMA_EEI_EEI9_MASK (0x200U)

#define	DMA_EEI_EEI9_SHIFT (9U)

#define	DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

#define	DMA_EEI_EEI10_MASK (0x400U)

#define	DMA_EEI_EEI10_SHIFT (10U)

#define	DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

#define	DMA_EEI_EEI11_MASK (0x800U)

#define	DMA_EEI_EEI11_SHIFT (11U)

#define	DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

#define	DMA_EEI_EEI12_MASK (0x1000U)

#define	DMA_EEI_EEI12_SHIFT (12U)

#define	DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

#define	DMA_EEI_EEI13_MASK (0x2000U)

#define	DMA_EEI_EEI13_SHIFT (13U)

#define	DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

#define	DMA_EEI_EEI14_MASK (0x4000U)

#define	DMA_EEI_EEI14_SHIFT (14U)

#define	DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

#define	DMA_EEI_EEI15_MASK (0x8000U)

#define	DMA_EEI_EEI15_SHIFT (15U)

#define	DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

#define	DMA_EEI_EEI16_MASK (0x10000U)

#define	DMA_EEI_EEI16_SHIFT (16U)

#define	DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

#define	DMA_EEI_EEI17_MASK (0x20000U)

#define	DMA_EEI_EEI17_SHIFT (17U)

#define	DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

#define	DMA_EEI_EEI18_MASK (0x40000U)

#define	DMA_EEI_EEI18_SHIFT (18U)

#define	DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

#define	DMA_EEI_EEI19_MASK (0x80000U)

#define	DMA_EEI_EEI19_SHIFT (19U)

#define	DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

#define	DMA_EEI_EEI20_MASK (0x100000U)

#define	DMA_EEI_EEI20_SHIFT (20U)

#define	DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

#define	DMA_EEI_EEI21_MASK (0x200000U)

#define	DMA_EEI_EEI21_SHIFT (21U)

#define	DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

#define	DMA_EEI_EEI22_MASK (0x400000U)

#define	DMA_EEI_EEI22_SHIFT (22U)

#define	DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

#define	DMA_EEI_EEI23_MASK (0x800000U)

#define	DMA_EEI_EEI23_SHIFT (23U)

#define	DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

#define	DMA_EEI_EEI24_MASK (0x1000000U)

#define	DMA_EEI_EEI24_SHIFT (24U)

#define	DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

#define	DMA_EEI_EEI25_MASK (0x2000000U)

#define	DMA_EEI_EEI25_SHIFT (25U)

#define	DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

#define	DMA_EEI_EEI26_MASK (0x4000000U)

#define	DMA_EEI_EEI26_SHIFT (26U)

#define	DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

#define	DMA_EEI_EEI27_MASK (0x8000000U)

#define	DMA_EEI_EEI27_SHIFT (27U)

#define	DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

#define	DMA_EEI_EEI28_MASK (0x10000000U)

#define	DMA_EEI_EEI28_SHIFT (28U)

#define	DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

#define	DMA_EEI_EEI29_MASK (0x20000000U)

#define	DMA_EEI_EEI29_SHIFT (29U)

#define	DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

#define	DMA_EEI_EEI30_MASK (0x40000000U)

#define	DMA_EEI_EEI30_SHIFT (30U)

#define	DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

#define	DMA_EEI_EEI31_MASK (0x80000000U)

#define	DMA_EEI_EEI31_SHIFT (31U)

#define	DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

CEEI - Clear Enable Error Interrupt Register
#define	DMA_CEEI_CEEI_MASK (0x1FU)

#define	DMA_CEEI_CEEI_SHIFT (0U)

#define	DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

#define	DMA_CEEI_CAEE_MASK (0x40U)

#define	DMA_CEEI_CAEE_SHIFT (6U)

#define	DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

#define	DMA_CEEI_NOP_MASK (0x80U)

#define	DMA_CEEI_NOP_SHIFT (7U)

#define	DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

SEEI - Set Enable Error Interrupt Register
#define	DMA_SEEI_SEEI_MASK (0x1FU)

#define	DMA_SEEI_SEEI_SHIFT (0U)

#define	DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

#define	DMA_SEEI_SAEE_MASK (0x40U)

#define	DMA_SEEI_SAEE_SHIFT (6U)

#define	DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

#define	DMA_SEEI_NOP_MASK (0x80U)

#define	DMA_SEEI_NOP_SHIFT (7U)

#define	DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

CERQ - Clear Enable Request Register
#define	DMA_CERQ_CERQ_MASK (0x1FU)

#define	DMA_CERQ_CERQ_SHIFT (0U)

#define	DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

#define	DMA_CERQ_CAER_MASK (0x40U)

#define	DMA_CERQ_CAER_SHIFT (6U)

#define	DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

#define	DMA_CERQ_NOP_MASK (0x80U)

#define	DMA_CERQ_NOP_SHIFT (7U)

#define	DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

SERQ - Set Enable Request Register
#define	DMA_SERQ_SERQ_MASK (0x1FU)

#define	DMA_SERQ_SERQ_SHIFT (0U)

#define	DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

#define	DMA_SERQ_SAER_MASK (0x40U)

#define	DMA_SERQ_SAER_SHIFT (6U)

#define	DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

#define	DMA_SERQ_NOP_MASK (0x80U)

#define	DMA_SERQ_NOP_SHIFT (7U)

#define	DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

CDNE - Clear DONE Status Bit Register
#define	DMA_CDNE_CDNE_MASK (0x1FU)

#define	DMA_CDNE_CDNE_SHIFT (0U)

#define	DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

#define	DMA_CDNE_CADN_MASK (0x40U)

#define	DMA_CDNE_CADN_SHIFT (6U)

#define	DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

#define	DMA_CDNE_NOP_MASK (0x80U)

#define	DMA_CDNE_NOP_SHIFT (7U)

#define	DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

SSRT - Set START Bit Register
#define	DMA_SSRT_SSRT_MASK (0x1FU)

#define	DMA_SSRT_SSRT_SHIFT (0U)

#define	DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

#define	DMA_SSRT_SAST_MASK (0x40U)

#define	DMA_SSRT_SAST_SHIFT (6U)

#define	DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

#define	DMA_SSRT_NOP_MASK (0x80U)

#define	DMA_SSRT_NOP_SHIFT (7U)

#define	DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

CERR - Clear Error Register
#define	DMA_CERR_CERR_MASK (0x1FU)

#define	DMA_CERR_CERR_SHIFT (0U)

#define	DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

#define	DMA_CERR_CAEI_MASK (0x40U)

#define	DMA_CERR_CAEI_SHIFT (6U)

#define	DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

#define	DMA_CERR_NOP_MASK (0x80U)

#define	DMA_CERR_NOP_SHIFT (7U)

#define	DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

CINT - Clear Interrupt Request Register
#define	DMA_CINT_CINT_MASK (0x1FU)

#define	DMA_CINT_CINT_SHIFT (0U)

#define	DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

#define	DMA_CINT_CAIR_MASK (0x40U)

#define	DMA_CINT_CAIR_SHIFT (6U)

#define	DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

#define	DMA_CINT_NOP_MASK (0x80U)

#define	DMA_CINT_NOP_SHIFT (7U)

#define	DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

INT - Interrupt Request Register
#define	DMA_INT_INT0_MASK (0x1U)

#define	DMA_INT_INT0_SHIFT (0U)

#define	DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

#define	DMA_INT_INT1_MASK (0x2U)

#define	DMA_INT_INT1_SHIFT (1U)

#define	DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

#define	DMA_INT_INT2_MASK (0x4U)

#define	DMA_INT_INT2_SHIFT (2U)

#define	DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

#define	DMA_INT_INT3_MASK (0x8U)

#define	DMA_INT_INT3_SHIFT (3U)

#define	DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

#define	DMA_INT_INT4_MASK (0x10U)

#define	DMA_INT_INT4_SHIFT (4U)

#define	DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

#define	DMA_INT_INT5_MASK (0x20U)

#define	DMA_INT_INT5_SHIFT (5U)

#define	DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

#define	DMA_INT_INT6_MASK (0x40U)

#define	DMA_INT_INT6_SHIFT (6U)

#define	DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

#define	DMA_INT_INT7_MASK (0x80U)

#define	DMA_INT_INT7_SHIFT (7U)

#define	DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

#define	DMA_INT_INT8_MASK (0x100U)

#define	DMA_INT_INT8_SHIFT (8U)

#define	DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

#define	DMA_INT_INT9_MASK (0x200U)

#define	DMA_INT_INT9_SHIFT (9U)

#define	DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

#define	DMA_INT_INT10_MASK (0x400U)

#define	DMA_INT_INT10_SHIFT (10U)

#define	DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

#define	DMA_INT_INT11_MASK (0x800U)

#define	DMA_INT_INT11_SHIFT (11U)

#define	DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

#define	DMA_INT_INT12_MASK (0x1000U)

#define	DMA_INT_INT12_SHIFT (12U)

#define	DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

#define	DMA_INT_INT13_MASK (0x2000U)

#define	DMA_INT_INT13_SHIFT (13U)

#define	DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

#define	DMA_INT_INT14_MASK (0x4000U)

#define	DMA_INT_INT14_SHIFT (14U)

#define	DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

#define	DMA_INT_INT15_MASK (0x8000U)

#define	DMA_INT_INT15_SHIFT (15U)

#define	DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

#define	DMA_INT_INT16_MASK (0x10000U)

#define	DMA_INT_INT16_SHIFT (16U)

#define	DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

#define	DMA_INT_INT17_MASK (0x20000U)

#define	DMA_INT_INT17_SHIFT (17U)

#define	DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

#define	DMA_INT_INT18_MASK (0x40000U)

#define	DMA_INT_INT18_SHIFT (18U)

#define	DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

#define	DMA_INT_INT19_MASK (0x80000U)

#define	DMA_INT_INT19_SHIFT (19U)

#define	DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

#define	DMA_INT_INT20_MASK (0x100000U)

#define	DMA_INT_INT20_SHIFT (20U)

#define	DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

#define	DMA_INT_INT21_MASK (0x200000U)

#define	DMA_INT_INT21_SHIFT (21U)

#define	DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

#define	DMA_INT_INT22_MASK (0x400000U)

#define	DMA_INT_INT22_SHIFT (22U)

#define	DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

#define	DMA_INT_INT23_MASK (0x800000U)

#define	DMA_INT_INT23_SHIFT (23U)

#define	DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

#define	DMA_INT_INT24_MASK (0x1000000U)

#define	DMA_INT_INT24_SHIFT (24U)

#define	DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

#define	DMA_INT_INT25_MASK (0x2000000U)

#define	DMA_INT_INT25_SHIFT (25U)

#define	DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

#define	DMA_INT_INT26_MASK (0x4000000U)

#define	DMA_INT_INT26_SHIFT (26U)

#define	DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

#define	DMA_INT_INT27_MASK (0x8000000U)

#define	DMA_INT_INT27_SHIFT (27U)

#define	DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

#define	DMA_INT_INT28_MASK (0x10000000U)

#define	DMA_INT_INT28_SHIFT (28U)

#define	DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

#define	DMA_INT_INT29_MASK (0x20000000U)

#define	DMA_INT_INT29_SHIFT (29U)

#define	DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

#define	DMA_INT_INT30_MASK (0x40000000U)

#define	DMA_INT_INT30_SHIFT (30U)

#define	DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

#define	DMA_INT_INT31_MASK (0x80000000U)

#define	DMA_INT_INT31_SHIFT (31U)

#define	DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

ERR - Error Register
#define	DMA_ERR_ERR0_MASK (0x1U)

#define	DMA_ERR_ERR0_SHIFT (0U)

#define	DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

#define	DMA_ERR_ERR1_MASK (0x2U)

#define	DMA_ERR_ERR1_SHIFT (1U)

#define	DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

#define	DMA_ERR_ERR2_MASK (0x4U)

#define	DMA_ERR_ERR2_SHIFT (2U)

#define	DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

#define	DMA_ERR_ERR3_MASK (0x8U)

#define	DMA_ERR_ERR3_SHIFT (3U)

#define	DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

#define	DMA_ERR_ERR4_MASK (0x10U)

#define	DMA_ERR_ERR4_SHIFT (4U)

#define	DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

#define	DMA_ERR_ERR5_MASK (0x20U)

#define	DMA_ERR_ERR5_SHIFT (5U)

#define	DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

#define	DMA_ERR_ERR6_MASK (0x40U)

#define	DMA_ERR_ERR6_SHIFT (6U)

#define	DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

#define	DMA_ERR_ERR7_MASK (0x80U)

#define	DMA_ERR_ERR7_SHIFT (7U)

#define	DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

#define	DMA_ERR_ERR8_MASK (0x100U)

#define	DMA_ERR_ERR8_SHIFT (8U)

#define	DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

#define	DMA_ERR_ERR9_MASK (0x200U)

#define	DMA_ERR_ERR9_SHIFT (9U)

#define	DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

#define	DMA_ERR_ERR10_MASK (0x400U)

#define	DMA_ERR_ERR10_SHIFT (10U)

#define	DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

#define	DMA_ERR_ERR11_MASK (0x800U)

#define	DMA_ERR_ERR11_SHIFT (11U)

#define	DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

#define	DMA_ERR_ERR12_MASK (0x1000U)

#define	DMA_ERR_ERR12_SHIFT (12U)

#define	DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

#define	DMA_ERR_ERR13_MASK (0x2000U)

#define	DMA_ERR_ERR13_SHIFT (13U)

#define	DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

#define	DMA_ERR_ERR14_MASK (0x4000U)

#define	DMA_ERR_ERR14_SHIFT (14U)

#define	DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

#define	DMA_ERR_ERR15_MASK (0x8000U)

#define	DMA_ERR_ERR15_SHIFT (15U)

#define	DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

#define	DMA_ERR_ERR16_MASK (0x10000U)

#define	DMA_ERR_ERR16_SHIFT (16U)

#define	DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

#define	DMA_ERR_ERR17_MASK (0x20000U)

#define	DMA_ERR_ERR17_SHIFT (17U)

#define	DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

#define	DMA_ERR_ERR18_MASK (0x40000U)

#define	DMA_ERR_ERR18_SHIFT (18U)

#define	DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

#define	DMA_ERR_ERR19_MASK (0x80000U)

#define	DMA_ERR_ERR19_SHIFT (19U)

#define	DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

#define	DMA_ERR_ERR20_MASK (0x100000U)

#define	DMA_ERR_ERR20_SHIFT (20U)

#define	DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

#define	DMA_ERR_ERR21_MASK (0x200000U)

#define	DMA_ERR_ERR21_SHIFT (21U)

#define	DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

#define	DMA_ERR_ERR22_MASK (0x400000U)

#define	DMA_ERR_ERR22_SHIFT (22U)

#define	DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

#define	DMA_ERR_ERR23_MASK (0x800000U)

#define	DMA_ERR_ERR23_SHIFT (23U)

#define	DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

#define	DMA_ERR_ERR24_MASK (0x1000000U)

#define	DMA_ERR_ERR24_SHIFT (24U)

#define	DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

#define	DMA_ERR_ERR25_MASK (0x2000000U)

#define	DMA_ERR_ERR25_SHIFT (25U)

#define	DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

#define	DMA_ERR_ERR26_MASK (0x4000000U)

#define	DMA_ERR_ERR26_SHIFT (26U)

#define	DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

#define	DMA_ERR_ERR27_MASK (0x8000000U)

#define	DMA_ERR_ERR27_SHIFT (27U)

#define	DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

#define	DMA_ERR_ERR28_MASK (0x10000000U)

#define	DMA_ERR_ERR28_SHIFT (28U)

#define	DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

#define	DMA_ERR_ERR29_MASK (0x20000000U)

#define	DMA_ERR_ERR29_SHIFT (29U)

#define	DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

#define	DMA_ERR_ERR30_MASK (0x40000000U)

#define	DMA_ERR_ERR30_SHIFT (30U)

#define	DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

#define	DMA_ERR_ERR31_MASK (0x80000000U)

#define	DMA_ERR_ERR31_SHIFT (31U)

#define	DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

HRS - Hardware Request Status Register
#define	DMA_HRS_HRS0_MASK (0x1U)

#define	DMA_HRS_HRS0_SHIFT (0U)

#define	DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

#define	DMA_HRS_HRS1_MASK (0x2U)

#define	DMA_HRS_HRS1_SHIFT (1U)

#define	DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

#define	DMA_HRS_HRS2_MASK (0x4U)

#define	DMA_HRS_HRS2_SHIFT (2U)

#define	DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

#define	DMA_HRS_HRS3_MASK (0x8U)

#define	DMA_HRS_HRS3_SHIFT (3U)

#define	DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

#define	DMA_HRS_HRS4_MASK (0x10U)

#define	DMA_HRS_HRS4_SHIFT (4U)

#define	DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

#define	DMA_HRS_HRS5_MASK (0x20U)

#define	DMA_HRS_HRS5_SHIFT (5U)

#define	DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

#define	DMA_HRS_HRS6_MASK (0x40U)

#define	DMA_HRS_HRS6_SHIFT (6U)

#define	DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

#define	DMA_HRS_HRS7_MASK (0x80U)

#define	DMA_HRS_HRS7_SHIFT (7U)

#define	DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

#define	DMA_HRS_HRS8_MASK (0x100U)

#define	DMA_HRS_HRS8_SHIFT (8U)

#define	DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

#define	DMA_HRS_HRS9_MASK (0x200U)

#define	DMA_HRS_HRS9_SHIFT (9U)

#define	DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

#define	DMA_HRS_HRS10_MASK (0x400U)

#define	DMA_HRS_HRS10_SHIFT (10U)

#define	DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

#define	DMA_HRS_HRS11_MASK (0x800U)

#define	DMA_HRS_HRS11_SHIFT (11U)

#define	DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

#define	DMA_HRS_HRS12_MASK (0x1000U)

#define	DMA_HRS_HRS12_SHIFT (12U)

#define	DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

#define	DMA_HRS_HRS13_MASK (0x2000U)

#define	DMA_HRS_HRS13_SHIFT (13U)

#define	DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

#define	DMA_HRS_HRS14_MASK (0x4000U)

#define	DMA_HRS_HRS14_SHIFT (14U)

#define	DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

#define	DMA_HRS_HRS15_MASK (0x8000U)

#define	DMA_HRS_HRS15_SHIFT (15U)

#define	DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

#define	DMA_HRS_HRS16_MASK (0x10000U)

#define	DMA_HRS_HRS16_SHIFT (16U)

#define	DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

#define	DMA_HRS_HRS17_MASK (0x20000U)

#define	DMA_HRS_HRS17_SHIFT (17U)

#define	DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

#define	DMA_HRS_HRS18_MASK (0x40000U)

#define	DMA_HRS_HRS18_SHIFT (18U)

#define	DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

#define	DMA_HRS_HRS19_MASK (0x80000U)

#define	DMA_HRS_HRS19_SHIFT (19U)

#define	DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

#define	DMA_HRS_HRS20_MASK (0x100000U)

#define	DMA_HRS_HRS20_SHIFT (20U)

#define	DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

#define	DMA_HRS_HRS21_MASK (0x200000U)

#define	DMA_HRS_HRS21_SHIFT (21U)

#define	DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

#define	DMA_HRS_HRS22_MASK (0x400000U)

#define	DMA_HRS_HRS22_SHIFT (22U)

#define	DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

#define	DMA_HRS_HRS23_MASK (0x800000U)

#define	DMA_HRS_HRS23_SHIFT (23U)

#define	DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

#define	DMA_HRS_HRS24_MASK (0x1000000U)

#define	DMA_HRS_HRS24_SHIFT (24U)

#define	DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

#define	DMA_HRS_HRS25_MASK (0x2000000U)

#define	DMA_HRS_HRS25_SHIFT (25U)

#define	DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

#define	DMA_HRS_HRS26_MASK (0x4000000U)

#define	DMA_HRS_HRS26_SHIFT (26U)

#define	DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

#define	DMA_HRS_HRS27_MASK (0x8000000U)

#define	DMA_HRS_HRS27_SHIFT (27U)

#define	DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

#define	DMA_HRS_HRS28_MASK (0x10000000U)

#define	DMA_HRS_HRS28_SHIFT (28U)

#define	DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

#define	DMA_HRS_HRS29_MASK (0x20000000U)

#define	DMA_HRS_HRS29_SHIFT (29U)

#define	DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

#define	DMA_HRS_HRS30_MASK (0x40000000U)

#define	DMA_HRS_HRS30_SHIFT (30U)

#define	DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

#define	DMA_HRS_HRS31_MASK (0x80000000U)

#define	DMA_HRS_HRS31_SHIFT (31U)

#define	DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

EARS - Enable Asynchronous Request in Stop Register
#define	DMA_EARS_EDREQ_0_MASK (0x1U)

#define	DMA_EARS_EDREQ_0_SHIFT (0U)

#define	DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

#define	DMA_EARS_EDREQ_1_MASK (0x2U)

#define	DMA_EARS_EDREQ_1_SHIFT (1U)

#define	DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

#define	DMA_EARS_EDREQ_2_MASK (0x4U)

#define	DMA_EARS_EDREQ_2_SHIFT (2U)

#define	DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

#define	DMA_EARS_EDREQ_3_MASK (0x8U)

#define	DMA_EARS_EDREQ_3_SHIFT (3U)

#define	DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

#define	DMA_EARS_EDREQ_4_MASK (0x10U)

#define	DMA_EARS_EDREQ_4_SHIFT (4U)

#define	DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

#define	DMA_EARS_EDREQ_5_MASK (0x20U)

#define	DMA_EARS_EDREQ_5_SHIFT (5U)

#define	DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

#define	DMA_EARS_EDREQ_6_MASK (0x40U)

#define	DMA_EARS_EDREQ_6_SHIFT (6U)

#define	DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

#define	DMA_EARS_EDREQ_7_MASK (0x80U)

#define	DMA_EARS_EDREQ_7_SHIFT (7U)

#define	DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

#define	DMA_EARS_EDREQ_8_MASK (0x100U)

#define	DMA_EARS_EDREQ_8_SHIFT (8U)

#define	DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

#define	DMA_EARS_EDREQ_9_MASK (0x200U)

#define	DMA_EARS_EDREQ_9_SHIFT (9U)

#define	DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

#define	DMA_EARS_EDREQ_10_MASK (0x400U)

#define	DMA_EARS_EDREQ_10_SHIFT (10U)

#define	DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

#define	DMA_EARS_EDREQ_11_MASK (0x800U)

#define	DMA_EARS_EDREQ_11_SHIFT (11U)

#define	DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

#define	DMA_EARS_EDREQ_12_MASK (0x1000U)

#define	DMA_EARS_EDREQ_12_SHIFT (12U)

#define	DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

#define	DMA_EARS_EDREQ_13_MASK (0x2000U)

#define	DMA_EARS_EDREQ_13_SHIFT (13U)

#define	DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

#define	DMA_EARS_EDREQ_14_MASK (0x4000U)

#define	DMA_EARS_EDREQ_14_SHIFT (14U)

#define	DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

#define	DMA_EARS_EDREQ_15_MASK (0x8000U)

#define	DMA_EARS_EDREQ_15_SHIFT (15U)

#define	DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

#define	DMA_EARS_EDREQ_16_MASK (0x10000U)

#define	DMA_EARS_EDREQ_16_SHIFT (16U)

#define	DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

#define	DMA_EARS_EDREQ_17_MASK (0x20000U)

#define	DMA_EARS_EDREQ_17_SHIFT (17U)

#define	DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

#define	DMA_EARS_EDREQ_18_MASK (0x40000U)

#define	DMA_EARS_EDREQ_18_SHIFT (18U)

#define	DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

#define	DMA_EARS_EDREQ_19_MASK (0x80000U)

#define	DMA_EARS_EDREQ_19_SHIFT (19U)

#define	DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

#define	DMA_EARS_EDREQ_20_MASK (0x100000U)

#define	DMA_EARS_EDREQ_20_SHIFT (20U)

#define	DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

#define	DMA_EARS_EDREQ_21_MASK (0x200000U)

#define	DMA_EARS_EDREQ_21_SHIFT (21U)

#define	DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

#define	DMA_EARS_EDREQ_22_MASK (0x400000U)

#define	DMA_EARS_EDREQ_22_SHIFT (22U)

#define	DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

#define	DMA_EARS_EDREQ_23_MASK (0x800000U)

#define	DMA_EARS_EDREQ_23_SHIFT (23U)

#define	DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

#define	DMA_EARS_EDREQ_24_MASK (0x1000000U)

#define	DMA_EARS_EDREQ_24_SHIFT (24U)

#define	DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

#define	DMA_EARS_EDREQ_25_MASK (0x2000000U)

#define	DMA_EARS_EDREQ_25_SHIFT (25U)

#define	DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

#define	DMA_EARS_EDREQ_26_MASK (0x4000000U)

#define	DMA_EARS_EDREQ_26_SHIFT (26U)

#define	DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

#define	DMA_EARS_EDREQ_27_MASK (0x8000000U)

#define	DMA_EARS_EDREQ_27_SHIFT (27U)

#define	DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

#define	DMA_EARS_EDREQ_28_MASK (0x10000000U)

#define	DMA_EARS_EDREQ_28_SHIFT (28U)

#define	DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

#define	DMA_EARS_EDREQ_29_MASK (0x20000000U)

#define	DMA_EARS_EDREQ_29_SHIFT (29U)

#define	DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

#define	DMA_EARS_EDREQ_30_MASK (0x40000000U)

#define	DMA_EARS_EDREQ_30_SHIFT (30U)

#define	DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

#define	DMA_EARS_EDREQ_31_MASK (0x80000000U)

#define	DMA_EARS_EDREQ_31_SHIFT (31U)

#define	DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

DCHPRI3 - Channel n Priority Register
#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

#define	DMA_DCHPRI3_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI3_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

#define	DMA_DCHPRI3_DPA_MASK (0x40U)

#define	DMA_DCHPRI3_DPA_SHIFT (6U)

#define	DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

#define	DMA_DCHPRI3_ECP_MASK (0x80U)

#define	DMA_DCHPRI3_ECP_SHIFT (7U)

#define	DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

DCHPRI2 - Channel n Priority Register
#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

#define	DMA_DCHPRI2_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI2_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

#define	DMA_DCHPRI2_DPA_MASK (0x40U)

#define	DMA_DCHPRI2_DPA_SHIFT (6U)

#define	DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

#define	DMA_DCHPRI2_ECP_MASK (0x80U)

#define	DMA_DCHPRI2_ECP_SHIFT (7U)

#define	DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

DCHPRI1 - Channel n Priority Register
#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

#define	DMA_DCHPRI1_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI1_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

#define	DMA_DCHPRI1_DPA_MASK (0x40U)

#define	DMA_DCHPRI1_DPA_SHIFT (6U)

#define	DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

#define	DMA_DCHPRI1_ECP_MASK (0x80U)

#define	DMA_DCHPRI1_ECP_SHIFT (7U)

#define	DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

DCHPRI0 - Channel n Priority Register
#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

#define	DMA_DCHPRI0_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI0_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

#define	DMA_DCHPRI0_DPA_MASK (0x40U)

#define	DMA_DCHPRI0_DPA_SHIFT (6U)

#define	DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

#define	DMA_DCHPRI0_ECP_MASK (0x80U)

#define	DMA_DCHPRI0_ECP_SHIFT (7U)

#define	DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

DCHPRI7 - Channel n Priority Register
#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

#define	DMA_DCHPRI7_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI7_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

#define	DMA_DCHPRI7_DPA_MASK (0x40U)

#define	DMA_DCHPRI7_DPA_SHIFT (6U)

#define	DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

#define	DMA_DCHPRI7_ECP_MASK (0x80U)

#define	DMA_DCHPRI7_ECP_SHIFT (7U)

#define	DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

DCHPRI6 - Channel n Priority Register
#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

#define	DMA_DCHPRI6_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI6_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

#define	DMA_DCHPRI6_DPA_MASK (0x40U)

#define	DMA_DCHPRI6_DPA_SHIFT (6U)

#define	DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

#define	DMA_DCHPRI6_ECP_MASK (0x80U)

#define	DMA_DCHPRI6_ECP_SHIFT (7U)

#define	DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

DCHPRI5 - Channel n Priority Register
#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

#define	DMA_DCHPRI5_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI5_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

#define	DMA_DCHPRI5_DPA_MASK (0x40U)

#define	DMA_DCHPRI5_DPA_SHIFT (6U)

#define	DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

#define	DMA_DCHPRI5_ECP_MASK (0x80U)

#define	DMA_DCHPRI5_ECP_SHIFT (7U)

#define	DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

DCHPRI4 - Channel n Priority Register
#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

#define	DMA_DCHPRI4_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI4_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

#define	DMA_DCHPRI4_DPA_MASK (0x40U)

#define	DMA_DCHPRI4_DPA_SHIFT (6U)

#define	DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

#define	DMA_DCHPRI4_ECP_MASK (0x80U)

#define	DMA_DCHPRI4_ECP_SHIFT (7U)

#define	DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

DCHPRI11 - Channel n Priority Register
#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

#define	DMA_DCHPRI11_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI11_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

#define	DMA_DCHPRI11_DPA_MASK (0x40U)

#define	DMA_DCHPRI11_DPA_SHIFT (6U)

#define	DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

#define	DMA_DCHPRI11_ECP_MASK (0x80U)

#define	DMA_DCHPRI11_ECP_SHIFT (7U)

#define	DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

DCHPRI10 - Channel n Priority Register
#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

#define	DMA_DCHPRI10_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI10_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

#define	DMA_DCHPRI10_DPA_MASK (0x40U)

#define	DMA_DCHPRI10_DPA_SHIFT (6U)

#define	DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

#define	DMA_DCHPRI10_ECP_MASK (0x80U)

#define	DMA_DCHPRI10_ECP_SHIFT (7U)

#define	DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

DCHPRI9 - Channel n Priority Register
#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

#define	DMA_DCHPRI9_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI9_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

#define	DMA_DCHPRI9_DPA_MASK (0x40U)

#define	DMA_DCHPRI9_DPA_SHIFT (6U)

#define	DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

#define	DMA_DCHPRI9_ECP_MASK (0x80U)

#define	DMA_DCHPRI9_ECP_SHIFT (7U)

#define	DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

DCHPRI8 - Channel n Priority Register
#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

#define	DMA_DCHPRI8_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI8_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

#define	DMA_DCHPRI8_DPA_MASK (0x40U)

#define	DMA_DCHPRI8_DPA_SHIFT (6U)

#define	DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

#define	DMA_DCHPRI8_ECP_MASK (0x80U)

#define	DMA_DCHPRI8_ECP_SHIFT (7U)

#define	DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

DCHPRI15 - Channel n Priority Register
#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

#define	DMA_DCHPRI15_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI15_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

#define	DMA_DCHPRI15_DPA_MASK (0x40U)

#define	DMA_DCHPRI15_DPA_SHIFT (6U)

#define	DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

#define	DMA_DCHPRI15_ECP_MASK (0x80U)

#define	DMA_DCHPRI15_ECP_SHIFT (7U)

#define	DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

DCHPRI14 - Channel n Priority Register
#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

#define	DMA_DCHPRI14_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI14_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

#define	DMA_DCHPRI14_DPA_MASK (0x40U)

#define	DMA_DCHPRI14_DPA_SHIFT (6U)

#define	DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

#define	DMA_DCHPRI14_ECP_MASK (0x80U)

#define	DMA_DCHPRI14_ECP_SHIFT (7U)

#define	DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

DCHPRI13 - Channel n Priority Register
#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

#define	DMA_DCHPRI13_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI13_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

#define	DMA_DCHPRI13_DPA_MASK (0x40U)

#define	DMA_DCHPRI13_DPA_SHIFT (6U)

#define	DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

#define	DMA_DCHPRI13_ECP_MASK (0x80U)

#define	DMA_DCHPRI13_ECP_SHIFT (7U)

#define	DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

DCHPRI12 - Channel n Priority Register
#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

#define	DMA_DCHPRI12_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI12_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

#define	DMA_DCHPRI12_DPA_MASK (0x40U)

#define	DMA_DCHPRI12_DPA_SHIFT (6U)

#define	DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

#define	DMA_DCHPRI12_ECP_MASK (0x80U)

#define	DMA_DCHPRI12_ECP_SHIFT (7U)

#define	DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

DCHPRI19 - Channel n Priority Register
#define	DMA_DCHPRI19_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI19_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

#define	DMA_DCHPRI19_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI19_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

#define	DMA_DCHPRI19_DPA_MASK (0x40U)

#define	DMA_DCHPRI19_DPA_SHIFT (6U)

#define	DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

#define	DMA_DCHPRI19_ECP_MASK (0x80U)

#define	DMA_DCHPRI19_ECP_SHIFT (7U)

#define	DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

DCHPRI18 - Channel n Priority Register
#define	DMA_DCHPRI18_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI18_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

#define	DMA_DCHPRI18_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI18_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

#define	DMA_DCHPRI18_DPA_MASK (0x40U)

#define	DMA_DCHPRI18_DPA_SHIFT (6U)

#define	DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

#define	DMA_DCHPRI18_ECP_MASK (0x80U)

#define	DMA_DCHPRI18_ECP_SHIFT (7U)

#define	DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

DCHPRI17 - Channel n Priority Register
#define	DMA_DCHPRI17_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI17_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

#define	DMA_DCHPRI17_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI17_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

#define	DMA_DCHPRI17_DPA_MASK (0x40U)

#define	DMA_DCHPRI17_DPA_SHIFT (6U)

#define	DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

#define	DMA_DCHPRI17_ECP_MASK (0x80U)

#define	DMA_DCHPRI17_ECP_SHIFT (7U)

#define	DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

DCHPRI16 - Channel n Priority Register
#define	DMA_DCHPRI16_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI16_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

#define	DMA_DCHPRI16_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI16_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

#define	DMA_DCHPRI16_DPA_MASK (0x40U)

#define	DMA_DCHPRI16_DPA_SHIFT (6U)

#define	DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

#define	DMA_DCHPRI16_ECP_MASK (0x80U)

#define	DMA_DCHPRI16_ECP_SHIFT (7U)

#define	DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

DCHPRI23 - Channel n Priority Register
#define	DMA_DCHPRI23_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI23_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

#define	DMA_DCHPRI23_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI23_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

#define	DMA_DCHPRI23_DPA_MASK (0x40U)

#define	DMA_DCHPRI23_DPA_SHIFT (6U)

#define	DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

#define	DMA_DCHPRI23_ECP_MASK (0x80U)

#define	DMA_DCHPRI23_ECP_SHIFT (7U)

#define	DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

DCHPRI22 - Channel n Priority Register
#define	DMA_DCHPRI22_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI22_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

#define	DMA_DCHPRI22_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI22_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

#define	DMA_DCHPRI22_DPA_MASK (0x40U)

#define	DMA_DCHPRI22_DPA_SHIFT (6U)

#define	DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

#define	DMA_DCHPRI22_ECP_MASK (0x80U)

#define	DMA_DCHPRI22_ECP_SHIFT (7U)

#define	DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

DCHPRI21 - Channel n Priority Register
#define	DMA_DCHPRI21_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI21_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

#define	DMA_DCHPRI21_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI21_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

#define	DMA_DCHPRI21_DPA_MASK (0x40U)

#define	DMA_DCHPRI21_DPA_SHIFT (6U)

#define	DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

#define	DMA_DCHPRI21_ECP_MASK (0x80U)

#define	DMA_DCHPRI21_ECP_SHIFT (7U)

#define	DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

DCHPRI20 - Channel n Priority Register
#define	DMA_DCHPRI20_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI20_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

#define	DMA_DCHPRI20_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI20_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

#define	DMA_DCHPRI20_DPA_MASK (0x40U)

#define	DMA_DCHPRI20_DPA_SHIFT (6U)

#define	DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

#define	DMA_DCHPRI20_ECP_MASK (0x80U)

#define	DMA_DCHPRI20_ECP_SHIFT (7U)

#define	DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

DCHPRI27 - Channel n Priority Register
#define	DMA_DCHPRI27_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI27_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

#define	DMA_DCHPRI27_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI27_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

#define	DMA_DCHPRI27_DPA_MASK (0x40U)

#define	DMA_DCHPRI27_DPA_SHIFT (6U)

#define	DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

#define	DMA_DCHPRI27_ECP_MASK (0x80U)

#define	DMA_DCHPRI27_ECP_SHIFT (7U)

#define	DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

DCHPRI26 - Channel n Priority Register
#define	DMA_DCHPRI26_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI26_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

#define	DMA_DCHPRI26_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI26_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

#define	DMA_DCHPRI26_DPA_MASK (0x40U)

#define	DMA_DCHPRI26_DPA_SHIFT (6U)

#define	DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

#define	DMA_DCHPRI26_ECP_MASK (0x80U)

#define	DMA_DCHPRI26_ECP_SHIFT (7U)

#define	DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

DCHPRI25 - Channel n Priority Register
#define	DMA_DCHPRI25_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI25_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

#define	DMA_DCHPRI25_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI25_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

#define	DMA_DCHPRI25_DPA_MASK (0x40U)

#define	DMA_DCHPRI25_DPA_SHIFT (6U)

#define	DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

#define	DMA_DCHPRI25_ECP_MASK (0x80U)

#define	DMA_DCHPRI25_ECP_SHIFT (7U)

#define	DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

DCHPRI24 - Channel n Priority Register
#define	DMA_DCHPRI24_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI24_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

#define	DMA_DCHPRI24_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI24_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

#define	DMA_DCHPRI24_DPA_MASK (0x40U)

#define	DMA_DCHPRI24_DPA_SHIFT (6U)

#define	DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

#define	DMA_DCHPRI24_ECP_MASK (0x80U)

#define	DMA_DCHPRI24_ECP_SHIFT (7U)

#define	DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

DCHPRI31 - Channel n Priority Register
#define	DMA_DCHPRI31_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI31_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

#define	DMA_DCHPRI31_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI31_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

#define	DMA_DCHPRI31_DPA_MASK (0x40U)

#define	DMA_DCHPRI31_DPA_SHIFT (6U)

#define	DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

#define	DMA_DCHPRI31_ECP_MASK (0x80U)

#define	DMA_DCHPRI31_ECP_SHIFT (7U)

#define	DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

DCHPRI30 - Channel n Priority Register
#define	DMA_DCHPRI30_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI30_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

#define	DMA_DCHPRI30_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI30_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

#define	DMA_DCHPRI30_DPA_MASK (0x40U)

#define	DMA_DCHPRI30_DPA_SHIFT (6U)

#define	DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

#define	DMA_DCHPRI30_ECP_MASK (0x80U)

#define	DMA_DCHPRI30_ECP_SHIFT (7U)

#define	DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

DCHPRI29 - Channel n Priority Register
#define	DMA_DCHPRI29_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI29_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

#define	DMA_DCHPRI29_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI29_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

#define	DMA_DCHPRI29_DPA_MASK (0x40U)

#define	DMA_DCHPRI29_DPA_SHIFT (6U)

#define	DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

#define	DMA_DCHPRI29_ECP_MASK (0x80U)

#define	DMA_DCHPRI29_ECP_SHIFT (7U)

#define	DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

DCHPRI28 - Channel n Priority Register
#define	DMA_DCHPRI28_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI28_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

#define	DMA_DCHPRI28_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI28_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

#define	DMA_DCHPRI28_DPA_MASK (0x40U)

#define	DMA_DCHPRI28_DPA_SHIFT (6U)

#define	DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

#define	DMA_DCHPRI28_ECP_MASK (0x80U)

#define	DMA_DCHPRI28_ECP_SHIFT (7U)

#define	DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

SADDR - TCD Source Address
#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)

#define	DMA_SADDR_SADDR_SHIFT (0U)

#define	DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

SOFF - TCD Signed Source Address Offset
#define	DMA_SOFF_SOFF_MASK (0xFFFFU)

#define	DMA_SOFF_SOFF_SHIFT (0U)

#define	DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

ATTR - TCD Transfer Attributes
#define	DMA_ATTR_DSIZE_MASK (0x7U)

#define	DMA_ATTR_DSIZE_SHIFT (0U)

#define	DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

#define	DMA_ATTR_DMOD_MASK (0xF8U)

#define	DMA_ATTR_DMOD_SHIFT (3U)

#define	DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

#define	DMA_ATTR_SSIZE_MASK (0x700U)

#define	DMA_ATTR_SSIZE_SHIFT (8U)

#define	DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

#define	DMA_ATTR_SMOD_MASK (0xF800U)

#define	DMA_ATTR_SMOD_SHIFT (11U)

#define	DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)
#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)

#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)

#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)

#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)

#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)

#define	DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SLAST - TCD Last Source Address Adjustment
#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)

#define	DMA_SLAST_SLAST_SHIFT (0U)

#define	DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

DADDR - TCD Destination Address
#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)

#define	DMA_DADDR_DADDR_SHIFT (0U)

#define	DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

DOFF - TCD Signed Destination Address Offset
#define	DMA_DOFF_DOFF_MASK (0xFFFFU)

#define	DMA_DOFF_DOFF_SHIFT (0U)

#define	DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)

#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)

#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)

#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)

#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)

#define	DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

CSR - TCD Control and Status
#define	DMA_CSR_START_MASK (0x1U)

#define	DMA_CSR_START_SHIFT (0U)

#define	DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

#define	DMA_CSR_INTMAJOR_MASK (0x2U)

#define	DMA_CSR_INTMAJOR_SHIFT (1U)

#define	DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

#define	DMA_CSR_INTHALF_MASK (0x4U)

#define	DMA_CSR_INTHALF_SHIFT (2U)

#define	DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

#define	DMA_CSR_DREQ_MASK (0x8U)

#define	DMA_CSR_DREQ_SHIFT (3U)

#define	DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

#define	DMA_CSR_ESG_MASK (0x10U)

#define	DMA_CSR_ESG_SHIFT (4U)

#define	DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

#define	DMA_CSR_MAJORELINK_MASK (0x20U)

#define	DMA_CSR_MAJORELINK_SHIFT (5U)

#define	DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

#define	DMA_CSR_ACTIVE_MASK (0x40U)

#define	DMA_CSR_ACTIVE_SHIFT (6U)

#define	DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

#define	DMA_CSR_DONE_MASK (0x80U)

#define	DMA_CSR_DONE_SHIFT (7U)

#define	DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

#define	DMA_CSR_MAJORLINKCH_MASK (0x1F00U)

#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)

#define	DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

#define	DMA_CSR_BWC_MASK (0xC000U)

#define	DMA_CSR_BWC_SHIFT (14U)

#define	DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)

#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)

#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)

#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

Detailed Description

Macro Definition Documentation

◆ DMA_ATTR_COUNT

#define DMA_ATTR_COUNT (32U)

Definition at line 14746 of file MIMXRT1052.h.

◆ DMA_ATTR_DMOD

#define DMA_ATTR_DMOD ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

DMOD - Destination Address Modulo

Definition at line 14715 of file MIMXRT1052.h.

◆ DMA_ATTR_DMOD_MASK

#define DMA_ATTR_DMOD_MASK (0xF8U)

Definition at line 14711 of file MIMXRT1052.h.

◆ DMA_ATTR_DMOD_SHIFT

#define DMA_ATTR_DMOD_SHIFT (3U)

Definition at line 14712 of file MIMXRT1052.h.

◆ DMA_ATTR_DSIZE

#define DMA_ATTR_DSIZE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

DSIZE - Destination data transfer size

Definition at line 14710 of file MIMXRT1052.h.

◆ DMA_ATTR_DSIZE_MASK

#define DMA_ATTR_DSIZE_MASK (0x7U)

Definition at line 14706 of file MIMXRT1052.h.

◆ DMA_ATTR_DSIZE_SHIFT

#define DMA_ATTR_DSIZE_SHIFT (0U)

Definition at line 14707 of file MIMXRT1052.h.

◆ DMA_ATTR_SMOD

#define DMA_ATTR_SMOD ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.

Definition at line 14742 of file MIMXRT1052.h.

◆ DMA_ATTR_SMOD_MASK

#define DMA_ATTR_SMOD_MASK (0xF800U)

Definition at line 14729 of file MIMXRT1052.h.

◆ DMA_ATTR_SMOD_SHIFT

#define DMA_ATTR_SMOD_SHIFT (11U)

Definition at line 14730 of file MIMXRT1052.h.

◆ DMA_ATTR_SSIZE

#define DMA_ATTR_SSIZE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..64-bit 0b100..Reserved 0b101..32-byte burst (4 beats of 64 bits) 0b110..Reserved 0b111..Reserved

Definition at line 14728 of file MIMXRT1052.h.

◆ DMA_ATTR_SSIZE_MASK

#define DMA_ATTR_SSIZE_MASK (0x700U)

Definition at line 14716 of file MIMXRT1052.h.

◆ DMA_ATTR_SSIZE_SHIFT

#define DMA_ATTR_SSIZE_SHIFT (8U)

Definition at line 14717 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKNO_BITER

#define DMA_BITER_ELINKNO_BITER ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

BITER - Starting Major Iteration Count

Definition at line 14989 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKNO_BITER_MASK

#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)

Definition at line 14985 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKNO_BITER_SHIFT

#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)

Definition at line 14986 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKNO_COUNT

#define DMA_BITER_ELINKNO_COUNT (32U)

Definition at line 15000 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKNO_ELINK

#define DMA_BITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

Definition at line 14996 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKNO_ELINK_MASK

#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)

Definition at line 14990 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKNO_ELINK_SHIFT

#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)

Definition at line 14991 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_BITER

#define DMA_BITER_ELINKYES_BITER ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

BITER - Starting major iteration count

Definition at line 15008 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_BITER_MASK

#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)

Definition at line 15004 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_BITER_SHIFT

#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)

Definition at line 15005 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_COUNT

#define DMA_BITER_ELINKYES_COUNT (32U)

Definition at line 15024 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_ELINK

#define DMA_BITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

Definition at line 15020 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_ELINK_MASK

#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)

Definition at line 15014 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_ELINK_SHIFT

#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)

Definition at line 15015 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_LINKCH

#define DMA_BITER_ELINKYES_LINKCH ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

LINKCH - Link Channel Number

Definition at line 15013 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_LINKCH_MASK

#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)

Definition at line 15009 of file MIMXRT1052.h.

◆ DMA_BITER_ELINKYES_LINKCH_SHIFT

#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)

Definition at line 15010 of file MIMXRT1052.h.

◆ DMA_CDNE_CADN

#define DMA_CDNE_CADN ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE Bits 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0b1..Clears all bits in TCDn_CSR[DONE]

Definition at line 12793 of file MIMXRT1052.h.

◆ DMA_CDNE_CADN_MASK

#define DMA_CDNE_CADN_MASK (0x40U)

Definition at line 12787 of file MIMXRT1052.h.

◆ DMA_CDNE_CADN_SHIFT

#define DMA_CDNE_CADN_SHIFT (6U)

Definition at line 12788 of file MIMXRT1052.h.

◆ DMA_CDNE_CDNE

#define DMA_CDNE_CDNE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

CDNE - Clear DONE Bit

Definition at line 12786 of file MIMXRT1052.h.

◆ DMA_CDNE_CDNE_MASK

#define DMA_CDNE_CDNE_MASK (0x1FU)

Definition at line 12782 of file MIMXRT1052.h.

◆ DMA_CDNE_CDNE_SHIFT

#define DMA_CDNE_CDNE_SHIFT (0U)

Definition at line 12783 of file MIMXRT1052.h.

◆ DMA_CDNE_NOP

#define DMA_CDNE_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 12800 of file MIMXRT1052.h.

◆ DMA_CDNE_NOP_MASK

#define DMA_CDNE_NOP_MASK (0x80U)

Definition at line 12794 of file MIMXRT1052.h.

◆ DMA_CDNE_NOP_SHIFT

#define DMA_CDNE_NOP_SHIFT (7U)

Definition at line 12795 of file MIMXRT1052.h.

◆ DMA_CEEI_CAEE

#define DMA_CEEI_CAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Clear only the EEI bit specified in the CEEI field 0b1..Clear all bits in EEI

Definition at line 12701 of file MIMXRT1052.h.

◆ DMA_CEEI_CAEE_MASK

#define DMA_CEEI_CAEE_MASK (0x40U)

Definition at line 12695 of file MIMXRT1052.h.

◆ DMA_CEEI_CAEE_SHIFT

#define DMA_CEEI_CAEE_SHIFT (6U)

Definition at line 12696 of file MIMXRT1052.h.

◆ DMA_CEEI_CEEI

#define DMA_CEEI_CEEI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

CEEI - Clear Enable Error Interrupt

Definition at line 12694 of file MIMXRT1052.h.

◆ DMA_CEEI_CEEI_MASK

#define DMA_CEEI_CEEI_MASK (0x1FU)

Definition at line 12690 of file MIMXRT1052.h.

◆ DMA_CEEI_CEEI_SHIFT

#define DMA_CEEI_CEEI_SHIFT (0U)

Definition at line 12691 of file MIMXRT1052.h.

◆ DMA_CEEI_NOP

#define DMA_CEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 12708 of file MIMXRT1052.h.

◆ DMA_CEEI_NOP_MASK

#define DMA_CEEI_NOP_MASK (0x80U)

Definition at line 12702 of file MIMXRT1052.h.

◆ DMA_CEEI_NOP_SHIFT

#define DMA_CEEI_NOP_SHIFT (7U)

Definition at line 12703 of file MIMXRT1052.h.

◆ DMA_CERQ_CAER

#define DMA_CERQ_CAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Clear only the ERQ bit specified in the CERQ field 0b1..Clear all bits in ERQ

Definition at line 12747 of file MIMXRT1052.h.

◆ DMA_CERQ_CAER_MASK

#define DMA_CERQ_CAER_MASK (0x40U)

Definition at line 12741 of file MIMXRT1052.h.

◆ DMA_CERQ_CAER_SHIFT

#define DMA_CERQ_CAER_SHIFT (6U)

Definition at line 12742 of file MIMXRT1052.h.

◆ DMA_CERQ_CERQ

#define DMA_CERQ_CERQ ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

CERQ - Clear Enable Request

Definition at line 12740 of file MIMXRT1052.h.

◆ DMA_CERQ_CERQ_MASK

#define DMA_CERQ_CERQ_MASK (0x1FU)

Definition at line 12736 of file MIMXRT1052.h.

◆ DMA_CERQ_CERQ_SHIFT

#define DMA_CERQ_CERQ_SHIFT (0U)

Definition at line 12737 of file MIMXRT1052.h.

◆ DMA_CERQ_NOP

#define DMA_CERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 12754 of file MIMXRT1052.h.

◆ DMA_CERQ_NOP_MASK

#define DMA_CERQ_NOP_MASK (0x80U)

Definition at line 12748 of file MIMXRT1052.h.

◆ DMA_CERQ_NOP_SHIFT

#define DMA_CERQ_NOP_SHIFT (7U)

Definition at line 12749 of file MIMXRT1052.h.

◆ DMA_CERR_CAEI

#define DMA_CERR_CAEI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Clear only the ERR bit specified in the CERR field 0b1..Clear all bits in ERR

Definition at line 12839 of file MIMXRT1052.h.

◆ DMA_CERR_CAEI_MASK

#define DMA_CERR_CAEI_MASK (0x40U)

Definition at line 12833 of file MIMXRT1052.h.

◆ DMA_CERR_CAEI_SHIFT

#define DMA_CERR_CAEI_SHIFT (6U)

Definition at line 12834 of file MIMXRT1052.h.

◆ DMA_CERR_CERR

#define DMA_CERR_CERR ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

CERR - Clear Error Indicator

Definition at line 12832 of file MIMXRT1052.h.

◆ DMA_CERR_CERR_MASK

#define DMA_CERR_CERR_MASK (0x1FU)

Definition at line 12828 of file MIMXRT1052.h.

◆ DMA_CERR_CERR_SHIFT

#define DMA_CERR_CERR_SHIFT (0U)

Definition at line 12829 of file MIMXRT1052.h.

◆ DMA_CERR_NOP

#define DMA_CERR_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 12846 of file MIMXRT1052.h.

◆ DMA_CERR_NOP_MASK

#define DMA_CERR_NOP_MASK (0x80U)

Definition at line 12840 of file MIMXRT1052.h.

◆ DMA_CERR_NOP_SHIFT

#define DMA_CERR_NOP_SHIFT (7U)

Definition at line 12841 of file MIMXRT1052.h.

◆ DMA_CINT_CAIR

#define DMA_CINT_CAIR ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT bit specified in the CINT field 0b1..Clear all bits in INT

Definition at line 12862 of file MIMXRT1052.h.

◆ DMA_CINT_CAIR_MASK

#define DMA_CINT_CAIR_MASK (0x40U)

Definition at line 12856 of file MIMXRT1052.h.

◆ DMA_CINT_CAIR_SHIFT

#define DMA_CINT_CAIR_SHIFT (6U)

Definition at line 12857 of file MIMXRT1052.h.

◆ DMA_CINT_CINT

#define DMA_CINT_CINT ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

CINT - Clear Interrupt Request

Definition at line 12855 of file MIMXRT1052.h.

◆ DMA_CINT_CINT_MASK

#define DMA_CINT_CINT_MASK (0x1FU)

Definition at line 12851 of file MIMXRT1052.h.

◆ DMA_CINT_CINT_SHIFT

#define DMA_CINT_CINT_SHIFT (0U)

Definition at line 12852 of file MIMXRT1052.h.

◆ DMA_CINT_NOP

#define DMA_CINT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 12869 of file MIMXRT1052.h.

◆ DMA_CINT_NOP_MASK

#define DMA_CINT_NOP_MASK (0x80U)

Definition at line 12863 of file MIMXRT1052.h.

◆ DMA_CINT_NOP_SHIFT

#define DMA_CINT_NOP_SHIFT (7U)

Definition at line 12864 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKNO_CITER

#define DMA_CITER_ELINKNO_CITER ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

CITER - Current Major Iteration Count

Definition at line 14860 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKNO_CITER_MASK

#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)

Definition at line 14856 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKNO_CITER_SHIFT

#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)

Definition at line 14857 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKNO_COUNT

#define DMA_CITER_ELINKNO_COUNT (32U)

Definition at line 14871 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKNO_ELINK

#define DMA_CITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

Definition at line 14867 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKNO_ELINK_MASK

#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)

Definition at line 14861 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKNO_ELINK_SHIFT

#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)

Definition at line 14862 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_CITER

#define DMA_CITER_ELINKYES_CITER ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

CITER - Current Major Iteration Count

Definition at line 14879 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_CITER_MASK

#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)

Definition at line 14875 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_CITER_SHIFT

#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)

Definition at line 14876 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_COUNT

#define DMA_CITER_ELINKYES_COUNT (32U)

Definition at line 14895 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_ELINK

#define DMA_CITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

Definition at line 14891 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_ELINK_MASK

#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)

Definition at line 14885 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_ELINK_SHIFT

#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)

Definition at line 14886 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_LINKCH

#define DMA_CITER_ELINKYES_LINKCH ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

LINKCH - Minor Loop Link Channel Number

Definition at line 14884 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_LINKCH_MASK

#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)

Definition at line 14880 of file MIMXRT1052.h.

◆ DMA_CITER_ELINKYES_LINKCH_SHIFT

#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)

Definition at line 14881 of file MIMXRT1052.h.

◆ DMA_CR_ACTIVE

#define DMA_CR_ACTIVE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)

ACTIVE - DMA Active Status 0b0..eDMA is idle. 0b1..eDMA is executing a channel.

Definition at line 12131 of file MIMXRT1052.h.

◆ DMA_CR_ACTIVE_MASK

#define DMA_CR_ACTIVE_MASK (0x80000000U)

Definition at line 12125 of file MIMXRT1052.h.

◆ DMA_CR_ACTIVE_SHIFT

#define DMA_CR_ACTIVE_SHIFT (31U)

Definition at line 12126 of file MIMXRT1052.h.

◆ DMA_CR_CLM

#define DMA_CR_CLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.

Definition at line 12085 of file MIMXRT1052.h.

◆ DMA_CR_CLM_MASK

#define DMA_CR_CLM_MASK (0x40U)

Definition at line 12076 of file MIMXRT1052.h.

◆ DMA_CR_CLM_SHIFT

#define DMA_CR_CLM_SHIFT (6U)

Definition at line 12077 of file MIMXRT1052.h.

◆ DMA_CR_CX

#define DMA_CR_CX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.

Definition at line 12124 of file MIMXRT1052.h.

◆ DMA_CR_CX_MASK

#define DMA_CR_CX_MASK (0x20000U)

Definition at line 12116 of file MIMXRT1052.h.

◆ DMA_CR_CX_SHIFT

#define DMA_CR_CX_SHIFT (17U)

Definition at line 12117 of file MIMXRT1052.h.

◆ DMA_CR_ECX

#define DMA_CR_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.

Definition at line 12115 of file MIMXRT1052.h.

◆ DMA_CR_ECX_MASK

#define DMA_CR_ECX_MASK (0x10000U)

Definition at line 12105 of file MIMXRT1052.h.

◆ DMA_CR_ECX_SHIFT

#define DMA_CR_ECX_SHIFT (16U)

Definition at line 12106 of file MIMXRT1052.h.

◆ DMA_CR_EDBG

#define DMA_CR_EDBG ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When in debug mode, the DMA continues to operate. 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.

Definition at line 12047 of file MIMXRT1052.h.

◆ DMA_CR_EDBG_MASK

#define DMA_CR_EDBG_MASK (0x2U)

Definition at line 12040 of file MIMXRT1052.h.

◆ DMA_CR_EDBG_SHIFT

#define DMA_CR_EDBG_SHIFT (1U)

Definition at line 12041 of file MIMXRT1052.h.

◆ DMA_CR_EMLM

#define DMA_CR_EMLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.

Definition at line 12094 of file MIMXRT1052.h.

◆ DMA_CR_EMLM_MASK

#define DMA_CR_EMLM_MASK (0x80U)

Definition at line 12086 of file MIMXRT1052.h.

◆ DMA_CR_EMLM_SHIFT

#define DMA_CR_EMLM_SHIFT (7U)

Definition at line 12087 of file MIMXRT1052.h.

◆ DMA_CR_ERCA

#define DMA_CR_ERCA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection within each group. 0b1..Round robin arbitration is used for channel selection within each group.

Definition at line 12054 of file MIMXRT1052.h.

◆ DMA_CR_ERCA_MASK

#define DMA_CR_ERCA_MASK (0x4U)

Definition at line 12048 of file MIMXRT1052.h.

◆ DMA_CR_ERCA_SHIFT

#define DMA_CR_ERCA_SHIFT (2U)

Definition at line 12049 of file MIMXRT1052.h.

◆ DMA_CR_ERGA

#define DMA_CR_ERGA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

ERGA - Enable Round Robin Group Arbitration 0b0..Fixed priority arbitration is used for selection among the groups. 0b1..Round robin arbitration is used for selection among the groups.

Definition at line 12061 of file MIMXRT1052.h.

◆ DMA_CR_ERGA_MASK

#define DMA_CR_ERGA_MASK (0x8U)

Definition at line 12055 of file MIMXRT1052.h.

◆ DMA_CR_ERGA_SHIFT

#define DMA_CR_ERGA_SHIFT (3U)

Definition at line 12056 of file MIMXRT1052.h.

◆ DMA_CR_GRP0PRI

#define DMA_CR_GRP0PRI ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

GRP0PRI - Channel Group 0 Priority

Definition at line 12099 of file MIMXRT1052.h.

◆ DMA_CR_GRP0PRI_MASK

#define DMA_CR_GRP0PRI_MASK (0x100U)

Definition at line 12095 of file MIMXRT1052.h.

◆ DMA_CR_GRP0PRI_SHIFT

#define DMA_CR_GRP0PRI_SHIFT (8U)

Definition at line 12096 of file MIMXRT1052.h.

◆ DMA_CR_GRP1PRI

#define DMA_CR_GRP1PRI ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

GRP1PRI - Channel Group 1 Priority

Definition at line 12104 of file MIMXRT1052.h.

◆ DMA_CR_GRP1PRI_MASK

#define DMA_CR_GRP1PRI_MASK (0x400U)

Definition at line 12100 of file MIMXRT1052.h.

◆ DMA_CR_GRP1PRI_SHIFT

#define DMA_CR_GRP1PRI_SHIFT (10U)

Definition at line 12101 of file MIMXRT1052.h.

◆ DMA_CR_HALT

#define DMA_CR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt DMA Operations 0b0..Normal operation 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.

Definition at line 12075 of file MIMXRT1052.h.

◆ DMA_CR_HALT_MASK

#define DMA_CR_HALT_MASK (0x20U)

Definition at line 12069 of file MIMXRT1052.h.

◆ DMA_CR_HALT_SHIFT

#define DMA_CR_HALT_SHIFT (5U)

Definition at line 12070 of file MIMXRT1052.h.

◆ DMA_CR_HOE

#define DMA_CR_HOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

Definition at line 12068 of file MIMXRT1052.h.

◆ DMA_CR_HOE_MASK

#define DMA_CR_HOE_MASK (0x10U)

Definition at line 12062 of file MIMXRT1052.h.

◆ DMA_CR_HOE_SHIFT

#define DMA_CR_HOE_SHIFT (4U)

Definition at line 12063 of file MIMXRT1052.h.

◆ DMA_CSR_ACTIVE

#define DMA_CSR_ACTIVE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

ACTIVE - Channel Active

Definition at line 14958 of file MIMXRT1052.h.

◆ DMA_CSR_ACTIVE_MASK

#define DMA_CSR_ACTIVE_MASK (0x40U)

Definition at line 14954 of file MIMXRT1052.h.

◆ DMA_CSR_ACTIVE_SHIFT

#define DMA_CSR_ACTIVE_SHIFT (6U)

Definition at line 14955 of file MIMXRT1052.h.

◆ DMA_CSR_BWC

#define DMA_CSR_BWC ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls. 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

Definition at line 14977 of file MIMXRT1052.h.

◆ DMA_CSR_BWC_MASK

#define DMA_CSR_BWC_MASK (0xC000U)

Definition at line 14969 of file MIMXRT1052.h.

◆ DMA_CSR_BWC_SHIFT

#define DMA_CSR_BWC_SHIFT (14U)

Definition at line 14970 of file MIMXRT1052.h.

◆ DMA_CSR_COUNT

#define DMA_CSR_COUNT (32U)

Definition at line 14981 of file MIMXRT1052.h.

◆ DMA_CSR_DONE

#define DMA_CSR_DONE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

DONE - Channel Done

Definition at line 14963 of file MIMXRT1052.h.

◆ DMA_CSR_DONE_MASK

#define DMA_CSR_DONE_MASK (0x80U)

Definition at line 14959 of file MIMXRT1052.h.

◆ DMA_CSR_DONE_SHIFT

#define DMA_CSR_DONE_SHIFT (7U)

Definition at line 14960 of file MIMXRT1052.h.

◆ DMA_CSR_DREQ

#define DMA_CSR_DREQ ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected. 0b1..The channel's ERQ bit is cleared when the major loop is complete.

Definition at line 14938 of file MIMXRT1052.h.

◆ DMA_CSR_DREQ_MASK

#define DMA_CSR_DREQ_MASK (0x8U)

Definition at line 14932 of file MIMXRT1052.h.

◆ DMA_CSR_DREQ_SHIFT

#define DMA_CSR_DREQ_SHIFT (3U)

Definition at line 14933 of file MIMXRT1052.h.

◆ DMA_CSR_ESG

#define DMA_CSR_ESG ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format. 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.

Definition at line 14946 of file MIMXRT1052.h.

◆ DMA_CSR_ESG_MASK

#define DMA_CSR_ESG_MASK (0x10U)

Definition at line 14939 of file MIMXRT1052.h.

◆ DMA_CSR_ESG_SHIFT

#define DMA_CSR_ESG_SHIFT (4U)

Definition at line 14940 of file MIMXRT1052.h.

◆ DMA_CSR_INTHALF

#define DMA_CSR_INTHALF ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled. 0b1..The half-point interrupt is enabled.

Definition at line 14931 of file MIMXRT1052.h.

◆ DMA_CSR_INTHALF_MASK

#define DMA_CSR_INTHALF_MASK (0x4U)

Definition at line 14925 of file MIMXRT1052.h.

◆ DMA_CSR_INTHALF_SHIFT

#define DMA_CSR_INTHALF_SHIFT (2U)

Definition at line 14926 of file MIMXRT1052.h.

◆ DMA_CSR_INTMAJOR

#define DMA_CSR_INTMAJOR ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..The end-of-major loop interrupt is disabled. 0b1..The end-of-major loop interrupt is enabled.

Definition at line 14924 of file MIMXRT1052.h.

◆ DMA_CSR_INTMAJOR_MASK

#define DMA_CSR_INTMAJOR_MASK (0x2U)

Definition at line 14918 of file MIMXRT1052.h.

◆ DMA_CSR_INTMAJOR_SHIFT

#define DMA_CSR_INTMAJOR_SHIFT (1U)

Definition at line 14919 of file MIMXRT1052.h.

◆ DMA_CSR_MAJORELINK

#define DMA_CSR_MAJORELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled. 0b1..The channel-to-channel linking is enabled.

Definition at line 14953 of file MIMXRT1052.h.

◆ DMA_CSR_MAJORELINK_MASK

#define DMA_CSR_MAJORELINK_MASK (0x20U)

Definition at line 14947 of file MIMXRT1052.h.

◆ DMA_CSR_MAJORELINK_SHIFT

#define DMA_CSR_MAJORELINK_SHIFT (5U)

Definition at line 14948 of file MIMXRT1052.h.

◆ DMA_CSR_MAJORLINKCH

#define DMA_CSR_MAJORLINKCH ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

MAJORLINKCH - Major Loop Link Channel Number

Definition at line 14968 of file MIMXRT1052.h.

◆ DMA_CSR_MAJORLINKCH_MASK

#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)

Definition at line 14964 of file MIMXRT1052.h.

◆ DMA_CSR_MAJORLINKCH_SHIFT

#define DMA_CSR_MAJORLINKCH_SHIFT (8U)

Definition at line 14965 of file MIMXRT1052.h.

◆ DMA_CSR_START

#define DMA_CSR_START ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..The channel is not explicitly started. 0b1..The channel is explicitly started via a software initiated service request.

Definition at line 14917 of file MIMXRT1052.h.

◆ DMA_CSR_START_MASK

#define DMA_CSR_START_MASK (0x1U)

Definition at line 14911 of file MIMXRT1052.h.

◆ DMA_CSR_START_SHIFT

#define DMA_CSR_START_SHIFT (0U)

Definition at line 14912 of file MIMXRT1052.h.

◆ DMA_DADDR_COUNT

#define DMA_DADDR_COUNT (32U)

Definition at line 14840 of file MIMXRT1052.h.

◆ DMA_DADDR_DADDR

#define DMA_DADDR_DADDR ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

DADDR - Destination Address

Definition at line 14836 of file MIMXRT1052.h.

◆ DMA_DADDR_DADDR_MASK

#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)

Definition at line 14832 of file MIMXRT1052.h.

◆ DMA_DADDR_DADDR_SHIFT

#define DMA_DADDR_DADDR_SHIFT (0U)

Definition at line 14833 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_CHPRI

#define DMA_DCHPRI0_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 13874 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_CHPRI_MASK

#define DMA_DCHPRI0_CHPRI_MASK (0xFU)

Definition at line 13870 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_CHPRI_SHIFT

#define DMA_DCHPRI0_CHPRI_SHIFT (0U)

Definition at line 13871 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_DPA

#define DMA_DCHPRI0_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 13886 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_DPA_MASK

#define DMA_DCHPRI0_DPA_MASK (0x40U)

Definition at line 13880 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_DPA_SHIFT

#define DMA_DCHPRI0_DPA_SHIFT (6U)

Definition at line 13881 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_ECP

#define DMA_DCHPRI0_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 13893 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_ECP_MASK

#define DMA_DCHPRI0_ECP_MASK (0x80U)

Definition at line 13887 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_ECP_SHIFT

#define DMA_DCHPRI0_ECP_SHIFT (7U)

Definition at line 13888 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_GRPPRI

#define DMA_DCHPRI0_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 13879 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_GRPPRI_MASK

#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)

Definition at line 13875 of file MIMXRT1052.h.

◆ DMA_DCHPRI0_GRPPRI_SHIFT

#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)

Definition at line 13876 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_CHPRI

#define DMA_DCHPRI10_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14042 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_CHPRI_MASK

#define DMA_DCHPRI10_CHPRI_MASK (0xFU)

Definition at line 14038 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_CHPRI_SHIFT

#define DMA_DCHPRI10_CHPRI_SHIFT (0U)

Definition at line 14039 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_DPA

#define DMA_DCHPRI10_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14054 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_DPA_MASK

#define DMA_DCHPRI10_DPA_MASK (0x40U)

Definition at line 14048 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_DPA_SHIFT

#define DMA_DCHPRI10_DPA_SHIFT (6U)

Definition at line 14049 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_ECP

#define DMA_DCHPRI10_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14061 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_ECP_MASK

#define DMA_DCHPRI10_ECP_MASK (0x80U)

Definition at line 14055 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_ECP_SHIFT

#define DMA_DCHPRI10_ECP_SHIFT (7U)

Definition at line 14056 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_GRPPRI

#define DMA_DCHPRI10_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14047 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_GRPPRI_MASK

#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)

Definition at line 14043 of file MIMXRT1052.h.

◆ DMA_DCHPRI10_GRPPRI_SHIFT

#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)

Definition at line 14044 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_CHPRI

#define DMA_DCHPRI11_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14014 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_CHPRI_MASK

#define DMA_DCHPRI11_CHPRI_MASK (0xFU)

Definition at line 14010 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_CHPRI_SHIFT

#define DMA_DCHPRI11_CHPRI_SHIFT (0U)

Definition at line 14011 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_DPA

#define DMA_DCHPRI11_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14026 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_DPA_MASK

#define DMA_DCHPRI11_DPA_MASK (0x40U)

Definition at line 14020 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_DPA_SHIFT

#define DMA_DCHPRI11_DPA_SHIFT (6U)

Definition at line 14021 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_ECP

#define DMA_DCHPRI11_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14033 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_ECP_MASK

#define DMA_DCHPRI11_ECP_MASK (0x80U)

Definition at line 14027 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_ECP_SHIFT

#define DMA_DCHPRI11_ECP_SHIFT (7U)

Definition at line 14028 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_GRPPRI

#define DMA_DCHPRI11_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14019 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_GRPPRI_MASK

#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)

Definition at line 14015 of file MIMXRT1052.h.

◆ DMA_DCHPRI11_GRPPRI_SHIFT

#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)

Definition at line 14016 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_CHPRI

#define DMA_DCHPRI12_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14210 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_CHPRI_MASK

#define DMA_DCHPRI12_CHPRI_MASK (0xFU)

Definition at line 14206 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_CHPRI_SHIFT

#define DMA_DCHPRI12_CHPRI_SHIFT (0U)

Definition at line 14207 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_DPA

#define DMA_DCHPRI12_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14222 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_DPA_MASK

#define DMA_DCHPRI12_DPA_MASK (0x40U)

Definition at line 14216 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_DPA_SHIFT

#define DMA_DCHPRI12_DPA_SHIFT (6U)

Definition at line 14217 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_ECP

#define DMA_DCHPRI12_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14229 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_ECP_MASK

#define DMA_DCHPRI12_ECP_MASK (0x80U)

Definition at line 14223 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_ECP_SHIFT

#define DMA_DCHPRI12_ECP_SHIFT (7U)

Definition at line 14224 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_GRPPRI

#define DMA_DCHPRI12_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14215 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_GRPPRI_MASK

#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)

Definition at line 14211 of file MIMXRT1052.h.

◆ DMA_DCHPRI12_GRPPRI_SHIFT

#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)

Definition at line 14212 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_CHPRI

#define DMA_DCHPRI13_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14182 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_CHPRI_MASK

#define DMA_DCHPRI13_CHPRI_MASK (0xFU)

Definition at line 14178 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_CHPRI_SHIFT

#define DMA_DCHPRI13_CHPRI_SHIFT (0U)

Definition at line 14179 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_DPA

#define DMA_DCHPRI13_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14194 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_DPA_MASK

#define DMA_DCHPRI13_DPA_MASK (0x40U)

Definition at line 14188 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_DPA_SHIFT

#define DMA_DCHPRI13_DPA_SHIFT (6U)

Definition at line 14189 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_ECP

#define DMA_DCHPRI13_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14201 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_ECP_MASK

#define DMA_DCHPRI13_ECP_MASK (0x80U)

Definition at line 14195 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_ECP_SHIFT

#define DMA_DCHPRI13_ECP_SHIFT (7U)

Definition at line 14196 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_GRPPRI

#define DMA_DCHPRI13_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14187 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_GRPPRI_MASK

#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)

Definition at line 14183 of file MIMXRT1052.h.

◆ DMA_DCHPRI13_GRPPRI_SHIFT

#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)

Definition at line 14184 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_CHPRI

#define DMA_DCHPRI14_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14154 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_CHPRI_MASK

#define DMA_DCHPRI14_CHPRI_MASK (0xFU)

Definition at line 14150 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_CHPRI_SHIFT

#define DMA_DCHPRI14_CHPRI_SHIFT (0U)

Definition at line 14151 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_DPA

#define DMA_DCHPRI14_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14166 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_DPA_MASK

#define DMA_DCHPRI14_DPA_MASK (0x40U)

Definition at line 14160 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_DPA_SHIFT

#define DMA_DCHPRI14_DPA_SHIFT (6U)

Definition at line 14161 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_ECP

#define DMA_DCHPRI14_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14173 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_ECP_MASK

#define DMA_DCHPRI14_ECP_MASK (0x80U)

Definition at line 14167 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_ECP_SHIFT

#define DMA_DCHPRI14_ECP_SHIFT (7U)

Definition at line 14168 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_GRPPRI

#define DMA_DCHPRI14_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14159 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_GRPPRI_MASK

#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)

Definition at line 14155 of file MIMXRT1052.h.

◆ DMA_DCHPRI14_GRPPRI_SHIFT

#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)

Definition at line 14156 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_CHPRI

#define DMA_DCHPRI15_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14126 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_CHPRI_MASK

#define DMA_DCHPRI15_CHPRI_MASK (0xFU)

Definition at line 14122 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_CHPRI_SHIFT

#define DMA_DCHPRI15_CHPRI_SHIFT (0U)

Definition at line 14123 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_DPA

#define DMA_DCHPRI15_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14138 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_DPA_MASK

#define DMA_DCHPRI15_DPA_MASK (0x40U)

Definition at line 14132 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_DPA_SHIFT

#define DMA_DCHPRI15_DPA_SHIFT (6U)

Definition at line 14133 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_ECP

#define DMA_DCHPRI15_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14145 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_ECP_MASK

#define DMA_DCHPRI15_ECP_MASK (0x80U)

Definition at line 14139 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_ECP_SHIFT

#define DMA_DCHPRI15_ECP_SHIFT (7U)

Definition at line 14140 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_GRPPRI

#define DMA_DCHPRI15_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14131 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_GRPPRI_MASK

#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)

Definition at line 14127 of file MIMXRT1052.h.

◆ DMA_DCHPRI15_GRPPRI_SHIFT

#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)

Definition at line 14128 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_CHPRI

#define DMA_DCHPRI16_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14322 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_CHPRI_MASK

#define DMA_DCHPRI16_CHPRI_MASK (0xFU)

Definition at line 14318 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_CHPRI_SHIFT

#define DMA_DCHPRI16_CHPRI_SHIFT (0U)

Definition at line 14319 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_DPA

#define DMA_DCHPRI16_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14334 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_DPA_MASK

#define DMA_DCHPRI16_DPA_MASK (0x40U)

Definition at line 14328 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_DPA_SHIFT

#define DMA_DCHPRI16_DPA_SHIFT (6U)

Definition at line 14329 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_ECP

#define DMA_DCHPRI16_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14341 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_ECP_MASK

#define DMA_DCHPRI16_ECP_MASK (0x80U)

Definition at line 14335 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_ECP_SHIFT

#define DMA_DCHPRI16_ECP_SHIFT (7U)

Definition at line 14336 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_GRPPRI

#define DMA_DCHPRI16_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14327 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_GRPPRI_MASK

#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)

Definition at line 14323 of file MIMXRT1052.h.

◆ DMA_DCHPRI16_GRPPRI_SHIFT

#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)

Definition at line 14324 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_CHPRI

#define DMA_DCHPRI17_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14294 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_CHPRI_MASK

#define DMA_DCHPRI17_CHPRI_MASK (0xFU)

Definition at line 14290 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_CHPRI_SHIFT

#define DMA_DCHPRI17_CHPRI_SHIFT (0U)

Definition at line 14291 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_DPA

#define DMA_DCHPRI17_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14306 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_DPA_MASK

#define DMA_DCHPRI17_DPA_MASK (0x40U)

Definition at line 14300 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_DPA_SHIFT

#define DMA_DCHPRI17_DPA_SHIFT (6U)

Definition at line 14301 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_ECP

#define DMA_DCHPRI17_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14313 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_ECP_MASK

#define DMA_DCHPRI17_ECP_MASK (0x80U)

Definition at line 14307 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_ECP_SHIFT

#define DMA_DCHPRI17_ECP_SHIFT (7U)

Definition at line 14308 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_GRPPRI

#define DMA_DCHPRI17_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14299 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_GRPPRI_MASK

#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)

Definition at line 14295 of file MIMXRT1052.h.

◆ DMA_DCHPRI17_GRPPRI_SHIFT

#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)

Definition at line 14296 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_CHPRI

#define DMA_DCHPRI18_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14266 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_CHPRI_MASK

#define DMA_DCHPRI18_CHPRI_MASK (0xFU)

Definition at line 14262 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_CHPRI_SHIFT

#define DMA_DCHPRI18_CHPRI_SHIFT (0U)

Definition at line 14263 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_DPA

#define DMA_DCHPRI18_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14278 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_DPA_MASK

#define DMA_DCHPRI18_DPA_MASK (0x40U)

Definition at line 14272 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_DPA_SHIFT

#define DMA_DCHPRI18_DPA_SHIFT (6U)

Definition at line 14273 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_ECP

#define DMA_DCHPRI18_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14285 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_ECP_MASK

#define DMA_DCHPRI18_ECP_MASK (0x80U)

Definition at line 14279 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_ECP_SHIFT

#define DMA_DCHPRI18_ECP_SHIFT (7U)

Definition at line 14280 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_GRPPRI

#define DMA_DCHPRI18_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14271 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_GRPPRI_MASK

#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)

Definition at line 14267 of file MIMXRT1052.h.

◆ DMA_DCHPRI18_GRPPRI_SHIFT

#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)

Definition at line 14268 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_CHPRI

#define DMA_DCHPRI19_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14238 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_CHPRI_MASK

#define DMA_DCHPRI19_CHPRI_MASK (0xFU)

Definition at line 14234 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_CHPRI_SHIFT

#define DMA_DCHPRI19_CHPRI_SHIFT (0U)

Definition at line 14235 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_DPA

#define DMA_DCHPRI19_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14250 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_DPA_MASK

#define DMA_DCHPRI19_DPA_MASK (0x40U)

Definition at line 14244 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_DPA_SHIFT

#define DMA_DCHPRI19_DPA_SHIFT (6U)

Definition at line 14245 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_ECP

#define DMA_DCHPRI19_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14257 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_ECP_MASK

#define DMA_DCHPRI19_ECP_MASK (0x80U)

Definition at line 14251 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_ECP_SHIFT

#define DMA_DCHPRI19_ECP_SHIFT (7U)

Definition at line 14252 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_GRPPRI

#define DMA_DCHPRI19_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14243 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_GRPPRI_MASK

#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)

Definition at line 14239 of file MIMXRT1052.h.

◆ DMA_DCHPRI19_GRPPRI_SHIFT

#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)

Definition at line 14240 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_CHPRI

#define DMA_DCHPRI1_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 13846 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_CHPRI_MASK

#define DMA_DCHPRI1_CHPRI_MASK (0xFU)

Definition at line 13842 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_CHPRI_SHIFT

#define DMA_DCHPRI1_CHPRI_SHIFT (0U)

Definition at line 13843 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_DPA

#define DMA_DCHPRI1_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 13858 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_DPA_MASK

#define DMA_DCHPRI1_DPA_MASK (0x40U)

Definition at line 13852 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_DPA_SHIFT

#define DMA_DCHPRI1_DPA_SHIFT (6U)

Definition at line 13853 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_ECP

#define DMA_DCHPRI1_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 13865 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_ECP_MASK

#define DMA_DCHPRI1_ECP_MASK (0x80U)

Definition at line 13859 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_ECP_SHIFT

#define DMA_DCHPRI1_ECP_SHIFT (7U)

Definition at line 13860 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_GRPPRI

#define DMA_DCHPRI1_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 13851 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_GRPPRI_MASK

#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)

Definition at line 13847 of file MIMXRT1052.h.

◆ DMA_DCHPRI1_GRPPRI_SHIFT

#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)

Definition at line 13848 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_CHPRI

#define DMA_DCHPRI20_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14434 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_CHPRI_MASK

#define DMA_DCHPRI20_CHPRI_MASK (0xFU)

Definition at line 14430 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_CHPRI_SHIFT

#define DMA_DCHPRI20_CHPRI_SHIFT (0U)

Definition at line 14431 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_DPA

#define DMA_DCHPRI20_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14446 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_DPA_MASK

#define DMA_DCHPRI20_DPA_MASK (0x40U)

Definition at line 14440 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_DPA_SHIFT

#define DMA_DCHPRI20_DPA_SHIFT (6U)

Definition at line 14441 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_ECP

#define DMA_DCHPRI20_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14453 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_ECP_MASK

#define DMA_DCHPRI20_ECP_MASK (0x80U)

Definition at line 14447 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_ECP_SHIFT

#define DMA_DCHPRI20_ECP_SHIFT (7U)

Definition at line 14448 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_GRPPRI

#define DMA_DCHPRI20_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14439 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_GRPPRI_MASK

#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)

Definition at line 14435 of file MIMXRT1052.h.

◆ DMA_DCHPRI20_GRPPRI_SHIFT

#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)

Definition at line 14436 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_CHPRI

#define DMA_DCHPRI21_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14406 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_CHPRI_MASK

#define DMA_DCHPRI21_CHPRI_MASK (0xFU)

Definition at line 14402 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_CHPRI_SHIFT

#define DMA_DCHPRI21_CHPRI_SHIFT (0U)

Definition at line 14403 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_DPA

#define DMA_DCHPRI21_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14418 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_DPA_MASK

#define DMA_DCHPRI21_DPA_MASK (0x40U)

Definition at line 14412 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_DPA_SHIFT

#define DMA_DCHPRI21_DPA_SHIFT (6U)

Definition at line 14413 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_ECP

#define DMA_DCHPRI21_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14425 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_ECP_MASK

#define DMA_DCHPRI21_ECP_MASK (0x80U)

Definition at line 14419 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_ECP_SHIFT

#define DMA_DCHPRI21_ECP_SHIFT (7U)

Definition at line 14420 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_GRPPRI

#define DMA_DCHPRI21_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14411 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_GRPPRI_MASK

#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)

Definition at line 14407 of file MIMXRT1052.h.

◆ DMA_DCHPRI21_GRPPRI_SHIFT

#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)

Definition at line 14408 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_CHPRI

#define DMA_DCHPRI22_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14378 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_CHPRI_MASK

#define DMA_DCHPRI22_CHPRI_MASK (0xFU)

Definition at line 14374 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_CHPRI_SHIFT

#define DMA_DCHPRI22_CHPRI_SHIFT (0U)

Definition at line 14375 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_DPA

#define DMA_DCHPRI22_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14390 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_DPA_MASK

#define DMA_DCHPRI22_DPA_MASK (0x40U)

Definition at line 14384 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_DPA_SHIFT

#define DMA_DCHPRI22_DPA_SHIFT (6U)

Definition at line 14385 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_ECP

#define DMA_DCHPRI22_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14397 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_ECP_MASK

#define DMA_DCHPRI22_ECP_MASK (0x80U)

Definition at line 14391 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_ECP_SHIFT

#define DMA_DCHPRI22_ECP_SHIFT (7U)

Definition at line 14392 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_GRPPRI

#define DMA_DCHPRI22_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14383 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_GRPPRI_MASK

#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)

Definition at line 14379 of file MIMXRT1052.h.

◆ DMA_DCHPRI22_GRPPRI_SHIFT

#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)

Definition at line 14380 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_CHPRI

#define DMA_DCHPRI23_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14350 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_CHPRI_MASK

#define DMA_DCHPRI23_CHPRI_MASK (0xFU)

Definition at line 14346 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_CHPRI_SHIFT

#define DMA_DCHPRI23_CHPRI_SHIFT (0U)

Definition at line 14347 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_DPA

#define DMA_DCHPRI23_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14362 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_DPA_MASK

#define DMA_DCHPRI23_DPA_MASK (0x40U)

Definition at line 14356 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_DPA_SHIFT

#define DMA_DCHPRI23_DPA_SHIFT (6U)

Definition at line 14357 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_ECP

#define DMA_DCHPRI23_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14369 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_ECP_MASK

#define DMA_DCHPRI23_ECP_MASK (0x80U)

Definition at line 14363 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_ECP_SHIFT

#define DMA_DCHPRI23_ECP_SHIFT (7U)

Definition at line 14364 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_GRPPRI

#define DMA_DCHPRI23_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14355 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_GRPPRI_MASK

#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)

Definition at line 14351 of file MIMXRT1052.h.

◆ DMA_DCHPRI23_GRPPRI_SHIFT

#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)

Definition at line 14352 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_CHPRI

#define DMA_DCHPRI24_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14546 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_CHPRI_MASK

#define DMA_DCHPRI24_CHPRI_MASK (0xFU)

Definition at line 14542 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_CHPRI_SHIFT

#define DMA_DCHPRI24_CHPRI_SHIFT (0U)

Definition at line 14543 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_DPA

#define DMA_DCHPRI24_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14558 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_DPA_MASK

#define DMA_DCHPRI24_DPA_MASK (0x40U)

Definition at line 14552 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_DPA_SHIFT

#define DMA_DCHPRI24_DPA_SHIFT (6U)

Definition at line 14553 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_ECP

#define DMA_DCHPRI24_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14565 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_ECP_MASK

#define DMA_DCHPRI24_ECP_MASK (0x80U)

Definition at line 14559 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_ECP_SHIFT

#define DMA_DCHPRI24_ECP_SHIFT (7U)

Definition at line 14560 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_GRPPRI

#define DMA_DCHPRI24_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14551 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_GRPPRI_MASK

#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)

Definition at line 14547 of file MIMXRT1052.h.

◆ DMA_DCHPRI24_GRPPRI_SHIFT

#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)

Definition at line 14548 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_CHPRI

#define DMA_DCHPRI25_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14518 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_CHPRI_MASK

#define DMA_DCHPRI25_CHPRI_MASK (0xFU)

Definition at line 14514 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_CHPRI_SHIFT

#define DMA_DCHPRI25_CHPRI_SHIFT (0U)

Definition at line 14515 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_DPA

#define DMA_DCHPRI25_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14530 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_DPA_MASK

#define DMA_DCHPRI25_DPA_MASK (0x40U)

Definition at line 14524 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_DPA_SHIFT

#define DMA_DCHPRI25_DPA_SHIFT (6U)

Definition at line 14525 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_ECP

#define DMA_DCHPRI25_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14537 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_ECP_MASK

#define DMA_DCHPRI25_ECP_MASK (0x80U)

Definition at line 14531 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_ECP_SHIFT

#define DMA_DCHPRI25_ECP_SHIFT (7U)

Definition at line 14532 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_GRPPRI

#define DMA_DCHPRI25_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14523 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_GRPPRI_MASK

#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)

Definition at line 14519 of file MIMXRT1052.h.

◆ DMA_DCHPRI25_GRPPRI_SHIFT

#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)

Definition at line 14520 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_CHPRI

#define DMA_DCHPRI26_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14490 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_CHPRI_MASK

#define DMA_DCHPRI26_CHPRI_MASK (0xFU)

Definition at line 14486 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_CHPRI_SHIFT

#define DMA_DCHPRI26_CHPRI_SHIFT (0U)

Definition at line 14487 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_DPA

#define DMA_DCHPRI26_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14502 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_DPA_MASK

#define DMA_DCHPRI26_DPA_MASK (0x40U)

Definition at line 14496 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_DPA_SHIFT

#define DMA_DCHPRI26_DPA_SHIFT (6U)

Definition at line 14497 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_ECP

#define DMA_DCHPRI26_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14509 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_ECP_MASK

#define DMA_DCHPRI26_ECP_MASK (0x80U)

Definition at line 14503 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_ECP_SHIFT

#define DMA_DCHPRI26_ECP_SHIFT (7U)

Definition at line 14504 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_GRPPRI

#define DMA_DCHPRI26_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14495 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_GRPPRI_MASK

#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)

Definition at line 14491 of file MIMXRT1052.h.

◆ DMA_DCHPRI26_GRPPRI_SHIFT

#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)

Definition at line 14492 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_CHPRI

#define DMA_DCHPRI27_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14462 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_CHPRI_MASK

#define DMA_DCHPRI27_CHPRI_MASK (0xFU)

Definition at line 14458 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_CHPRI_SHIFT

#define DMA_DCHPRI27_CHPRI_SHIFT (0U)

Definition at line 14459 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_DPA

#define DMA_DCHPRI27_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14474 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_DPA_MASK

#define DMA_DCHPRI27_DPA_MASK (0x40U)

Definition at line 14468 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_DPA_SHIFT

#define DMA_DCHPRI27_DPA_SHIFT (6U)

Definition at line 14469 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_ECP

#define DMA_DCHPRI27_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14481 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_ECP_MASK

#define DMA_DCHPRI27_ECP_MASK (0x80U)

Definition at line 14475 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_ECP_SHIFT

#define DMA_DCHPRI27_ECP_SHIFT (7U)

Definition at line 14476 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_GRPPRI

#define DMA_DCHPRI27_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14467 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_GRPPRI_MASK

#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)

Definition at line 14463 of file MIMXRT1052.h.

◆ DMA_DCHPRI27_GRPPRI_SHIFT

#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)

Definition at line 14464 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_CHPRI

#define DMA_DCHPRI28_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14658 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_CHPRI_MASK

#define DMA_DCHPRI28_CHPRI_MASK (0xFU)

Definition at line 14654 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_CHPRI_SHIFT

#define DMA_DCHPRI28_CHPRI_SHIFT (0U)

Definition at line 14655 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_DPA

#define DMA_DCHPRI28_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14670 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_DPA_MASK

#define DMA_DCHPRI28_DPA_MASK (0x40U)

Definition at line 14664 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_DPA_SHIFT

#define DMA_DCHPRI28_DPA_SHIFT (6U)

Definition at line 14665 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_ECP

#define DMA_DCHPRI28_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14677 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_ECP_MASK

#define DMA_DCHPRI28_ECP_MASK (0x80U)

Definition at line 14671 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_ECP_SHIFT

#define DMA_DCHPRI28_ECP_SHIFT (7U)

Definition at line 14672 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_GRPPRI

#define DMA_DCHPRI28_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14663 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_GRPPRI_MASK

#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)

Definition at line 14659 of file MIMXRT1052.h.

◆ DMA_DCHPRI28_GRPPRI_SHIFT

#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)

Definition at line 14660 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_CHPRI

#define DMA_DCHPRI29_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14630 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_CHPRI_MASK

#define DMA_DCHPRI29_CHPRI_MASK (0xFU)

Definition at line 14626 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_CHPRI_SHIFT

#define DMA_DCHPRI29_CHPRI_SHIFT (0U)

Definition at line 14627 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_DPA

#define DMA_DCHPRI29_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14642 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_DPA_MASK

#define DMA_DCHPRI29_DPA_MASK (0x40U)

Definition at line 14636 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_DPA_SHIFT

#define DMA_DCHPRI29_DPA_SHIFT (6U)

Definition at line 14637 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_ECP

#define DMA_DCHPRI29_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14649 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_ECP_MASK

#define DMA_DCHPRI29_ECP_MASK (0x80U)

Definition at line 14643 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_ECP_SHIFT

#define DMA_DCHPRI29_ECP_SHIFT (7U)

Definition at line 14644 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_GRPPRI

#define DMA_DCHPRI29_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14635 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_GRPPRI_MASK

#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)

Definition at line 14631 of file MIMXRT1052.h.

◆ DMA_DCHPRI29_GRPPRI_SHIFT

#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)

Definition at line 14632 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_CHPRI

#define DMA_DCHPRI2_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 13818 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_CHPRI_MASK

#define DMA_DCHPRI2_CHPRI_MASK (0xFU)

Definition at line 13814 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_CHPRI_SHIFT

#define DMA_DCHPRI2_CHPRI_SHIFT (0U)

Definition at line 13815 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_DPA

#define DMA_DCHPRI2_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 13830 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_DPA_MASK

#define DMA_DCHPRI2_DPA_MASK (0x40U)

Definition at line 13824 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_DPA_SHIFT

#define DMA_DCHPRI2_DPA_SHIFT (6U)

Definition at line 13825 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_ECP

#define DMA_DCHPRI2_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 13837 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_ECP_MASK

#define DMA_DCHPRI2_ECP_MASK (0x80U)

Definition at line 13831 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_ECP_SHIFT

#define DMA_DCHPRI2_ECP_SHIFT (7U)

Definition at line 13832 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_GRPPRI

#define DMA_DCHPRI2_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 13823 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_GRPPRI_MASK

#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)

Definition at line 13819 of file MIMXRT1052.h.

◆ DMA_DCHPRI2_GRPPRI_SHIFT

#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)

Definition at line 13820 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_CHPRI

#define DMA_DCHPRI30_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14602 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_CHPRI_MASK

#define DMA_DCHPRI30_CHPRI_MASK (0xFU)

Definition at line 14598 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_CHPRI_SHIFT

#define DMA_DCHPRI30_CHPRI_SHIFT (0U)

Definition at line 14599 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_DPA

#define DMA_DCHPRI30_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14614 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_DPA_MASK

#define DMA_DCHPRI30_DPA_MASK (0x40U)

Definition at line 14608 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_DPA_SHIFT

#define DMA_DCHPRI30_DPA_SHIFT (6U)

Definition at line 14609 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_ECP

#define DMA_DCHPRI30_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14621 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_ECP_MASK

#define DMA_DCHPRI30_ECP_MASK (0x80U)

Definition at line 14615 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_ECP_SHIFT

#define DMA_DCHPRI30_ECP_SHIFT (7U)

Definition at line 14616 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_GRPPRI

#define DMA_DCHPRI30_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14607 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_GRPPRI_MASK

#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)

Definition at line 14603 of file MIMXRT1052.h.

◆ DMA_DCHPRI30_GRPPRI_SHIFT

#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)

Definition at line 14604 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_CHPRI

#define DMA_DCHPRI31_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14574 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_CHPRI_MASK

#define DMA_DCHPRI31_CHPRI_MASK (0xFU)

Definition at line 14570 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_CHPRI_SHIFT

#define DMA_DCHPRI31_CHPRI_SHIFT (0U)

Definition at line 14571 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_DPA

#define DMA_DCHPRI31_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14586 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_DPA_MASK

#define DMA_DCHPRI31_DPA_MASK (0x40U)

Definition at line 14580 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_DPA_SHIFT

#define DMA_DCHPRI31_DPA_SHIFT (6U)

Definition at line 14581 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_ECP

#define DMA_DCHPRI31_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14593 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_ECP_MASK

#define DMA_DCHPRI31_ECP_MASK (0x80U)

Definition at line 14587 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_ECP_SHIFT

#define DMA_DCHPRI31_ECP_SHIFT (7U)

Definition at line 14588 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_GRPPRI

#define DMA_DCHPRI31_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14579 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_GRPPRI_MASK

#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)

Definition at line 14575 of file MIMXRT1052.h.

◆ DMA_DCHPRI31_GRPPRI_SHIFT

#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)

Definition at line 14576 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_CHPRI

#define DMA_DCHPRI3_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 13790 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_CHPRI_MASK

#define DMA_DCHPRI3_CHPRI_MASK (0xFU)

Definition at line 13786 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_CHPRI_SHIFT

#define DMA_DCHPRI3_CHPRI_SHIFT (0U)

Definition at line 13787 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_DPA

#define DMA_DCHPRI3_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 13802 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_DPA_MASK

#define DMA_DCHPRI3_DPA_MASK (0x40U)

Definition at line 13796 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_DPA_SHIFT

#define DMA_DCHPRI3_DPA_SHIFT (6U)

Definition at line 13797 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_ECP

#define DMA_DCHPRI3_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 13809 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_ECP_MASK

#define DMA_DCHPRI3_ECP_MASK (0x80U)

Definition at line 13803 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_ECP_SHIFT

#define DMA_DCHPRI3_ECP_SHIFT (7U)

Definition at line 13804 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_GRPPRI

#define DMA_DCHPRI3_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 13795 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_GRPPRI_MASK

#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)

Definition at line 13791 of file MIMXRT1052.h.

◆ DMA_DCHPRI3_GRPPRI_SHIFT

#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)

Definition at line 13792 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_CHPRI

#define DMA_DCHPRI4_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 13986 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_CHPRI_MASK

#define DMA_DCHPRI4_CHPRI_MASK (0xFU)

Definition at line 13982 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_CHPRI_SHIFT

#define DMA_DCHPRI4_CHPRI_SHIFT (0U)

Definition at line 13983 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_DPA

#define DMA_DCHPRI4_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 13998 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_DPA_MASK

#define DMA_DCHPRI4_DPA_MASK (0x40U)

Definition at line 13992 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_DPA_SHIFT

#define DMA_DCHPRI4_DPA_SHIFT (6U)

Definition at line 13993 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_ECP

#define DMA_DCHPRI4_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14005 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_ECP_MASK

#define DMA_DCHPRI4_ECP_MASK (0x80U)

Definition at line 13999 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_ECP_SHIFT

#define DMA_DCHPRI4_ECP_SHIFT (7U)

Definition at line 14000 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_GRPPRI

#define DMA_DCHPRI4_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 13991 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_GRPPRI_MASK

#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)

Definition at line 13987 of file MIMXRT1052.h.

◆ DMA_DCHPRI4_GRPPRI_SHIFT

#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)

Definition at line 13988 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_CHPRI

#define DMA_DCHPRI5_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 13958 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_CHPRI_MASK

#define DMA_DCHPRI5_CHPRI_MASK (0xFU)

Definition at line 13954 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_CHPRI_SHIFT

#define DMA_DCHPRI5_CHPRI_SHIFT (0U)

Definition at line 13955 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_DPA

#define DMA_DCHPRI5_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 13970 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_DPA_MASK

#define DMA_DCHPRI5_DPA_MASK (0x40U)

Definition at line 13964 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_DPA_SHIFT

#define DMA_DCHPRI5_DPA_SHIFT (6U)

Definition at line 13965 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_ECP

#define DMA_DCHPRI5_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 13977 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_ECP_MASK

#define DMA_DCHPRI5_ECP_MASK (0x80U)

Definition at line 13971 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_ECP_SHIFT

#define DMA_DCHPRI5_ECP_SHIFT (7U)

Definition at line 13972 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_GRPPRI

#define DMA_DCHPRI5_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 13963 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_GRPPRI_MASK

#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)

Definition at line 13959 of file MIMXRT1052.h.

◆ DMA_DCHPRI5_GRPPRI_SHIFT

#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)

Definition at line 13960 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_CHPRI

#define DMA_DCHPRI6_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 13930 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_CHPRI_MASK

#define DMA_DCHPRI6_CHPRI_MASK (0xFU)

Definition at line 13926 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_CHPRI_SHIFT

#define DMA_DCHPRI6_CHPRI_SHIFT (0U)

Definition at line 13927 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_DPA

#define DMA_DCHPRI6_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 13942 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_DPA_MASK

#define DMA_DCHPRI6_DPA_MASK (0x40U)

Definition at line 13936 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_DPA_SHIFT

#define DMA_DCHPRI6_DPA_SHIFT (6U)

Definition at line 13937 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_ECP

#define DMA_DCHPRI6_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 13949 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_ECP_MASK

#define DMA_DCHPRI6_ECP_MASK (0x80U)

Definition at line 13943 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_ECP_SHIFT

#define DMA_DCHPRI6_ECP_SHIFT (7U)

Definition at line 13944 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_GRPPRI

#define DMA_DCHPRI6_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 13935 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_GRPPRI_MASK

#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)

Definition at line 13931 of file MIMXRT1052.h.

◆ DMA_DCHPRI6_GRPPRI_SHIFT

#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)

Definition at line 13932 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_CHPRI

#define DMA_DCHPRI7_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 13902 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_CHPRI_MASK

#define DMA_DCHPRI7_CHPRI_MASK (0xFU)

Definition at line 13898 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_CHPRI_SHIFT

#define DMA_DCHPRI7_CHPRI_SHIFT (0U)

Definition at line 13899 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_DPA

#define DMA_DCHPRI7_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 13914 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_DPA_MASK

#define DMA_DCHPRI7_DPA_MASK (0x40U)

Definition at line 13908 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_DPA_SHIFT

#define DMA_DCHPRI7_DPA_SHIFT (6U)

Definition at line 13909 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_ECP

#define DMA_DCHPRI7_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 13921 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_ECP_MASK

#define DMA_DCHPRI7_ECP_MASK (0x80U)

Definition at line 13915 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_ECP_SHIFT

#define DMA_DCHPRI7_ECP_SHIFT (7U)

Definition at line 13916 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_GRPPRI

#define DMA_DCHPRI7_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 13907 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_GRPPRI_MASK

#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)

Definition at line 13903 of file MIMXRT1052.h.

◆ DMA_DCHPRI7_GRPPRI_SHIFT

#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)

Definition at line 13904 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_CHPRI

#define DMA_DCHPRI8_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14098 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_CHPRI_MASK

#define DMA_DCHPRI8_CHPRI_MASK (0xFU)

Definition at line 14094 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_CHPRI_SHIFT

#define DMA_DCHPRI8_CHPRI_SHIFT (0U)

Definition at line 14095 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_DPA

#define DMA_DCHPRI8_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14110 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_DPA_MASK

#define DMA_DCHPRI8_DPA_MASK (0x40U)

Definition at line 14104 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_DPA_SHIFT

#define DMA_DCHPRI8_DPA_SHIFT (6U)

Definition at line 14105 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_ECP

#define DMA_DCHPRI8_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14117 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_ECP_MASK

#define DMA_DCHPRI8_ECP_MASK (0x80U)

Definition at line 14111 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_ECP_SHIFT

#define DMA_DCHPRI8_ECP_SHIFT (7U)

Definition at line 14112 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_GRPPRI

#define DMA_DCHPRI8_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14103 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_GRPPRI_MASK

#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)

Definition at line 14099 of file MIMXRT1052.h.

◆ DMA_DCHPRI8_GRPPRI_SHIFT

#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)

Definition at line 14100 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_CHPRI

#define DMA_DCHPRI9_CHPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14070 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_CHPRI_MASK

#define DMA_DCHPRI9_CHPRI_MASK (0xFU)

Definition at line 14066 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_CHPRI_SHIFT

#define DMA_DCHPRI9_CHPRI_SHIFT (0U)

Definition at line 14067 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_DPA

#define DMA_DCHPRI9_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14082 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_DPA_MASK

#define DMA_DCHPRI9_DPA_MASK (0x40U)

Definition at line 14076 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_DPA_SHIFT

#define DMA_DCHPRI9_DPA_SHIFT (6U)

Definition at line 14077 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_ECP

#define DMA_DCHPRI9_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14089 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_ECP_MASK

#define DMA_DCHPRI9_ECP_MASK (0x80U)

Definition at line 14083 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_ECP_SHIFT

#define DMA_DCHPRI9_ECP_SHIFT (7U)

Definition at line 14084 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_GRPPRI

#define DMA_DCHPRI9_GRPPRI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14075 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_GRPPRI_MASK

#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)

Definition at line 14071 of file MIMXRT1052.h.

◆ DMA_DCHPRI9_GRPPRI_SHIFT

#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)

Definition at line 14072 of file MIMXRT1052.h.

◆ DMA_DLAST_SGA_COUNT

#define DMA_DLAST_SGA_COUNT (32U)

Definition at line 14907 of file MIMXRT1052.h.

◆ DMA_DLAST_SGA_DLASTSGA

#define DMA_DLAST_SGA_DLASTSGA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

DLASTSGA - DLASTSGA

Definition at line 14903 of file MIMXRT1052.h.

◆ DMA_DLAST_SGA_DLASTSGA_MASK

#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)

Definition at line 14899 of file MIMXRT1052.h.

◆ DMA_DLAST_SGA_DLASTSGA_SHIFT

#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)

Definition at line 14900 of file MIMXRT1052.h.

◆ DMA_DOFF_COUNT

#define DMA_DOFF_COUNT (32U)

Definition at line 14852 of file MIMXRT1052.h.

◆ DMA_DOFF_DOFF

#define DMA_DOFF_DOFF ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

DOFF - Destination Address Signed Offset

Definition at line 14848 of file MIMXRT1052.h.

◆ DMA_DOFF_DOFF_MASK

#define DMA_DOFF_DOFF_MASK (0xFFFFU)

Definition at line 14844 of file MIMXRT1052.h.

◆ DMA_DOFF_DOFF_SHIFT

#define DMA_DOFF_DOFF_SHIFT (0U)

Definition at line 14845 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_0

#define DMA_EARS_EDREQ_0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 0b0..Disable asynchronous DMA request for channel 0. 0b1..Enable asynchronous DMA request for channel 0.

Definition at line 13564 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_0_MASK

#define DMA_EARS_EDREQ_0_MASK (0x1U)

Definition at line 13558 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_0_SHIFT

#define DMA_EARS_EDREQ_0_SHIFT (0U)

Definition at line 13559 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_1

#define DMA_EARS_EDREQ_1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 0b0..Disable asynchronous DMA request for channel 1 0b1..Enable asynchronous DMA request for channel 1.

Definition at line 13571 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_10

#define DMA_EARS_EDREQ_10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 0b0..Disable asynchronous DMA request for channel 10. 0b1..Enable asynchronous DMA request for channel 10.

Definition at line 13634 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_10_MASK

#define DMA_EARS_EDREQ_10_MASK (0x400U)

Definition at line 13628 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_10_SHIFT

#define DMA_EARS_EDREQ_10_SHIFT (10U)

Definition at line 13629 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_11

#define DMA_EARS_EDREQ_11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 0b0..Disable asynchronous DMA request for channel 11. 0b1..Enable asynchronous DMA request for channel 11.

Definition at line 13641 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_11_MASK

#define DMA_EARS_EDREQ_11_MASK (0x800U)

Definition at line 13635 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_11_SHIFT

#define DMA_EARS_EDREQ_11_SHIFT (11U)

Definition at line 13636 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_12

#define DMA_EARS_EDREQ_12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 0b0..Disable asynchronous DMA request for channel 12. 0b1..Enable asynchronous DMA request for channel 12.

Definition at line 13648 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_12_MASK

#define DMA_EARS_EDREQ_12_MASK (0x1000U)

Definition at line 13642 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_12_SHIFT

#define DMA_EARS_EDREQ_12_SHIFT (12U)

Definition at line 13643 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_13

#define DMA_EARS_EDREQ_13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 0b0..Disable asynchronous DMA request for channel 13. 0b1..Enable asynchronous DMA request for channel 13.

Definition at line 13655 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_13_MASK

#define DMA_EARS_EDREQ_13_MASK (0x2000U)

Definition at line 13649 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_13_SHIFT

#define DMA_EARS_EDREQ_13_SHIFT (13U)

Definition at line 13650 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_14

#define DMA_EARS_EDREQ_14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 0b0..Disable asynchronous DMA request for channel 14. 0b1..Enable asynchronous DMA request for channel 14.

Definition at line 13662 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_14_MASK

#define DMA_EARS_EDREQ_14_MASK (0x4000U)

Definition at line 13656 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_14_SHIFT

#define DMA_EARS_EDREQ_14_SHIFT (14U)

Definition at line 13657 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_15

#define DMA_EARS_EDREQ_15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 0b0..Disable asynchronous DMA request for channel 15. 0b1..Enable asynchronous DMA request for channel 15.

Definition at line 13669 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_15_MASK

#define DMA_EARS_EDREQ_15_MASK (0x8000U)

Definition at line 13663 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_15_SHIFT

#define DMA_EARS_EDREQ_15_SHIFT (15U)

Definition at line 13664 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_16

#define DMA_EARS_EDREQ_16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 0b0..Disable asynchronous DMA request for channel 16 0b1..Enable asynchronous DMA request for channel 16

Definition at line 13676 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_16_MASK

#define DMA_EARS_EDREQ_16_MASK (0x10000U)

Definition at line 13670 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_16_SHIFT

#define DMA_EARS_EDREQ_16_SHIFT (16U)

Definition at line 13671 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_17

#define DMA_EARS_EDREQ_17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 0b0..Disable asynchronous DMA request for channel 17 0b1..Enable asynchronous DMA request for channel 17

Definition at line 13683 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_17_MASK

#define DMA_EARS_EDREQ_17_MASK (0x20000U)

Definition at line 13677 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_17_SHIFT

#define DMA_EARS_EDREQ_17_SHIFT (17U)

Definition at line 13678 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_18

#define DMA_EARS_EDREQ_18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 0b0..Disable asynchronous DMA request for channel 18 0b1..Enable asynchronous DMA request for channel 18

Definition at line 13690 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_18_MASK

#define DMA_EARS_EDREQ_18_MASK (0x40000U)

Definition at line 13684 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_18_SHIFT

#define DMA_EARS_EDREQ_18_SHIFT (18U)

Definition at line 13685 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_19

#define DMA_EARS_EDREQ_19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 0b0..Disable asynchronous DMA request for channel 19 0b1..Enable asynchronous DMA request for channel 19

Definition at line 13697 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_19_MASK

#define DMA_EARS_EDREQ_19_MASK (0x80000U)

Definition at line 13691 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_19_SHIFT

#define DMA_EARS_EDREQ_19_SHIFT (19U)

Definition at line 13692 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_1_MASK

#define DMA_EARS_EDREQ_1_MASK (0x2U)

Definition at line 13565 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_1_SHIFT

#define DMA_EARS_EDREQ_1_SHIFT (1U)

Definition at line 13566 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_2

#define DMA_EARS_EDREQ_2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 0b0..Disable asynchronous DMA request for channel 2. 0b1..Enable asynchronous DMA request for channel 2.

Definition at line 13578 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_20

#define DMA_EARS_EDREQ_20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 0b0..Disable asynchronous DMA request for channel 20 0b1..Enable asynchronous DMA request for channel 20

Definition at line 13704 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_20_MASK

#define DMA_EARS_EDREQ_20_MASK (0x100000U)

Definition at line 13698 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_20_SHIFT

#define DMA_EARS_EDREQ_20_SHIFT (20U)

Definition at line 13699 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_21

#define DMA_EARS_EDREQ_21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 0b0..Disable asynchronous DMA request for channel 21 0b1..Enable asynchronous DMA request for channel 21

Definition at line 13711 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_21_MASK

#define DMA_EARS_EDREQ_21_MASK (0x200000U)

Definition at line 13705 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_21_SHIFT

#define DMA_EARS_EDREQ_21_SHIFT (21U)

Definition at line 13706 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_22

#define DMA_EARS_EDREQ_22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 0b0..Disable asynchronous DMA request for channel 22 0b1..Enable asynchronous DMA request for channel 22

Definition at line 13718 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_22_MASK

#define DMA_EARS_EDREQ_22_MASK (0x400000U)

Definition at line 13712 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_22_SHIFT

#define DMA_EARS_EDREQ_22_SHIFT (22U)

Definition at line 13713 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_23

#define DMA_EARS_EDREQ_23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 0b0..Disable asynchronous DMA request for channel 23 0b1..Enable asynchronous DMA request for channel 23

Definition at line 13725 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_23_MASK

#define DMA_EARS_EDREQ_23_MASK (0x800000U)

Definition at line 13719 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_23_SHIFT

#define DMA_EARS_EDREQ_23_SHIFT (23U)

Definition at line 13720 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_24

#define DMA_EARS_EDREQ_24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 0b0..Disable asynchronous DMA request for channel 24 0b1..Enable asynchronous DMA request for channel 24

Definition at line 13732 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_24_MASK

#define DMA_EARS_EDREQ_24_MASK (0x1000000U)

Definition at line 13726 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_24_SHIFT

#define DMA_EARS_EDREQ_24_SHIFT (24U)

Definition at line 13727 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_25

#define DMA_EARS_EDREQ_25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 0b0..Disable asynchronous DMA request for channel 25 0b1..Enable asynchronous DMA request for channel 25

Definition at line 13739 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_25_MASK

#define DMA_EARS_EDREQ_25_MASK (0x2000000U)

Definition at line 13733 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_25_SHIFT

#define DMA_EARS_EDREQ_25_SHIFT (25U)

Definition at line 13734 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_26

#define DMA_EARS_EDREQ_26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 0b0..Disable asynchronous DMA request for channel 26 0b1..Enable asynchronous DMA request for channel 26

Definition at line 13746 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_26_MASK

#define DMA_EARS_EDREQ_26_MASK (0x4000000U)

Definition at line 13740 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_26_SHIFT

#define DMA_EARS_EDREQ_26_SHIFT (26U)

Definition at line 13741 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_27

#define DMA_EARS_EDREQ_27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 0b0..Disable asynchronous DMA request for channel 27 0b1..Enable asynchronous DMA request for channel 27

Definition at line 13753 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_27_MASK

#define DMA_EARS_EDREQ_27_MASK (0x8000000U)

Definition at line 13747 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_27_SHIFT

#define DMA_EARS_EDREQ_27_SHIFT (27U)

Definition at line 13748 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_28

#define DMA_EARS_EDREQ_28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 0b0..Disable asynchronous DMA request for channel 28 0b1..Enable asynchronous DMA request for channel 28

Definition at line 13760 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_28_MASK

#define DMA_EARS_EDREQ_28_MASK (0x10000000U)

Definition at line 13754 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_28_SHIFT

#define DMA_EARS_EDREQ_28_SHIFT (28U)

Definition at line 13755 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_29

#define DMA_EARS_EDREQ_29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 0b0..Disable asynchronous DMA request for channel 29 0b1..Enable asynchronous DMA request for channel 29

Definition at line 13767 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_29_MASK

#define DMA_EARS_EDREQ_29_MASK (0x20000000U)

Definition at line 13761 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_29_SHIFT

#define DMA_EARS_EDREQ_29_SHIFT (29U)

Definition at line 13762 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_2_MASK

#define DMA_EARS_EDREQ_2_MASK (0x4U)

Definition at line 13572 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_2_SHIFT

#define DMA_EARS_EDREQ_2_SHIFT (2U)

Definition at line 13573 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_3

#define DMA_EARS_EDREQ_3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 0b0..Disable asynchronous DMA request for channel 3. 0b1..Enable asynchronous DMA request for channel 3.

Definition at line 13585 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_30

#define DMA_EARS_EDREQ_30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 0b0..Disable asynchronous DMA request for channel 30 0b1..Enable asynchronous DMA request for channel 30

Definition at line 13774 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_30_MASK

#define DMA_EARS_EDREQ_30_MASK (0x40000000U)

Definition at line 13768 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_30_SHIFT

#define DMA_EARS_EDREQ_30_SHIFT (30U)

Definition at line 13769 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_31

#define DMA_EARS_EDREQ_31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 0b0..Disable asynchronous DMA request for channel 31 0b1..Enable asynchronous DMA request for channel 31

Definition at line 13781 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_31_MASK

#define DMA_EARS_EDREQ_31_MASK (0x80000000U)

Definition at line 13775 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_31_SHIFT

#define DMA_EARS_EDREQ_31_SHIFT (31U)

Definition at line 13776 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_3_MASK

#define DMA_EARS_EDREQ_3_MASK (0x8U)

Definition at line 13579 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_3_SHIFT

#define DMA_EARS_EDREQ_3_SHIFT (3U)

Definition at line 13580 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_4

#define DMA_EARS_EDREQ_4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 0b0..Disable asynchronous DMA request for channel 4. 0b1..Enable asynchronous DMA request for channel 4.

Definition at line 13592 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_4_MASK

#define DMA_EARS_EDREQ_4_MASK (0x10U)

Definition at line 13586 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_4_SHIFT

#define DMA_EARS_EDREQ_4_SHIFT (4U)

Definition at line 13587 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_5

#define DMA_EARS_EDREQ_5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 0b0..Disable asynchronous DMA request for channel 5. 0b1..Enable asynchronous DMA request for channel 5.

Definition at line 13599 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_5_MASK

#define DMA_EARS_EDREQ_5_MASK (0x20U)

Definition at line 13593 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_5_SHIFT

#define DMA_EARS_EDREQ_5_SHIFT (5U)

Definition at line 13594 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_6

#define DMA_EARS_EDREQ_6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 0b0..Disable asynchronous DMA request for channel 6. 0b1..Enable asynchronous DMA request for channel 6.

Definition at line 13606 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_6_MASK

#define DMA_EARS_EDREQ_6_MASK (0x40U)

Definition at line 13600 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_6_SHIFT

#define DMA_EARS_EDREQ_6_SHIFT (6U)

Definition at line 13601 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_7

#define DMA_EARS_EDREQ_7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 0b0..Disable asynchronous DMA request for channel 7. 0b1..Enable asynchronous DMA request for channel 7.

Definition at line 13613 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_7_MASK

#define DMA_EARS_EDREQ_7_MASK (0x80U)

Definition at line 13607 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_7_SHIFT

#define DMA_EARS_EDREQ_7_SHIFT (7U)

Definition at line 13608 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_8

#define DMA_EARS_EDREQ_8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 0b0..Disable asynchronous DMA request for channel 8. 0b1..Enable asynchronous DMA request for channel 8.

Definition at line 13620 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_8_MASK

#define DMA_EARS_EDREQ_8_MASK (0x100U)

Definition at line 13614 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_8_SHIFT

#define DMA_EARS_EDREQ_8_SHIFT (8U)

Definition at line 13615 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_9

#define DMA_EARS_EDREQ_9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 0b0..Disable asynchronous DMA request for channel 9. 0b1..Enable asynchronous DMA request for channel 9.

Definition at line 13627 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_9_MASK

#define DMA_EARS_EDREQ_9_MASK (0x200U)

Definition at line 13621 of file MIMXRT1052.h.

◆ DMA_EARS_EDREQ_9_SHIFT

#define DMA_EARS_EDREQ_9_SHIFT (9U)

Definition at line 13622 of file MIMXRT1052.h.

◆ DMA_EEI_EEI0

#define DMA_EEI_EEI0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12468 of file MIMXRT1052.h.

◆ DMA_EEI_EEI0_MASK

#define DMA_EEI_EEI0_MASK (0x1U)

Definition at line 12462 of file MIMXRT1052.h.

◆ DMA_EEI_EEI0_SHIFT

#define DMA_EEI_EEI0_SHIFT (0U)

Definition at line 12463 of file MIMXRT1052.h.

◆ DMA_EEI_EEI1

#define DMA_EEI_EEI1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12475 of file MIMXRT1052.h.

◆ DMA_EEI_EEI10

#define DMA_EEI_EEI10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12538 of file MIMXRT1052.h.

◆ DMA_EEI_EEI10_MASK

#define DMA_EEI_EEI10_MASK (0x400U)

Definition at line 12532 of file MIMXRT1052.h.

◆ DMA_EEI_EEI10_SHIFT

#define DMA_EEI_EEI10_SHIFT (10U)

Definition at line 12533 of file MIMXRT1052.h.

◆ DMA_EEI_EEI11

#define DMA_EEI_EEI11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12545 of file MIMXRT1052.h.

◆ DMA_EEI_EEI11_MASK

#define DMA_EEI_EEI11_MASK (0x800U)

Definition at line 12539 of file MIMXRT1052.h.

◆ DMA_EEI_EEI11_SHIFT

#define DMA_EEI_EEI11_SHIFT (11U)

Definition at line 12540 of file MIMXRT1052.h.

◆ DMA_EEI_EEI12

#define DMA_EEI_EEI12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12552 of file MIMXRT1052.h.

◆ DMA_EEI_EEI12_MASK

#define DMA_EEI_EEI12_MASK (0x1000U)

Definition at line 12546 of file MIMXRT1052.h.

◆ DMA_EEI_EEI12_SHIFT

#define DMA_EEI_EEI12_SHIFT (12U)

Definition at line 12547 of file MIMXRT1052.h.

◆ DMA_EEI_EEI13

#define DMA_EEI_EEI13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12559 of file MIMXRT1052.h.

◆ DMA_EEI_EEI13_MASK

#define DMA_EEI_EEI13_MASK (0x2000U)

Definition at line 12553 of file MIMXRT1052.h.

◆ DMA_EEI_EEI13_SHIFT

#define DMA_EEI_EEI13_SHIFT (13U)

Definition at line 12554 of file MIMXRT1052.h.

◆ DMA_EEI_EEI14

#define DMA_EEI_EEI14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12566 of file MIMXRT1052.h.

◆ DMA_EEI_EEI14_MASK

#define DMA_EEI_EEI14_MASK (0x4000U)

Definition at line 12560 of file MIMXRT1052.h.

◆ DMA_EEI_EEI14_SHIFT

#define DMA_EEI_EEI14_SHIFT (14U)

Definition at line 12561 of file MIMXRT1052.h.

◆ DMA_EEI_EEI15

#define DMA_EEI_EEI15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12573 of file MIMXRT1052.h.

◆ DMA_EEI_EEI15_MASK

#define DMA_EEI_EEI15_MASK (0x8000U)

Definition at line 12567 of file MIMXRT1052.h.

◆ DMA_EEI_EEI15_SHIFT

#define DMA_EEI_EEI15_SHIFT (15U)

Definition at line 12568 of file MIMXRT1052.h.

◆ DMA_EEI_EEI16

#define DMA_EEI_EEI16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

EEI16 - Enable Error Interrupt 16 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12580 of file MIMXRT1052.h.

◆ DMA_EEI_EEI16_MASK

#define DMA_EEI_EEI16_MASK (0x10000U)

Definition at line 12574 of file MIMXRT1052.h.

◆ DMA_EEI_EEI16_SHIFT

#define DMA_EEI_EEI16_SHIFT (16U)

Definition at line 12575 of file MIMXRT1052.h.

◆ DMA_EEI_EEI17

#define DMA_EEI_EEI17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

EEI17 - Enable Error Interrupt 17 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12587 of file MIMXRT1052.h.

◆ DMA_EEI_EEI17_MASK

#define DMA_EEI_EEI17_MASK (0x20000U)

Definition at line 12581 of file MIMXRT1052.h.

◆ DMA_EEI_EEI17_SHIFT

#define DMA_EEI_EEI17_SHIFT (17U)

Definition at line 12582 of file MIMXRT1052.h.

◆ DMA_EEI_EEI18

#define DMA_EEI_EEI18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

EEI18 - Enable Error Interrupt 18 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12594 of file MIMXRT1052.h.

◆ DMA_EEI_EEI18_MASK

#define DMA_EEI_EEI18_MASK (0x40000U)

Definition at line 12588 of file MIMXRT1052.h.

◆ DMA_EEI_EEI18_SHIFT

#define DMA_EEI_EEI18_SHIFT (18U)

Definition at line 12589 of file MIMXRT1052.h.

◆ DMA_EEI_EEI19

#define DMA_EEI_EEI19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

EEI19 - Enable Error Interrupt 19 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12601 of file MIMXRT1052.h.

◆ DMA_EEI_EEI19_MASK

#define DMA_EEI_EEI19_MASK (0x80000U)

Definition at line 12595 of file MIMXRT1052.h.

◆ DMA_EEI_EEI19_SHIFT

#define DMA_EEI_EEI19_SHIFT (19U)

Definition at line 12596 of file MIMXRT1052.h.

◆ DMA_EEI_EEI1_MASK

#define DMA_EEI_EEI1_MASK (0x2U)

Definition at line 12469 of file MIMXRT1052.h.

◆ DMA_EEI_EEI1_SHIFT

#define DMA_EEI_EEI1_SHIFT (1U)

Definition at line 12470 of file MIMXRT1052.h.

◆ DMA_EEI_EEI2

#define DMA_EEI_EEI2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12482 of file MIMXRT1052.h.

◆ DMA_EEI_EEI20

#define DMA_EEI_EEI20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

EEI20 - Enable Error Interrupt 20 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12608 of file MIMXRT1052.h.

◆ DMA_EEI_EEI20_MASK

#define DMA_EEI_EEI20_MASK (0x100000U)

Definition at line 12602 of file MIMXRT1052.h.

◆ DMA_EEI_EEI20_SHIFT

#define DMA_EEI_EEI20_SHIFT (20U)

Definition at line 12603 of file MIMXRT1052.h.

◆ DMA_EEI_EEI21

#define DMA_EEI_EEI21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

EEI21 - Enable Error Interrupt 21 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12615 of file MIMXRT1052.h.

◆ DMA_EEI_EEI21_MASK

#define DMA_EEI_EEI21_MASK (0x200000U)

Definition at line 12609 of file MIMXRT1052.h.

◆ DMA_EEI_EEI21_SHIFT

#define DMA_EEI_EEI21_SHIFT (21U)

Definition at line 12610 of file MIMXRT1052.h.

◆ DMA_EEI_EEI22

#define DMA_EEI_EEI22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

EEI22 - Enable Error Interrupt 22 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12622 of file MIMXRT1052.h.

◆ DMA_EEI_EEI22_MASK

#define DMA_EEI_EEI22_MASK (0x400000U)

Definition at line 12616 of file MIMXRT1052.h.

◆ DMA_EEI_EEI22_SHIFT

#define DMA_EEI_EEI22_SHIFT (22U)

Definition at line 12617 of file MIMXRT1052.h.

◆ DMA_EEI_EEI23

#define DMA_EEI_EEI23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

EEI23 - Enable Error Interrupt 23 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12629 of file MIMXRT1052.h.

◆ DMA_EEI_EEI23_MASK

#define DMA_EEI_EEI23_MASK (0x800000U)

Definition at line 12623 of file MIMXRT1052.h.

◆ DMA_EEI_EEI23_SHIFT

#define DMA_EEI_EEI23_SHIFT (23U)

Definition at line 12624 of file MIMXRT1052.h.

◆ DMA_EEI_EEI24

#define DMA_EEI_EEI24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

EEI24 - Enable Error Interrupt 24 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12636 of file MIMXRT1052.h.

◆ DMA_EEI_EEI24_MASK

#define DMA_EEI_EEI24_MASK (0x1000000U)

Definition at line 12630 of file MIMXRT1052.h.

◆ DMA_EEI_EEI24_SHIFT

#define DMA_EEI_EEI24_SHIFT (24U)

Definition at line 12631 of file MIMXRT1052.h.

◆ DMA_EEI_EEI25

#define DMA_EEI_EEI25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

EEI25 - Enable Error Interrupt 25 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12643 of file MIMXRT1052.h.

◆ DMA_EEI_EEI25_MASK

#define DMA_EEI_EEI25_MASK (0x2000000U)

Definition at line 12637 of file MIMXRT1052.h.

◆ DMA_EEI_EEI25_SHIFT

#define DMA_EEI_EEI25_SHIFT (25U)

Definition at line 12638 of file MIMXRT1052.h.

◆ DMA_EEI_EEI26

#define DMA_EEI_EEI26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

EEI26 - Enable Error Interrupt 26 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12650 of file MIMXRT1052.h.

◆ DMA_EEI_EEI26_MASK

#define DMA_EEI_EEI26_MASK (0x4000000U)

Definition at line 12644 of file MIMXRT1052.h.

◆ DMA_EEI_EEI26_SHIFT

#define DMA_EEI_EEI26_SHIFT (26U)

Definition at line 12645 of file MIMXRT1052.h.

◆ DMA_EEI_EEI27

#define DMA_EEI_EEI27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

EEI27 - Enable Error Interrupt 27 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12657 of file MIMXRT1052.h.

◆ DMA_EEI_EEI27_MASK

#define DMA_EEI_EEI27_MASK (0x8000000U)

Definition at line 12651 of file MIMXRT1052.h.

◆ DMA_EEI_EEI27_SHIFT

#define DMA_EEI_EEI27_SHIFT (27U)

Definition at line 12652 of file MIMXRT1052.h.

◆ DMA_EEI_EEI28

#define DMA_EEI_EEI28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

EEI28 - Enable Error Interrupt 28 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12664 of file MIMXRT1052.h.

◆ DMA_EEI_EEI28_MASK

#define DMA_EEI_EEI28_MASK (0x10000000U)

Definition at line 12658 of file MIMXRT1052.h.

◆ DMA_EEI_EEI28_SHIFT

#define DMA_EEI_EEI28_SHIFT (28U)

Definition at line 12659 of file MIMXRT1052.h.

◆ DMA_EEI_EEI29

#define DMA_EEI_EEI29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

EEI29 - Enable Error Interrupt 29 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12671 of file MIMXRT1052.h.

◆ DMA_EEI_EEI29_MASK

#define DMA_EEI_EEI29_MASK (0x20000000U)

Definition at line 12665 of file MIMXRT1052.h.

◆ DMA_EEI_EEI29_SHIFT

#define DMA_EEI_EEI29_SHIFT (29U)

Definition at line 12666 of file MIMXRT1052.h.

◆ DMA_EEI_EEI2_MASK

#define DMA_EEI_EEI2_MASK (0x4U)

Definition at line 12476 of file MIMXRT1052.h.

◆ DMA_EEI_EEI2_SHIFT

#define DMA_EEI_EEI2_SHIFT (2U)

Definition at line 12477 of file MIMXRT1052.h.

◆ DMA_EEI_EEI3

#define DMA_EEI_EEI3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12489 of file MIMXRT1052.h.

◆ DMA_EEI_EEI30

#define DMA_EEI_EEI30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

EEI30 - Enable Error Interrupt 30 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12678 of file MIMXRT1052.h.

◆ DMA_EEI_EEI30_MASK

#define DMA_EEI_EEI30_MASK (0x40000000U)

Definition at line 12672 of file MIMXRT1052.h.

◆ DMA_EEI_EEI30_SHIFT

#define DMA_EEI_EEI30_SHIFT (30U)

Definition at line 12673 of file MIMXRT1052.h.

◆ DMA_EEI_EEI31

#define DMA_EEI_EEI31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

EEI31 - Enable Error Interrupt 31 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12685 of file MIMXRT1052.h.

◆ DMA_EEI_EEI31_MASK

#define DMA_EEI_EEI31_MASK (0x80000000U)

Definition at line 12679 of file MIMXRT1052.h.

◆ DMA_EEI_EEI31_SHIFT

#define DMA_EEI_EEI31_SHIFT (31U)

Definition at line 12680 of file MIMXRT1052.h.

◆ DMA_EEI_EEI3_MASK

#define DMA_EEI_EEI3_MASK (0x8U)

Definition at line 12483 of file MIMXRT1052.h.

◆ DMA_EEI_EEI3_SHIFT

#define DMA_EEI_EEI3_SHIFT (3U)

Definition at line 12484 of file MIMXRT1052.h.

◆ DMA_EEI_EEI4

#define DMA_EEI_EEI4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12496 of file MIMXRT1052.h.

◆ DMA_EEI_EEI4_MASK

#define DMA_EEI_EEI4_MASK (0x10U)

Definition at line 12490 of file MIMXRT1052.h.

◆ DMA_EEI_EEI4_SHIFT

#define DMA_EEI_EEI4_SHIFT (4U)

Definition at line 12491 of file MIMXRT1052.h.

◆ DMA_EEI_EEI5

#define DMA_EEI_EEI5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12503 of file MIMXRT1052.h.

◆ DMA_EEI_EEI5_MASK

#define DMA_EEI_EEI5_MASK (0x20U)

Definition at line 12497 of file MIMXRT1052.h.

◆ DMA_EEI_EEI5_SHIFT

#define DMA_EEI_EEI5_SHIFT (5U)

Definition at line 12498 of file MIMXRT1052.h.

◆ DMA_EEI_EEI6

#define DMA_EEI_EEI6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12510 of file MIMXRT1052.h.

◆ DMA_EEI_EEI6_MASK

#define DMA_EEI_EEI6_MASK (0x40U)

Definition at line 12504 of file MIMXRT1052.h.

◆ DMA_EEI_EEI6_SHIFT

#define DMA_EEI_EEI6_SHIFT (6U)

Definition at line 12505 of file MIMXRT1052.h.

◆ DMA_EEI_EEI7

#define DMA_EEI_EEI7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12517 of file MIMXRT1052.h.

◆ DMA_EEI_EEI7_MASK

#define DMA_EEI_EEI7_MASK (0x80U)

Definition at line 12511 of file MIMXRT1052.h.

◆ DMA_EEI_EEI7_SHIFT

#define DMA_EEI_EEI7_SHIFT (7U)

Definition at line 12512 of file MIMXRT1052.h.

◆ DMA_EEI_EEI8

#define DMA_EEI_EEI8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12524 of file MIMXRT1052.h.

◆ DMA_EEI_EEI8_MASK

#define DMA_EEI_EEI8_MASK (0x100U)

Definition at line 12518 of file MIMXRT1052.h.

◆ DMA_EEI_EEI8_SHIFT

#define DMA_EEI_EEI8_SHIFT (8U)

Definition at line 12519 of file MIMXRT1052.h.

◆ DMA_EEI_EEI9

#define DMA_EEI_EEI9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 12531 of file MIMXRT1052.h.

◆ DMA_EEI_EEI9_MASK

#define DMA_EEI_EEI9_MASK (0x200U)

Definition at line 12525 of file MIMXRT1052.h.

◆ DMA_EEI_EEI9_SHIFT

#define DMA_EEI_EEI9_SHIFT (9U)

Definition at line 12526 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ0

#define DMA_ERQ_ERQ0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12240 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ0_MASK

#define DMA_ERQ_ERQ0_MASK (0x1U)

Definition at line 12234 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ0_SHIFT

#define DMA_ERQ_ERQ0_SHIFT (0U)

Definition at line 12235 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ1

#define DMA_ERQ_ERQ1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12247 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ10

#define DMA_ERQ_ERQ10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12310 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ10_MASK

#define DMA_ERQ_ERQ10_MASK (0x400U)

Definition at line 12304 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ10_SHIFT

#define DMA_ERQ_ERQ10_SHIFT (10U)

Definition at line 12305 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ11

#define DMA_ERQ_ERQ11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12317 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ11_MASK

#define DMA_ERQ_ERQ11_MASK (0x800U)

Definition at line 12311 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ11_SHIFT

#define DMA_ERQ_ERQ11_SHIFT (11U)

Definition at line 12312 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ12

#define DMA_ERQ_ERQ12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12324 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ12_MASK

#define DMA_ERQ_ERQ12_MASK (0x1000U)

Definition at line 12318 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ12_SHIFT

#define DMA_ERQ_ERQ12_SHIFT (12U)

Definition at line 12319 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ13

#define DMA_ERQ_ERQ13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12331 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ13_MASK

#define DMA_ERQ_ERQ13_MASK (0x2000U)

Definition at line 12325 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ13_SHIFT

#define DMA_ERQ_ERQ13_SHIFT (13U)

Definition at line 12326 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ14

#define DMA_ERQ_ERQ14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12338 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ14_MASK

#define DMA_ERQ_ERQ14_MASK (0x4000U)

Definition at line 12332 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ14_SHIFT

#define DMA_ERQ_ERQ14_SHIFT (14U)

Definition at line 12333 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ15

#define DMA_ERQ_ERQ15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12345 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ15_MASK

#define DMA_ERQ_ERQ15_MASK (0x8000U)

Definition at line 12339 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ15_SHIFT

#define DMA_ERQ_ERQ15_SHIFT (15U)

Definition at line 12340 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ16

#define DMA_ERQ_ERQ16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

ERQ16 - Enable DMA Request 16 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12352 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ16_MASK

#define DMA_ERQ_ERQ16_MASK (0x10000U)

Definition at line 12346 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ16_SHIFT

#define DMA_ERQ_ERQ16_SHIFT (16U)

Definition at line 12347 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ17

#define DMA_ERQ_ERQ17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

ERQ17 - Enable DMA Request 17 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12359 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ17_MASK

#define DMA_ERQ_ERQ17_MASK (0x20000U)

Definition at line 12353 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ17_SHIFT

#define DMA_ERQ_ERQ17_SHIFT (17U)

Definition at line 12354 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ18

#define DMA_ERQ_ERQ18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

ERQ18 - Enable DMA Request 18 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12366 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ18_MASK

#define DMA_ERQ_ERQ18_MASK (0x40000U)

Definition at line 12360 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ18_SHIFT

#define DMA_ERQ_ERQ18_SHIFT (18U)

Definition at line 12361 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ19

#define DMA_ERQ_ERQ19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

ERQ19 - Enable DMA Request 19 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12373 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ19_MASK

#define DMA_ERQ_ERQ19_MASK (0x80000U)

Definition at line 12367 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ19_SHIFT

#define DMA_ERQ_ERQ19_SHIFT (19U)

Definition at line 12368 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ1_MASK

#define DMA_ERQ_ERQ1_MASK (0x2U)

Definition at line 12241 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ1_SHIFT

#define DMA_ERQ_ERQ1_SHIFT (1U)

Definition at line 12242 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ2

#define DMA_ERQ_ERQ2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12254 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ20

#define DMA_ERQ_ERQ20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

ERQ20 - Enable DMA Request 20 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12380 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ20_MASK

#define DMA_ERQ_ERQ20_MASK (0x100000U)

Definition at line 12374 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ20_SHIFT

#define DMA_ERQ_ERQ20_SHIFT (20U)

Definition at line 12375 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ21

#define DMA_ERQ_ERQ21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

ERQ21 - Enable DMA Request 21 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12387 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ21_MASK

#define DMA_ERQ_ERQ21_MASK (0x200000U)

Definition at line 12381 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ21_SHIFT

#define DMA_ERQ_ERQ21_SHIFT (21U)

Definition at line 12382 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ22

#define DMA_ERQ_ERQ22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

ERQ22 - Enable DMA Request 22 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12394 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ22_MASK

#define DMA_ERQ_ERQ22_MASK (0x400000U)

Definition at line 12388 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ22_SHIFT

#define DMA_ERQ_ERQ22_SHIFT (22U)

Definition at line 12389 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ23

#define DMA_ERQ_ERQ23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

ERQ23 - Enable DMA Request 23 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12401 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ23_MASK

#define DMA_ERQ_ERQ23_MASK (0x800000U)

Definition at line 12395 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ23_SHIFT

#define DMA_ERQ_ERQ23_SHIFT (23U)

Definition at line 12396 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ24

#define DMA_ERQ_ERQ24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

ERQ24 - Enable DMA Request 24 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12408 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ24_MASK

#define DMA_ERQ_ERQ24_MASK (0x1000000U)

Definition at line 12402 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ24_SHIFT

#define DMA_ERQ_ERQ24_SHIFT (24U)

Definition at line 12403 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ25

#define DMA_ERQ_ERQ25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

ERQ25 - Enable DMA Request 25 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12415 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ25_MASK

#define DMA_ERQ_ERQ25_MASK (0x2000000U)

Definition at line 12409 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ25_SHIFT

#define DMA_ERQ_ERQ25_SHIFT (25U)

Definition at line 12410 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ26

#define DMA_ERQ_ERQ26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

ERQ26 - Enable DMA Request 26 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12422 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ26_MASK

#define DMA_ERQ_ERQ26_MASK (0x4000000U)

Definition at line 12416 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ26_SHIFT

#define DMA_ERQ_ERQ26_SHIFT (26U)

Definition at line 12417 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ27

#define DMA_ERQ_ERQ27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

ERQ27 - Enable DMA Request 27 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12429 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ27_MASK

#define DMA_ERQ_ERQ27_MASK (0x8000000U)

Definition at line 12423 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ27_SHIFT

#define DMA_ERQ_ERQ27_SHIFT (27U)

Definition at line 12424 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ28

#define DMA_ERQ_ERQ28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

ERQ28 - Enable DMA Request 28 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12436 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ28_MASK

#define DMA_ERQ_ERQ28_MASK (0x10000000U)

Definition at line 12430 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ28_SHIFT

#define DMA_ERQ_ERQ28_SHIFT (28U)

Definition at line 12431 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ29

#define DMA_ERQ_ERQ29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

ERQ29 - Enable DMA Request 29 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12443 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ29_MASK

#define DMA_ERQ_ERQ29_MASK (0x20000000U)

Definition at line 12437 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ29_SHIFT

#define DMA_ERQ_ERQ29_SHIFT (29U)

Definition at line 12438 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ2_MASK

#define DMA_ERQ_ERQ2_MASK (0x4U)

Definition at line 12248 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ2_SHIFT

#define DMA_ERQ_ERQ2_SHIFT (2U)

Definition at line 12249 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ3

#define DMA_ERQ_ERQ3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12261 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ30

#define DMA_ERQ_ERQ30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

ERQ30 - Enable DMA Request 30 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12450 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ30_MASK

#define DMA_ERQ_ERQ30_MASK (0x40000000U)

Definition at line 12444 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ30_SHIFT

#define DMA_ERQ_ERQ30_SHIFT (30U)

Definition at line 12445 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ31

#define DMA_ERQ_ERQ31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

ERQ31 - Enable DMA Request 31 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12457 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ31_MASK

#define DMA_ERQ_ERQ31_MASK (0x80000000U)

Definition at line 12451 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ31_SHIFT

#define DMA_ERQ_ERQ31_SHIFT (31U)

Definition at line 12452 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ3_MASK

#define DMA_ERQ_ERQ3_MASK (0x8U)

Definition at line 12255 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ3_SHIFT

#define DMA_ERQ_ERQ3_SHIFT (3U)

Definition at line 12256 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ4

#define DMA_ERQ_ERQ4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12268 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ4_MASK

#define DMA_ERQ_ERQ4_MASK (0x10U)

Definition at line 12262 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ4_SHIFT

#define DMA_ERQ_ERQ4_SHIFT (4U)

Definition at line 12263 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ5

#define DMA_ERQ_ERQ5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12275 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ5_MASK

#define DMA_ERQ_ERQ5_MASK (0x20U)

Definition at line 12269 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ5_SHIFT

#define DMA_ERQ_ERQ5_SHIFT (5U)

Definition at line 12270 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ6

#define DMA_ERQ_ERQ6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12282 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ6_MASK

#define DMA_ERQ_ERQ6_MASK (0x40U)

Definition at line 12276 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ6_SHIFT

#define DMA_ERQ_ERQ6_SHIFT (6U)

Definition at line 12277 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ7

#define DMA_ERQ_ERQ7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12289 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ7_MASK

#define DMA_ERQ_ERQ7_MASK (0x80U)

Definition at line 12283 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ7_SHIFT

#define DMA_ERQ_ERQ7_SHIFT (7U)

Definition at line 12284 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ8

#define DMA_ERQ_ERQ8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12296 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ8_MASK

#define DMA_ERQ_ERQ8_MASK (0x100U)

Definition at line 12290 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ8_SHIFT

#define DMA_ERQ_ERQ8_SHIFT (8U)

Definition at line 12291 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ9

#define DMA_ERQ_ERQ9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 12303 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ9_MASK

#define DMA_ERQ_ERQ9_MASK (0x200U)

Definition at line 12297 of file MIMXRT1052.h.

◆ DMA_ERQ_ERQ9_SHIFT

#define DMA_ERQ_ERQ9_SHIFT (9U)

Definition at line 12298 of file MIMXRT1052.h.

◆ DMA_ERR_ERR0

#define DMA_ERR_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13108 of file MIMXRT1052.h.

◆ DMA_ERR_ERR0_MASK

#define DMA_ERR_ERR0_MASK (0x1U)

Definition at line 13102 of file MIMXRT1052.h.

◆ DMA_ERR_ERR0_SHIFT

#define DMA_ERR_ERR0_SHIFT (0U)

Definition at line 13103 of file MIMXRT1052.h.

◆ DMA_ERR_ERR1

#define DMA_ERR_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13115 of file MIMXRT1052.h.

◆ DMA_ERR_ERR10

#define DMA_ERR_ERR10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13178 of file MIMXRT1052.h.

◆ DMA_ERR_ERR10_MASK

#define DMA_ERR_ERR10_MASK (0x400U)

Definition at line 13172 of file MIMXRT1052.h.

◆ DMA_ERR_ERR10_SHIFT

#define DMA_ERR_ERR10_SHIFT (10U)

Definition at line 13173 of file MIMXRT1052.h.

◆ DMA_ERR_ERR11

#define DMA_ERR_ERR11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13185 of file MIMXRT1052.h.

◆ DMA_ERR_ERR11_MASK

#define DMA_ERR_ERR11_MASK (0x800U)

Definition at line 13179 of file MIMXRT1052.h.

◆ DMA_ERR_ERR11_SHIFT

#define DMA_ERR_ERR11_SHIFT (11U)

Definition at line 13180 of file MIMXRT1052.h.

◆ DMA_ERR_ERR12

#define DMA_ERR_ERR12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13192 of file MIMXRT1052.h.

◆ DMA_ERR_ERR12_MASK

#define DMA_ERR_ERR12_MASK (0x1000U)

Definition at line 13186 of file MIMXRT1052.h.

◆ DMA_ERR_ERR12_SHIFT

#define DMA_ERR_ERR12_SHIFT (12U)

Definition at line 13187 of file MIMXRT1052.h.

◆ DMA_ERR_ERR13

#define DMA_ERR_ERR13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13199 of file MIMXRT1052.h.

◆ DMA_ERR_ERR13_MASK

#define DMA_ERR_ERR13_MASK (0x2000U)

Definition at line 13193 of file MIMXRT1052.h.

◆ DMA_ERR_ERR13_SHIFT

#define DMA_ERR_ERR13_SHIFT (13U)

Definition at line 13194 of file MIMXRT1052.h.

◆ DMA_ERR_ERR14

#define DMA_ERR_ERR14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13206 of file MIMXRT1052.h.

◆ DMA_ERR_ERR14_MASK

#define DMA_ERR_ERR14_MASK (0x4000U)

Definition at line 13200 of file MIMXRT1052.h.

◆ DMA_ERR_ERR14_SHIFT

#define DMA_ERR_ERR14_SHIFT (14U)

Definition at line 13201 of file MIMXRT1052.h.

◆ DMA_ERR_ERR15

#define DMA_ERR_ERR15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13213 of file MIMXRT1052.h.

◆ DMA_ERR_ERR15_MASK

#define DMA_ERR_ERR15_MASK (0x8000U)

Definition at line 13207 of file MIMXRT1052.h.

◆ DMA_ERR_ERR15_SHIFT

#define DMA_ERR_ERR15_SHIFT (15U)

Definition at line 13208 of file MIMXRT1052.h.

◆ DMA_ERR_ERR16

#define DMA_ERR_ERR16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

ERR16 - Error In Channel 16 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13220 of file MIMXRT1052.h.

◆ DMA_ERR_ERR16_MASK

#define DMA_ERR_ERR16_MASK (0x10000U)

Definition at line 13214 of file MIMXRT1052.h.

◆ DMA_ERR_ERR16_SHIFT

#define DMA_ERR_ERR16_SHIFT (16U)

Definition at line 13215 of file MIMXRT1052.h.

◆ DMA_ERR_ERR17

#define DMA_ERR_ERR17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

ERR17 - Error In Channel 17 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13227 of file MIMXRT1052.h.

◆ DMA_ERR_ERR17_MASK

#define DMA_ERR_ERR17_MASK (0x20000U)

Definition at line 13221 of file MIMXRT1052.h.

◆ DMA_ERR_ERR17_SHIFT

#define DMA_ERR_ERR17_SHIFT (17U)

Definition at line 13222 of file MIMXRT1052.h.

◆ DMA_ERR_ERR18

#define DMA_ERR_ERR18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

ERR18 - Error In Channel 18 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13234 of file MIMXRT1052.h.

◆ DMA_ERR_ERR18_MASK

#define DMA_ERR_ERR18_MASK (0x40000U)

Definition at line 13228 of file MIMXRT1052.h.

◆ DMA_ERR_ERR18_SHIFT

#define DMA_ERR_ERR18_SHIFT (18U)

Definition at line 13229 of file MIMXRT1052.h.

◆ DMA_ERR_ERR19

#define DMA_ERR_ERR19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

ERR19 - Error In Channel 19 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13241 of file MIMXRT1052.h.

◆ DMA_ERR_ERR19_MASK

#define DMA_ERR_ERR19_MASK (0x80000U)

Definition at line 13235 of file MIMXRT1052.h.

◆ DMA_ERR_ERR19_SHIFT

#define DMA_ERR_ERR19_SHIFT (19U)

Definition at line 13236 of file MIMXRT1052.h.

◆ DMA_ERR_ERR1_MASK

#define DMA_ERR_ERR1_MASK (0x2U)

Definition at line 13109 of file MIMXRT1052.h.

◆ DMA_ERR_ERR1_SHIFT

#define DMA_ERR_ERR1_SHIFT (1U)

Definition at line 13110 of file MIMXRT1052.h.

◆ DMA_ERR_ERR2

#define DMA_ERR_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13122 of file MIMXRT1052.h.

◆ DMA_ERR_ERR20

#define DMA_ERR_ERR20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

ERR20 - Error In Channel 20 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13248 of file MIMXRT1052.h.

◆ DMA_ERR_ERR20_MASK

#define DMA_ERR_ERR20_MASK (0x100000U)

Definition at line 13242 of file MIMXRT1052.h.

◆ DMA_ERR_ERR20_SHIFT

#define DMA_ERR_ERR20_SHIFT (20U)

Definition at line 13243 of file MIMXRT1052.h.

◆ DMA_ERR_ERR21

#define DMA_ERR_ERR21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

ERR21 - Error In Channel 21 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13255 of file MIMXRT1052.h.

◆ DMA_ERR_ERR21_MASK

#define DMA_ERR_ERR21_MASK (0x200000U)

Definition at line 13249 of file MIMXRT1052.h.

◆ DMA_ERR_ERR21_SHIFT

#define DMA_ERR_ERR21_SHIFT (21U)

Definition at line 13250 of file MIMXRT1052.h.

◆ DMA_ERR_ERR22

#define DMA_ERR_ERR22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

ERR22 - Error In Channel 22 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13262 of file MIMXRT1052.h.

◆ DMA_ERR_ERR22_MASK

#define DMA_ERR_ERR22_MASK (0x400000U)

Definition at line 13256 of file MIMXRT1052.h.

◆ DMA_ERR_ERR22_SHIFT

#define DMA_ERR_ERR22_SHIFT (22U)

Definition at line 13257 of file MIMXRT1052.h.

◆ DMA_ERR_ERR23

#define DMA_ERR_ERR23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

ERR23 - Error In Channel 23 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13269 of file MIMXRT1052.h.

◆ DMA_ERR_ERR23_MASK

#define DMA_ERR_ERR23_MASK (0x800000U)

Definition at line 13263 of file MIMXRT1052.h.

◆ DMA_ERR_ERR23_SHIFT

#define DMA_ERR_ERR23_SHIFT (23U)

Definition at line 13264 of file MIMXRT1052.h.

◆ DMA_ERR_ERR24

#define DMA_ERR_ERR24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

ERR24 - Error In Channel 24 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13276 of file MIMXRT1052.h.

◆ DMA_ERR_ERR24_MASK

#define DMA_ERR_ERR24_MASK (0x1000000U)

Definition at line 13270 of file MIMXRT1052.h.

◆ DMA_ERR_ERR24_SHIFT

#define DMA_ERR_ERR24_SHIFT (24U)

Definition at line 13271 of file MIMXRT1052.h.

◆ DMA_ERR_ERR25

#define DMA_ERR_ERR25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

ERR25 - Error In Channel 25 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13283 of file MIMXRT1052.h.

◆ DMA_ERR_ERR25_MASK

#define DMA_ERR_ERR25_MASK (0x2000000U)

Definition at line 13277 of file MIMXRT1052.h.

◆ DMA_ERR_ERR25_SHIFT

#define DMA_ERR_ERR25_SHIFT (25U)

Definition at line 13278 of file MIMXRT1052.h.

◆ DMA_ERR_ERR26

#define DMA_ERR_ERR26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

ERR26 - Error In Channel 26 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13290 of file MIMXRT1052.h.

◆ DMA_ERR_ERR26_MASK

#define DMA_ERR_ERR26_MASK (0x4000000U)

Definition at line 13284 of file MIMXRT1052.h.

◆ DMA_ERR_ERR26_SHIFT

#define DMA_ERR_ERR26_SHIFT (26U)

Definition at line 13285 of file MIMXRT1052.h.

◆ DMA_ERR_ERR27

#define DMA_ERR_ERR27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

ERR27 - Error In Channel 27 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13297 of file MIMXRT1052.h.

◆ DMA_ERR_ERR27_MASK

#define DMA_ERR_ERR27_MASK (0x8000000U)

Definition at line 13291 of file MIMXRT1052.h.

◆ DMA_ERR_ERR27_SHIFT

#define DMA_ERR_ERR27_SHIFT (27U)

Definition at line 13292 of file MIMXRT1052.h.

◆ DMA_ERR_ERR28

#define DMA_ERR_ERR28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

ERR28 - Error In Channel 28 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13304 of file MIMXRT1052.h.

◆ DMA_ERR_ERR28_MASK

#define DMA_ERR_ERR28_MASK (0x10000000U)

Definition at line 13298 of file MIMXRT1052.h.

◆ DMA_ERR_ERR28_SHIFT

#define DMA_ERR_ERR28_SHIFT (28U)

Definition at line 13299 of file MIMXRT1052.h.

◆ DMA_ERR_ERR29

#define DMA_ERR_ERR29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

ERR29 - Error In Channel 29 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13311 of file MIMXRT1052.h.

◆ DMA_ERR_ERR29_MASK

#define DMA_ERR_ERR29_MASK (0x20000000U)

Definition at line 13305 of file MIMXRT1052.h.

◆ DMA_ERR_ERR29_SHIFT

#define DMA_ERR_ERR29_SHIFT (29U)

Definition at line 13306 of file MIMXRT1052.h.

◆ DMA_ERR_ERR2_MASK

#define DMA_ERR_ERR2_MASK (0x4U)

Definition at line 13116 of file MIMXRT1052.h.

◆ DMA_ERR_ERR2_SHIFT

#define DMA_ERR_ERR2_SHIFT (2U)

Definition at line 13117 of file MIMXRT1052.h.

◆ DMA_ERR_ERR3

#define DMA_ERR_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13129 of file MIMXRT1052.h.

◆ DMA_ERR_ERR30

#define DMA_ERR_ERR30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

ERR30 - Error In Channel 30 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13318 of file MIMXRT1052.h.

◆ DMA_ERR_ERR30_MASK

#define DMA_ERR_ERR30_MASK (0x40000000U)

Definition at line 13312 of file MIMXRT1052.h.

◆ DMA_ERR_ERR30_SHIFT

#define DMA_ERR_ERR30_SHIFT (30U)

Definition at line 13313 of file MIMXRT1052.h.

◆ DMA_ERR_ERR31

#define DMA_ERR_ERR31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

ERR31 - Error In Channel 31 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13325 of file MIMXRT1052.h.

◆ DMA_ERR_ERR31_MASK

#define DMA_ERR_ERR31_MASK (0x80000000U)

Definition at line 13319 of file MIMXRT1052.h.

◆ DMA_ERR_ERR31_SHIFT

#define DMA_ERR_ERR31_SHIFT (31U)

Definition at line 13320 of file MIMXRT1052.h.

◆ DMA_ERR_ERR3_MASK

#define DMA_ERR_ERR3_MASK (0x8U)

Definition at line 13123 of file MIMXRT1052.h.

◆ DMA_ERR_ERR3_SHIFT

#define DMA_ERR_ERR3_SHIFT (3U)

Definition at line 13124 of file MIMXRT1052.h.

◆ DMA_ERR_ERR4

#define DMA_ERR_ERR4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13136 of file MIMXRT1052.h.

◆ DMA_ERR_ERR4_MASK

#define DMA_ERR_ERR4_MASK (0x10U)

Definition at line 13130 of file MIMXRT1052.h.

◆ DMA_ERR_ERR4_SHIFT

#define DMA_ERR_ERR4_SHIFT (4U)

Definition at line 13131 of file MIMXRT1052.h.

◆ DMA_ERR_ERR5

#define DMA_ERR_ERR5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13143 of file MIMXRT1052.h.

◆ DMA_ERR_ERR5_MASK

#define DMA_ERR_ERR5_MASK (0x20U)

Definition at line 13137 of file MIMXRT1052.h.

◆ DMA_ERR_ERR5_SHIFT

#define DMA_ERR_ERR5_SHIFT (5U)

Definition at line 13138 of file MIMXRT1052.h.

◆ DMA_ERR_ERR6

#define DMA_ERR_ERR6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13150 of file MIMXRT1052.h.

◆ DMA_ERR_ERR6_MASK

#define DMA_ERR_ERR6_MASK (0x40U)

Definition at line 13144 of file MIMXRT1052.h.

◆ DMA_ERR_ERR6_SHIFT

#define DMA_ERR_ERR6_SHIFT (6U)

Definition at line 13145 of file MIMXRT1052.h.

◆ DMA_ERR_ERR7

#define DMA_ERR_ERR7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13157 of file MIMXRT1052.h.

◆ DMA_ERR_ERR7_MASK

#define DMA_ERR_ERR7_MASK (0x80U)

Definition at line 13151 of file MIMXRT1052.h.

◆ DMA_ERR_ERR7_SHIFT

#define DMA_ERR_ERR7_SHIFT (7U)

Definition at line 13152 of file MIMXRT1052.h.

◆ DMA_ERR_ERR8

#define DMA_ERR_ERR8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13164 of file MIMXRT1052.h.

◆ DMA_ERR_ERR8_MASK

#define DMA_ERR_ERR8_MASK (0x100U)

Definition at line 13158 of file MIMXRT1052.h.

◆ DMA_ERR_ERR8_SHIFT

#define DMA_ERR_ERR8_SHIFT (8U)

Definition at line 13159 of file MIMXRT1052.h.

◆ DMA_ERR_ERR9

#define DMA_ERR_ERR9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 13171 of file MIMXRT1052.h.

◆ DMA_ERR_ERR9_MASK

#define DMA_ERR_ERR9_MASK (0x200U)

Definition at line 13165 of file MIMXRT1052.h.

◆ DMA_ERR_ERR9_SHIFT

#define DMA_ERR_ERR9_SHIFT (9U)

Definition at line 13166 of file MIMXRT1052.h.

◆ DMA_ES_CPE

#define DMA_ES_CPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

Definition at line 12208 of file MIMXRT1052.h.

◆ DMA_ES_CPE_MASK

#define DMA_ES_CPE_MASK (0x4000U)

Definition at line 12201 of file MIMXRT1052.h.

◆ DMA_ES_CPE_SHIFT

#define DMA_ES_CPE_SHIFT (14U)

Definition at line 12202 of file MIMXRT1052.h.

◆ DMA_ES_DAE

#define DMA_ES_DAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

Definition at line 12181 of file MIMXRT1052.h.

◆ DMA_ES_DAE_MASK

#define DMA_ES_DAE_MASK (0x20U)

Definition at line 12175 of file MIMXRT1052.h.

◆ DMA_ES_DAE_SHIFT

#define DMA_ES_DAE_SHIFT (5U)

Definition at line 12176 of file MIMXRT1052.h.

◆ DMA_ES_DBE

#define DMA_ES_DBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error 0b1..The last recorded error was a bus error on a destination write

Definition at line 12142 of file MIMXRT1052.h.

◆ DMA_ES_DBE_MASK

#define DMA_ES_DBE_MASK (0x1U)

Definition at line 12136 of file MIMXRT1052.h.

◆ DMA_ES_DBE_SHIFT

#define DMA_ES_DBE_SHIFT (0U)

Definition at line 12137 of file MIMXRT1052.h.

◆ DMA_ES_DOE

#define DMA_ES_DOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

Definition at line 12174 of file MIMXRT1052.h.

◆ DMA_ES_DOE_MASK

#define DMA_ES_DOE_MASK (0x10U)

Definition at line 12168 of file MIMXRT1052.h.

◆ DMA_ES_DOE_SHIFT

#define DMA_ES_DOE_SHIFT (4U)

Definition at line 12169 of file MIMXRT1052.h.

◆ DMA_ES_ECX

#define DMA_ES_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input

Definition at line 12222 of file MIMXRT1052.h.

◆ DMA_ES_ECX_MASK

#define DMA_ES_ECX_MASK (0x10000U)

Definition at line 12216 of file MIMXRT1052.h.

◆ DMA_ES_ECX_SHIFT

#define DMA_ES_ECX_SHIFT (16U)

Definition at line 12217 of file MIMXRT1052.h.

◆ DMA_ES_ERRCHN

#define DMA_ES_ERRCHN ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

ERRCHN - Error Channel Number or Canceled Channel Number

Definition at line 12200 of file MIMXRT1052.h.

◆ DMA_ES_ERRCHN_MASK

#define DMA_ES_ERRCHN_MASK (0x1F00U)

Definition at line 12196 of file MIMXRT1052.h.

◆ DMA_ES_ERRCHN_SHIFT

#define DMA_ES_ERRCHN_SHIFT (8U)

Definition at line 12197 of file MIMXRT1052.h.

◆ DMA_ES_GPE

#define DMA_ES_GPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

GPE - Group Priority Error 0b0..No group priority error 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.

Definition at line 12215 of file MIMXRT1052.h.

◆ DMA_ES_GPE_MASK

#define DMA_ES_GPE_MASK (0x8000U)

Definition at line 12209 of file MIMXRT1052.h.

◆ DMA_ES_GPE_SHIFT

#define DMA_ES_GPE_SHIFT (15U)

Definition at line 12210 of file MIMXRT1052.h.

◆ DMA_ES_NCE

#define DMA_ES_NCE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]

Definition at line 12167 of file MIMXRT1052.h.

◆ DMA_ES_NCE_MASK

#define DMA_ES_NCE_MASK (0x8U)

Definition at line 12159 of file MIMXRT1052.h.

◆ DMA_ES_NCE_SHIFT

#define DMA_ES_NCE_SHIFT (3U)

Definition at line 12160 of file MIMXRT1052.h.

◆ DMA_ES_SAE

#define DMA_ES_SAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

Definition at line 12195 of file MIMXRT1052.h.

◆ DMA_ES_SAE_MASK

#define DMA_ES_SAE_MASK (0x80U)

Definition at line 12189 of file MIMXRT1052.h.

◆ DMA_ES_SAE_SHIFT

#define DMA_ES_SAE_SHIFT (7U)

Definition at line 12190 of file MIMXRT1052.h.

◆ DMA_ES_SBE

#define DMA_ES_SBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error 0b1..The last recorded error was a bus error on a source read

Definition at line 12149 of file MIMXRT1052.h.

◆ DMA_ES_SBE_MASK

#define DMA_ES_SBE_MASK (0x2U)

Definition at line 12143 of file MIMXRT1052.h.

◆ DMA_ES_SBE_SHIFT

#define DMA_ES_SBE_SHIFT (1U)

Definition at line 12144 of file MIMXRT1052.h.

◆ DMA_ES_SGE

#define DMA_ES_SGE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.

Definition at line 12158 of file MIMXRT1052.h.

◆ DMA_ES_SGE_MASK

#define DMA_ES_SGE_MASK (0x4U)

Definition at line 12150 of file MIMXRT1052.h.

◆ DMA_ES_SGE_SHIFT

#define DMA_ES_SGE_SHIFT (2U)

Definition at line 12151 of file MIMXRT1052.h.

◆ DMA_ES_SOE

#define DMA_ES_SOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

Definition at line 12188 of file MIMXRT1052.h.

◆ DMA_ES_SOE_MASK

#define DMA_ES_SOE_MASK (0x40U)

Definition at line 12182 of file MIMXRT1052.h.

◆ DMA_ES_SOE_SHIFT

#define DMA_ES_SOE_SHIFT (6U)

Definition at line 12183 of file MIMXRT1052.h.

◆ DMA_ES_VLD

#define DMA_ES_VLD ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD - VLD 0b0..No ERR bits are set. 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.

Definition at line 12229 of file MIMXRT1052.h.

◆ DMA_ES_VLD_MASK

#define DMA_ES_VLD_MASK (0x80000000U)

Definition at line 12223 of file MIMXRT1052.h.

◆ DMA_ES_VLD_SHIFT

#define DMA_ES_VLD_SHIFT (31U)

Definition at line 12224 of file MIMXRT1052.h.

◆ DMA_HRS_HRS0

#define DMA_HRS_HRS0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

Definition at line 13336 of file MIMXRT1052.h.

◆ DMA_HRS_HRS0_MASK

#define DMA_HRS_HRS0_MASK (0x1U)

Definition at line 13330 of file MIMXRT1052.h.

◆ DMA_HRS_HRS0_SHIFT

#define DMA_HRS_HRS0_SHIFT (0U)

Definition at line 13331 of file MIMXRT1052.h.

◆ DMA_HRS_HRS1

#define DMA_HRS_HRS1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

Definition at line 13343 of file MIMXRT1052.h.

◆ DMA_HRS_HRS10

#define DMA_HRS_HRS10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

Definition at line 13406 of file MIMXRT1052.h.

◆ DMA_HRS_HRS10_MASK

#define DMA_HRS_HRS10_MASK (0x400U)

Definition at line 13400 of file MIMXRT1052.h.

◆ DMA_HRS_HRS10_SHIFT

#define DMA_HRS_HRS10_SHIFT (10U)

Definition at line 13401 of file MIMXRT1052.h.

◆ DMA_HRS_HRS11

#define DMA_HRS_HRS11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

Definition at line 13413 of file MIMXRT1052.h.

◆ DMA_HRS_HRS11_MASK

#define DMA_HRS_HRS11_MASK (0x800U)

Definition at line 13407 of file MIMXRT1052.h.

◆ DMA_HRS_HRS11_SHIFT

#define DMA_HRS_HRS11_SHIFT (11U)

Definition at line 13408 of file MIMXRT1052.h.

◆ DMA_HRS_HRS12

#define DMA_HRS_HRS12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

Definition at line 13420 of file MIMXRT1052.h.

◆ DMA_HRS_HRS12_MASK

#define DMA_HRS_HRS12_MASK (0x1000U)

Definition at line 13414 of file MIMXRT1052.h.

◆ DMA_HRS_HRS12_SHIFT

#define DMA_HRS_HRS12_SHIFT (12U)

Definition at line 13415 of file MIMXRT1052.h.

◆ DMA_HRS_HRS13

#define DMA_HRS_HRS13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

Definition at line 13427 of file MIMXRT1052.h.

◆ DMA_HRS_HRS13_MASK

#define DMA_HRS_HRS13_MASK (0x2000U)

Definition at line 13421 of file MIMXRT1052.h.

◆ DMA_HRS_HRS13_SHIFT

#define DMA_HRS_HRS13_SHIFT (13U)

Definition at line 13422 of file MIMXRT1052.h.

◆ DMA_HRS_HRS14

#define DMA_HRS_HRS14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

Definition at line 13434 of file MIMXRT1052.h.

◆ DMA_HRS_HRS14_MASK

#define DMA_HRS_HRS14_MASK (0x4000U)

Definition at line 13428 of file MIMXRT1052.h.

◆ DMA_HRS_HRS14_SHIFT

#define DMA_HRS_HRS14_SHIFT (14U)

Definition at line 13429 of file MIMXRT1052.h.

◆ DMA_HRS_HRS15

#define DMA_HRS_HRS15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

Definition at line 13441 of file MIMXRT1052.h.

◆ DMA_HRS_HRS15_MASK

#define DMA_HRS_HRS15_MASK (0x8000U)

Definition at line 13435 of file MIMXRT1052.h.

◆ DMA_HRS_HRS15_SHIFT

#define DMA_HRS_HRS15_SHIFT (15U)

Definition at line 13436 of file MIMXRT1052.h.

◆ DMA_HRS_HRS16

#define DMA_HRS_HRS16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

HRS16 - Hardware Request Status Channel 16 0b0..A hardware service request for channel 16 is not present 0b1..A hardware service request for channel 16 is present

Definition at line 13448 of file MIMXRT1052.h.

◆ DMA_HRS_HRS16_MASK

#define DMA_HRS_HRS16_MASK (0x10000U)

Definition at line 13442 of file MIMXRT1052.h.

◆ DMA_HRS_HRS16_SHIFT

#define DMA_HRS_HRS16_SHIFT (16U)

Definition at line 13443 of file MIMXRT1052.h.

◆ DMA_HRS_HRS17

#define DMA_HRS_HRS17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

HRS17 - Hardware Request Status Channel 17 0b0..A hardware service request for channel 17 is not present 0b1..A hardware service request for channel 17 is present

Definition at line 13455 of file MIMXRT1052.h.

◆ DMA_HRS_HRS17_MASK

#define DMA_HRS_HRS17_MASK (0x20000U)

Definition at line 13449 of file MIMXRT1052.h.

◆ DMA_HRS_HRS17_SHIFT

#define DMA_HRS_HRS17_SHIFT (17U)

Definition at line 13450 of file MIMXRT1052.h.

◆ DMA_HRS_HRS18

#define DMA_HRS_HRS18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

HRS18 - Hardware Request Status Channel 18 0b0..A hardware service request for channel 18 is not present 0b1..A hardware service request for channel 18 is present

Definition at line 13462 of file MIMXRT1052.h.

◆ DMA_HRS_HRS18_MASK

#define DMA_HRS_HRS18_MASK (0x40000U)

Definition at line 13456 of file MIMXRT1052.h.

◆ DMA_HRS_HRS18_SHIFT

#define DMA_HRS_HRS18_SHIFT (18U)

Definition at line 13457 of file MIMXRT1052.h.

◆ DMA_HRS_HRS19

#define DMA_HRS_HRS19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

HRS19 - Hardware Request Status Channel 19 0b0..A hardware service request for channel 19 is not present 0b1..A hardware service request for channel 19 is present

Definition at line 13469 of file MIMXRT1052.h.

◆ DMA_HRS_HRS19_MASK

#define DMA_HRS_HRS19_MASK (0x80000U)

Definition at line 13463 of file MIMXRT1052.h.

◆ DMA_HRS_HRS19_SHIFT

#define DMA_HRS_HRS19_SHIFT (19U)

Definition at line 13464 of file MIMXRT1052.h.

◆ DMA_HRS_HRS1_MASK

#define DMA_HRS_HRS1_MASK (0x2U)

Definition at line 13337 of file MIMXRT1052.h.

◆ DMA_HRS_HRS1_SHIFT

#define DMA_HRS_HRS1_SHIFT (1U)

Definition at line 13338 of file MIMXRT1052.h.

◆ DMA_HRS_HRS2

#define DMA_HRS_HRS2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

Definition at line 13350 of file MIMXRT1052.h.

◆ DMA_HRS_HRS20

#define DMA_HRS_HRS20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

HRS20 - Hardware Request Status Channel 20 0b0..A hardware service request for channel 20 is not present 0b1..A hardware service request for channel 20 is present

Definition at line 13476 of file MIMXRT1052.h.

◆ DMA_HRS_HRS20_MASK

#define DMA_HRS_HRS20_MASK (0x100000U)

Definition at line 13470 of file MIMXRT1052.h.

◆ DMA_HRS_HRS20_SHIFT

#define DMA_HRS_HRS20_SHIFT (20U)

Definition at line 13471 of file MIMXRT1052.h.

◆ DMA_HRS_HRS21

#define DMA_HRS_HRS21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

HRS21 - Hardware Request Status Channel 21 0b0..A hardware service request for channel 21 is not present 0b1..A hardware service request for channel 21 is present

Definition at line 13483 of file MIMXRT1052.h.

◆ DMA_HRS_HRS21_MASK

#define DMA_HRS_HRS21_MASK (0x200000U)

Definition at line 13477 of file MIMXRT1052.h.

◆ DMA_HRS_HRS21_SHIFT

#define DMA_HRS_HRS21_SHIFT (21U)

Definition at line 13478 of file MIMXRT1052.h.

◆ DMA_HRS_HRS22

#define DMA_HRS_HRS22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

HRS22 - Hardware Request Status Channel 22 0b0..A hardware service request for channel 22 is not present 0b1..A hardware service request for channel 22 is present

Definition at line 13490 of file MIMXRT1052.h.

◆ DMA_HRS_HRS22_MASK

#define DMA_HRS_HRS22_MASK (0x400000U)

Definition at line 13484 of file MIMXRT1052.h.

◆ DMA_HRS_HRS22_SHIFT

#define DMA_HRS_HRS22_SHIFT (22U)

Definition at line 13485 of file MIMXRT1052.h.

◆ DMA_HRS_HRS23

#define DMA_HRS_HRS23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

HRS23 - Hardware Request Status Channel 23 0b0..A hardware service request for channel 23 is not present 0b1..A hardware service request for channel 23 is present

Definition at line 13497 of file MIMXRT1052.h.

◆ DMA_HRS_HRS23_MASK

#define DMA_HRS_HRS23_MASK (0x800000U)

Definition at line 13491 of file MIMXRT1052.h.

◆ DMA_HRS_HRS23_SHIFT

#define DMA_HRS_HRS23_SHIFT (23U)

Definition at line 13492 of file MIMXRT1052.h.

◆ DMA_HRS_HRS24

#define DMA_HRS_HRS24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

HRS24 - Hardware Request Status Channel 24 0b0..A hardware service request for channel 24 is not present 0b1..A hardware service request for channel 24 is present

Definition at line 13504 of file MIMXRT1052.h.

◆ DMA_HRS_HRS24_MASK

#define DMA_HRS_HRS24_MASK (0x1000000U)

Definition at line 13498 of file MIMXRT1052.h.

◆ DMA_HRS_HRS24_SHIFT

#define DMA_HRS_HRS24_SHIFT (24U)

Definition at line 13499 of file MIMXRT1052.h.

◆ DMA_HRS_HRS25

#define DMA_HRS_HRS25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

HRS25 - Hardware Request Status Channel 25 0b0..A hardware service request for channel 25 is not present 0b1..A hardware service request for channel 25 is present

Definition at line 13511 of file MIMXRT1052.h.

◆ DMA_HRS_HRS25_MASK

#define DMA_HRS_HRS25_MASK (0x2000000U)

Definition at line 13505 of file MIMXRT1052.h.

◆ DMA_HRS_HRS25_SHIFT

#define DMA_HRS_HRS25_SHIFT (25U)

Definition at line 13506 of file MIMXRT1052.h.

◆ DMA_HRS_HRS26

#define DMA_HRS_HRS26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

HRS26 - Hardware Request Status Channel 26 0b0..A hardware service request for channel 26 is not present 0b1..A hardware service request for channel 26 is present

Definition at line 13518 of file MIMXRT1052.h.

◆ DMA_HRS_HRS26_MASK

#define DMA_HRS_HRS26_MASK (0x4000000U)

Definition at line 13512 of file MIMXRT1052.h.

◆ DMA_HRS_HRS26_SHIFT

#define DMA_HRS_HRS26_SHIFT (26U)

Definition at line 13513 of file MIMXRT1052.h.

◆ DMA_HRS_HRS27

#define DMA_HRS_HRS27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

HRS27 - Hardware Request Status Channel 27 0b0..A hardware service request for channel 27 is not present 0b1..A hardware service request for channel 27 is present

Definition at line 13525 of file MIMXRT1052.h.

◆ DMA_HRS_HRS27_MASK

#define DMA_HRS_HRS27_MASK (0x8000000U)

Definition at line 13519 of file MIMXRT1052.h.

◆ DMA_HRS_HRS27_SHIFT

#define DMA_HRS_HRS27_SHIFT (27U)

Definition at line 13520 of file MIMXRT1052.h.

◆ DMA_HRS_HRS28

#define DMA_HRS_HRS28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

HRS28 - Hardware Request Status Channel 28 0b0..A hardware service request for channel 28 is not present 0b1..A hardware service request for channel 28 is present

Definition at line 13532 of file MIMXRT1052.h.

◆ DMA_HRS_HRS28_MASK

#define DMA_HRS_HRS28_MASK (0x10000000U)

Definition at line 13526 of file MIMXRT1052.h.

◆ DMA_HRS_HRS28_SHIFT

#define DMA_HRS_HRS28_SHIFT (28U)

Definition at line 13527 of file MIMXRT1052.h.

◆ DMA_HRS_HRS29

#define DMA_HRS_HRS29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

HRS29 - Hardware Request Status Channel 29 0b0..A hardware service request for channel 29 is not preset 0b1..A hardware service request for channel 29 is present

Definition at line 13539 of file MIMXRT1052.h.

◆ DMA_HRS_HRS29_MASK

#define DMA_HRS_HRS29_MASK (0x20000000U)

Definition at line 13533 of file MIMXRT1052.h.

◆ DMA_HRS_HRS29_SHIFT

#define DMA_HRS_HRS29_SHIFT (29U)

Definition at line 13534 of file MIMXRT1052.h.

◆ DMA_HRS_HRS2_MASK

#define DMA_HRS_HRS2_MASK (0x4U)

Definition at line 13344 of file MIMXRT1052.h.

◆ DMA_HRS_HRS2_SHIFT

#define DMA_HRS_HRS2_SHIFT (2U)

Definition at line 13345 of file MIMXRT1052.h.

◆ DMA_HRS_HRS3

#define DMA_HRS_HRS3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

Definition at line 13357 of file MIMXRT1052.h.

◆ DMA_HRS_HRS30

#define DMA_HRS_HRS30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

HRS30 - Hardware Request Status Channel 30 0b0..A hardware service request for channel 30 is not present 0b1..A hardware service request for channel 30 is present

Definition at line 13546 of file MIMXRT1052.h.

◆ DMA_HRS_HRS30_MASK

#define DMA_HRS_HRS30_MASK (0x40000000U)

Definition at line 13540 of file MIMXRT1052.h.

◆ DMA_HRS_HRS30_SHIFT

#define DMA_HRS_HRS30_SHIFT (30U)

Definition at line 13541 of file MIMXRT1052.h.

◆ DMA_HRS_HRS31

#define DMA_HRS_HRS31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

HRS31 - Hardware Request Status Channel 31 0b0..A hardware service request for channel 31 is not present 0b1..A hardware service request for channel 31 is present

Definition at line 13553 of file MIMXRT1052.h.

◆ DMA_HRS_HRS31_MASK

#define DMA_HRS_HRS31_MASK (0x80000000U)

Definition at line 13547 of file MIMXRT1052.h.

◆ DMA_HRS_HRS31_SHIFT

#define DMA_HRS_HRS31_SHIFT (31U)

Definition at line 13548 of file MIMXRT1052.h.

◆ DMA_HRS_HRS3_MASK

#define DMA_HRS_HRS3_MASK (0x8U)

Definition at line 13351 of file MIMXRT1052.h.

◆ DMA_HRS_HRS3_SHIFT

#define DMA_HRS_HRS3_SHIFT (3U)

Definition at line 13352 of file MIMXRT1052.h.

◆ DMA_HRS_HRS4

#define DMA_HRS_HRS4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

Definition at line 13364 of file MIMXRT1052.h.

◆ DMA_HRS_HRS4_MASK

#define DMA_HRS_HRS4_MASK (0x10U)

Definition at line 13358 of file MIMXRT1052.h.

◆ DMA_HRS_HRS4_SHIFT

#define DMA_HRS_HRS4_SHIFT (4U)

Definition at line 13359 of file MIMXRT1052.h.

◆ DMA_HRS_HRS5

#define DMA_HRS_HRS5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

Definition at line 13371 of file MIMXRT1052.h.

◆ DMA_HRS_HRS5_MASK

#define DMA_HRS_HRS5_MASK (0x20U)

Definition at line 13365 of file MIMXRT1052.h.

◆ DMA_HRS_HRS5_SHIFT

#define DMA_HRS_HRS5_SHIFT (5U)

Definition at line 13366 of file MIMXRT1052.h.

◆ DMA_HRS_HRS6

#define DMA_HRS_HRS6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

Definition at line 13378 of file MIMXRT1052.h.

◆ DMA_HRS_HRS6_MASK

#define DMA_HRS_HRS6_MASK (0x40U)

Definition at line 13372 of file MIMXRT1052.h.

◆ DMA_HRS_HRS6_SHIFT

#define DMA_HRS_HRS6_SHIFT (6U)

Definition at line 13373 of file MIMXRT1052.h.

◆ DMA_HRS_HRS7

#define DMA_HRS_HRS7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

Definition at line 13385 of file MIMXRT1052.h.

◆ DMA_HRS_HRS7_MASK

#define DMA_HRS_HRS7_MASK (0x80U)

Definition at line 13379 of file MIMXRT1052.h.

◆ DMA_HRS_HRS7_SHIFT

#define DMA_HRS_HRS7_SHIFT (7U)

Definition at line 13380 of file MIMXRT1052.h.

◆ DMA_HRS_HRS8

#define DMA_HRS_HRS8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

Definition at line 13392 of file MIMXRT1052.h.

◆ DMA_HRS_HRS8_MASK

#define DMA_HRS_HRS8_MASK (0x100U)

Definition at line 13386 of file MIMXRT1052.h.

◆ DMA_HRS_HRS8_SHIFT

#define DMA_HRS_HRS8_SHIFT (8U)

Definition at line 13387 of file MIMXRT1052.h.

◆ DMA_HRS_HRS9

#define DMA_HRS_HRS9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

Definition at line 13399 of file MIMXRT1052.h.

◆ DMA_HRS_HRS9_MASK

#define DMA_HRS_HRS9_MASK (0x200U)

Definition at line 13393 of file MIMXRT1052.h.

◆ DMA_HRS_HRS9_SHIFT

#define DMA_HRS_HRS9_SHIFT (9U)

Definition at line 13394 of file MIMXRT1052.h.

◆ DMA_INT_INT0

#define DMA_INT_INT0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12880 of file MIMXRT1052.h.

◆ DMA_INT_INT0_MASK

#define DMA_INT_INT0_MASK (0x1U)

Definition at line 12874 of file MIMXRT1052.h.

◆ DMA_INT_INT0_SHIFT

#define DMA_INT_INT0_SHIFT (0U)

Definition at line 12875 of file MIMXRT1052.h.

◆ DMA_INT_INT1

#define DMA_INT_INT1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12887 of file MIMXRT1052.h.

◆ DMA_INT_INT10

#define DMA_INT_INT10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12950 of file MIMXRT1052.h.

◆ DMA_INT_INT10_MASK

#define DMA_INT_INT10_MASK (0x400U)

Definition at line 12944 of file MIMXRT1052.h.

◆ DMA_INT_INT10_SHIFT

#define DMA_INT_INT10_SHIFT (10U)

Definition at line 12945 of file MIMXRT1052.h.

◆ DMA_INT_INT11

#define DMA_INT_INT11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12957 of file MIMXRT1052.h.

◆ DMA_INT_INT11_MASK

#define DMA_INT_INT11_MASK (0x800U)

Definition at line 12951 of file MIMXRT1052.h.

◆ DMA_INT_INT11_SHIFT

#define DMA_INT_INT11_SHIFT (11U)

Definition at line 12952 of file MIMXRT1052.h.

◆ DMA_INT_INT12

#define DMA_INT_INT12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12964 of file MIMXRT1052.h.

◆ DMA_INT_INT12_MASK

#define DMA_INT_INT12_MASK (0x1000U)

Definition at line 12958 of file MIMXRT1052.h.

◆ DMA_INT_INT12_SHIFT

#define DMA_INT_INT12_SHIFT (12U)

Definition at line 12959 of file MIMXRT1052.h.

◆ DMA_INT_INT13

#define DMA_INT_INT13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12971 of file MIMXRT1052.h.

◆ DMA_INT_INT13_MASK

#define DMA_INT_INT13_MASK (0x2000U)

Definition at line 12965 of file MIMXRT1052.h.

◆ DMA_INT_INT13_SHIFT

#define DMA_INT_INT13_SHIFT (13U)

Definition at line 12966 of file MIMXRT1052.h.

◆ DMA_INT_INT14

#define DMA_INT_INT14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12978 of file MIMXRT1052.h.

◆ DMA_INT_INT14_MASK

#define DMA_INT_INT14_MASK (0x4000U)

Definition at line 12972 of file MIMXRT1052.h.

◆ DMA_INT_INT14_SHIFT

#define DMA_INT_INT14_SHIFT (14U)

Definition at line 12973 of file MIMXRT1052.h.

◆ DMA_INT_INT15

#define DMA_INT_INT15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12985 of file MIMXRT1052.h.

◆ DMA_INT_INT15_MASK

#define DMA_INT_INT15_MASK (0x8000U)

Definition at line 12979 of file MIMXRT1052.h.

◆ DMA_INT_INT15_SHIFT

#define DMA_INT_INT15_SHIFT (15U)

Definition at line 12980 of file MIMXRT1052.h.

◆ DMA_INT_INT16

#define DMA_INT_INT16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

INT16 - Interrupt Request 16 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12992 of file MIMXRT1052.h.

◆ DMA_INT_INT16_MASK

#define DMA_INT_INT16_MASK (0x10000U)

Definition at line 12986 of file MIMXRT1052.h.

◆ DMA_INT_INT16_SHIFT

#define DMA_INT_INT16_SHIFT (16U)

Definition at line 12987 of file MIMXRT1052.h.

◆ DMA_INT_INT17

#define DMA_INT_INT17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

INT17 - Interrupt Request 17 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12999 of file MIMXRT1052.h.

◆ DMA_INT_INT17_MASK

#define DMA_INT_INT17_MASK (0x20000U)

Definition at line 12993 of file MIMXRT1052.h.

◆ DMA_INT_INT17_SHIFT

#define DMA_INT_INT17_SHIFT (17U)

Definition at line 12994 of file MIMXRT1052.h.

◆ DMA_INT_INT18

#define DMA_INT_INT18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

INT18 - Interrupt Request 18 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13006 of file MIMXRT1052.h.

◆ DMA_INT_INT18_MASK

#define DMA_INT_INT18_MASK (0x40000U)

Definition at line 13000 of file MIMXRT1052.h.

◆ DMA_INT_INT18_SHIFT

#define DMA_INT_INT18_SHIFT (18U)

Definition at line 13001 of file MIMXRT1052.h.

◆ DMA_INT_INT19

#define DMA_INT_INT19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

INT19 - Interrupt Request 19 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13013 of file MIMXRT1052.h.

◆ DMA_INT_INT19_MASK

#define DMA_INT_INT19_MASK (0x80000U)

Definition at line 13007 of file MIMXRT1052.h.

◆ DMA_INT_INT19_SHIFT

#define DMA_INT_INT19_SHIFT (19U)

Definition at line 13008 of file MIMXRT1052.h.

◆ DMA_INT_INT1_MASK

#define DMA_INT_INT1_MASK (0x2U)

Definition at line 12881 of file MIMXRT1052.h.

◆ DMA_INT_INT1_SHIFT

#define DMA_INT_INT1_SHIFT (1U)

Definition at line 12882 of file MIMXRT1052.h.

◆ DMA_INT_INT2

#define DMA_INT_INT2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12894 of file MIMXRT1052.h.

◆ DMA_INT_INT20

#define DMA_INT_INT20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

INT20 - Interrupt Request 20 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13020 of file MIMXRT1052.h.

◆ DMA_INT_INT20_MASK

#define DMA_INT_INT20_MASK (0x100000U)

Definition at line 13014 of file MIMXRT1052.h.

◆ DMA_INT_INT20_SHIFT

#define DMA_INT_INT20_SHIFT (20U)

Definition at line 13015 of file MIMXRT1052.h.

◆ DMA_INT_INT21

#define DMA_INT_INT21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

INT21 - Interrupt Request 21 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13027 of file MIMXRT1052.h.

◆ DMA_INT_INT21_MASK

#define DMA_INT_INT21_MASK (0x200000U)

Definition at line 13021 of file MIMXRT1052.h.

◆ DMA_INT_INT21_SHIFT

#define DMA_INT_INT21_SHIFT (21U)

Definition at line 13022 of file MIMXRT1052.h.

◆ DMA_INT_INT22

#define DMA_INT_INT22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

INT22 - Interrupt Request 22 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13034 of file MIMXRT1052.h.

◆ DMA_INT_INT22_MASK

#define DMA_INT_INT22_MASK (0x400000U)

Definition at line 13028 of file MIMXRT1052.h.

◆ DMA_INT_INT22_SHIFT

#define DMA_INT_INT22_SHIFT (22U)

Definition at line 13029 of file MIMXRT1052.h.

◆ DMA_INT_INT23

#define DMA_INT_INT23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

INT23 - Interrupt Request 23 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13041 of file MIMXRT1052.h.

◆ DMA_INT_INT23_MASK

#define DMA_INT_INT23_MASK (0x800000U)

Definition at line 13035 of file MIMXRT1052.h.

◆ DMA_INT_INT23_SHIFT

#define DMA_INT_INT23_SHIFT (23U)

Definition at line 13036 of file MIMXRT1052.h.

◆ DMA_INT_INT24

#define DMA_INT_INT24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

INT24 - Interrupt Request 24 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13048 of file MIMXRT1052.h.

◆ DMA_INT_INT24_MASK

#define DMA_INT_INT24_MASK (0x1000000U)

Definition at line 13042 of file MIMXRT1052.h.

◆ DMA_INT_INT24_SHIFT

#define DMA_INT_INT24_SHIFT (24U)

Definition at line 13043 of file MIMXRT1052.h.

◆ DMA_INT_INT25

#define DMA_INT_INT25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

INT25 - Interrupt Request 25 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13055 of file MIMXRT1052.h.

◆ DMA_INT_INT25_MASK

#define DMA_INT_INT25_MASK (0x2000000U)

Definition at line 13049 of file MIMXRT1052.h.

◆ DMA_INT_INT25_SHIFT

#define DMA_INT_INT25_SHIFT (25U)

Definition at line 13050 of file MIMXRT1052.h.

◆ DMA_INT_INT26

#define DMA_INT_INT26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

INT26 - Interrupt Request 26 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13062 of file MIMXRT1052.h.

◆ DMA_INT_INT26_MASK

#define DMA_INT_INT26_MASK (0x4000000U)

Definition at line 13056 of file MIMXRT1052.h.

◆ DMA_INT_INT26_SHIFT

#define DMA_INT_INT26_SHIFT (26U)

Definition at line 13057 of file MIMXRT1052.h.

◆ DMA_INT_INT27

#define DMA_INT_INT27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

INT27 - Interrupt Request 27 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13069 of file MIMXRT1052.h.

◆ DMA_INT_INT27_MASK

#define DMA_INT_INT27_MASK (0x8000000U)

Definition at line 13063 of file MIMXRT1052.h.

◆ DMA_INT_INT27_SHIFT

#define DMA_INT_INT27_SHIFT (27U)

Definition at line 13064 of file MIMXRT1052.h.

◆ DMA_INT_INT28

#define DMA_INT_INT28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

INT28 - Interrupt Request 28 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13076 of file MIMXRT1052.h.

◆ DMA_INT_INT28_MASK

#define DMA_INT_INT28_MASK (0x10000000U)

Definition at line 13070 of file MIMXRT1052.h.

◆ DMA_INT_INT28_SHIFT

#define DMA_INT_INT28_SHIFT (28U)

Definition at line 13071 of file MIMXRT1052.h.

◆ DMA_INT_INT29

#define DMA_INT_INT29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

INT29 - Interrupt Request 29 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13083 of file MIMXRT1052.h.

◆ DMA_INT_INT29_MASK

#define DMA_INT_INT29_MASK (0x20000000U)

Definition at line 13077 of file MIMXRT1052.h.

◆ DMA_INT_INT29_SHIFT

#define DMA_INT_INT29_SHIFT (29U)

Definition at line 13078 of file MIMXRT1052.h.

◆ DMA_INT_INT2_MASK

#define DMA_INT_INT2_MASK (0x4U)

Definition at line 12888 of file MIMXRT1052.h.

◆ DMA_INT_INT2_SHIFT

#define DMA_INT_INT2_SHIFT (2U)

Definition at line 12889 of file MIMXRT1052.h.

◆ DMA_INT_INT3

#define DMA_INT_INT3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12901 of file MIMXRT1052.h.

◆ DMA_INT_INT30

#define DMA_INT_INT30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

INT30 - Interrupt Request 30 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13090 of file MIMXRT1052.h.

◆ DMA_INT_INT30_MASK

#define DMA_INT_INT30_MASK (0x40000000U)

Definition at line 13084 of file MIMXRT1052.h.

◆ DMA_INT_INT30_SHIFT

#define DMA_INT_INT30_SHIFT (30U)

Definition at line 13085 of file MIMXRT1052.h.

◆ DMA_INT_INT31

#define DMA_INT_INT31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

INT31 - Interrupt Request 31 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 13097 of file MIMXRT1052.h.

◆ DMA_INT_INT31_MASK

#define DMA_INT_INT31_MASK (0x80000000U)

Definition at line 13091 of file MIMXRT1052.h.

◆ DMA_INT_INT31_SHIFT

#define DMA_INT_INT31_SHIFT (31U)

Definition at line 13092 of file MIMXRT1052.h.

◆ DMA_INT_INT3_MASK

#define DMA_INT_INT3_MASK (0x8U)

Definition at line 12895 of file MIMXRT1052.h.

◆ DMA_INT_INT3_SHIFT

#define DMA_INT_INT3_SHIFT (3U)

Definition at line 12896 of file MIMXRT1052.h.

◆ DMA_INT_INT4

#define DMA_INT_INT4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12908 of file MIMXRT1052.h.

◆ DMA_INT_INT4_MASK

#define DMA_INT_INT4_MASK (0x10U)

Definition at line 12902 of file MIMXRT1052.h.

◆ DMA_INT_INT4_SHIFT

#define DMA_INT_INT4_SHIFT (4U)

Definition at line 12903 of file MIMXRT1052.h.

◆ DMA_INT_INT5

#define DMA_INT_INT5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12915 of file MIMXRT1052.h.

◆ DMA_INT_INT5_MASK

#define DMA_INT_INT5_MASK (0x20U)

Definition at line 12909 of file MIMXRT1052.h.

◆ DMA_INT_INT5_SHIFT

#define DMA_INT_INT5_SHIFT (5U)

Definition at line 12910 of file MIMXRT1052.h.

◆ DMA_INT_INT6

#define DMA_INT_INT6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12922 of file MIMXRT1052.h.

◆ DMA_INT_INT6_MASK

#define DMA_INT_INT6_MASK (0x40U)

Definition at line 12916 of file MIMXRT1052.h.

◆ DMA_INT_INT6_SHIFT

#define DMA_INT_INT6_SHIFT (6U)

Definition at line 12917 of file MIMXRT1052.h.

◆ DMA_INT_INT7

#define DMA_INT_INT7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12929 of file MIMXRT1052.h.

◆ DMA_INT_INT7_MASK

#define DMA_INT_INT7_MASK (0x80U)

Definition at line 12923 of file MIMXRT1052.h.

◆ DMA_INT_INT7_SHIFT

#define DMA_INT_INT7_SHIFT (7U)

Definition at line 12924 of file MIMXRT1052.h.

◆ DMA_INT_INT8

#define DMA_INT_INT8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12936 of file MIMXRT1052.h.

◆ DMA_INT_INT8_MASK

#define DMA_INT_INT8_MASK (0x100U)

Definition at line 12930 of file MIMXRT1052.h.

◆ DMA_INT_INT8_SHIFT

#define DMA_INT_INT8_SHIFT (8U)

Definition at line 12931 of file MIMXRT1052.h.

◆ DMA_INT_INT9

#define DMA_INT_INT9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 12943 of file MIMXRT1052.h.

◆ DMA_INT_INT9_MASK

#define DMA_INT_INT9_MASK (0x200U)

Definition at line 12937 of file MIMXRT1052.h.

◆ DMA_INT_INT9_SHIFT

#define DMA_INT_INT9_SHIFT (9U)

Definition at line 12938 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLNO_COUNT

#define DMA_NBYTES_MLNO_COUNT (32U)

Definition at line 14758 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLNO_NBYTES

#define DMA_NBYTES_MLNO_NBYTES ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

Definition at line 14754 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLNO_NBYTES_MASK

#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)

Definition at line 14750 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLNO_NBYTES_SHIFT

#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)

Definition at line 14751 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_COUNT

#define DMA_NBYTES_MLOFFNO_COUNT (32U)

Definition at line 14784 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_DMLOE

#define DMA_NBYTES_MLOFFNO_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

Definition at line 14773 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_DMLOE_MASK

#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)

Definition at line 14767 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_DMLOE_SHIFT

#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)

Definition at line 14768 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_NBYTES

#define DMA_NBYTES_MLOFFNO_NBYTES ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

Definition at line 14766 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_NBYTES_MASK

#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)

Definition at line 14762 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_NBYTES_SHIFT

#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)

Definition at line 14763 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_SMLOE

#define DMA_NBYTES_MLOFFNO_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

Definition at line 14780 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_SMLOE_MASK

#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)

Definition at line 14774 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFNO_SMLOE_SHIFT

#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)

Definition at line 14775 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_COUNT

#define DMA_NBYTES_MLOFFYES_COUNT (32U)

Definition at line 14816 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_DMLOE

#define DMA_NBYTES_MLOFFYES_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

Definition at line 14805 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_DMLOE_MASK

#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)

Definition at line 14799 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_DMLOE_SHIFT

#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)

Definition at line 14800 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_MLOFF

#define DMA_NBYTES_MLOFFYES_MLOFF ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

MLOFF - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

Definition at line 14798 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_MLOFF_MASK

#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)

Definition at line 14793 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_MLOFF_SHIFT

#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)

Definition at line 14794 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_NBYTES

#define DMA_NBYTES_MLOFFYES_NBYTES ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

Definition at line 14792 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_NBYTES_MASK

#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)

Definition at line 14788 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_NBYTES_SHIFT

#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)

Definition at line 14789 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_SMLOE

#define DMA_NBYTES_MLOFFYES_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

Definition at line 14812 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_SMLOE_MASK

#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)

Definition at line 14806 of file MIMXRT1052.h.

◆ DMA_NBYTES_MLOFFYES_SMLOE_SHIFT

#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)

Definition at line 14807 of file MIMXRT1052.h.

◆ DMA_SADDR_COUNT

#define DMA_SADDR_COUNT (32U)

Definition at line 14690 of file MIMXRT1052.h.

◆ DMA_SADDR_SADDR

#define DMA_SADDR_SADDR ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

SADDR - Source Address

Definition at line 14686 of file MIMXRT1052.h.

◆ DMA_SADDR_SADDR_MASK

#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)

Definition at line 14682 of file MIMXRT1052.h.

◆ DMA_SADDR_SADDR_SHIFT

#define DMA_SADDR_SADDR_SHIFT (0U)

Definition at line 14683 of file MIMXRT1052.h.

◆ DMA_SEEI_NOP

#define DMA_SEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 12731 of file MIMXRT1052.h.

◆ DMA_SEEI_NOP_MASK

#define DMA_SEEI_NOP_MASK (0x80U)

Definition at line 12725 of file MIMXRT1052.h.

◆ DMA_SEEI_NOP_SHIFT

#define DMA_SEEI_NOP_SHIFT (7U)

Definition at line 12726 of file MIMXRT1052.h.

◆ DMA_SEEI_SAEE

#define DMA_SEEI_SAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Sets All Enable Error Interrupts 0b0..Set only the EEI bit specified in the SEEI field. 0b1..Sets all bits in EEI

Definition at line 12724 of file MIMXRT1052.h.

◆ DMA_SEEI_SAEE_MASK

#define DMA_SEEI_SAEE_MASK (0x40U)

Definition at line 12718 of file MIMXRT1052.h.

◆ DMA_SEEI_SAEE_SHIFT

#define DMA_SEEI_SAEE_SHIFT (6U)

Definition at line 12719 of file MIMXRT1052.h.

◆ DMA_SEEI_SEEI

#define DMA_SEEI_SEEI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

SEEI - Set Enable Error Interrupt

Definition at line 12717 of file MIMXRT1052.h.

◆ DMA_SEEI_SEEI_MASK

#define DMA_SEEI_SEEI_MASK (0x1FU)

Definition at line 12713 of file MIMXRT1052.h.

◆ DMA_SEEI_SEEI_SHIFT

#define DMA_SEEI_SEEI_SHIFT (0U)

Definition at line 12714 of file MIMXRT1052.h.

◆ DMA_SERQ_NOP

#define DMA_SERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 12777 of file MIMXRT1052.h.

◆ DMA_SERQ_NOP_MASK

#define DMA_SERQ_NOP_MASK (0x80U)

Definition at line 12771 of file MIMXRT1052.h.

◆ DMA_SERQ_NOP_SHIFT

#define DMA_SERQ_NOP_SHIFT (7U)

Definition at line 12772 of file MIMXRT1052.h.

◆ DMA_SERQ_SAER

#define DMA_SERQ_SAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Set only the ERQ bit specified in the SERQ field 0b1..Set all bits in ERQ

Definition at line 12770 of file MIMXRT1052.h.

◆ DMA_SERQ_SAER_MASK

#define DMA_SERQ_SAER_MASK (0x40U)

Definition at line 12764 of file MIMXRT1052.h.

◆ DMA_SERQ_SAER_SHIFT

#define DMA_SERQ_SAER_SHIFT (6U)

Definition at line 12765 of file MIMXRT1052.h.

◆ DMA_SERQ_SERQ

#define DMA_SERQ_SERQ ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

SERQ - Set Enable Request

Definition at line 12763 of file MIMXRT1052.h.

◆ DMA_SERQ_SERQ_MASK

#define DMA_SERQ_SERQ_MASK (0x1FU)

Definition at line 12759 of file MIMXRT1052.h.

◆ DMA_SERQ_SERQ_SHIFT

#define DMA_SERQ_SERQ_SHIFT (0U)

Definition at line 12760 of file MIMXRT1052.h.

◆ DMA_SLAST_COUNT

#define DMA_SLAST_COUNT (32U)

Definition at line 14828 of file MIMXRT1052.h.

◆ DMA_SLAST_SLAST

#define DMA_SLAST_SLAST ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

SLAST - Last Source Address Adjustment

Definition at line 14824 of file MIMXRT1052.h.

◆ DMA_SLAST_SLAST_MASK

#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)

Definition at line 14820 of file MIMXRT1052.h.

◆ DMA_SLAST_SLAST_SHIFT

#define DMA_SLAST_SLAST_SHIFT (0U)

Definition at line 14821 of file MIMXRT1052.h.

◆ DMA_SOFF_COUNT

#define DMA_SOFF_COUNT (32U)

Definition at line 14702 of file MIMXRT1052.h.

◆ DMA_SOFF_SOFF

#define DMA_SOFF_SOFF ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

SOFF - Source address signed offset

Definition at line 14698 of file MIMXRT1052.h.

◆ DMA_SOFF_SOFF_MASK

#define DMA_SOFF_SOFF_MASK (0xFFFFU)

Definition at line 14694 of file MIMXRT1052.h.

◆ DMA_SOFF_SOFF_SHIFT

#define DMA_SOFF_SOFF_SHIFT (0U)

Definition at line 14695 of file MIMXRT1052.h.

◆ DMA_SSRT_NOP

#define DMA_SSRT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 12823 of file MIMXRT1052.h.

◆ DMA_SSRT_NOP_MASK

#define DMA_SSRT_NOP_MASK (0x80U)

Definition at line 12817 of file MIMXRT1052.h.

◆ DMA_SSRT_NOP_SHIFT

#define DMA_SSRT_NOP_SHIFT (7U)

Definition at line 12818 of file MIMXRT1052.h.

◆ DMA_SSRT_SAST

#define DMA_SSRT_SAST ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START Bits (activates all channels) 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field 0b1..Set all bits in TCDn_CSR[START]

Definition at line 12816 of file MIMXRT1052.h.

◆ DMA_SSRT_SAST_MASK

#define DMA_SSRT_SAST_MASK (0x40U)

Definition at line 12810 of file MIMXRT1052.h.

◆ DMA_SSRT_SAST_SHIFT

#define DMA_SSRT_SAST_SHIFT (6U)

Definition at line 12811 of file MIMXRT1052.h.

◆ DMA_SSRT_SSRT

#define DMA_SSRT_SSRT ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

SSRT - Set START Bit

Definition at line 12809 of file MIMXRT1052.h.

◆ DMA_SSRT_SSRT_MASK

#define DMA_SSRT_SSRT_MASK (0x1FU)

Definition at line 12805 of file MIMXRT1052.h.

◆ DMA_SSRT_SSRT_SHIFT

#define DMA_SSRT_SSRT_SHIFT (0U)

Definition at line 12806 of file MIMXRT1052.h.

◆ LPSPI_CR_DBGEN

#define LPSPI_CR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..Module is disabled in debug mode 0b1..Module is enabled in debug mode

Definition at line 26246 of file MIMXRT1052.h.

◆ LPSPI_CR_DBGEN_MASK

#define LPSPI_CR_DBGEN_MASK (0x8U)

Definition at line 26240 of file MIMXRT1052.h.

◆ LPSPI_CR_DBGEN_SHIFT

#define LPSPI_CR_DBGEN_SHIFT (3U)

Definition at line 26241 of file MIMXRT1052.h.

◆ LPSPI_CR_DOZEN

#define LPSPI_CR_DOZEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

DOZEN - Doze mode enable 0b0..Module is enabled in Doze mode 0b1..Module is disabled in Doze mode

Definition at line 26239 of file MIMXRT1052.h.

◆ LPSPI_CR_DOZEN_MASK

#define LPSPI_CR_DOZEN_MASK (0x4U)

Definition at line 26233 of file MIMXRT1052.h.

◆ LPSPI_CR_DOZEN_SHIFT

#define LPSPI_CR_DOZEN_SHIFT (2U)

Definition at line 26234 of file MIMXRT1052.h.

◆ LPSPI_CR_MEN

#define LPSPI_CR_MEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

MEN - Module Enable 0b0..Module is disabled 0b1..Module is enabled

Definition at line 26225 of file MIMXRT1052.h.

◆ LPSPI_CR_MEN_MASK

#define LPSPI_CR_MEN_MASK (0x1U)

Definition at line 26219 of file MIMXRT1052.h.

◆ LPSPI_CR_MEN_SHIFT

#define LPSPI_CR_MEN_SHIFT (0U)

Definition at line 26220 of file MIMXRT1052.h.

◆ LPSPI_CR_RRF

#define LPSPI_CR_RRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive FIFO is reset

Definition at line 26260 of file MIMXRT1052.h.

◆ LPSPI_CR_RRF_MASK

#define LPSPI_CR_RRF_MASK (0x200U)

Definition at line 26254 of file MIMXRT1052.h.

◆ LPSPI_CR_RRF_SHIFT

#define LPSPI_CR_RRF_SHIFT (9U)

Definition at line 26255 of file MIMXRT1052.h.

◆ LPSPI_CR_RST

#define LPSPI_CR_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

RST - Software Reset 0b0..Module is not reset 0b1..Module is reset

Definition at line 26232 of file MIMXRT1052.h.

◆ LPSPI_CR_RST_MASK

#define LPSPI_CR_RST_MASK (0x2U)

Definition at line 26226 of file MIMXRT1052.h.

◆ LPSPI_CR_RST_SHIFT

#define LPSPI_CR_RST_SHIFT (1U)

Definition at line 26227 of file MIMXRT1052.h.

◆ LPSPI_CR_RTF

#define LPSPI_CR_RTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit FIFO is reset

Definition at line 26253 of file MIMXRT1052.h.

◆ LPSPI_CR_RTF_MASK

#define LPSPI_CR_RTF_MASK (0x100U)

Definition at line 26247 of file MIMXRT1052.h.

◆ LPSPI_CR_RTF_SHIFT

#define LPSPI_CR_RTF_SHIFT (8U)

Definition at line 26248 of file MIMXRT1052.h.

Macros

CR - Control Register

ES - Error Status Register

ERQ - Enable Request Register

EEI - Enable Error Interrupt Register

CEEI - Clear Enable Error Interrupt Register

SEEI - Set Enable Error Interrupt Register

CERQ - Clear Enable Request Register

SERQ - Set Enable Request Register

CDNE - Clear DONE Status Bit Register

SSRT - Set START Bit Register

CERR - Clear Error Register

CINT - Clear Interrupt Request Register

INT - Interrupt Request Register

ERR - Error Register

HRS - Hardware Request Status Register

EARS - Enable Asynchronous Request in Stop Register

DCHPRI3 - Channel n Priority Register

DCHPRI2 - Channel n Priority Register

DCHPRI1 - Channel n Priority Register

DCHPRI0 - Channel n Priority Register

DCHPRI7 - Channel n Priority Register

DCHPRI6 - Channel n Priority Register

DCHPRI5 - Channel n Priority Register

DCHPRI4 - Channel n Priority Register

DCHPRI11 - Channel n Priority Register

DCHPRI10 - Channel n Priority Register

DCHPRI9 - Channel n Priority Register

DCHPRI8 - Channel n Priority Register

DCHPRI15 - Channel n Priority Register

DCHPRI14 - Channel n Priority Register

DCHPRI13 - Channel n Priority Register

DCHPRI12 - Channel n Priority Register

DCHPRI19 - Channel n Priority Register

DCHPRI18 - Channel n Priority Register

DCHPRI17 - Channel n Priority Register

DCHPRI16 - Channel n Priority Register

DCHPRI23 - Channel n Priority Register

DCHPRI22 - Channel n Priority Register

DCHPRI21 - Channel n Priority Register

DCHPRI20 - Channel n Priority Register

DCHPRI27 - Channel n Priority Register

DCHPRI26 - Channel n Priority Register

DCHPRI25 - Channel n Priority Register

DCHPRI24 - Channel n Priority Register

DCHPRI31 - Channel n Priority Register

DCHPRI30 - Channel n Priority Register

DCHPRI29 - Channel n Priority Register

DCHPRI28 - Channel n Priority Register

SADDR - TCD Source Address

SOFF - TCD Signed Source Address Offset

ATTR - TCD Transfer Attributes

NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)

NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)

NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)

SLAST - TCD Last Source Address Adjustment

DADDR - TCD Destination Address

DOFF - TCD Signed Destination Address Offset

CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address

CSR - TCD Control and Status

BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

Detailed Description

Macro Definition Documentation

◆ DMA_ATTR_COUNT

◆ DMA_ATTR_DMOD

◆ DMA_ATTR_DMOD_MASK

◆ DMA_ATTR_DMOD_SHIFT

◆ DMA_ATTR_DSIZE

◆ DMA_ATTR_DSIZE_MASK

◆ DMA_ATTR_DSIZE_SHIFT

◆ DMA_ATTR_SMOD

◆ DMA_ATTR_SMOD_MASK

◆ DMA_ATTR_SMOD_SHIFT

◆ DMA_ATTR_SSIZE

◆ DMA_ATTR_SSIZE_MASK

◆ DMA_ATTR_SSIZE_SHIFT

◆ DMA_BITER_ELINKNO_BITER