Macros
CAN Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » CAN Peripheral Access Layer
Collaboration diagram for CAN Register Masks:

Macros

#define CAN_CS_COUNT   (64U)
 
#define CAN_ID_COUNT   (64U)
 
#define CAN_RXIMR_COUNT   (64U)
 
#define CAN_WORD0_COUNT   (64U)
 
#define CAN_WORD1_COUNT   (64U)
 

MCR - Module Configuration Register

#define CAN_MCR_MAXMB_MASK   (0x7FU)
 
#define CAN_MCR_MAXMB_SHIFT   (0U)
 
#define CAN_MCR_MAXMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
 
#define CAN_MCR_IDAM_MASK   (0x300U)
 
#define CAN_MCR_IDAM_SHIFT   (8U)
 
#define CAN_MCR_IDAM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
 
#define CAN_MCR_AEN_MASK   (0x1000U)
 
#define CAN_MCR_AEN_SHIFT   (12U)
 
#define CAN_MCR_AEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
 
#define CAN_MCR_LPRIOEN_MASK   (0x2000U)
 
#define CAN_MCR_LPRIOEN_SHIFT   (13U)
 
#define CAN_MCR_LPRIOEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
 
#define CAN_MCR_IRMQ_MASK   (0x10000U)
 
#define CAN_MCR_IRMQ_SHIFT   (16U)
 
#define CAN_MCR_IRMQ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
 
#define CAN_MCR_SRXDIS_MASK   (0x20000U)
 
#define CAN_MCR_SRXDIS_SHIFT   (17U)
 
#define CAN_MCR_SRXDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
 
#define CAN_MCR_WAKSRC_MASK   (0x80000U)
 
#define CAN_MCR_WAKSRC_SHIFT   (19U)
 
#define CAN_MCR_WAKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
 
#define CAN_MCR_LPMACK_MASK   (0x100000U)
 
#define CAN_MCR_LPMACK_SHIFT   (20U)
 
#define CAN_MCR_LPMACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
 
#define CAN_MCR_WRNEN_MASK   (0x200000U)
 
#define CAN_MCR_WRNEN_SHIFT   (21U)
 
#define CAN_MCR_WRNEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
 
#define CAN_MCR_SLFWAK_MASK   (0x400000U)
 
#define CAN_MCR_SLFWAK_SHIFT   (22U)
 
#define CAN_MCR_SLFWAK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
 
#define CAN_MCR_SUPV_MASK   (0x800000U)
 
#define CAN_MCR_SUPV_SHIFT   (23U)
 
#define CAN_MCR_SUPV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
 
#define CAN_MCR_FRZACK_MASK   (0x1000000U)
 
#define CAN_MCR_FRZACK_SHIFT   (24U)
 
#define CAN_MCR_FRZACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
 
#define CAN_MCR_SOFTRST_MASK   (0x2000000U)
 
#define CAN_MCR_SOFTRST_SHIFT   (25U)
 
#define CAN_MCR_SOFTRST(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
 
#define CAN_MCR_WAKMSK_MASK   (0x4000000U)
 
#define CAN_MCR_WAKMSK_SHIFT   (26U)
 
#define CAN_MCR_WAKMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
 
#define CAN_MCR_NOTRDY_MASK   (0x8000000U)
 
#define CAN_MCR_NOTRDY_SHIFT   (27U)
 
#define CAN_MCR_NOTRDY(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
 
#define CAN_MCR_HALT_MASK   (0x10000000U)
 
#define CAN_MCR_HALT_SHIFT   (28U)
 
#define CAN_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
 
#define CAN_MCR_RFEN_MASK   (0x20000000U)
 
#define CAN_MCR_RFEN_SHIFT   (29U)
 
#define CAN_MCR_RFEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
 
#define CAN_MCR_FRZ_MASK   (0x40000000U)
 
#define CAN_MCR_FRZ_SHIFT   (30U)
 
#define CAN_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
 
#define CAN_MCR_MDIS_MASK   (0x80000000U)
 
#define CAN_MCR_MDIS_SHIFT   (31U)
 
#define CAN_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
 

CTRL1 - Control 1 Register

#define CAN_CTRL1_PROPSEG_MASK   (0x7U)
 
#define CAN_CTRL1_PROPSEG_SHIFT   (0U)
 
#define CAN_CTRL1_PROPSEG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
 
#define CAN_CTRL1_LOM_MASK   (0x8U)
 
#define CAN_CTRL1_LOM_SHIFT   (3U)
 
#define CAN_CTRL1_LOM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
 
#define CAN_CTRL1_LBUF_MASK   (0x10U)
 
#define CAN_CTRL1_LBUF_SHIFT   (4U)
 
#define CAN_CTRL1_LBUF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
 
#define CAN_CTRL1_TSYN_MASK   (0x20U)
 
#define CAN_CTRL1_TSYN_SHIFT   (5U)
 
#define CAN_CTRL1_TSYN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
 
#define CAN_CTRL1_BOFFREC_MASK   (0x40U)
 
#define CAN_CTRL1_BOFFREC_SHIFT   (6U)
 
#define CAN_CTRL1_BOFFREC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
 
#define CAN_CTRL1_SMP_MASK   (0x80U)
 
#define CAN_CTRL1_SMP_SHIFT   (7U)
 
#define CAN_CTRL1_SMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
 
#define CAN_CTRL1_RWRNMSK_MASK   (0x400U)
 
#define CAN_CTRL1_RWRNMSK_SHIFT   (10U)
 
#define CAN_CTRL1_RWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
 
#define CAN_CTRL1_TWRNMSK_MASK   (0x800U)
 
#define CAN_CTRL1_TWRNMSK_SHIFT   (11U)
 
#define CAN_CTRL1_TWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
 
#define CAN_CTRL1_LPB_MASK   (0x1000U)
 
#define CAN_CTRL1_LPB_SHIFT   (12U)
 
#define CAN_CTRL1_LPB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
 
#define CAN_CTRL1_ERRMSK_MASK   (0x4000U)
 
#define CAN_CTRL1_ERRMSK_SHIFT   (14U)
 
#define CAN_CTRL1_ERRMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
 
#define CAN_CTRL1_BOFFMSK_MASK   (0x8000U)
 
#define CAN_CTRL1_BOFFMSK_SHIFT   (15U)
 
#define CAN_CTRL1_BOFFMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
 
#define CAN_CTRL1_PSEG2_MASK   (0x70000U)
 
#define CAN_CTRL1_PSEG2_SHIFT   (16U)
 
#define CAN_CTRL1_PSEG2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
 
#define CAN_CTRL1_PSEG1_MASK   (0x380000U)
 
#define CAN_CTRL1_PSEG1_SHIFT   (19U)
 
#define CAN_CTRL1_PSEG1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
 
#define CAN_CTRL1_RJW_MASK   (0xC00000U)
 
#define CAN_CTRL1_RJW_SHIFT   (22U)
 
#define CAN_CTRL1_RJW(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
 
#define CAN_CTRL1_PRESDIV_MASK   (0xFF000000U)
 
#define CAN_CTRL1_PRESDIV_SHIFT   (24U)
 
#define CAN_CTRL1_PRESDIV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
 

TIMER - Free Running Timer Register

#define CAN_TIMER_TIMER_MASK   (0xFFFFU)
 
#define CAN_TIMER_TIMER_SHIFT   (0U)
 
#define CAN_TIMER_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
 

RXMGMASK - Rx Mailboxes Global Mask Register

#define CAN_RXMGMASK_MG_MASK   (0xFFFFFFFFU)
 
#define CAN_RXMGMASK_MG_SHIFT   (0U)
 
#define CAN_RXMGMASK_MG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
 

RX14MASK - Rx Buffer 14 Mask Register

#define CAN_RX14MASK_RX14M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX14MASK_RX14M_SHIFT   (0U)
 
#define CAN_RX14MASK_RX14M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
 

RX15MASK - Rx Buffer 15 Mask Register

#define CAN_RX15MASK_RX15M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX15MASK_RX15M_SHIFT   (0U)
 
#define CAN_RX15MASK_RX15M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
 

ECR - Error Counter Register

#define CAN_ECR_TX_ERR_COUNTER_MASK   (0xFFU)
 
#define CAN_ECR_TX_ERR_COUNTER_SHIFT   (0U)
 
#define CAN_ECR_TX_ERR_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
 
#define CAN_ECR_RX_ERR_COUNTER_MASK   (0xFF00U)
 
#define CAN_ECR_RX_ERR_COUNTER_SHIFT   (8U)
 
#define CAN_ECR_RX_ERR_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
 

ESR1 - Error and Status 1 Register

#define CAN_ESR1_WAKINT_MASK   (0x1U)
 
#define CAN_ESR1_WAKINT_SHIFT   (0U)
 
#define CAN_ESR1_WAKINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
 
#define CAN_ESR1_ERRINT_MASK   (0x2U)
 
#define CAN_ESR1_ERRINT_SHIFT   (1U)
 
#define CAN_ESR1_ERRINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
 
#define CAN_ESR1_BOFFINT_MASK   (0x4U)
 
#define CAN_ESR1_BOFFINT_SHIFT   (2U)
 
#define CAN_ESR1_BOFFINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
 
#define CAN_ESR1_RX_MASK   (0x8U)
 
#define CAN_ESR1_RX_SHIFT   (3U)
 
#define CAN_ESR1_RX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
 
#define CAN_ESR1_FLTCONF_MASK   (0x30U)
 
#define CAN_ESR1_FLTCONF_SHIFT   (4U)
 
#define CAN_ESR1_FLTCONF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
 
#define CAN_ESR1_TX_MASK   (0x40U)
 
#define CAN_ESR1_TX_SHIFT   (6U)
 
#define CAN_ESR1_TX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
 
#define CAN_ESR1_IDLE_MASK   (0x80U)
 
#define CAN_ESR1_IDLE_SHIFT   (7U)
 
#define CAN_ESR1_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
 
#define CAN_ESR1_RXWRN_MASK   (0x100U)
 
#define CAN_ESR1_RXWRN_SHIFT   (8U)
 
#define CAN_ESR1_RXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
 
#define CAN_ESR1_TXWRN_MASK   (0x200U)
 
#define CAN_ESR1_TXWRN_SHIFT   (9U)
 
#define CAN_ESR1_TXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
 
#define CAN_ESR1_STFERR_MASK   (0x400U)
 
#define CAN_ESR1_STFERR_SHIFT   (10U)
 
#define CAN_ESR1_STFERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
 
#define CAN_ESR1_FRMERR_MASK   (0x800U)
 
#define CAN_ESR1_FRMERR_SHIFT   (11U)
 
#define CAN_ESR1_FRMERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
 
#define CAN_ESR1_CRCERR_MASK   (0x1000U)
 
#define CAN_ESR1_CRCERR_SHIFT   (12U)
 
#define CAN_ESR1_CRCERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
 
#define CAN_ESR1_ACKERR_MASK   (0x2000U)
 
#define CAN_ESR1_ACKERR_SHIFT   (13U)
 
#define CAN_ESR1_ACKERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
 
#define CAN_ESR1_BIT0ERR_MASK   (0x4000U)
 
#define CAN_ESR1_BIT0ERR_SHIFT   (14U)
 
#define CAN_ESR1_BIT0ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
 
#define CAN_ESR1_BIT1ERR_MASK   (0x8000U)
 
#define CAN_ESR1_BIT1ERR_SHIFT   (15U)
 
#define CAN_ESR1_BIT1ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
 
#define CAN_ESR1_RWRNINT_MASK   (0x10000U)
 
#define CAN_ESR1_RWRNINT_SHIFT   (16U)
 
#define CAN_ESR1_RWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
 
#define CAN_ESR1_TWRNINT_MASK   (0x20000U)
 
#define CAN_ESR1_TWRNINT_SHIFT   (17U)
 
#define CAN_ESR1_TWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
 
#define CAN_ESR1_SYNCH_MASK   (0x40000U)
 
#define CAN_ESR1_SYNCH_SHIFT   (18U)
 
#define CAN_ESR1_SYNCH(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
 

IMASK2 - Interrupt Masks 2 Register

#define CAN_IMASK2_BUFHM_MASK   (0xFFFFFFFFU)
 
#define CAN_IMASK2_BUFHM_SHIFT   (0U)
 
#define CAN_IMASK2_BUFHM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
 

IMASK1 - Interrupt Masks 1 Register

#define CAN_IMASK1_BUFLM_MASK   (0xFFFFFFFFU)
 
#define CAN_IMASK1_BUFLM_SHIFT   (0U)
 
#define CAN_IMASK1_BUFLM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
 

IFLAG2 - Interrupt Flags 2 Register

#define CAN_IFLAG2_BUFHI_MASK   (0xFFFFFFFFU)
 
#define CAN_IFLAG2_BUFHI_SHIFT   (0U)
 
#define CAN_IFLAG2_BUFHI(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
 

IFLAG1 - Interrupt Flags 1 Register

#define CAN_IFLAG1_BUF4TO0I_MASK   (0x1FU)
 
#define CAN_IFLAG1_BUF4TO0I_SHIFT   (0U)
 
#define CAN_IFLAG1_BUF4TO0I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
 
#define CAN_IFLAG1_BUF5I_MASK   (0x20U)
 
#define CAN_IFLAG1_BUF5I_SHIFT   (5U)
 
#define CAN_IFLAG1_BUF5I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
 
#define CAN_IFLAG1_BUF6I_MASK   (0x40U)
 
#define CAN_IFLAG1_BUF6I_SHIFT   (6U)
 
#define CAN_IFLAG1_BUF6I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
 
#define CAN_IFLAG1_BUF7I_MASK   (0x80U)
 
#define CAN_IFLAG1_BUF7I_SHIFT   (7U)
 
#define CAN_IFLAG1_BUF7I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
 
#define CAN_IFLAG1_BUF31TO8I_MASK   (0xFFFFFF00U)
 
#define CAN_IFLAG1_BUF31TO8I_SHIFT   (8U)
 
#define CAN_IFLAG1_BUF31TO8I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
 

CTRL2 - Control 2 Register

#define CAN_CTRL2_EACEN_MASK   (0x10000U)
 
#define CAN_CTRL2_EACEN_SHIFT   (16U)
 
#define CAN_CTRL2_EACEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
 
#define CAN_CTRL2_RRS_MASK   (0x20000U)
 
#define CAN_CTRL2_RRS_SHIFT   (17U)
 
#define CAN_CTRL2_RRS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
 
#define CAN_CTRL2_MRP_MASK   (0x40000U)
 
#define CAN_CTRL2_MRP_SHIFT   (18U)
 
#define CAN_CTRL2_MRP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
 
#define CAN_CTRL2_TASD_MASK   (0xF80000U)
 
#define CAN_CTRL2_TASD_SHIFT   (19U)
 
#define CAN_CTRL2_TASD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
 
#define CAN_CTRL2_RFFN_MASK   (0xF000000U)
 
#define CAN_CTRL2_RFFN_SHIFT   (24U)
 
#define CAN_CTRL2_RFFN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
 
#define CAN_CTRL2_WRMFRZ_MASK   (0x10000000U)
 
#define CAN_CTRL2_WRMFRZ_SHIFT   (28U)
 
#define CAN_CTRL2_WRMFRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
 
#define ENC_CTRL2_UPDHLD_MASK   (0x1U)
 
#define ENC_CTRL2_UPDHLD_SHIFT   (0U)
 
#define ENC_CTRL2_UPDHLD(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
 
#define ENC_CTRL2_UPDPOS_MASK   (0x2U)
 
#define ENC_CTRL2_UPDPOS_SHIFT   (1U)
 
#define ENC_CTRL2_UPDPOS(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
 
#define ENC_CTRL2_MOD_MASK   (0x4U)
 
#define ENC_CTRL2_MOD_SHIFT   (2U)
 
#define ENC_CTRL2_MOD(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
 
#define ENC_CTRL2_DIR_MASK   (0x8U)
 
#define ENC_CTRL2_DIR_SHIFT   (3U)
 
#define ENC_CTRL2_DIR(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
 
#define ENC_CTRL2_RUIE_MASK   (0x10U)
 
#define ENC_CTRL2_RUIE_SHIFT   (4U)
 
#define ENC_CTRL2_RUIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
 
#define ENC_CTRL2_RUIRQ_MASK   (0x20U)
 
#define ENC_CTRL2_RUIRQ_SHIFT   (5U)
 
#define ENC_CTRL2_RUIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
 
#define ENC_CTRL2_ROIE_MASK   (0x40U)
 
#define ENC_CTRL2_ROIE_SHIFT   (6U)
 
#define ENC_CTRL2_ROIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
 
#define ENC_CTRL2_ROIRQ_MASK   (0x80U)
 
#define ENC_CTRL2_ROIRQ_SHIFT   (7U)
 
#define ENC_CTRL2_ROIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
 
#define ENC_CTRL2_REVMOD_MASK   (0x100U)
 
#define ENC_CTRL2_REVMOD_SHIFT   (8U)
 
#define ENC_CTRL2_REVMOD(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
 
#define ENC_CTRL2_OUTCTL_MASK   (0x200U)
 
#define ENC_CTRL2_OUTCTL_SHIFT   (9U)
 
#define ENC_CTRL2_OUTCTL(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
 
#define ENC_CTRL2_SABIE_MASK   (0x400U)
 
#define ENC_CTRL2_SABIE_SHIFT   (10U)
 
#define ENC_CTRL2_SABIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
 
#define ENC_CTRL2_SABIRQ_MASK   (0x800U)
 
#define ENC_CTRL2_SABIRQ_SHIFT   (11U)
 
#define ENC_CTRL2_SABIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
 
#define PWM_CTRL2_CLK_SEL_MASK   (0x3U)
 
#define PWM_CTRL2_CLK_SEL_SHIFT   (0U)
 
#define PWM_CTRL2_CLK_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
 
#define PWM_CTRL2_RELOAD_SEL_MASK   (0x4U)
 
#define PWM_CTRL2_RELOAD_SEL_SHIFT   (2U)
 
#define PWM_CTRL2_RELOAD_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
 
#define PWM_CTRL2_FORCE_SEL_MASK   (0x38U)
 
#define PWM_CTRL2_FORCE_SEL_SHIFT   (3U)
 
#define PWM_CTRL2_FORCE_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
 
#define PWM_CTRL2_FORCE_MASK   (0x40U)
 
#define PWM_CTRL2_FORCE_SHIFT   (6U)
 
#define PWM_CTRL2_FORCE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
 
#define PWM_CTRL2_FRCEN_MASK   (0x80U)
 
#define PWM_CTRL2_FRCEN_SHIFT   (7U)
 
#define PWM_CTRL2_FRCEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
 
#define PWM_CTRL2_INIT_SEL_MASK   (0x300U)
 
#define PWM_CTRL2_INIT_SEL_SHIFT   (8U)
 
#define PWM_CTRL2_INIT_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
 
#define PWM_CTRL2_PWMX_INIT_MASK   (0x400U)
 
#define PWM_CTRL2_PWMX_INIT_SHIFT   (10U)
 
#define PWM_CTRL2_PWMX_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
 
#define PWM_CTRL2_PWM45_INIT_MASK   (0x800U)
 
#define PWM_CTRL2_PWM45_INIT_SHIFT   (11U)
 
#define PWM_CTRL2_PWM45_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
 
#define PWM_CTRL2_PWM23_INIT_MASK   (0x1000U)
 
#define PWM_CTRL2_PWM23_INIT_SHIFT   (12U)
 
#define PWM_CTRL2_PWM23_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
 
#define PWM_CTRL2_INDEP_MASK   (0x2000U)
 
#define PWM_CTRL2_INDEP_SHIFT   (13U)
 
#define PWM_CTRL2_INDEP(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
 
#define PWM_CTRL2_WAITEN_MASK   (0x4000U)
 
#define PWM_CTRL2_WAITEN_SHIFT   (14U)
 
#define PWM_CTRL2_WAITEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
 
#define PWM_CTRL2_DBGEN_MASK   (0x8000U)
 
#define PWM_CTRL2_DBGEN_SHIFT   (15U)
 
#define PWM_CTRL2_DBGEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
 

ESR2 - Error and Status 2 Register

#define CAN_ESR2_IMB_MASK   (0x2000U)
 
#define CAN_ESR2_IMB_SHIFT   (13U)
 
#define CAN_ESR2_IMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
 
#define CAN_ESR2_VPS_MASK   (0x4000U)
 
#define CAN_ESR2_VPS_SHIFT   (14U)
 
#define CAN_ESR2_VPS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
 
#define CAN_ESR2_LPTM_MASK   (0x7F0000U)
 
#define CAN_ESR2_LPTM_SHIFT   (16U)
 
#define CAN_ESR2_LPTM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
 

CRCR - CRC Register

#define CAN_CRCR_TXCRC_MASK   (0x7FFFU)
 
#define CAN_CRCR_TXCRC_SHIFT   (0U)
 
#define CAN_CRCR_TXCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
 
#define CAN_CRCR_MBCRC_MASK   (0x7F0000U)
 
#define CAN_CRCR_MBCRC_SHIFT   (16U)
 
#define CAN_CRCR_MBCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
 

RXFGMASK - Rx FIFO Global Mask Register

#define CAN_RXFGMASK_FGM_MASK   (0xFFFFFFFFU)
 
#define CAN_RXFGMASK_FGM_SHIFT   (0U)
 
#define CAN_RXFGMASK_FGM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
 

RXFIR - Rx FIFO Information Register

#define CAN_RXFIR_IDHIT_MASK   (0x1FFU)
 
#define CAN_RXFIR_IDHIT_SHIFT   (0U)
 
#define CAN_RXFIR_IDHIT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
 

DBG1 - Debug 1 register

#define CAN_DBG1_CFSM_MASK   (0x3FU)
 
#define CAN_DBG1_CFSM_SHIFT   (0U)
 
#define CAN_DBG1_CFSM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
 
#define CAN_DBG1_CBN_MASK   (0x1F000000U)
 
#define CAN_DBG1_CBN_SHIFT   (24U)
 
#define CAN_DBG1_CBN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
 

DBG2 - Debug 2 register

#define CAN_DBG2_RMP_MASK   (0x7FU)
 
#define CAN_DBG2_RMP_SHIFT   (0U)
 
#define CAN_DBG2_RMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
 
#define CAN_DBG2_MPP_MASK   (0x80U)
 
#define CAN_DBG2_MPP_SHIFT   (7U)
 
#define CAN_DBG2_MPP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
 
#define CAN_DBG2_TAP_MASK   (0x7F00U)
 
#define CAN_DBG2_TAP_SHIFT   (8U)
 
#define CAN_DBG2_TAP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
 
#define CAN_DBG2_APP_MASK   (0x8000U)
 
#define CAN_DBG2_APP_SHIFT   (15U)
 
#define CAN_DBG2_APP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
 

CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register

#define CAN_CS_TIME_STAMP_MASK   (0xFFFFU)
 
#define CAN_CS_TIME_STAMP_SHIFT   (0U)
 
#define CAN_CS_TIME_STAMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
 
#define CAN_CS_DLC_MASK   (0xF0000U)
 
#define CAN_CS_DLC_SHIFT   (16U)
 
#define CAN_CS_DLC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
 
#define CAN_CS_RTR_MASK   (0x100000U)
 
#define CAN_CS_RTR_SHIFT   (20U)
 
#define CAN_CS_RTR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
 
#define CAN_CS_IDE_MASK   (0x200000U)
 
#define CAN_CS_IDE_SHIFT   (21U)
 
#define CAN_CS_IDE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
 
#define CAN_CS_SRR_MASK   (0x400000U)
 
#define CAN_CS_SRR_SHIFT   (22U)
 
#define CAN_CS_SRR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
 
#define CAN_CS_CODE_MASK   (0xF000000U)
 
#define CAN_CS_CODE_SHIFT   (24U)
 
#define CAN_CS_CODE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
 

ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register

#define CAN_ID_EXT_MASK   (0x3FFFFU)
 
#define CAN_ID_EXT_SHIFT   (0U)
 
#define CAN_ID_EXT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
 
#define CAN_ID_STD_MASK   (0x1FFC0000U)
 
#define CAN_ID_STD_SHIFT   (18U)
 
#define CAN_ID_STD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
 
#define CAN_ID_PRIO_MASK   (0xE0000000U)
 
#define CAN_ID_PRIO_SHIFT   (29U)
 
#define CAN_ID_PRIO(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
 

WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register

#define CAN_WORD0_DATA_BYTE_3_MASK   (0xFFU)
 
#define CAN_WORD0_DATA_BYTE_3_SHIFT   (0U)
 
#define CAN_WORD0_DATA_BYTE_3(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
 
#define CAN_WORD0_DATA_BYTE_2_MASK   (0xFF00U)
 
#define CAN_WORD0_DATA_BYTE_2_SHIFT   (8U)
 
#define CAN_WORD0_DATA_BYTE_2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
 
#define CAN_WORD0_DATA_BYTE_1_MASK   (0xFF0000U)
 
#define CAN_WORD0_DATA_BYTE_1_SHIFT   (16U)
 
#define CAN_WORD0_DATA_BYTE_1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
 
#define CAN_WORD0_DATA_BYTE_0_MASK   (0xFF000000U)
 
#define CAN_WORD0_DATA_BYTE_0_SHIFT   (24U)
 
#define CAN_WORD0_DATA_BYTE_0(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
 

WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register

#define CAN_WORD1_DATA_BYTE_7_MASK   (0xFFU)
 
#define CAN_WORD1_DATA_BYTE_7_SHIFT   (0U)
 
#define CAN_WORD1_DATA_BYTE_7(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
 
#define CAN_WORD1_DATA_BYTE_6_MASK   (0xFF00U)
 
#define CAN_WORD1_DATA_BYTE_6_SHIFT   (8U)
 
#define CAN_WORD1_DATA_BYTE_6(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
 
#define CAN_WORD1_DATA_BYTE_5_MASK   (0xFF0000U)
 
#define CAN_WORD1_DATA_BYTE_5_SHIFT   (16U)
 
#define CAN_WORD1_DATA_BYTE_5(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
 
#define CAN_WORD1_DATA_BYTE_4_MASK   (0xFF000000U)
 
#define CAN_WORD1_DATA_BYTE_4_SHIFT   (24U)
 
#define CAN_WORD1_DATA_BYTE_4(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
 

RXIMR - Rx Individual Mask Registers

#define CAN_RXIMR_MI_MASK   (0xFFFFFFFFU)
 
#define CAN_RXIMR_MI_SHIFT   (0U)
 
#define CAN_RXIMR_MI(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
 

GFWR - Glitch Filter Width Registers

#define CAN_GFWR_GFWR_MASK   (0xFFU)
 
#define CAN_GFWR_GFWR_SHIFT   (0U)
 
#define CAN_GFWR_GFWR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
 

Detailed Description

Macro Definition Documentation

◆ CAN_CRCR_MBCRC

#define CAN_CRCR_MBCRC (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)

Definition at line 3903 of file MIMXRT1052.h.

◆ CAN_CRCR_MBCRC_MASK

#define CAN_CRCR_MBCRC_MASK   (0x7F0000U)

Definition at line 3901 of file MIMXRT1052.h.

◆ CAN_CRCR_MBCRC_SHIFT

#define CAN_CRCR_MBCRC_SHIFT   (16U)

Definition at line 3902 of file MIMXRT1052.h.

◆ CAN_CRCR_TXCRC

#define CAN_CRCR_TXCRC (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)

Definition at line 3900 of file MIMXRT1052.h.

◆ CAN_CRCR_TXCRC_MASK

#define CAN_CRCR_TXCRC_MASK   (0x7FFFU)

Definition at line 3898 of file MIMXRT1052.h.

◆ CAN_CRCR_TXCRC_SHIFT

#define CAN_CRCR_TXCRC_SHIFT   (0U)

Definition at line 3899 of file MIMXRT1052.h.

◆ CAN_CS_CODE

#define CAN_CS_CODE (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

CODE - Reserved

Definition at line 3999 of file MIMXRT1052.h.

◆ CAN_CS_CODE_MASK

#define CAN_CS_CODE_MASK   (0xF000000U)

Definition at line 3995 of file MIMXRT1052.h.

◆ CAN_CS_CODE_SHIFT

#define CAN_CS_CODE_SHIFT   (24U)

Definition at line 3996 of file MIMXRT1052.h.

◆ CAN_CS_COUNT

#define CAN_CS_COUNT   (64U)

Definition at line 4003 of file MIMXRT1052.h.

◆ CAN_CS_DLC

#define CAN_CS_DLC (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

DLC - Length of the data to be stored/transmitted.

Definition at line 3979 of file MIMXRT1052.h.

◆ CAN_CS_DLC_MASK

#define CAN_CS_DLC_MASK   (0xF0000U)

Definition at line 3975 of file MIMXRT1052.h.

◆ CAN_CS_DLC_SHIFT

#define CAN_CS_DLC_SHIFT   (16U)

Definition at line 3976 of file MIMXRT1052.h.

◆ CAN_CS_IDE

#define CAN_CS_IDE (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

IDE - ID Extended. One/zero for extended/standard format frame.

Definition at line 3989 of file MIMXRT1052.h.

◆ CAN_CS_IDE_MASK

#define CAN_CS_IDE_MASK   (0x200000U)

Definition at line 3985 of file MIMXRT1052.h.

◆ CAN_CS_IDE_SHIFT

#define CAN_CS_IDE_SHIFT   (21U)

Definition at line 3986 of file MIMXRT1052.h.

◆ CAN_CS_RTR

#define CAN_CS_RTR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

RTR - Remote Transmission Request. One/zero for remote/data frame.

Definition at line 3984 of file MIMXRT1052.h.

◆ CAN_CS_RTR_MASK

#define CAN_CS_RTR_MASK   (0x100000U)

Definition at line 3980 of file MIMXRT1052.h.

◆ CAN_CS_RTR_SHIFT

#define CAN_CS_RTR_SHIFT   (20U)

Definition at line 3981 of file MIMXRT1052.h.

◆ CAN_CS_SRR

#define CAN_CS_SRR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

SRR - Substitute Remote Request. Contains a fixed recessive bit.

Definition at line 3994 of file MIMXRT1052.h.

◆ CAN_CS_SRR_MASK

#define CAN_CS_SRR_MASK   (0x400000U)

Definition at line 3990 of file MIMXRT1052.h.

◆ CAN_CS_SRR_SHIFT

#define CAN_CS_SRR_SHIFT   (22U)

Definition at line 3991 of file MIMXRT1052.h.

◆ CAN_CS_TIME_STAMP

#define CAN_CS_TIME_STAMP (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

Definition at line 3974 of file MIMXRT1052.h.

◆ CAN_CS_TIME_STAMP_MASK

#define CAN_CS_TIME_STAMP_MASK   (0xFFFFU)

Definition at line 3968 of file MIMXRT1052.h.

◆ CAN_CS_TIME_STAMP_SHIFT

#define CAN_CS_TIME_STAMP_SHIFT   (0U)

Definition at line 3969 of file MIMXRT1052.h.

◆ CAN_CTRL1_BOFFMSK

#define CAN_CTRL1_BOFFMSK (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK 0b1..Bus Off interrupt enabled 0b0..Bus Off interrupt disabled

Definition at line 3568 of file MIMXRT1052.h.

◆ CAN_CTRL1_BOFFMSK_MASK

#define CAN_CTRL1_BOFFMSK_MASK   (0x8000U)

Definition at line 3562 of file MIMXRT1052.h.

◆ CAN_CTRL1_BOFFMSK_SHIFT

#define CAN_CTRL1_BOFFMSK_SHIFT   (15U)

Definition at line 3563 of file MIMXRT1052.h.

◆ CAN_CTRL1_BOFFREC

#define CAN_CTRL1_BOFFREC (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC 0b1..Automatic recovering from Bus Off state disabled 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B

Definition at line 3525 of file MIMXRT1052.h.

◆ CAN_CTRL1_BOFFREC_MASK

#define CAN_CTRL1_BOFFREC_MASK   (0x40U)

Definition at line 3519 of file MIMXRT1052.h.

◆ CAN_CTRL1_BOFFREC_SHIFT

#define CAN_CTRL1_BOFFREC_SHIFT   (6U)

Definition at line 3520 of file MIMXRT1052.h.

◆ CAN_CTRL1_ERRMSK

#define CAN_CTRL1_ERRMSK (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK 0b1..Error interrupt enabled 0b0..Error interrupt disabled

Definition at line 3561 of file MIMXRT1052.h.

◆ CAN_CTRL1_ERRMSK_MASK

#define CAN_CTRL1_ERRMSK_MASK   (0x4000U)

Definition at line 3555 of file MIMXRT1052.h.

◆ CAN_CTRL1_ERRMSK_SHIFT

#define CAN_CTRL1_ERRMSK_SHIFT   (14U)

Definition at line 3556 of file MIMXRT1052.h.

◆ CAN_CTRL1_LBUF

#define CAN_CTRL1_LBUF (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF 0b1..Lowest number buffer is transmitted first 0b0..Buffer with highest priority is transmitted first

Definition at line 3511 of file MIMXRT1052.h.

◆ CAN_CTRL1_LBUF_MASK

#define CAN_CTRL1_LBUF_MASK   (0x10U)

Definition at line 3505 of file MIMXRT1052.h.

◆ CAN_CTRL1_LBUF_SHIFT

#define CAN_CTRL1_LBUF_SHIFT   (4U)

Definition at line 3506 of file MIMXRT1052.h.

◆ CAN_CTRL1_LOM

#define CAN_CTRL1_LOM (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM 0b1..FLEXCAN module operates in Listen Only Mode 0b0..Listen Only Mode is deactivated

Definition at line 3504 of file MIMXRT1052.h.

◆ CAN_CTRL1_LOM_MASK

#define CAN_CTRL1_LOM_MASK   (0x8U)

Definition at line 3498 of file MIMXRT1052.h.

◆ CAN_CTRL1_LOM_SHIFT

#define CAN_CTRL1_LOM_SHIFT   (3U)

Definition at line 3499 of file MIMXRT1052.h.

◆ CAN_CTRL1_LPB

#define CAN_CTRL1_LPB (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB 0b1..Loop Back enabled 0b0..Loop Back disabled

Definition at line 3554 of file MIMXRT1052.h.

◆ CAN_CTRL1_LPB_MASK

#define CAN_CTRL1_LPB_MASK   (0x1000U)

Definition at line 3548 of file MIMXRT1052.h.

◆ CAN_CTRL1_LPB_SHIFT

#define CAN_CTRL1_LPB_SHIFT   (12U)

Definition at line 3549 of file MIMXRT1052.h.

◆ CAN_CTRL1_PRESDIV

#define CAN_CTRL1_PRESDIV (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)

Definition at line 3580 of file MIMXRT1052.h.

◆ CAN_CTRL1_PRESDIV_MASK

#define CAN_CTRL1_PRESDIV_MASK   (0xFF000000U)

Definition at line 3578 of file MIMXRT1052.h.

◆ CAN_CTRL1_PRESDIV_SHIFT

#define CAN_CTRL1_PRESDIV_SHIFT   (24U)

Definition at line 3579 of file MIMXRT1052.h.

◆ CAN_CTRL1_PROPSEG

#define CAN_CTRL1_PROPSEG (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)

Definition at line 3497 of file MIMXRT1052.h.

◆ CAN_CTRL1_PROPSEG_MASK

#define CAN_CTRL1_PROPSEG_MASK   (0x7U)

Definition at line 3495 of file MIMXRT1052.h.

◆ CAN_CTRL1_PROPSEG_SHIFT

#define CAN_CTRL1_PROPSEG_SHIFT   (0U)

Definition at line 3496 of file MIMXRT1052.h.

◆ CAN_CTRL1_PSEG1

#define CAN_CTRL1_PSEG1 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)

Definition at line 3574 of file MIMXRT1052.h.

◆ CAN_CTRL1_PSEG1_MASK

#define CAN_CTRL1_PSEG1_MASK   (0x380000U)

Definition at line 3572 of file MIMXRT1052.h.

◆ CAN_CTRL1_PSEG1_SHIFT

#define CAN_CTRL1_PSEG1_SHIFT   (19U)

Definition at line 3573 of file MIMXRT1052.h.

◆ CAN_CTRL1_PSEG2

#define CAN_CTRL1_PSEG2 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)

Definition at line 3571 of file MIMXRT1052.h.

◆ CAN_CTRL1_PSEG2_MASK

#define CAN_CTRL1_PSEG2_MASK   (0x70000U)

Definition at line 3569 of file MIMXRT1052.h.

◆ CAN_CTRL1_PSEG2_SHIFT

#define CAN_CTRL1_PSEG2_SHIFT   (16U)

Definition at line 3570 of file MIMXRT1052.h.

◆ CAN_CTRL1_RJW

#define CAN_CTRL1_RJW (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)

Definition at line 3577 of file MIMXRT1052.h.

◆ CAN_CTRL1_RJW_MASK

#define CAN_CTRL1_RJW_MASK   (0xC00000U)

Definition at line 3575 of file MIMXRT1052.h.

◆ CAN_CTRL1_RJW_SHIFT

#define CAN_CTRL1_RJW_SHIFT   (22U)

Definition at line 3576 of file MIMXRT1052.h.

◆ CAN_CTRL1_RWRNMSK

#define CAN_CTRL1_RWRNMSK (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK 0b1..Rx Warning Interrupt enabled 0b0..Rx Warning Interrupt disabled

Definition at line 3540 of file MIMXRT1052.h.

◆ CAN_CTRL1_RWRNMSK_MASK

#define CAN_CTRL1_RWRNMSK_MASK   (0x400U)

Definition at line 3534 of file MIMXRT1052.h.

◆ CAN_CTRL1_RWRNMSK_SHIFT

#define CAN_CTRL1_RWRNMSK_SHIFT   (10U)

Definition at line 3535 of file MIMXRT1052.h.

◆ CAN_CTRL1_SMP

#define CAN_CTRL1_SMP (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used 0b0..Just one sample is used to determine the bit value

Definition at line 3533 of file MIMXRT1052.h.

◆ CAN_CTRL1_SMP_MASK

#define CAN_CTRL1_SMP_MASK   (0x80U)

Definition at line 3526 of file MIMXRT1052.h.

◆ CAN_CTRL1_SMP_SHIFT

#define CAN_CTRL1_SMP_SHIFT   (7U)

Definition at line 3527 of file MIMXRT1052.h.

◆ CAN_CTRL1_TSYN

#define CAN_CTRL1_TSYN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN 0b1..Timer Sync feature enabled 0b0..Timer Sync feature disabled

Definition at line 3518 of file MIMXRT1052.h.

◆ CAN_CTRL1_TSYN_MASK

#define CAN_CTRL1_TSYN_MASK   (0x20U)

Definition at line 3512 of file MIMXRT1052.h.

◆ CAN_CTRL1_TSYN_SHIFT

#define CAN_CTRL1_TSYN_SHIFT   (5U)

Definition at line 3513 of file MIMXRT1052.h.

◆ CAN_CTRL1_TWRNMSK

#define CAN_CTRL1_TWRNMSK (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK 0b1..Tx Warning Interrupt enabled 0b0..Tx Warning Interrupt disabled

Definition at line 3547 of file MIMXRT1052.h.

◆ CAN_CTRL1_TWRNMSK_MASK

#define CAN_CTRL1_TWRNMSK_MASK   (0x800U)

Definition at line 3541 of file MIMXRT1052.h.

◆ CAN_CTRL1_TWRNMSK_SHIFT

#define CAN_CTRL1_TWRNMSK_SHIFT   (11U)

Definition at line 3542 of file MIMXRT1052.h.

◆ CAN_CTRL2_EACEN

#define CAN_CTRL2_EACEN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.

Definition at line 3845 of file MIMXRT1052.h.

◆ CAN_CTRL2_EACEN_MASK

#define CAN_CTRL2_EACEN_MASK   (0x10000U)

Definition at line 3838 of file MIMXRT1052.h.

◆ CAN_CTRL2_EACEN_SHIFT

#define CAN_CTRL2_EACEN_SHIFT   (16U)

Definition at line 3839 of file MIMXRT1052.h.

◆ CAN_CTRL2_MRP

#define CAN_CTRL2_MRP (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP 0b1..Matching starts from Mailboxes and continues on Rx FIFO 0b0..Matching starts from Rx FIFO and continues on Mailboxes

Definition at line 3859 of file MIMXRT1052.h.

◆ CAN_CTRL2_MRP_MASK

#define CAN_CTRL2_MRP_MASK   (0x40000U)

Definition at line 3853 of file MIMXRT1052.h.

◆ CAN_CTRL2_MRP_SHIFT

#define CAN_CTRL2_MRP_SHIFT   (18U)

Definition at line 3854 of file MIMXRT1052.h.

◆ CAN_CTRL2_RFFN

#define CAN_CTRL2_RFFN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)

Definition at line 3865 of file MIMXRT1052.h.

◆ CAN_CTRL2_RFFN_MASK

#define CAN_CTRL2_RFFN_MASK   (0xF000000U)

Definition at line 3863 of file MIMXRT1052.h.

◆ CAN_CTRL2_RFFN_SHIFT

#define CAN_CTRL2_RFFN_SHIFT   (24U)

Definition at line 3864 of file MIMXRT1052.h.

◆ CAN_CTRL2_RRS

#define CAN_CTRL2_RRS (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS 0b1..Remote Request Frame is stored 0b0..Remote Response Frame is generated

Definition at line 3852 of file MIMXRT1052.h.

◆ CAN_CTRL2_RRS_MASK

#define CAN_CTRL2_RRS_MASK   (0x20000U)

Definition at line 3846 of file MIMXRT1052.h.

◆ CAN_CTRL2_RRS_SHIFT

#define CAN_CTRL2_RRS_SHIFT   (17U)

Definition at line 3847 of file MIMXRT1052.h.

◆ CAN_CTRL2_TASD

#define CAN_CTRL2_TASD (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)

Definition at line 3862 of file MIMXRT1052.h.

◆ CAN_CTRL2_TASD_MASK

#define CAN_CTRL2_TASD_MASK   (0xF80000U)

Definition at line 3860 of file MIMXRT1052.h.

◆ CAN_CTRL2_TASD_SHIFT

#define CAN_CTRL2_TASD_SHIFT   (19U)

Definition at line 3861 of file MIMXRT1052.h.

◆ CAN_CTRL2_WRMFRZ

#define CAN_CTRL2_WRMFRZ (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

WRMFRZ 0b1..Enable unrestricted write access to FlexCAN memory 0b0..Keep the write access restricted in some regions of FlexCAN memory

Definition at line 3872 of file MIMXRT1052.h.

◆ CAN_CTRL2_WRMFRZ_MASK

#define CAN_CTRL2_WRMFRZ_MASK   (0x10000000U)

Definition at line 3866 of file MIMXRT1052.h.

◆ CAN_CTRL2_WRMFRZ_SHIFT

#define CAN_CTRL2_WRMFRZ_SHIFT   (28U)

Definition at line 3867 of file MIMXRT1052.h.

◆ CAN_DBG1_CBN

#define CAN_DBG1_CBN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)

CBN - CAN Bit Number

Definition at line 3935 of file MIMXRT1052.h.

◆ CAN_DBG1_CBN_MASK

#define CAN_DBG1_CBN_MASK   (0x1F000000U)

Definition at line 3931 of file MIMXRT1052.h.

◆ CAN_DBG1_CBN_SHIFT

#define CAN_DBG1_CBN_SHIFT   (24U)

Definition at line 3932 of file MIMXRT1052.h.

◆ CAN_DBG1_CFSM

#define CAN_DBG1_CFSM (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)

CFSM - CAN Finite State Machine

Definition at line 3930 of file MIMXRT1052.h.

◆ CAN_DBG1_CFSM_MASK

#define CAN_DBG1_CFSM_MASK   (0x3FU)

Definition at line 3926 of file MIMXRT1052.h.

◆ CAN_DBG1_CFSM_SHIFT

#define CAN_DBG1_CFSM_SHIFT   (0U)

Definition at line 3927 of file MIMXRT1052.h.

◆ CAN_DBG2_APP

#define CAN_DBG2_APP (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)

APP - Arbitration Process in Progress 0b0..No matching process ongoing. 0b1..Matching process is in progress.

Definition at line 3963 of file MIMXRT1052.h.

◆ CAN_DBG2_APP_MASK

#define CAN_DBG2_APP_MASK   (0x8000U)

Definition at line 3957 of file MIMXRT1052.h.

◆ CAN_DBG2_APP_SHIFT

#define CAN_DBG2_APP_SHIFT   (15U)

Definition at line 3958 of file MIMXRT1052.h.

◆ CAN_DBG2_MPP

#define CAN_DBG2_MPP (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)

MPP - Matching Process in Progress 0b0..No matching process ongoing. 0b1..Matching process is in progress.

Definition at line 3951 of file MIMXRT1052.h.

◆ CAN_DBG2_MPP_MASK

#define CAN_DBG2_MPP_MASK   (0x80U)

Definition at line 3945 of file MIMXRT1052.h.

◆ CAN_DBG2_MPP_SHIFT

#define CAN_DBG2_MPP_SHIFT   (7U)

Definition at line 3946 of file MIMXRT1052.h.

◆ CAN_DBG2_RMP

#define CAN_DBG2_RMP (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)

RMP - Rx Matching Pointer

Definition at line 3944 of file MIMXRT1052.h.

◆ CAN_DBG2_RMP_MASK

#define CAN_DBG2_RMP_MASK   (0x7FU)

Definition at line 3940 of file MIMXRT1052.h.

◆ CAN_DBG2_RMP_SHIFT

#define CAN_DBG2_RMP_SHIFT   (0U)

Definition at line 3941 of file MIMXRT1052.h.

◆ CAN_DBG2_TAP

#define CAN_DBG2_TAP (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)

TAP - Tx Arbitration Pointer

Definition at line 3956 of file MIMXRT1052.h.

◆ CAN_DBG2_TAP_MASK

#define CAN_DBG2_TAP_MASK   (0x7F00U)

Definition at line 3952 of file MIMXRT1052.h.

◆ CAN_DBG2_TAP_SHIFT

#define CAN_DBG2_TAP_SHIFT   (8U)

Definition at line 3953 of file MIMXRT1052.h.

◆ CAN_ECR_RX_ERR_COUNTER

#define CAN_ECR_RX_ERR_COUNTER (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)

Definition at line 3630 of file MIMXRT1052.h.

◆ CAN_ECR_RX_ERR_COUNTER_MASK

#define CAN_ECR_RX_ERR_COUNTER_MASK   (0xFF00U)

Definition at line 3628 of file MIMXRT1052.h.

◆ CAN_ECR_RX_ERR_COUNTER_SHIFT

#define CAN_ECR_RX_ERR_COUNTER_SHIFT   (8U)

Definition at line 3629 of file MIMXRT1052.h.

◆ CAN_ECR_TX_ERR_COUNTER

#define CAN_ECR_TX_ERR_COUNTER (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)

Definition at line 3627 of file MIMXRT1052.h.

◆ CAN_ECR_TX_ERR_COUNTER_MASK

#define CAN_ECR_TX_ERR_COUNTER_MASK   (0xFFU)

Definition at line 3625 of file MIMXRT1052.h.

◆ CAN_ECR_TX_ERR_COUNTER_SHIFT

#define CAN_ECR_TX_ERR_COUNTER_SHIFT   (0U)

Definition at line 3626 of file MIMXRT1052.h.

◆ CAN_ESR1_ACKERR

#define CAN_ESR1_ACKERR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR 0b1..An ACK error occurred since last read of this register 0b0..No such occurrence

Definition at line 3726 of file MIMXRT1052.h.

◆ CAN_ESR1_ACKERR_MASK

#define CAN_ESR1_ACKERR_MASK   (0x2000U)

Definition at line 3720 of file MIMXRT1052.h.

◆ CAN_ESR1_ACKERR_SHIFT

#define CAN_ESR1_ACKERR_SHIFT   (13U)

Definition at line 3721 of file MIMXRT1052.h.

◆ CAN_ESR1_BIT0ERR

#define CAN_ESR1_BIT0ERR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR 0b1..At least one bit sent as dominant is received as recessive 0b0..No such occurrence

Definition at line 3733 of file MIMXRT1052.h.

◆ CAN_ESR1_BIT0ERR_MASK

#define CAN_ESR1_BIT0ERR_MASK   (0x4000U)

Definition at line 3727 of file MIMXRT1052.h.

◆ CAN_ESR1_BIT0ERR_SHIFT

#define CAN_ESR1_BIT0ERR_SHIFT   (14U)

Definition at line 3728 of file MIMXRT1052.h.

◆ CAN_ESR1_BIT1ERR

#define CAN_ESR1_BIT1ERR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR 0b1..At least one bit sent as recessive is received as dominant 0b0..No such occurrence

Definition at line 3740 of file MIMXRT1052.h.

◆ CAN_ESR1_BIT1ERR_MASK

#define CAN_ESR1_BIT1ERR_MASK   (0x8000U)

Definition at line 3734 of file MIMXRT1052.h.

◆ CAN_ESR1_BIT1ERR_SHIFT

#define CAN_ESR1_BIT1ERR_SHIFT   (15U)

Definition at line 3735 of file MIMXRT1052.h.

◆ CAN_ESR1_BOFFINT

#define CAN_ESR1_BOFFINT (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT 0b1..FLEXCAN module entered 'Bus Off' state 0b0..No such occurrence

Definition at line 3655 of file MIMXRT1052.h.

◆ CAN_ESR1_BOFFINT_MASK

#define CAN_ESR1_BOFFINT_MASK   (0x4U)

Definition at line 3649 of file MIMXRT1052.h.

◆ CAN_ESR1_BOFFINT_SHIFT

#define CAN_ESR1_BOFFINT_SHIFT   (2U)

Definition at line 3650 of file MIMXRT1052.h.

◆ CAN_ESR1_CRCERR

#define CAN_ESR1_CRCERR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR 0b1..A CRC error occurred since last read of this register. 0b0..No such occurrence

Definition at line 3719 of file MIMXRT1052.h.

◆ CAN_ESR1_CRCERR_MASK

#define CAN_ESR1_CRCERR_MASK   (0x1000U)

Definition at line 3713 of file MIMXRT1052.h.

◆ CAN_ESR1_CRCERR_SHIFT

#define CAN_ESR1_CRCERR_SHIFT   (12U)

Definition at line 3714 of file MIMXRT1052.h.

◆ CAN_ESR1_ERRINT

#define CAN_ESR1_ERRINT (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT 0b1..Indicates setting of any Error Bit in the Error and Status Register 0b0..No such occurrence

Definition at line 3648 of file MIMXRT1052.h.

◆ CAN_ESR1_ERRINT_MASK

#define CAN_ESR1_ERRINT_MASK   (0x2U)

Definition at line 3642 of file MIMXRT1052.h.

◆ CAN_ESR1_ERRINT_SHIFT

#define CAN_ESR1_ERRINT_SHIFT   (1U)

Definition at line 3643 of file MIMXRT1052.h.

◆ CAN_ESR1_FLTCONF

#define CAN_ESR1_FLTCONF (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF 0b00..Error Active 0b01..Error Passive 0b1x..Bus off

Definition at line 3670 of file MIMXRT1052.h.

◆ CAN_ESR1_FLTCONF_MASK

#define CAN_ESR1_FLTCONF_MASK   (0x30U)

Definition at line 3663 of file MIMXRT1052.h.

◆ CAN_ESR1_FLTCONF_SHIFT

#define CAN_ESR1_FLTCONF_SHIFT   (4U)

Definition at line 3664 of file MIMXRT1052.h.

◆ CAN_ESR1_FRMERR

#define CAN_ESR1_FRMERR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR 0b1..A Form Error occurred since last read of this register 0b0..No such occurrence

Definition at line 3712 of file MIMXRT1052.h.

◆ CAN_ESR1_FRMERR_MASK

#define CAN_ESR1_FRMERR_MASK   (0x800U)

Definition at line 3706 of file MIMXRT1052.h.

◆ CAN_ESR1_FRMERR_SHIFT

#define CAN_ESR1_FRMERR_SHIFT   (11U)

Definition at line 3707 of file MIMXRT1052.h.

◆ CAN_ESR1_IDLE

#define CAN_ESR1_IDLE (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE 0b1..CAN bus is now IDLE 0b0..No such occurrence

Definition at line 3684 of file MIMXRT1052.h.

◆ CAN_ESR1_IDLE_MASK

#define CAN_ESR1_IDLE_MASK   (0x80U)

Definition at line 3678 of file MIMXRT1052.h.

◆ CAN_ESR1_IDLE_SHIFT

#define CAN_ESR1_IDLE_SHIFT   (7U)

Definition at line 3679 of file MIMXRT1052.h.

◆ CAN_ESR1_RWRNINT

#define CAN_ESR1_RWRNINT (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT 0b1..The Rx error counter transition from < 96 to >= 96 0b0..No such occurrence

Definition at line 3747 of file MIMXRT1052.h.

◆ CAN_ESR1_RWRNINT_MASK

#define CAN_ESR1_RWRNINT_MASK   (0x10000U)

Definition at line 3741 of file MIMXRT1052.h.

◆ CAN_ESR1_RWRNINT_SHIFT

#define CAN_ESR1_RWRNINT_SHIFT   (16U)

Definition at line 3742 of file MIMXRT1052.h.

◆ CAN_ESR1_RX

#define CAN_ESR1_RX (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX 0b1..FLEXCAN is transmitting a message 0b0..FLEXCAN is receiving a message

Definition at line 3662 of file MIMXRT1052.h.

◆ CAN_ESR1_RX_MASK

#define CAN_ESR1_RX_MASK   (0x8U)

Definition at line 3656 of file MIMXRT1052.h.

◆ CAN_ESR1_RX_SHIFT

#define CAN_ESR1_RX_SHIFT   (3U)

Definition at line 3657 of file MIMXRT1052.h.

◆ CAN_ESR1_RXWRN

#define CAN_ESR1_RXWRN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN 0b1..Rx_Err_Counter >= 96 0b0..No such occurrence

Definition at line 3691 of file MIMXRT1052.h.

◆ CAN_ESR1_RXWRN_MASK

#define CAN_ESR1_RXWRN_MASK   (0x100U)

Definition at line 3685 of file MIMXRT1052.h.

◆ CAN_ESR1_RXWRN_SHIFT

#define CAN_ESR1_RXWRN_SHIFT   (8U)

Definition at line 3686 of file MIMXRT1052.h.

◆ CAN_ESR1_STFERR

#define CAN_ESR1_STFERR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR 0b1..A Stuffing Error occurred since last read of this register. 0b0..No such occurrence.

Definition at line 3705 of file MIMXRT1052.h.

◆ CAN_ESR1_STFERR_MASK

#define CAN_ESR1_STFERR_MASK   (0x400U)

Definition at line 3699 of file MIMXRT1052.h.

◆ CAN_ESR1_STFERR_SHIFT

#define CAN_ESR1_STFERR_SHIFT   (10U)

Definition at line 3700 of file MIMXRT1052.h.

◆ CAN_ESR1_SYNCH

#define CAN_ESR1_SYNCH (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH 0b1..FlexCAN is synchronized to the CAN bus 0b0..FlexCAN is not synchronized to the CAN bus

Definition at line 3761 of file MIMXRT1052.h.

◆ CAN_ESR1_SYNCH_MASK

#define CAN_ESR1_SYNCH_MASK   (0x40000U)

Definition at line 3755 of file MIMXRT1052.h.

◆ CAN_ESR1_SYNCH_SHIFT

#define CAN_ESR1_SYNCH_SHIFT   (18U)

Definition at line 3756 of file MIMXRT1052.h.

◆ CAN_ESR1_TWRNINT

#define CAN_ESR1_TWRNINT (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT 0b1..The Tx error counter transition from < 96 to >= 96 0b0..No such occurrence

Definition at line 3754 of file MIMXRT1052.h.

◆ CAN_ESR1_TWRNINT_MASK

#define CAN_ESR1_TWRNINT_MASK   (0x20000U)

Definition at line 3748 of file MIMXRT1052.h.

◆ CAN_ESR1_TWRNINT_SHIFT

#define CAN_ESR1_TWRNINT_SHIFT   (17U)

Definition at line 3749 of file MIMXRT1052.h.

◆ CAN_ESR1_TX

#define CAN_ESR1_TX (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX 0b1..FLEXCAN is transmitting a message 0b0..FLEXCAN is receiving a message

Definition at line 3677 of file MIMXRT1052.h.

◆ CAN_ESR1_TX_MASK

#define CAN_ESR1_TX_MASK   (0x40U)

Definition at line 3671 of file MIMXRT1052.h.

◆ CAN_ESR1_TX_SHIFT

#define CAN_ESR1_TX_SHIFT   (6U)

Definition at line 3672 of file MIMXRT1052.h.

◆ CAN_ESR1_TXWRN

#define CAN_ESR1_TXWRN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN 0b1..TX_Err_Counter >= 96 0b0..No such occurrence

Definition at line 3698 of file MIMXRT1052.h.

◆ CAN_ESR1_TXWRN_MASK

#define CAN_ESR1_TXWRN_MASK   (0x200U)

Definition at line 3692 of file MIMXRT1052.h.

◆ CAN_ESR1_TXWRN_SHIFT

#define CAN_ESR1_TXWRN_SHIFT   (9U)

Definition at line 3693 of file MIMXRT1052.h.

◆ CAN_ESR1_WAKINT

#define CAN_ESR1_WAKINT (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode 0b0..No such occurrence

Definition at line 3641 of file MIMXRT1052.h.

◆ CAN_ESR1_WAKINT_MASK

#define CAN_ESR1_WAKINT_MASK   (0x1U)

Definition at line 3635 of file MIMXRT1052.h.

◆ CAN_ESR1_WAKINT_SHIFT

#define CAN_ESR1_WAKINT_SHIFT   (0U)

Definition at line 3636 of file MIMXRT1052.h.

◆ CAN_ESR2_IMB

#define CAN_ESR2_IMB (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.

Definition at line 3883 of file MIMXRT1052.h.

◆ CAN_ESR2_IMB_MASK

#define CAN_ESR2_IMB_MASK   (0x2000U)

Definition at line 3877 of file MIMXRT1052.h.

◆ CAN_ESR2_IMB_SHIFT

#define CAN_ESR2_IMB_SHIFT   (13U)

Definition at line 3878 of file MIMXRT1052.h.

◆ CAN_ESR2_LPTM

#define CAN_ESR2_LPTM (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)

Definition at line 3893 of file MIMXRT1052.h.

◆ CAN_ESR2_LPTM_MASK

#define CAN_ESR2_LPTM_MASK   (0x7F0000U)

Definition at line 3891 of file MIMXRT1052.h.

◆ CAN_ESR2_LPTM_SHIFT

#define CAN_ESR2_LPTM_SHIFT   (16U)

Definition at line 3892 of file MIMXRT1052.h.

◆ CAN_ESR2_VPS

#define CAN_ESR2_VPS (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS 0b1..Contents of IMB and LPTM are valid 0b0..Contents of IMB and LPTM are invalid

Definition at line 3890 of file MIMXRT1052.h.

◆ CAN_ESR2_VPS_MASK

#define CAN_ESR2_VPS_MASK   (0x4000U)

Definition at line 3884 of file MIMXRT1052.h.

◆ CAN_ESR2_VPS_SHIFT

#define CAN_ESR2_VPS_SHIFT   (14U)

Definition at line 3885 of file MIMXRT1052.h.

◆ CAN_GFWR_GFWR

#define CAN_GFWR_GFWR (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)

Definition at line 4101 of file MIMXRT1052.h.

◆ CAN_GFWR_GFWR_MASK

#define CAN_GFWR_GFWR_MASK   (0xFFU)

Definition at line 4099 of file MIMXRT1052.h.

◆ CAN_GFWR_GFWR_SHIFT

#define CAN_GFWR_GFWR_SHIFT   (0U)

Definition at line 4100 of file MIMXRT1052.h.

◆ CAN_ID_COUNT

#define CAN_ID_COUNT   (64U)

Definition at line 4027 of file MIMXRT1052.h.

◆ CAN_ID_EXT

#define CAN_ID_EXT (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

EXT - Contains extended (LOW word) identifier of message buffer.

Definition at line 4011 of file MIMXRT1052.h.

◆ CAN_ID_EXT_MASK

#define CAN_ID_EXT_MASK   (0x3FFFFU)

Definition at line 4007 of file MIMXRT1052.h.

◆ CAN_ID_EXT_SHIFT

#define CAN_ID_EXT_SHIFT   (0U)

Definition at line 4008 of file MIMXRT1052.h.

◆ CAN_ID_PRIO

#define CAN_ID_PRIO (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

Definition at line 4023 of file MIMXRT1052.h.

◆ CAN_ID_PRIO_MASK

#define CAN_ID_PRIO_MASK   (0xE0000000U)

Definition at line 4017 of file MIMXRT1052.h.

◆ CAN_ID_PRIO_SHIFT

#define CAN_ID_PRIO_SHIFT   (29U)

Definition at line 4018 of file MIMXRT1052.h.

◆ CAN_ID_STD

#define CAN_ID_STD (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

STD - Contains standard/extended (HIGH word) identifier of message buffer.

Definition at line 4016 of file MIMXRT1052.h.

◆ CAN_ID_STD_MASK

#define CAN_ID_STD_MASK   (0x1FFC0000U)

Definition at line 4012 of file MIMXRT1052.h.

◆ CAN_ID_STD_SHIFT

#define CAN_ID_STD_SHIFT   (18U)

Definition at line 4013 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF31TO8I

#define CAN_IFLAG1_BUF31TO8I (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception 0b000000000000000000000000..No such occurrence

Definition at line 3833 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF31TO8I_MASK

#define CAN_IFLAG1_BUF31TO8I_MASK   (0xFFFFFF00U)

Definition at line 3827 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF31TO8I_SHIFT

#define CAN_IFLAG1_BUF31TO8I_SHIFT   (8U)

Definition at line 3828 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF4TO0I

#define CAN_IFLAG1_BUF4TO0I (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)

BUF4TO0I 0b00001..Corresponding MB completed transmission/reception 0b00000..No such occurrence

Definition at line 3805 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF4TO0I_MASK

#define CAN_IFLAG1_BUF4TO0I_MASK   (0x1FU)

Definition at line 3799 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF4TO0I_SHIFT

#define CAN_IFLAG1_BUF4TO0I_SHIFT   (0U)

Definition at line 3800 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF5I

#define CAN_IFLAG1_BUF5I (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I 0b1..MB5 completed transmission/reception or frames available in the FIFO 0b0..No such occurrence

Definition at line 3812 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF5I_MASK

#define CAN_IFLAG1_BUF5I_MASK   (0x20U)

Definition at line 3806 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF5I_SHIFT

#define CAN_IFLAG1_BUF5I_SHIFT   (5U)

Definition at line 3807 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF6I

#define CAN_IFLAG1_BUF6I (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I 0b1..MB6 completed transmission/reception or FIFO almost full 0b0..No such occurrence

Definition at line 3819 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF6I_MASK

#define CAN_IFLAG1_BUF6I_MASK   (0x40U)

Definition at line 3813 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF6I_SHIFT

#define CAN_IFLAG1_BUF6I_SHIFT   (6U)

Definition at line 3814 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF7I

#define CAN_IFLAG1_BUF7I (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I 0b1..MB7 completed transmission/reception or FIFO overflow 0b0..No such occurrence

Definition at line 3826 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF7I_MASK

#define CAN_IFLAG1_BUF7I_MASK   (0x80U)

Definition at line 3820 of file MIMXRT1052.h.

◆ CAN_IFLAG1_BUF7I_SHIFT

#define CAN_IFLAG1_BUF7I_SHIFT   (7U)

Definition at line 3821 of file MIMXRT1052.h.

◆ CAN_IFLAG2_BUFHI

#define CAN_IFLAG2_BUFHI (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)

BUFHI 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception 0b00000000000000000000000000000000..No such occurrence

Definition at line 3794 of file MIMXRT1052.h.

◆ CAN_IFLAG2_BUFHI_MASK

#define CAN_IFLAG2_BUFHI_MASK   (0xFFFFFFFFU)

Definition at line 3788 of file MIMXRT1052.h.

◆ CAN_IFLAG2_BUFHI_SHIFT

#define CAN_IFLAG2_BUFHI_SHIFT   (0U)

Definition at line 3789 of file MIMXRT1052.h.

◆ CAN_IMASK1_BUFLM

#define CAN_IMASK1_BUFLM (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)

BUFLM 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled

Definition at line 3783 of file MIMXRT1052.h.

◆ CAN_IMASK1_BUFLM_MASK

#define CAN_IMASK1_BUFLM_MASK   (0xFFFFFFFFU)

Definition at line 3777 of file MIMXRT1052.h.

◆ CAN_IMASK1_BUFLM_SHIFT

#define CAN_IMASK1_BUFLM_SHIFT   (0U)

Definition at line 3778 of file MIMXRT1052.h.

◆ CAN_IMASK2_BUFHM

#define CAN_IMASK2_BUFHM (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)

BUFHM 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled

Definition at line 3772 of file MIMXRT1052.h.

◆ CAN_IMASK2_BUFHM_MASK

#define CAN_IMASK2_BUFHM_MASK   (0xFFFFFFFFU)

Definition at line 3766 of file MIMXRT1052.h.

◆ CAN_IMASK2_BUFHM_SHIFT

#define CAN_IMASK2_BUFHM_SHIFT   (0U)

Definition at line 3767 of file MIMXRT1052.h.

◆ CAN_MCR_AEN

#define CAN_MCR_AEN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN 0b1..Abort enabled 0b0..Abort disabled

Definition at line 3377 of file MIMXRT1052.h.

◆ CAN_MCR_AEN_MASK

#define CAN_MCR_AEN_MASK   (0x1000U)

Definition at line 3371 of file MIMXRT1052.h.

◆ CAN_MCR_AEN_SHIFT

#define CAN_MCR_AEN_SHIFT   (12U)

Definition at line 3372 of file MIMXRT1052.h.

◆ CAN_MCR_FRZ

#define CAN_MCR_FRZ (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ 0b1..Enabled to enter Freeze Mode 0b0..Not enabled to enter Freeze Mode

Definition at line 3483 of file MIMXRT1052.h.

◆ CAN_MCR_FRZ_MASK

#define CAN_MCR_FRZ_MASK   (0x40000000U)

Definition at line 3477 of file MIMXRT1052.h.

◆ CAN_MCR_FRZ_SHIFT

#define CAN_MCR_FRZ_SHIFT   (30U)

Definition at line 3478 of file MIMXRT1052.h.

◆ CAN_MCR_FRZACK

#define CAN_MCR_FRZACK (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK 0b1..FLEXCAN in Freeze Mode, prescaler stopped 0b0..FLEXCAN not in Freeze Mode, prescaler running

Definition at line 3441 of file MIMXRT1052.h.

◆ CAN_MCR_FRZACK_MASK

#define CAN_MCR_FRZACK_MASK   (0x1000000U)

Definition at line 3435 of file MIMXRT1052.h.

◆ CAN_MCR_FRZACK_SHIFT

#define CAN_MCR_FRZACK_SHIFT   (24U)

Definition at line 3436 of file MIMXRT1052.h.

◆ CAN_MCR_HALT

#define CAN_MCR_HALT (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT 0b1..Enters Freeze Mode if the FRZ bit is asserted. 0b0..No Freeze Mode request.

Definition at line 3469 of file MIMXRT1052.h.

◆ CAN_MCR_HALT_MASK

#define CAN_MCR_HALT_MASK   (0x10000000U)

Definition at line 3463 of file MIMXRT1052.h.

◆ CAN_MCR_HALT_SHIFT

#define CAN_MCR_HALT_SHIFT   (28U)

Definition at line 3464 of file MIMXRT1052.h.

◆ CAN_MCR_IDAM

#define CAN_MCR_IDAM (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM 0b00..Format A One full ID (standard or extended) per ID filter Table element. 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. 0b11..Format D All frames rejected.

Definition at line 3370 of file MIMXRT1052.h.

◆ CAN_MCR_IDAM_MASK

#define CAN_MCR_IDAM_MASK   (0x300U)

Definition at line 3362 of file MIMXRT1052.h.

◆ CAN_MCR_IDAM_SHIFT

#define CAN_MCR_IDAM_SHIFT   (8U)

Definition at line 3363 of file MIMXRT1052.h.

◆ CAN_MCR_IRMQ

#define CAN_MCR_IRMQ (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ 0b1..Individual Rx masking and queue feature are enabled. 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.

Definition at line 3391 of file MIMXRT1052.h.

◆ CAN_MCR_IRMQ_MASK

#define CAN_MCR_IRMQ_MASK   (0x10000U)

Definition at line 3385 of file MIMXRT1052.h.

◆ CAN_MCR_IRMQ_SHIFT

#define CAN_MCR_IRMQ_SHIFT   (16U)

Definition at line 3386 of file MIMXRT1052.h.

◆ CAN_MCR_LPMACK

#define CAN_MCR_LPMACK (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK 0b1..FLEXCAN is either in Disable Mode, or Stop mode 0b0..FLEXCAN not in any of the low power modes

Definition at line 3412 of file MIMXRT1052.h.

◆ CAN_MCR_LPMACK_MASK

#define CAN_MCR_LPMACK_MASK   (0x100000U)

Definition at line 3406 of file MIMXRT1052.h.

◆ CAN_MCR_LPMACK_SHIFT

#define CAN_MCR_LPMACK_SHIFT   (20U)

Definition at line 3407 of file MIMXRT1052.h.

◆ CAN_MCR_LPRIOEN

#define CAN_MCR_LPRIOEN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN 0b1..Local Priority enabled 0b0..Local Priority disabled

Definition at line 3384 of file MIMXRT1052.h.

◆ CAN_MCR_LPRIOEN_MASK

#define CAN_MCR_LPRIOEN_MASK   (0x2000U)

Definition at line 3378 of file MIMXRT1052.h.

◆ CAN_MCR_LPRIOEN_SHIFT

#define CAN_MCR_LPRIOEN_SHIFT   (13U)

Definition at line 3379 of file MIMXRT1052.h.

◆ CAN_MCR_MAXMB

#define CAN_MCR_MAXMB (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)

Definition at line 3361 of file MIMXRT1052.h.

◆ CAN_MCR_MAXMB_MASK

#define CAN_MCR_MAXMB_MASK   (0x7FU)

Definition at line 3359 of file MIMXRT1052.h.

◆ CAN_MCR_MAXMB_SHIFT

#define CAN_MCR_MAXMB_SHIFT   (0U)

Definition at line 3360 of file MIMXRT1052.h.

◆ CAN_MCR_MDIS

#define CAN_MCR_MDIS (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS 0b1..Disable the FLEXCAN module 0b0..Enable the FLEXCAN module

Definition at line 3490 of file MIMXRT1052.h.

◆ CAN_MCR_MDIS_MASK

#define CAN_MCR_MDIS_MASK   (0x80000000U)

Definition at line 3484 of file MIMXRT1052.h.

◆ CAN_MCR_MDIS_SHIFT

#define CAN_MCR_MDIS_SHIFT   (31U)

Definition at line 3485 of file MIMXRT1052.h.

◆ CAN_MCR_NOTRDY

#define CAN_MCR_NOTRDY (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode

Definition at line 3462 of file MIMXRT1052.h.

◆ CAN_MCR_NOTRDY_MASK

#define CAN_MCR_NOTRDY_MASK   (0x8000000U)

Definition at line 3456 of file MIMXRT1052.h.

◆ CAN_MCR_NOTRDY_SHIFT

#define CAN_MCR_NOTRDY_SHIFT   (27U)

Definition at line 3457 of file MIMXRT1052.h.

◆ CAN_MCR_RFEN

#define CAN_MCR_RFEN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN 0b1..FIFO enabled 0b0..FIFO not enabled

Definition at line 3476 of file MIMXRT1052.h.

◆ CAN_MCR_RFEN_MASK

#define CAN_MCR_RFEN_MASK   (0x20000000U)

Definition at line 3470 of file MIMXRT1052.h.

◆ CAN_MCR_RFEN_SHIFT

#define CAN_MCR_RFEN_SHIFT   (29U)

Definition at line 3471 of file MIMXRT1052.h.

◆ CAN_MCR_SLFWAK

#define CAN_MCR_SLFWAK (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK 0b1..FLEXCAN Self Wake Up feature is enabled 0b0..FLEXCAN Self Wake Up feature is disabled

Definition at line 3426 of file MIMXRT1052.h.

◆ CAN_MCR_SLFWAK_MASK

#define CAN_MCR_SLFWAK_MASK   (0x400000U)

Definition at line 3420 of file MIMXRT1052.h.

◆ CAN_MCR_SLFWAK_SHIFT

#define CAN_MCR_SLFWAK_SHIFT   (22U)

Definition at line 3421 of file MIMXRT1052.h.

◆ CAN_MCR_SOFTRST

#define CAN_MCR_SOFTRST (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST 0b1..Reset the registers 0b0..No reset request

Definition at line 3448 of file MIMXRT1052.h.

◆ CAN_MCR_SOFTRST_MASK

#define CAN_MCR_SOFTRST_MASK   (0x2000000U)

Definition at line 3442 of file MIMXRT1052.h.

◆ CAN_MCR_SOFTRST_SHIFT

#define CAN_MCR_SOFTRST_SHIFT   (25U)

Definition at line 3443 of file MIMXRT1052.h.

◆ CAN_MCR_SRXDIS

#define CAN_MCR_SRXDIS (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS 0b1..Self reception disabled 0b0..Self reception enabled

Definition at line 3398 of file MIMXRT1052.h.

◆ CAN_MCR_SRXDIS_MASK

#define CAN_MCR_SRXDIS_MASK   (0x20000U)

Definition at line 3392 of file MIMXRT1052.h.

◆ CAN_MCR_SRXDIS_SHIFT

#define CAN_MCR_SRXDIS_SHIFT   (17U)

Definition at line 3393 of file MIMXRT1052.h.

◆ CAN_MCR_SUPV

#define CAN_MCR_SUPV (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses

Definition at line 3434 of file MIMXRT1052.h.

◆ CAN_MCR_SUPV_MASK

#define CAN_MCR_SUPV_MASK   (0x800000U)

Definition at line 3427 of file MIMXRT1052.h.

◆ CAN_MCR_SUPV_SHIFT

#define CAN_MCR_SUPV_SHIFT   (23U)

Definition at line 3428 of file MIMXRT1052.h.

◆ CAN_MCR_WAKMSK

#define CAN_MCR_WAKMSK (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK 0b1..Wake Up Interrupt is enabled 0b0..Wake Up Interrupt is disabled

Definition at line 3455 of file MIMXRT1052.h.

◆ CAN_MCR_WAKMSK_MASK

#define CAN_MCR_WAKMSK_MASK   (0x4000000U)

Definition at line 3449 of file MIMXRT1052.h.

◆ CAN_MCR_WAKMSK_SHIFT

#define CAN_MCR_WAKMSK_SHIFT   (26U)

Definition at line 3450 of file MIMXRT1052.h.

◆ CAN_MCR_WAKSRC

#define CAN_MCR_WAKSRC (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.

Definition at line 3405 of file MIMXRT1052.h.

◆ CAN_MCR_WAKSRC_MASK

#define CAN_MCR_WAKSRC_MASK   (0x80000U)

Definition at line 3399 of file MIMXRT1052.h.

◆ CAN_MCR_WAKSRC_SHIFT

#define CAN_MCR_WAKSRC_SHIFT   (19U)

Definition at line 3400 of file MIMXRT1052.h.

◆ CAN_MCR_WRNEN

#define CAN_MCR_WRNEN (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.

Definition at line 3419 of file MIMXRT1052.h.

◆ CAN_MCR_WRNEN_MASK

#define CAN_MCR_WRNEN_MASK   (0x200000U)

Definition at line 3413 of file MIMXRT1052.h.

◆ CAN_MCR_WRNEN_SHIFT

#define CAN_MCR_WRNEN_SHIFT   (21U)

Definition at line 3414 of file MIMXRT1052.h.

◆ CAN_RX14MASK_RX14M

#define CAN_RX14MASK_RX14M (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M 0b00000000000000000000000000000001..The corresponding bit in the filter is checked 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"

Definition at line 3609 of file MIMXRT1052.h.

◆ CAN_RX14MASK_RX14M_MASK

#define CAN_RX14MASK_RX14M_MASK   (0xFFFFFFFFU)

Definition at line 3603 of file MIMXRT1052.h.

◆ CAN_RX14MASK_RX14M_SHIFT

#define CAN_RX14MASK_RX14M_SHIFT   (0U)

Definition at line 3604 of file MIMXRT1052.h.

◆ CAN_RX15MASK_RX15M

#define CAN_RX15MASK_RX15M (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M 0b00000000000000000000000000000001..The corresponding bit in the filter is checked 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"

Definition at line 3620 of file MIMXRT1052.h.

◆ CAN_RX15MASK_RX15M_MASK

#define CAN_RX15MASK_RX15M_MASK   (0xFFFFFFFFU)

Definition at line 3614 of file MIMXRT1052.h.

◆ CAN_RX15MASK_RX15M_SHIFT

#define CAN_RX15MASK_RX15M_SHIFT   (0U)

Definition at line 3615 of file MIMXRT1052.h.

◆ CAN_RXFGMASK_FGM

#define CAN_RXFGMASK_FGM (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM 0b00000000000000000000000000000001..The corresponding bit in the filter is checked 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"

Definition at line 3914 of file MIMXRT1052.h.

◆ CAN_RXFGMASK_FGM_MASK

#define CAN_RXFGMASK_FGM_MASK   (0xFFFFFFFFU)

Definition at line 3908 of file MIMXRT1052.h.

◆ CAN_RXFGMASK_FGM_SHIFT

#define CAN_RXFGMASK_FGM_SHIFT   (0U)

Definition at line 3909 of file MIMXRT1052.h.

◆ CAN_RXFIR_IDHIT

#define CAN_RXFIR_IDHIT (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)

Definition at line 3921 of file MIMXRT1052.h.

◆ CAN_RXFIR_IDHIT_MASK

#define CAN_RXFIR_IDHIT_MASK   (0x1FFU)

Definition at line 3919 of file MIMXRT1052.h.

◆ CAN_RXFIR_IDHIT_SHIFT

#define CAN_RXFIR_IDHIT_SHIFT   (0U)

Definition at line 3920 of file MIMXRT1052.h.

◆ CAN_RXIMR_COUNT

#define CAN_RXIMR_COUNT   (64U)

Definition at line 4095 of file MIMXRT1052.h.

◆ CAN_RXIMR_MI

#define CAN_RXIMR_MI (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI 0b00000000000000000000000000000001..The corresponding bit in the filter is checked 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"

Definition at line 4091 of file MIMXRT1052.h.

◆ CAN_RXIMR_MI_MASK

#define CAN_RXIMR_MI_MASK   (0xFFFFFFFFU)

Definition at line 4085 of file MIMXRT1052.h.

◆ CAN_RXIMR_MI_SHIFT

#define CAN_RXIMR_MI_SHIFT   (0U)

Definition at line 4086 of file MIMXRT1052.h.

◆ CAN_RXMGMASK_MG

#define CAN_RXMGMASK_MG (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"

Definition at line 3598 of file MIMXRT1052.h.

◆ CAN_RXMGMASK_MG_MASK

#define CAN_RXMGMASK_MG_MASK   (0xFFFFFFFFU)

Definition at line 3592 of file MIMXRT1052.h.

◆ CAN_RXMGMASK_MG_SHIFT

#define CAN_RXMGMASK_MG_SHIFT   (0U)

Definition at line 3593 of file MIMXRT1052.h.

◆ CAN_TIMER_TIMER

#define CAN_TIMER_TIMER (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)

Definition at line 3587 of file MIMXRT1052.h.

◆ CAN_TIMER_TIMER_MASK

#define CAN_TIMER_TIMER_MASK   (0xFFFFU)

Definition at line 3585 of file MIMXRT1052.h.

◆ CAN_TIMER_TIMER_SHIFT

#define CAN_TIMER_TIMER_SHIFT   (0U)

Definition at line 3586 of file MIMXRT1052.h.

◆ CAN_WORD0_COUNT

#define CAN_WORD0_COUNT   (64U)

Definition at line 4054 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_0

#define CAN_WORD0_DATA_BYTE_0 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)

DATA_BYTE_0 - Data byte 0 of Rx/Tx frame.

Definition at line 4050 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_0_MASK

#define CAN_WORD0_DATA_BYTE_0_MASK   (0xFF000000U)

Definition at line 4046 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_0_SHIFT

#define CAN_WORD0_DATA_BYTE_0_SHIFT   (24U)

Definition at line 4047 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_1

#define CAN_WORD0_DATA_BYTE_1 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

DATA_BYTE_1 - Data byte 1 of Rx/Tx frame.

Definition at line 4045 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_1_MASK

#define CAN_WORD0_DATA_BYTE_1_MASK   (0xFF0000U)

Definition at line 4041 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_1_SHIFT

#define CAN_WORD0_DATA_BYTE_1_SHIFT   (16U)

Definition at line 4042 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_2

#define CAN_WORD0_DATA_BYTE_2 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

DATA_BYTE_2 - Data byte 2 of Rx/Tx frame.

Definition at line 4040 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_2_MASK

#define CAN_WORD0_DATA_BYTE_2_MASK   (0xFF00U)

Definition at line 4036 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_2_SHIFT

#define CAN_WORD0_DATA_BYTE_2_SHIFT   (8U)

Definition at line 4037 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_3

#define CAN_WORD0_DATA_BYTE_3 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

DATA_BYTE_3 - Data byte 3 of Rx/Tx frame.

Definition at line 4035 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_3_MASK

#define CAN_WORD0_DATA_BYTE_3_MASK   (0xFFU)

Definition at line 4031 of file MIMXRT1052.h.

◆ CAN_WORD0_DATA_BYTE_3_SHIFT

#define CAN_WORD0_DATA_BYTE_3_SHIFT   (0U)

Definition at line 4032 of file MIMXRT1052.h.

◆ CAN_WORD1_COUNT

#define CAN_WORD1_COUNT   (64U)

Definition at line 4081 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_4

#define CAN_WORD1_DATA_BYTE_4 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)

DATA_BYTE_4 - Data byte 4 of Rx/Tx frame.

Definition at line 4077 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_4_MASK

#define CAN_WORD1_DATA_BYTE_4_MASK   (0xFF000000U)

Definition at line 4073 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_4_SHIFT

#define CAN_WORD1_DATA_BYTE_4_SHIFT   (24U)

Definition at line 4074 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_5

#define CAN_WORD1_DATA_BYTE_5 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

DATA_BYTE_5 - Data byte 5 of Rx/Tx frame.

Definition at line 4072 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_5_MASK

#define CAN_WORD1_DATA_BYTE_5_MASK   (0xFF0000U)

Definition at line 4068 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_5_SHIFT

#define CAN_WORD1_DATA_BYTE_5_SHIFT   (16U)

Definition at line 4069 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_6

#define CAN_WORD1_DATA_BYTE_6 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

DATA_BYTE_6 - Data byte 6 of Rx/Tx frame.

Definition at line 4067 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_6_MASK

#define CAN_WORD1_DATA_BYTE_6_MASK   (0xFF00U)

Definition at line 4063 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_6_SHIFT

#define CAN_WORD1_DATA_BYTE_6_SHIFT   (8U)

Definition at line 4064 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_7

#define CAN_WORD1_DATA_BYTE_7 (   x)    (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

DATA_BYTE_7 - Data byte 7 of Rx/Tx frame.

Definition at line 4062 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_7_MASK

#define CAN_WORD1_DATA_BYTE_7_MASK   (0xFFU)

Definition at line 4058 of file MIMXRT1052.h.

◆ CAN_WORD1_DATA_BYTE_7_SHIFT

#define CAN_WORD1_DATA_BYTE_7_SHIFT   (0U)

Definition at line 4059 of file MIMXRT1052.h.

◆ ENC_CTRL2_DIR

#define ENC_CTRL2_DIR (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

Definition at line 15468 of file MIMXRT1052.h.

◆ ENC_CTRL2_DIR_MASK

#define ENC_CTRL2_DIR_MASK   (0x8U)

Definition at line 15462 of file MIMXRT1052.h.

◆ ENC_CTRL2_DIR_SHIFT

#define ENC_CTRL2_DIR_SHIFT   (3U)

Definition at line 15463 of file MIMXRT1052.h.

◆ ENC_CTRL2_MOD

#define ENC_CTRL2_MOD (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

Definition at line 15461 of file MIMXRT1052.h.

◆ ENC_CTRL2_MOD_MASK

#define ENC_CTRL2_MOD_MASK   (0x4U)

Definition at line 15455 of file MIMXRT1052.h.

◆ ENC_CTRL2_MOD_SHIFT

#define ENC_CTRL2_MOD_SHIFT   (2U)

Definition at line 15456 of file MIMXRT1052.h.

◆ ENC_CTRL2_OUTCTL

#define ENC_CTRL2_OUTCTL (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.

Definition at line 15510 of file MIMXRT1052.h.

◆ ENC_CTRL2_OUTCTL_MASK

#define ENC_CTRL2_OUTCTL_MASK   (0x200U)

Definition at line 15504 of file MIMXRT1052.h.

◆ ENC_CTRL2_OUTCTL_SHIFT

#define ENC_CTRL2_OUTCTL_SHIFT   (9U)

Definition at line 15505 of file MIMXRT1052.h.

◆ ENC_CTRL2_REVMOD

#define ENC_CTRL2_REVMOD (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV).

Definition at line 15503 of file MIMXRT1052.h.

◆ ENC_CTRL2_REVMOD_MASK

#define ENC_CTRL2_REVMOD_MASK   (0x100U)

Definition at line 15497 of file MIMXRT1052.h.

◆ ENC_CTRL2_REVMOD_SHIFT

#define ENC_CTRL2_REVMOD_SHIFT   (8U)

Definition at line 15498 of file MIMXRT1052.h.

◆ ENC_CTRL2_ROIE

#define ENC_CTRL2_ROIE (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Roll-over interrupt is disabled 0b1..Roll-over interrupt is enabled

Definition at line 15489 of file MIMXRT1052.h.

◆ ENC_CTRL2_ROIE_MASK

#define ENC_CTRL2_ROIE_MASK   (0x40U)

Definition at line 15483 of file MIMXRT1052.h.

◆ ENC_CTRL2_ROIE_SHIFT

#define ENC_CTRL2_ROIE_SHIFT   (6U)

Definition at line 15484 of file MIMXRT1052.h.

◆ ENC_CTRL2_ROIRQ

#define ENC_CTRL2_ROIRQ (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

Definition at line 15496 of file MIMXRT1052.h.

◆ ENC_CTRL2_ROIRQ_MASK

#define ENC_CTRL2_ROIRQ_MASK   (0x80U)

Definition at line 15490 of file MIMXRT1052.h.

◆ ENC_CTRL2_ROIRQ_SHIFT

#define ENC_CTRL2_ROIRQ_SHIFT   (7U)

Definition at line 15491 of file MIMXRT1052.h.

◆ ENC_CTRL2_RUIE

#define ENC_CTRL2_RUIE (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Roll-under interrupt is disabled 0b1..Roll-under interrupt is enabled

Definition at line 15475 of file MIMXRT1052.h.

◆ ENC_CTRL2_RUIE_MASK

#define ENC_CTRL2_RUIE_MASK   (0x10U)

Definition at line 15469 of file MIMXRT1052.h.

◆ ENC_CTRL2_RUIE_SHIFT

#define ENC_CTRL2_RUIE_SHIFT   (4U)

Definition at line 15470 of file MIMXRT1052.h.

◆ ENC_CTRL2_RUIRQ

#define ENC_CTRL2_RUIRQ (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

Definition at line 15482 of file MIMXRT1052.h.

◆ ENC_CTRL2_RUIRQ_MASK

#define ENC_CTRL2_RUIRQ_MASK   (0x20U)

Definition at line 15476 of file MIMXRT1052.h.

◆ ENC_CTRL2_RUIRQ_SHIFT

#define ENC_CTRL2_RUIRQ_SHIFT   (5U)

Definition at line 15477 of file MIMXRT1052.h.

◆ ENC_CTRL2_SABIE

#define ENC_CTRL2_SABIE (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled.

Definition at line 15517 of file MIMXRT1052.h.

◆ ENC_CTRL2_SABIE_MASK

#define ENC_CTRL2_SABIE_MASK   (0x400U)

Definition at line 15511 of file MIMXRT1052.h.

◆ ENC_CTRL2_SABIE_SHIFT

#define ENC_CTRL2_SABIE_SHIFT   (10U)

Definition at line 15512 of file MIMXRT1052.h.

◆ ENC_CTRL2_SABIRQ

#define ENC_CTRL2_SABIRQ (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request 0b0..No simultaneous change of PHASEA and PHASEB has occurred. 0b1..A simultaneous change of PHASEA and PHASEB has occurred.

Definition at line 15524 of file MIMXRT1052.h.

◆ ENC_CTRL2_SABIRQ_MASK

#define ENC_CTRL2_SABIRQ_MASK   (0x800U)

Definition at line 15518 of file MIMXRT1052.h.

◆ ENC_CTRL2_SABIRQ_SHIFT

#define ENC_CTRL2_SABIRQ_SHIFT   (11U)

Definition at line 15519 of file MIMXRT1052.h.

◆ ENC_CTRL2_UPDHLD

#define ENC_CTRL2_UPDHLD (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on rising edge of TRIGGER 0b1..Enable updates of hold registers on rising edge of TRIGGER

Definition at line 15447 of file MIMXRT1052.h.

◆ ENC_CTRL2_UPDHLD_MASK

#define ENC_CTRL2_UPDHLD_MASK   (0x1U)

Definition at line 15441 of file MIMXRT1052.h.

◆ ENC_CTRL2_UPDHLD_SHIFT

#define ENC_CTRL2_UPDHLD_SHIFT   (0U)

Definition at line 15442 of file MIMXRT1052.h.

◆ ENC_CTRL2_UPDPOS

#define ENC_CTRL2_UPDPOS (   x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER

Definition at line 15454 of file MIMXRT1052.h.

◆ ENC_CTRL2_UPDPOS_MASK

#define ENC_CTRL2_UPDPOS_MASK   (0x2U)

Definition at line 15448 of file MIMXRT1052.h.

◆ ENC_CTRL2_UPDPOS_SHIFT

#define ENC_CTRL2_UPDPOS_SHIFT   (1U)

Definition at line 15449 of file MIMXRT1052.h.

◆ PWM_CTRL2_CLK_SEL

#define PWM_CTRL2_CLK_SEL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

CLK_SEL - Clock Source Select 0b00..The IPBus clock is used as the clock for the local prescaler and counter. 0b01..EXT_CLK is used as the clock for the local prescaler and counter. 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0b11..reserved

Definition at line 30947 of file MIMXRT1052.h.

◆ PWM_CTRL2_CLK_SEL_MASK

#define PWM_CTRL2_CLK_SEL_MASK   (0x3U)

Definition at line 30938 of file MIMXRT1052.h.

◆ PWM_CTRL2_CLK_SEL_SHIFT

#define PWM_CTRL2_CLK_SEL_SHIFT   (0U)

Definition at line 30939 of file MIMXRT1052.h.

◆ PWM_CTRL2_DBGEN

#define PWM_CTRL2_DBGEN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)

DBGEN - Debug Enable

Definition at line 31027 of file MIMXRT1052.h.

◆ PWM_CTRL2_DBGEN_MASK

#define PWM_CTRL2_DBGEN_MASK   (0x8000U)

Definition at line 31023 of file MIMXRT1052.h.

◆ PWM_CTRL2_DBGEN_SHIFT

#define PWM_CTRL2_DBGEN_SHIFT   (15U)

Definition at line 31024 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE

#define PWM_CTRL2_FORCE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

FORCE - Force Initialization

Definition at line 30976 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_MASK

#define PWM_CTRL2_FORCE_MASK   (0x40U)

Definition at line 30972 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_SEL

#define PWM_CTRL2_FORCE_SEL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b100..The local sync signal from this submodule is used to force updates. 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.

Definition at line 30971 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_SEL_MASK

#define PWM_CTRL2_FORCE_SEL_MASK   (0x38U)

Definition at line 30956 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_SEL_SHIFT

#define PWM_CTRL2_FORCE_SEL_SHIFT   (3U)

Definition at line 30957 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_SHIFT

#define PWM_CTRL2_FORCE_SHIFT   (6U)

Definition at line 30973 of file MIMXRT1052.h.

◆ PWM_CTRL2_FRCEN

#define PWM_CTRL2_FRCEN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

FRCEN - FRCEN 0b0..Initialization from a FORCE_OUT is disabled. 0b1..Initialization from a FORCE_OUT is enabled.

Definition at line 30983 of file MIMXRT1052.h.

◆ PWM_CTRL2_FRCEN_MASK

#define PWM_CTRL2_FRCEN_MASK   (0x80U)

Definition at line 30977 of file MIMXRT1052.h.

◆ PWM_CTRL2_FRCEN_SHIFT

#define PWM_CTRL2_FRCEN_SHIFT   (7U)

Definition at line 30978 of file MIMXRT1052.h.

◆ PWM_CTRL2_INDEP

#define PWM_CTRL2_INDEP (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

INDEP - Independent or Complementary Pair Operation 0b0..PWM_A and PWM_B form a complementary PWM pair. 0b1..PWM_A and PWM_B outputs are independent PWMs.

Definition at line 31017 of file MIMXRT1052.h.

◆ PWM_CTRL2_INDEP_MASK

#define PWM_CTRL2_INDEP_MASK   (0x2000U)

Definition at line 31011 of file MIMXRT1052.h.

◆ PWM_CTRL2_INDEP_SHIFT

#define PWM_CTRL2_INDEP_SHIFT   (13U)

Definition at line 31012 of file MIMXRT1052.h.

◆ PWM_CTRL2_INIT_SEL

#define PWM_CTRL2_INIT_SEL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

INIT_SEL - Initialization Control Select 0b00..Local sync (PWM_X) causes initialization. 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0b11..EXT_SYNC causes initialization.

Definition at line 30995 of file MIMXRT1052.h.

◆ PWM_CTRL2_INIT_SEL_MASK

#define PWM_CTRL2_INIT_SEL_MASK   (0x300U)

Definition at line 30984 of file MIMXRT1052.h.

◆ PWM_CTRL2_INIT_SEL_SHIFT

#define PWM_CTRL2_INIT_SEL_SHIFT   (8U)

Definition at line 30985 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM23_INIT

#define PWM_CTRL2_PWM23_INIT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

PWM23_INIT - PWM23 Initial Value

Definition at line 31010 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM23_INIT_MASK

#define PWM_CTRL2_PWM23_INIT_MASK   (0x1000U)

Definition at line 31006 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM23_INIT_SHIFT

#define PWM_CTRL2_PWM23_INIT_SHIFT   (12U)

Definition at line 31007 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM45_INIT

#define PWM_CTRL2_PWM45_INIT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

PWM45_INIT - PWM45 Initial Value

Definition at line 31005 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM45_INIT_MASK

#define PWM_CTRL2_PWM45_INIT_MASK   (0x800U)

Definition at line 31001 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM45_INIT_SHIFT

#define PWM_CTRL2_PWM45_INIT_SHIFT   (11U)

Definition at line 31002 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWMX_INIT

#define PWM_CTRL2_PWMX_INIT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

PWMX_INIT - PWM_X Initial Value

Definition at line 31000 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWMX_INIT_MASK

#define PWM_CTRL2_PWMX_INIT_MASK   (0x400U)

Definition at line 30996 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWMX_INIT_SHIFT

#define PWM_CTRL2_PWMX_INIT_SHIFT   (10U)

Definition at line 30997 of file MIMXRT1052.h.

◆ PWM_CTRL2_RELOAD_SEL

#define PWM_CTRL2_RELOAD_SEL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

RELOAD_SEL - Reload Source Select 0b0..The local RELOAD signal is used to reload registers. 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.

Definition at line 30955 of file MIMXRT1052.h.

◆ PWM_CTRL2_RELOAD_SEL_MASK

#define PWM_CTRL2_RELOAD_SEL_MASK   (0x4U)

Definition at line 30948 of file MIMXRT1052.h.

◆ PWM_CTRL2_RELOAD_SEL_SHIFT

#define PWM_CTRL2_RELOAD_SEL_SHIFT   (2U)

Definition at line 30949 of file MIMXRT1052.h.

◆ PWM_CTRL2_WAITEN

#define PWM_CTRL2_WAITEN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

WAITEN - WAIT Enable

Definition at line 31022 of file MIMXRT1052.h.

◆ PWM_CTRL2_WAITEN_MASK

#define PWM_CTRL2_WAITEN_MASK   (0x4000U)

Definition at line 31018 of file MIMXRT1052.h.

◆ PWM_CTRL2_WAITEN_SHIFT

#define PWM_CTRL2_WAITEN_SHIFT   (14U)

Definition at line 31019 of file MIMXRT1052.h.


picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:09