ENET Register Masks

Collaboration diagram for ENET Register Masks:

Macros
#define	ENET_TCCR_COUNT   (4U)
#define	ENET_TCSR_COUNT   (4U)

EIR - Interrupt Event Register
#define	ENET_EIR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define	ENET_EIR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define	ENET_EIR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIR_WAKEUP_SHIFT   (17U)
#define	ENET_EIR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define	ENET_EIR_PLR_MASK   (0x40000U)
#define	ENET_EIR_PLR_SHIFT   (18U)
#define	ENET_EIR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define	ENET_EIR_UN_MASK   (0x80000U)
#define	ENET_EIR_UN_SHIFT   (19U)
#define	ENET_EIR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define	ENET_EIR_RL_MASK   (0x100000U)
#define	ENET_EIR_RL_SHIFT   (20U)
#define	ENET_EIR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define	ENET_EIR_LC_MASK   (0x200000U)
#define	ENET_EIR_LC_SHIFT   (21U)
#define	ENET_EIR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define	ENET_EIR_EBERR_MASK   (0x400000U)
#define	ENET_EIR_EBERR_SHIFT   (22U)
#define	ENET_EIR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define	ENET_EIR_MII_MASK   (0x800000U)
#define	ENET_EIR_MII_SHIFT   (23U)
#define	ENET_EIR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define	ENET_EIR_RXB_MASK   (0x1000000U)
#define	ENET_EIR_RXB_SHIFT   (24U)
#define	ENET_EIR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define	ENET_EIR_RXF_MASK   (0x2000000U)
#define	ENET_EIR_RXF_SHIFT   (25U)
#define	ENET_EIR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define	ENET_EIR_TXB_MASK   (0x4000000U)
#define	ENET_EIR_TXB_SHIFT   (26U)
#define	ENET_EIR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define	ENET_EIR_TXF_MASK   (0x8000000U)
#define	ENET_EIR_TXF_SHIFT   (27U)
#define	ENET_EIR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define	ENET_EIR_GRA_MASK   (0x10000000U)
#define	ENET_EIR_GRA_SHIFT   (28U)
#define	ENET_EIR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define	ENET_EIR_BABT_MASK   (0x20000000U)
#define	ENET_EIR_BABT_SHIFT   (29U)
#define	ENET_EIR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define	ENET_EIR_BABR_MASK   (0x40000000U)
#define	ENET_EIR_BABR_SHIFT   (30U)
#define	ENET_EIR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

EIMR - Interrupt Mask Register
#define	ENET_EIMR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIMR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIMR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define	ENET_EIMR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIMR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIMR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define	ENET_EIMR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIMR_WAKEUP_SHIFT   (17U)
#define	ENET_EIMR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define	ENET_EIMR_PLR_MASK   (0x40000U)
#define	ENET_EIMR_PLR_SHIFT   (18U)
#define	ENET_EIMR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define	ENET_EIMR_UN_MASK   (0x80000U)
#define	ENET_EIMR_UN_SHIFT   (19U)
#define	ENET_EIMR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define	ENET_EIMR_RL_MASK   (0x100000U)
#define	ENET_EIMR_RL_SHIFT   (20U)
#define	ENET_EIMR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define	ENET_EIMR_LC_MASK   (0x200000U)
#define	ENET_EIMR_LC_SHIFT   (21U)
#define	ENET_EIMR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define	ENET_EIMR_EBERR_MASK   (0x400000U)
#define	ENET_EIMR_EBERR_SHIFT   (22U)
#define	ENET_EIMR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define	ENET_EIMR_MII_MASK   (0x800000U)
#define	ENET_EIMR_MII_SHIFT   (23U)
#define	ENET_EIMR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define	ENET_EIMR_RXB_MASK   (0x1000000U)
#define	ENET_EIMR_RXB_SHIFT   (24U)
#define	ENET_EIMR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define	ENET_EIMR_RXF_MASK   (0x2000000U)
#define	ENET_EIMR_RXF_SHIFT   (25U)
#define	ENET_EIMR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define	ENET_EIMR_TXB_MASK   (0x4000000U)
#define	ENET_EIMR_TXB_SHIFT   (26U)
#define	ENET_EIMR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define	ENET_EIMR_TXF_MASK   (0x8000000U)
#define	ENET_EIMR_TXF_SHIFT   (27U)
#define	ENET_EIMR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define	ENET_EIMR_GRA_MASK   (0x10000000U)
#define	ENET_EIMR_GRA_SHIFT   (28U)
#define	ENET_EIMR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define	ENET_EIMR_BABT_MASK   (0x20000000U)
#define	ENET_EIMR_BABT_SHIFT   (29U)
#define	ENET_EIMR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define	ENET_EIMR_BABR_MASK   (0x40000000U)
#define	ENET_EIMR_BABR_SHIFT   (30U)
#define	ENET_EIMR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

RDAR - Receive Descriptor Active Register
#define	ENET_RDAR_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR_RDAR_SHIFT   (24U)
#define	ENET_RDAR_RDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

TDAR - Transmit Descriptor Active Register
#define	ENET_TDAR_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR_TDAR_SHIFT   (24U)
#define	ENET_TDAR_TDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)

ECR - Ethernet Control Register
#define	ENET_ECR_RESET_MASK   (0x1U)
#define	ENET_ECR_RESET_SHIFT   (0U)
#define	ENET_ECR_RESET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define	ENET_ECR_ETHEREN_MASK   (0x2U)
#define	ENET_ECR_ETHEREN_SHIFT   (1U)
#define	ENET_ECR_ETHEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define	ENET_ECR_MAGICEN_MASK   (0x4U)
#define	ENET_ECR_MAGICEN_SHIFT   (2U)
#define	ENET_ECR_MAGICEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define	ENET_ECR_SLEEP_MASK   (0x8U)
#define	ENET_ECR_SLEEP_SHIFT   (3U)
#define	ENET_ECR_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define	ENET_ECR_EN1588_MASK   (0x10U)
#define	ENET_ECR_EN1588_SHIFT   (4U)
#define	ENET_ECR_EN1588(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define	ENET_ECR_DBGEN_MASK   (0x40U)
#define	ENET_ECR_DBGEN_SHIFT   (6U)
#define	ENET_ECR_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define	ENET_ECR_DBSWP_MASK   (0x100U)
#define	ENET_ECR_DBSWP_SHIFT   (8U)
#define	ENET_ECR_DBSWP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

MMFR - MII Management Frame Register
#define	ENET_MMFR_DATA_MASK   (0xFFFFU)
#define	ENET_MMFR_DATA_SHIFT   (0U)
#define	ENET_MMFR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define	ENET_MMFR_TA_MASK   (0x30000U)
#define	ENET_MMFR_TA_SHIFT   (16U)
#define	ENET_MMFR_TA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define	ENET_MMFR_RA_MASK   (0x7C0000U)
#define	ENET_MMFR_RA_SHIFT   (18U)
#define	ENET_MMFR_RA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define	ENET_MMFR_PA_MASK   (0xF800000U)
#define	ENET_MMFR_PA_SHIFT   (23U)
#define	ENET_MMFR_PA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define	ENET_MMFR_OP_MASK   (0x30000000U)
#define	ENET_MMFR_OP_SHIFT   (28U)
#define	ENET_MMFR_OP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define	ENET_MMFR_ST_MASK   (0xC0000000U)
#define	ENET_MMFR_ST_SHIFT   (30U)
#define	ENET_MMFR_ST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

MSCR - MII Speed Control Register
#define	ENET_MSCR_MII_SPEED_MASK   (0x7EU)
#define	ENET_MSCR_MII_SPEED_SHIFT   (1U)
#define	ENET_MSCR_MII_SPEED(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define	ENET_MSCR_DIS_PRE_MASK   (0x80U)
#define	ENET_MSCR_DIS_PRE_SHIFT   (7U)
#define	ENET_MSCR_DIS_PRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define	ENET_MSCR_HOLDTIME_MASK   (0x700U)
#define	ENET_MSCR_HOLDTIME_SHIFT   (8U)
#define	ENET_MSCR_HOLDTIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

MIBC - MIB Control Register
#define	ENET_MIBC_MIB_CLEAR_MASK   (0x20000000U)
#define	ENET_MIBC_MIB_CLEAR_SHIFT   (29U)
#define	ENET_MIBC_MIB_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define	ENET_MIBC_MIB_IDLE_MASK   (0x40000000U)
#define	ENET_MIBC_MIB_IDLE_SHIFT   (30U)
#define	ENET_MIBC_MIB_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define	ENET_MIBC_MIB_DIS_MASK   (0x80000000U)
#define	ENET_MIBC_MIB_DIS_SHIFT   (31U)
#define	ENET_MIBC_MIB_DIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

RCR - Receive Control Register
#define	ENET_RCR_LOOP_MASK   (0x1U)
#define	ENET_RCR_LOOP_SHIFT   (0U)
#define	ENET_RCR_LOOP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define	ENET_RCR_DRT_MASK   (0x2U)
#define	ENET_RCR_DRT_SHIFT   (1U)
#define	ENET_RCR_DRT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define	ENET_RCR_MII_MODE_MASK   (0x4U)
#define	ENET_RCR_MII_MODE_SHIFT   (2U)
#define	ENET_RCR_MII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define	ENET_RCR_PROM_MASK   (0x8U)
#define	ENET_RCR_PROM_SHIFT   (3U)
#define	ENET_RCR_PROM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define	ENET_RCR_BC_REJ_MASK   (0x10U)
#define	ENET_RCR_BC_REJ_SHIFT   (4U)
#define	ENET_RCR_BC_REJ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define	ENET_RCR_FCE_MASK   (0x20U)
#define	ENET_RCR_FCE_SHIFT   (5U)
#define	ENET_RCR_FCE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define	ENET_RCR_RMII_MODE_MASK   (0x100U)
#define	ENET_RCR_RMII_MODE_SHIFT   (8U)
#define	ENET_RCR_RMII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define	ENET_RCR_RMII_10T_MASK   (0x200U)
#define	ENET_RCR_RMII_10T_SHIFT   (9U)
#define	ENET_RCR_RMII_10T(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define	ENET_RCR_PADEN_MASK   (0x1000U)
#define	ENET_RCR_PADEN_SHIFT   (12U)
#define	ENET_RCR_PADEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define	ENET_RCR_PAUFWD_MASK   (0x2000U)
#define	ENET_RCR_PAUFWD_SHIFT   (13U)
#define	ENET_RCR_PAUFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define	ENET_RCR_CRCFWD_MASK   (0x4000U)
#define	ENET_RCR_CRCFWD_SHIFT   (14U)
#define	ENET_RCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define	ENET_RCR_CFEN_MASK   (0x8000U)
#define	ENET_RCR_CFEN_SHIFT   (15U)
#define	ENET_RCR_CFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define	ENET_RCR_MAX_FL_MASK   (0x3FFF0000U)
#define	ENET_RCR_MAX_FL_SHIFT   (16U)
#define	ENET_RCR_MAX_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define	ENET_RCR_NLC_MASK   (0x40000000U)
#define	ENET_RCR_NLC_SHIFT   (30U)
#define	ENET_RCR_NLC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define	ENET_RCR_GRS_MASK   (0x80000000U)
#define	ENET_RCR_GRS_SHIFT   (31U)
#define	ENET_RCR_GRS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

TCR - Transmit Control Register
#define	ENET_TCR_GTS_MASK   (0x1U)
#define	ENET_TCR_GTS_SHIFT   (0U)
#define	ENET_TCR_GTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define	ENET_TCR_FDEN_MASK   (0x4U)
#define	ENET_TCR_FDEN_SHIFT   (2U)
#define	ENET_TCR_FDEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define	ENET_TCR_TFC_PAUSE_MASK   (0x8U)
#define	ENET_TCR_TFC_PAUSE_SHIFT   (3U)
#define	ENET_TCR_TFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define	ENET_TCR_RFC_PAUSE_MASK   (0x10U)
#define	ENET_TCR_RFC_PAUSE_SHIFT   (4U)
#define	ENET_TCR_RFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define	ENET_TCR_ADDSEL_MASK   (0xE0U)
#define	ENET_TCR_ADDSEL_SHIFT   (5U)
#define	ENET_TCR_ADDSEL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define	ENET_TCR_ADDINS_MASK   (0x100U)
#define	ENET_TCR_ADDINS_SHIFT   (8U)
#define	ENET_TCR_ADDINS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define	ENET_TCR_CRCFWD_MASK   (0x200U)
#define	ENET_TCR_CRCFWD_SHIFT   (9U)
#define	ENET_TCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

PALR - Physical Address Lower Register
#define	ENET_PALR_PADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_PALR_PADDR1_SHIFT   (0U)
#define	ENET_PALR_PADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PAUR - Physical Address Upper Register
#define	ENET_PAUR_TYPE_MASK   (0xFFFFU)
#define	ENET_PAUR_TYPE_SHIFT   (0U)
#define	ENET_PAUR_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define	ENET_PAUR_PADDR2_MASK   (0xFFFF0000U)
#define	ENET_PAUR_PADDR2_SHIFT   (16U)
#define	ENET_PAUR_PADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)

OPD - Opcode/Pause Duration Register
#define	ENET_OPD_PAUSE_DUR_MASK   (0xFFFFU)
#define	ENET_OPD_PAUSE_DUR_SHIFT   (0U)
#define	ENET_OPD_PAUSE_DUR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define	ENET_OPD_OPCODE_MASK   (0xFFFF0000U)
#define	ENET_OPD_OPCODE_SHIFT   (16U)
#define	ENET_OPD_OPCODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

TXIC - Transmit Interrupt Coalescing Register
#define	ENET_TXIC_ICTT_MASK   (0xFFFFU)
#define	ENET_TXIC_ICTT_SHIFT   (0U)
#define	ENET_TXIC_ICTT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
#define	ENET_TXIC_ICFT_MASK   (0xFF00000U)
#define	ENET_TXIC_ICFT_SHIFT   (20U)
#define	ENET_TXIC_ICFT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
#define	ENET_TXIC_ICCS_MASK   (0x40000000U)
#define	ENET_TXIC_ICCS_SHIFT   (30U)
#define	ENET_TXIC_ICCS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
#define	ENET_TXIC_ICEN_MASK   (0x80000000U)
#define	ENET_TXIC_ICEN_SHIFT   (31U)
#define	ENET_TXIC_ICEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)

RXIC - Receive Interrupt Coalescing Register
#define	ENET_RXIC_ICTT_MASK   (0xFFFFU)
#define	ENET_RXIC_ICTT_SHIFT   (0U)
#define	ENET_RXIC_ICTT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
#define	ENET_RXIC_ICFT_MASK   (0xFF00000U)
#define	ENET_RXIC_ICFT_SHIFT   (20U)
#define	ENET_RXIC_ICFT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
#define	ENET_RXIC_ICCS_MASK   (0x40000000U)
#define	ENET_RXIC_ICCS_SHIFT   (30U)
#define	ENET_RXIC_ICCS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
#define	ENET_RXIC_ICEN_MASK   (0x80000000U)
#define	ENET_RXIC_ICEN_SHIFT   (31U)
#define	ENET_RXIC_ICEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)

IAUR - Descriptor Individual Upper Address Register
#define	ENET_IAUR_IADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_IAUR_IADDR1_SHIFT   (0U)
#define	ENET_IAUR_IADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)

IALR - Descriptor Individual Lower Address Register
#define	ENET_IALR_IADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_IALR_IADDR2_SHIFT   (0U)
#define	ENET_IALR_IADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)

GAUR - Descriptor Group Upper Address Register
#define	ENET_GAUR_GADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_GAUR_GADDR1_SHIFT   (0U)
#define	ENET_GAUR_GADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)

GALR - Descriptor Group Lower Address Register
#define	ENET_GALR_GADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_GALR_GADDR2_SHIFT   (0U)
#define	ENET_GALR_GADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)

TFWR - Transmit FIFO Watermark Register
#define	ENET_TFWR_TFWR_MASK   (0x3FU)
#define	ENET_TFWR_TFWR_SHIFT   (0U)
#define	ENET_TFWR_TFWR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define	ENET_TFWR_STRFWD_MASK   (0x100U)
#define	ENET_TFWR_STRFWD_SHIFT   (8U)
#define	ENET_TFWR_STRFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

RDSR - Receive Descriptor Ring Start Register
#define	ENET_RDSR_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR_R_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)

TDSR - Transmit Buffer Descriptor Ring Start Register
#define	ENET_TDSR_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR_X_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)

MRBR - Maximum Receive Buffer Size Register
#define	ENET_MRBR_R_BUF_SIZE_MASK   (0x3FF0U)
#define	ENET_MRBR_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR_R_BUF_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)

RSFL - Receive FIFO Section Full Threshold
#define	ENET_RSFL_RX_SECTION_FULL_MASK   (0xFFU)
#define	ENET_RSFL_RX_SECTION_FULL_SHIFT   (0U)
#define	ENET_RSFL_RX_SECTION_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)

RSEM - Receive FIFO Section Empty Threshold
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_RSEM_RX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK   (0x1F0000U)
#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT   (16U)
#define	ENET_RSEM_STAT_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

RAEM - Receive FIFO Almost Empty Threshold
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_RAEM_RX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)

RAFL - Receive FIFO Almost Full Threshold
#define	ENET_RAFL_RX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_RAFL_RX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)

TSEM - Transmit FIFO Section Empty Threshold
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_TSEM_TX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)

TAEM - Transmit FIFO Almost Empty Threshold
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_TAEM_TX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)

TAFL - Transmit FIFO Almost Full Threshold
#define	ENET_TAFL_TX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_TAFL_TX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)

TIPG - Transmit Inter-Packet Gap
#define	ENET_TIPG_IPG_MASK   (0x1FU)
#define	ENET_TIPG_IPG_SHIFT   (0U)
#define	ENET_TIPG_IPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)

FTRL - Frame Truncation Length
#define	ENET_FTRL_TRUNC_FL_MASK   (0x3FFFU)
#define	ENET_FTRL_TRUNC_FL_SHIFT   (0U)
#define	ENET_FTRL_TRUNC_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TACC - Transmit Accelerator Function Configuration
#define	ENET_TACC_SHIFT16_MASK   (0x1U)
#define	ENET_TACC_SHIFT16_SHIFT   (0U)
#define	ENET_TACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define	ENET_TACC_IPCHK_MASK   (0x8U)
#define	ENET_TACC_IPCHK_SHIFT   (3U)
#define	ENET_TACC_IPCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define	ENET_TACC_PROCHK_MASK   (0x10U)
#define	ENET_TACC_PROCHK_SHIFT   (4U)
#define	ENET_TACC_PROCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

RACC - Receive Accelerator Function Configuration
#define	ENET_RACC_PADREM_MASK   (0x1U)
#define	ENET_RACC_PADREM_SHIFT   (0U)
#define	ENET_RACC_PADREM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define	ENET_RACC_IPDIS_MASK   (0x2U)
#define	ENET_RACC_IPDIS_SHIFT   (1U)
#define	ENET_RACC_IPDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define	ENET_RACC_PRODIS_MASK   (0x4U)
#define	ENET_RACC_PRODIS_SHIFT   (2U)
#define	ENET_RACC_PRODIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define	ENET_RACC_LINEDIS_MASK   (0x40U)
#define	ENET_RACC_LINEDIS_SHIFT   (6U)
#define	ENET_RACC_LINEDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define	ENET_RACC_SHIFT16_MASK   (0x80U)
#define	ENET_RACC_SHIFT16_SHIFT   (7U)
#define	ENET_RACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

RMON_T_PACKETS - Tx Packet Count Statistic Register
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_PACKETS_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_BC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_MC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_OVERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_FRAG_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_FRAG_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_JAB_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_JAB_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_JAB_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

RMON_T_COL - Tx Collision Count Statistic Register
#define	ENET_RMON_T_COL_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_COL_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_COL_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

RMON_T_P64 - Tx 64-Byte Packets Statistic Register
#define	ENET_RMON_T_P64_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P64_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P64_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P65TO127_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P128TO255_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P256TO511_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P512TO1023_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P1024TO2047_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P_GTE2048_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

RMON_T_OCTETS - Tx Octets Statistic Register
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT   (0U)
#define	ENET_RMON_T_OCTETS_TXOCTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
#define	ENET_IEEE_T_1COL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_1COL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_1COL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
#define	ENET_IEEE_T_MCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
#define	ENET_IEEE_T_DEF_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_DEF_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_DEF_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
#define	ENET_IEEE_T_LCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_LCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_LCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
#define	ENET_IEEE_T_EXCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_EXCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
#define	ENET_IEEE_T_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
#define	ENET_IEEE_T_CSERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_CSERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_CSERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

IEEE_T_SQE - Reserved Statistic Register
#define	ENET_IEEE_T_SQE_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_SQE_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_SQE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
#define	ENET_IEEE_T_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

RMON_R_PACKETS - Rx Packet Count Statistic Register
#define	ENET_RMON_R_PACKETS_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_PACKETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_PACKETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
#define	ENET_RMON_R_BC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_BC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
#define	ENET_RMON_R_MC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_MC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_CRC_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_UNDERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OVERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_FRAG_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_FRAG_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_FRAG_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_JAB_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_JAB_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_JAB_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

RMON_R_P64 - Rx 64-Byte Packets Statistic Register
#define	ENET_RMON_R_P64_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P64_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P64_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
#define	ENET_RMON_R_P65TO127_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P65TO127_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P65TO127_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
#define	ENET_RMON_R_P128TO255_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P128TO255_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P128TO255_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
#define	ENET_RMON_R_P256TO511_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P256TO511_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P256TO511_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
#define	ENET_RMON_R_P512TO1023_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P512TO1023_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P1024TO2047_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P_GTE2048_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

RMON_R_OCTETS - Rx Octets Statistic Register
#define	ENET_RMON_R_OCTETS_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_R_OCTETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OCTETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

IEEE_R_DROP - Frames not Counted Correctly Statistic Register
#define	ENET_IEEE_R_DROP_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_DROP_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_DROP_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

IEEE_R_FRAME_OK - Frames Received OK Statistic Register
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

IEEE_R_CRC - Frames Received with CRC Error Statistic Register
#define	ENET_IEEE_R_CRC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_CRC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_CRC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
#define	ENET_IEEE_R_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
#define	ENET_IEEE_R_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
#define	ENET_IEEE_R_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

ATCR - Adjustable Timer Control Register
#define	ENET_ATCR_EN_MASK   (0x1U)
#define	ENET_ATCR_EN_SHIFT   (0U)
#define	ENET_ATCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define	ENET_ATCR_OFFEN_MASK   (0x4U)
#define	ENET_ATCR_OFFEN_SHIFT   (2U)
#define	ENET_ATCR_OFFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define	ENET_ATCR_OFFRST_MASK   (0x8U)
#define	ENET_ATCR_OFFRST_SHIFT   (3U)
#define	ENET_ATCR_OFFRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define	ENET_ATCR_PEREN_MASK   (0x10U)
#define	ENET_ATCR_PEREN_SHIFT   (4U)
#define	ENET_ATCR_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define	ENET_ATCR_PINPER_MASK   (0x80U)
#define	ENET_ATCR_PINPER_SHIFT   (7U)
#define	ENET_ATCR_PINPER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define	ENET_ATCR_RESTART_MASK   (0x200U)
#define	ENET_ATCR_RESTART_SHIFT   (9U)
#define	ENET_ATCR_RESTART(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define	ENET_ATCR_CAPTURE_MASK   (0x800U)
#define	ENET_ATCR_CAPTURE_SHIFT   (11U)
#define	ENET_ATCR_CAPTURE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define	ENET_ATCR_SLAVE_MASK   (0x2000U)
#define	ENET_ATCR_SLAVE_SHIFT   (13U)
#define	ENET_ATCR_SLAVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

ATVR - Timer Value Register
#define	ENET_ATVR_ATIME_MASK   (0xFFFFFFFFU)
#define	ENET_ATVR_ATIME_SHIFT   (0U)
#define	ENET_ATVR_ATIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)

ATOFF - Timer Offset Register
#define	ENET_ATOFF_OFFSET_MASK   (0xFFFFFFFFU)
#define	ENET_ATOFF_OFFSET_SHIFT   (0U)
#define	ENET_ATOFF_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)

ATPER - Timer Period Register
#define	ENET_ATPER_PERIOD_MASK   (0xFFFFFFFFU)
#define	ENET_ATPER_PERIOD_SHIFT   (0U)
#define	ENET_ATPER_PERIOD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

ATCOR - Timer Correction Register
#define	ENET_ATCOR_COR_MASK   (0x7FFFFFFFU)
#define	ENET_ATCOR_COR_SHIFT   (0U)
#define	ENET_ATCOR_COR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

ATINC - Time-Stamping Clock Period Register
#define	ENET_ATINC_INC_MASK   (0x7FU)
#define	ENET_ATINC_INC_SHIFT   (0U)
#define	ENET_ATINC_INC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define	ENET_ATINC_INC_CORR_MASK   (0x7F00U)
#define	ENET_ATINC_INC_CORR_SHIFT   (8U)
#define	ENET_ATINC_INC_CORR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

ATSTMP - Timestamp of Last Transmitted Frame
#define	ENET_ATSTMP_TIMESTAMP_MASK   (0xFFFFFFFFU)
#define	ENET_ATSTMP_TIMESTAMP_SHIFT   (0U)
#define	ENET_ATSTMP_TIMESTAMP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

TGSR - Timer Global Status Register
#define	ENET_TGSR_TF0_MASK   (0x1U)
#define	ENET_TGSR_TF0_SHIFT   (0U)
#define	ENET_TGSR_TF0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define	ENET_TGSR_TF1_MASK   (0x2U)
#define	ENET_TGSR_TF1_SHIFT   (1U)
#define	ENET_TGSR_TF1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define	ENET_TGSR_TF2_MASK   (0x4U)
#define	ENET_TGSR_TF2_SHIFT   (2U)
#define	ENET_TGSR_TF2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define	ENET_TGSR_TF3_MASK   (0x8U)
#define	ENET_TGSR_TF3_SHIFT   (3U)
#define	ENET_TGSR_TF3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TCSR - Timer Control Status Register
#define	ENET_TCSR_TDRE_MASK   (0x1U)
#define	ENET_TCSR_TDRE_SHIFT   (0U)
#define	ENET_TCSR_TDRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define	ENET_TCSR_TMODE_MASK   (0x3CU)
#define	ENET_TCSR_TMODE_SHIFT   (2U)
#define	ENET_TCSR_TMODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define	ENET_TCSR_TIE_MASK   (0x40U)
#define	ENET_TCSR_TIE_SHIFT   (6U)
#define	ENET_TCSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define	ENET_TCSR_TF_MASK   (0x80U)
#define	ENET_TCSR_TF_SHIFT   (7U)
#define	ENET_TCSR_TF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
#define	ENET_TCSR_TPWC_MASK   (0xF800U)
#define	ENET_TCSR_TPWC_SHIFT   (11U)
#define	ENET_TCSR_TPWC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)

TCCR - Timer Compare Capture Register
#define	ENET_TCCR_TCC_MASK   (0xFFFFFFFFU)
#define	ENET_TCCR_TCC_SHIFT   (0U)
#define	ENET_TCCR_TCC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

Detailed Description

Macro Definition Documentation

ENET_ATCOR_COR

#define ENET_ATCOR_COR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

COR - Correction Counter Wrap-Around Value

Definition at line 17082 of file MIMXRT1052.h.

ENET_ATCOR_COR_MASK

#define ENET_ATCOR_COR_MASK   (0x7FFFFFFFU)

Definition at line 17078 of file MIMXRT1052.h.

ENET_ATCOR_COR_SHIFT

#define ENET_ATCOR_COR_SHIFT   (0U)

Definition at line 17079 of file MIMXRT1052.h.

ENET_ATCR_CAPTURE

#define ENET_ATCR_CAPTURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

Definition at line 17044 of file MIMXRT1052.h.

ENET_ATCR_CAPTURE_MASK

#define ENET_ATCR_CAPTURE_MASK   (0x800U)

Definition at line 17038 of file MIMXRT1052.h.

ENET_ATCR_CAPTURE_SHIFT

#define ENET_ATCR_CAPTURE_SHIFT   (11U)

Definition at line 17039 of file MIMXRT1052.h.

ENET_ATCR_EN

#define ENET_ATCR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

Definition at line 17000 of file MIMXRT1052.h.

ENET_ATCR_EN_MASK

#define ENET_ATCR_EN_MASK   (0x1U)

Definition at line 16994 of file MIMXRT1052.h.

ENET_ATCR_EN_SHIFT

#define ENET_ATCR_EN_SHIFT   (0U)

Definition at line 16995 of file MIMXRT1052.h.

ENET_ATCR_OFFEN

#define ENET_ATCR_OFFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

Definition at line 17009 of file MIMXRT1052.h.

ENET_ATCR_OFFEN_MASK

#define ENET_ATCR_OFFEN_MASK   (0x4U)

Definition at line 17001 of file MIMXRT1052.h.

ENET_ATCR_OFFEN_SHIFT

#define ENET_ATCR_OFFEN_SHIFT   (2U)

Definition at line 17002 of file MIMXRT1052.h.

ENET_ATCR_OFFRST

#define ENET_ATCR_OFFRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

Definition at line 17016 of file MIMXRT1052.h.

ENET_ATCR_OFFRST_MASK

#define ENET_ATCR_OFFRST_MASK   (0x8U)

Definition at line 17010 of file MIMXRT1052.h.

ENET_ATCR_OFFRST_SHIFT

#define ENET_ATCR_OFFRST_SHIFT   (3U)

Definition at line 17011 of file MIMXRT1052.h.

ENET_ATCR_PEREN

#define ENET_ATCR_PEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

Definition at line 17025 of file MIMXRT1052.h.

ENET_ATCR_PEREN_MASK

#define ENET_ATCR_PEREN_MASK   (0x10U)

Definition at line 17017 of file MIMXRT1052.h.

ENET_ATCR_PEREN_SHIFT

#define ENET_ATCR_PEREN_SHIFT   (4U)

Definition at line 17018 of file MIMXRT1052.h.

ENET_ATCR_PINPER

#define ENET_ATCR_PINPER

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER 0b0..Disable. 0b1..Enable.

Definition at line 17032 of file MIMXRT1052.h.

ENET_ATCR_PINPER_MASK

#define ENET_ATCR_PINPER_MASK   (0x80U)

Definition at line 17026 of file MIMXRT1052.h.

ENET_ATCR_PINPER_SHIFT

#define ENET_ATCR_PINPER_SHIFT   (7U)

Definition at line 17027 of file MIMXRT1052.h.

ENET_ATCR_RESTART

#define ENET_ATCR_RESTART

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)

RESTART - Reset Timer

Definition at line 17037 of file MIMXRT1052.h.

ENET_ATCR_RESTART_MASK

#define ENET_ATCR_RESTART_MASK   (0x200U)

Definition at line 17033 of file MIMXRT1052.h.

ENET_ATCR_RESTART_SHIFT

#define ENET_ATCR_RESTART_SHIFT   (9U)

Definition at line 17034 of file MIMXRT1052.h.

ENET_ATCR_SLAVE

#define ENET_ATCR_SLAVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

Definition at line 17052 of file MIMXRT1052.h.

ENET_ATCR_SLAVE_MASK

#define ENET_ATCR_SLAVE_MASK   (0x2000U)

Definition at line 17045 of file MIMXRT1052.h.

ENET_ATCR_SLAVE_SHIFT

#define ENET_ATCR_SLAVE_SHIFT   (13U)

Definition at line 17046 of file MIMXRT1052.h.

ENET_ATINC_INC

#define ENET_ATINC_INC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)

INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds

Definition at line 17091 of file MIMXRT1052.h.

ENET_ATINC_INC_CORR

#define ENET_ATINC_INC_CORR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

INC_CORR - Correction Increment Value

Definition at line 17096 of file MIMXRT1052.h.

ENET_ATINC_INC_CORR_MASK

#define ENET_ATINC_INC_CORR_MASK   (0x7F00U)

Definition at line 17092 of file MIMXRT1052.h.

ENET_ATINC_INC_CORR_SHIFT

#define ENET_ATINC_INC_CORR_SHIFT   (8U)

Definition at line 17093 of file MIMXRT1052.h.

ENET_ATINC_INC_MASK

#define ENET_ATINC_INC_MASK   (0x7FU)

Definition at line 17087 of file MIMXRT1052.h.

ENET_ATINC_INC_SHIFT

#define ENET_ATINC_INC_SHIFT   (0U)

Definition at line 17088 of file MIMXRT1052.h.

ENET_ATOFF_OFFSET

#define ENET_ATOFF_OFFSET

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)

Definition at line 17066 of file MIMXRT1052.h.

ENET_ATOFF_OFFSET_MASK

#define ENET_ATOFF_OFFSET_MASK   (0xFFFFFFFFU)

Definition at line 17064 of file MIMXRT1052.h.

ENET_ATOFF_OFFSET_SHIFT

#define ENET_ATOFF_OFFSET_SHIFT   (0U)

Definition at line 17065 of file MIMXRT1052.h.

ENET_ATPER_PERIOD

#define ENET_ATPER_PERIOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

Definition at line 17073 of file MIMXRT1052.h.

ENET_ATPER_PERIOD_MASK

#define ENET_ATPER_PERIOD_MASK   (0xFFFFFFFFU)

Definition at line 17071 of file MIMXRT1052.h.

ENET_ATPER_PERIOD_SHIFT

#define ENET_ATPER_PERIOD_SHIFT   (0U)

Definition at line 17072 of file MIMXRT1052.h.

ENET_ATSTMP_TIMESTAMP

#define ENET_ATSTMP_TIMESTAMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

Definition at line 17103 of file MIMXRT1052.h.

ENET_ATSTMP_TIMESTAMP_MASK

#define ENET_ATSTMP_TIMESTAMP_MASK   (0xFFFFFFFFU)

Definition at line 17101 of file MIMXRT1052.h.

ENET_ATSTMP_TIMESTAMP_SHIFT

#define ENET_ATSTMP_TIMESTAMP_SHIFT   (0U)

Definition at line 17102 of file MIMXRT1052.h.

ENET_ATVR_ATIME

#define ENET_ATVR_ATIME

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)

Definition at line 17059 of file MIMXRT1052.h.

ENET_ATVR_ATIME_MASK

#define ENET_ATVR_ATIME_MASK   (0xFFFFFFFFU)

Definition at line 17057 of file MIMXRT1052.h.

ENET_ATVR_ATIME_SHIFT

#define ENET_ATVR_ATIME_SHIFT   (0U)

Definition at line 17058 of file MIMXRT1052.h.

ENET_ECR_DBGEN

#define ENET_ECR_DBGEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

Definition at line 15971 of file MIMXRT1052.h.

ENET_ECR_DBGEN_MASK

#define ENET_ECR_DBGEN_MASK   (0x40U)

Definition at line 15965 of file MIMXRT1052.h.

ENET_ECR_DBGEN_SHIFT

#define ENET_ECR_DBGEN_SHIFT   (6U)

Definition at line 15966 of file MIMXRT1052.h.

ENET_ECR_DBSWP

#define ENET_ECR_DBSWP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

Definition at line 15978 of file MIMXRT1052.h.

ENET_ECR_DBSWP_MASK

#define ENET_ECR_DBSWP_MASK   (0x100U)

Definition at line 15972 of file MIMXRT1052.h.

ENET_ECR_DBSWP_SHIFT

#define ENET_ECR_DBSWP_SHIFT   (8U)

Definition at line 15973 of file MIMXRT1052.h.

ENET_ECR_EN1588

#define ENET_ECR_EN1588

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.

Definition at line 15964 of file MIMXRT1052.h.

ENET_ECR_EN1588_MASK

#define ENET_ECR_EN1588_MASK   (0x10U)

Definition at line 15958 of file MIMXRT1052.h.

ENET_ECR_EN1588_SHIFT

#define ENET_ECR_EN1588_SHIFT   (4U)

Definition at line 15959 of file MIMXRT1052.h.

ENET_ECR_ETHEREN

#define ENET_ECR_ETHEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

Definition at line 15943 of file MIMXRT1052.h.

ENET_ECR_ETHEREN_MASK

#define ENET_ECR_ETHEREN_MASK   (0x2U)

Definition at line 15937 of file MIMXRT1052.h.

ENET_ECR_ETHEREN_SHIFT

#define ENET_ECR_ETHEREN_SHIFT   (1U)

Definition at line 15938 of file MIMXRT1052.h.

ENET_ECR_MAGICEN

#define ENET_ECR_MAGICEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

Definition at line 15950 of file MIMXRT1052.h.

ENET_ECR_MAGICEN_MASK

#define ENET_ECR_MAGICEN_MASK   (0x4U)

Definition at line 15944 of file MIMXRT1052.h.

ENET_ECR_MAGICEN_SHIFT

#define ENET_ECR_MAGICEN_SHIFT   (2U)

Definition at line 15945 of file MIMXRT1052.h.

ENET_ECR_RESET

#define ENET_ECR_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)

RESET - Ethernet MAC Reset

Definition at line 15936 of file MIMXRT1052.h.

ENET_ECR_RESET_MASK

#define ENET_ECR_RESET_MASK   (0x1U)

Definition at line 15932 of file MIMXRT1052.h.

ENET_ECR_RESET_SHIFT

#define ENET_ECR_RESET_SHIFT   (0U)

Definition at line 15933 of file MIMXRT1052.h.

ENET_ECR_SLEEP

#define ENET_ECR_SLEEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

Definition at line 15957 of file MIMXRT1052.h.

ENET_ECR_SLEEP_MASK

#define ENET_ECR_SLEEP_MASK   (0x8U)

Definition at line 15951 of file MIMXRT1052.h.

ENET_ECR_SLEEP_SHIFT

#define ENET_ECR_SLEEP_SHIFT   (3U)

Definition at line 15952 of file MIMXRT1052.h.

ENET_EIMR_BABR

#define ENET_EIMR_BABR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

Definition at line 15909 of file MIMXRT1052.h.

ENET_EIMR_BABR_MASK

#define ENET_EIMR_BABR_MASK   (0x40000000U)

Definition at line 15903 of file MIMXRT1052.h.

ENET_EIMR_BABR_SHIFT

#define ENET_EIMR_BABR_SHIFT   (30U)

Definition at line 15904 of file MIMXRT1052.h.

ENET_EIMR_BABT

#define ENET_EIMR_BABT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

Definition at line 15902 of file MIMXRT1052.h.

ENET_EIMR_BABT_MASK

#define ENET_EIMR_BABT_MASK   (0x20000000U)

Definition at line 15896 of file MIMXRT1052.h.

ENET_EIMR_BABT_SHIFT

#define ENET_EIMR_BABT_SHIFT   (29U)

Definition at line 15897 of file MIMXRT1052.h.

ENET_EIMR_EBERR

#define ENET_EIMR_EBERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)

EBERR - EBERR Interrupt Mask

Definition at line 15859 of file MIMXRT1052.h.

ENET_EIMR_EBERR_MASK

#define ENET_EIMR_EBERR_MASK   (0x400000U)

Definition at line 15855 of file MIMXRT1052.h.

ENET_EIMR_EBERR_SHIFT

#define ENET_EIMR_EBERR_SHIFT   (22U)

Definition at line 15856 of file MIMXRT1052.h.

ENET_EIMR_GRA

#define ENET_EIMR_GRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

Definition at line 15895 of file MIMXRT1052.h.

ENET_EIMR_GRA_MASK

#define ENET_EIMR_GRA_MASK   (0x10000000U)

Definition at line 15889 of file MIMXRT1052.h.

ENET_EIMR_GRA_SHIFT

#define ENET_EIMR_GRA_SHIFT   (28U)

Definition at line 15890 of file MIMXRT1052.h.

ENET_EIMR_LC

#define ENET_EIMR_LC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)

LC - LC Interrupt Mask

Definition at line 15854 of file MIMXRT1052.h.

ENET_EIMR_LC_MASK

#define ENET_EIMR_LC_MASK   (0x200000U)

Definition at line 15850 of file MIMXRT1052.h.

ENET_EIMR_LC_SHIFT

#define ENET_EIMR_LC_SHIFT   (21U)

Definition at line 15851 of file MIMXRT1052.h.

ENET_EIMR_MII

#define ENET_EIMR_MII

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)

MII - MII Interrupt Mask

Definition at line 15864 of file MIMXRT1052.h.

ENET_EIMR_MII_MASK

#define ENET_EIMR_MII_MASK   (0x800000U)

Definition at line 15860 of file MIMXRT1052.h.

ENET_EIMR_MII_SHIFT

#define ENET_EIMR_MII_SHIFT   (23U)

Definition at line 15861 of file MIMXRT1052.h.

ENET_EIMR_PLR

#define ENET_EIMR_PLR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)

PLR - PLR Interrupt Mask

Definition at line 15839 of file MIMXRT1052.h.

ENET_EIMR_PLR_MASK

#define ENET_EIMR_PLR_MASK   (0x40000U)

Definition at line 15835 of file MIMXRT1052.h.

ENET_EIMR_PLR_SHIFT

#define ENET_EIMR_PLR_SHIFT   (18U)

Definition at line 15836 of file MIMXRT1052.h.

ENET_EIMR_RL

#define ENET_EIMR_RL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)

RL - RL Interrupt Mask

Definition at line 15849 of file MIMXRT1052.h.

ENET_EIMR_RL_MASK

#define ENET_EIMR_RL_MASK   (0x100000U)

Definition at line 15845 of file MIMXRT1052.h.

ENET_EIMR_RL_SHIFT

#define ENET_EIMR_RL_SHIFT   (20U)

Definition at line 15846 of file MIMXRT1052.h.

ENET_EIMR_RXB

#define ENET_EIMR_RXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)

RXB - RXB Interrupt Mask

Definition at line 15869 of file MIMXRT1052.h.

ENET_EIMR_RXB_MASK

#define ENET_EIMR_RXB_MASK   (0x1000000U)

Definition at line 15865 of file MIMXRT1052.h.

ENET_EIMR_RXB_SHIFT

#define ENET_EIMR_RXB_SHIFT   (24U)

Definition at line 15866 of file MIMXRT1052.h.

ENET_EIMR_RXF

#define ENET_EIMR_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)

RXF - RXF Interrupt Mask

Definition at line 15874 of file MIMXRT1052.h.

ENET_EIMR_RXF_MASK

#define ENET_EIMR_RXF_MASK   (0x2000000U)

Definition at line 15870 of file MIMXRT1052.h.

ENET_EIMR_RXF_SHIFT

#define ENET_EIMR_RXF_SHIFT   (25U)

Definition at line 15871 of file MIMXRT1052.h.

ENET_EIMR_TS_AVAIL

#define ENET_EIMR_TS_AVAIL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)

TS_AVAIL - TS_AVAIL Interrupt Mask

Definition at line 15829 of file MIMXRT1052.h.

ENET_EIMR_TS_AVAIL_MASK

#define ENET_EIMR_TS_AVAIL_MASK   (0x10000U)

Definition at line 15825 of file MIMXRT1052.h.

ENET_EIMR_TS_AVAIL_SHIFT

#define ENET_EIMR_TS_AVAIL_SHIFT   (16U)

Definition at line 15826 of file MIMXRT1052.h.

ENET_EIMR_TS_TIMER

#define ENET_EIMR_TS_TIMER

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)

TS_TIMER - TS_TIMER Interrupt Mask

Definition at line 15824 of file MIMXRT1052.h.

ENET_EIMR_TS_TIMER_MASK

#define ENET_EIMR_TS_TIMER_MASK   (0x8000U)

Definition at line 15820 of file MIMXRT1052.h.

ENET_EIMR_TS_TIMER_SHIFT

#define ENET_EIMR_TS_TIMER_SHIFT   (15U)

Definition at line 15821 of file MIMXRT1052.h.

ENET_EIMR_TXB

#define ENET_EIMR_TXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

Definition at line 15881 of file MIMXRT1052.h.

ENET_EIMR_TXB_MASK

#define ENET_EIMR_TXB_MASK   (0x4000000U)

Definition at line 15875 of file MIMXRT1052.h.

ENET_EIMR_TXB_SHIFT

#define ENET_EIMR_TXB_SHIFT   (26U)

Definition at line 15876 of file MIMXRT1052.h.

ENET_EIMR_TXF

#define ENET_EIMR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

Definition at line 15888 of file MIMXRT1052.h.

ENET_EIMR_TXF_MASK

#define ENET_EIMR_TXF_MASK   (0x8000000U)

Definition at line 15882 of file MIMXRT1052.h.

ENET_EIMR_TXF_SHIFT

#define ENET_EIMR_TXF_SHIFT   (27U)

Definition at line 15883 of file MIMXRT1052.h.

ENET_EIMR_UN

#define ENET_EIMR_UN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)

UN - UN Interrupt Mask

Definition at line 15844 of file MIMXRT1052.h.

ENET_EIMR_UN_MASK

#define ENET_EIMR_UN_MASK   (0x80000U)

Definition at line 15840 of file MIMXRT1052.h.

ENET_EIMR_UN_SHIFT

#define ENET_EIMR_UN_SHIFT   (19U)

Definition at line 15841 of file MIMXRT1052.h.

ENET_EIMR_WAKEUP

#define ENET_EIMR_WAKEUP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)

WAKEUP - WAKEUP Interrupt Mask

Definition at line 15834 of file MIMXRT1052.h.

ENET_EIMR_WAKEUP_MASK

#define ENET_EIMR_WAKEUP_MASK   (0x20000U)

Definition at line 15830 of file MIMXRT1052.h.

ENET_EIMR_WAKEUP_SHIFT

#define ENET_EIMR_WAKEUP_SHIFT   (17U)

Definition at line 15831 of file MIMXRT1052.h.

ENET_EIR_BABR

#define ENET_EIR_BABR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

BABR - Babbling Receive Error

Definition at line 15815 of file MIMXRT1052.h.

ENET_EIR_BABR_MASK

#define ENET_EIR_BABR_MASK   (0x40000000U)

Definition at line 15811 of file MIMXRT1052.h.

ENET_EIR_BABR_SHIFT

#define ENET_EIR_BABR_SHIFT   (30U)

Definition at line 15812 of file MIMXRT1052.h.

ENET_EIR_BABT

#define ENET_EIR_BABT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)

BABT - Babbling Transmit Error

Definition at line 15810 of file MIMXRT1052.h.

ENET_EIR_BABT_MASK

#define ENET_EIR_BABT_MASK   (0x20000000U)

Definition at line 15806 of file MIMXRT1052.h.

ENET_EIR_BABT_SHIFT

#define ENET_EIR_BABT_SHIFT   (29U)

Definition at line 15807 of file MIMXRT1052.h.

ENET_EIR_EBERR

#define ENET_EIR_EBERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)

EBERR - Ethernet Bus Error

Definition at line 15775 of file MIMXRT1052.h.

ENET_EIR_EBERR_MASK

#define ENET_EIR_EBERR_MASK   (0x400000U)

Definition at line 15771 of file MIMXRT1052.h.

ENET_EIR_EBERR_SHIFT

#define ENET_EIR_EBERR_SHIFT   (22U)

Definition at line 15772 of file MIMXRT1052.h.

ENET_EIR_GRA

#define ENET_EIR_GRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)

GRA - Graceful Stop Complete

Definition at line 15805 of file MIMXRT1052.h.

ENET_EIR_GRA_MASK

#define ENET_EIR_GRA_MASK   (0x10000000U)

Definition at line 15801 of file MIMXRT1052.h.

ENET_EIR_GRA_SHIFT

#define ENET_EIR_GRA_SHIFT   (28U)

Definition at line 15802 of file MIMXRT1052.h.

ENET_EIR_LC

#define ENET_EIR_LC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)

LC - Late Collision

Definition at line 15770 of file MIMXRT1052.h.

ENET_EIR_LC_MASK

#define ENET_EIR_LC_MASK   (0x200000U)

Definition at line 15766 of file MIMXRT1052.h.

ENET_EIR_LC_SHIFT

#define ENET_EIR_LC_SHIFT   (21U)

Definition at line 15767 of file MIMXRT1052.h.

ENET_EIR_MII

#define ENET_EIR_MII

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)

MII - MII Interrupt.

Definition at line 15780 of file MIMXRT1052.h.

ENET_EIR_MII_MASK

#define ENET_EIR_MII_MASK   (0x800000U)

Definition at line 15776 of file MIMXRT1052.h.

ENET_EIR_MII_SHIFT

#define ENET_EIR_MII_SHIFT   (23U)

Definition at line 15777 of file MIMXRT1052.h.

ENET_EIR_PLR

#define ENET_EIR_PLR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)

PLR - Payload Receive Error

Definition at line 15755 of file MIMXRT1052.h.

ENET_EIR_PLR_MASK

#define ENET_EIR_PLR_MASK   (0x40000U)

Definition at line 15751 of file MIMXRT1052.h.

ENET_EIR_PLR_SHIFT

#define ENET_EIR_PLR_SHIFT   (18U)

Definition at line 15752 of file MIMXRT1052.h.

ENET_EIR_RL

#define ENET_EIR_RL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)

RL - Collision Retry Limit

Definition at line 15765 of file MIMXRT1052.h.

ENET_EIR_RL_MASK

#define ENET_EIR_RL_MASK   (0x100000U)

Definition at line 15761 of file MIMXRT1052.h.

ENET_EIR_RL_SHIFT

#define ENET_EIR_RL_SHIFT   (20U)

Definition at line 15762 of file MIMXRT1052.h.

ENET_EIR_RXB

#define ENET_EIR_RXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)

RXB - Receive Buffer Interrupt

Definition at line 15785 of file MIMXRT1052.h.

ENET_EIR_RXB_MASK

#define ENET_EIR_RXB_MASK   (0x1000000U)

Definition at line 15781 of file MIMXRT1052.h.

ENET_EIR_RXB_SHIFT

#define ENET_EIR_RXB_SHIFT   (24U)

Definition at line 15782 of file MIMXRT1052.h.

ENET_EIR_RXF

#define ENET_EIR_RXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)

RXF - Receive Frame Interrupt

Definition at line 15790 of file MIMXRT1052.h.

ENET_EIR_RXF_MASK

#define ENET_EIR_RXF_MASK   (0x2000000U)

Definition at line 15786 of file MIMXRT1052.h.

ENET_EIR_RXF_SHIFT

#define ENET_EIR_RXF_SHIFT   (25U)

Definition at line 15787 of file MIMXRT1052.h.

ENET_EIR_TS_AVAIL

#define ENET_EIR_TS_AVAIL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)

TS_AVAIL - Transmit Timestamp Available

Definition at line 15745 of file MIMXRT1052.h.

ENET_EIR_TS_AVAIL_MASK

#define ENET_EIR_TS_AVAIL_MASK   (0x10000U)

Definition at line 15741 of file MIMXRT1052.h.

ENET_EIR_TS_AVAIL_SHIFT

#define ENET_EIR_TS_AVAIL_SHIFT   (16U)

Definition at line 15742 of file MIMXRT1052.h.

ENET_EIR_TS_TIMER

#define ENET_EIR_TS_TIMER

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)

TS_TIMER - Timestamp Timer

Definition at line 15740 of file MIMXRT1052.h.

ENET_EIR_TS_TIMER_MASK

#define ENET_EIR_TS_TIMER_MASK   (0x8000U)

Definition at line 15736 of file MIMXRT1052.h.

ENET_EIR_TS_TIMER_SHIFT

#define ENET_EIR_TS_TIMER_SHIFT   (15U)

Definition at line 15737 of file MIMXRT1052.h.

ENET_EIR_TXB

#define ENET_EIR_TXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)

TXB - Transmit Buffer Interrupt

Definition at line 15795 of file MIMXRT1052.h.

ENET_EIR_TXB_MASK

#define ENET_EIR_TXB_MASK   (0x4000000U)

Definition at line 15791 of file MIMXRT1052.h.

ENET_EIR_TXB_SHIFT

#define ENET_EIR_TXB_SHIFT   (26U)

Definition at line 15792 of file MIMXRT1052.h.

ENET_EIR_TXF

#define ENET_EIR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)

TXF - Transmit Frame Interrupt

Definition at line 15800 of file MIMXRT1052.h.

ENET_EIR_TXF_MASK

#define ENET_EIR_TXF_MASK   (0x8000000U)

Definition at line 15796 of file MIMXRT1052.h.

ENET_EIR_TXF_SHIFT

#define ENET_EIR_TXF_SHIFT   (27U)

Definition at line 15797 of file MIMXRT1052.h.

ENET_EIR_UN

#define ENET_EIR_UN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)

UN - Transmit FIFO Underrun

Definition at line 15760 of file MIMXRT1052.h.

ENET_EIR_UN_MASK

#define ENET_EIR_UN_MASK   (0x80000U)

Definition at line 15756 of file MIMXRT1052.h.

ENET_EIR_UN_SHIFT

#define ENET_EIR_UN_SHIFT   (19U)

Definition at line 15757 of file MIMXRT1052.h.

ENET_EIR_WAKEUP

#define ENET_EIR_WAKEUP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)

WAKEUP - Node Wakeup Request Indication

Definition at line 15750 of file MIMXRT1052.h.

ENET_EIR_WAKEUP_MASK

#define ENET_EIR_WAKEUP_MASK   (0x20000U)

Definition at line 15746 of file MIMXRT1052.h.

ENET_EIR_WAKEUP_SHIFT

#define ENET_EIR_WAKEUP_SHIFT   (17U)

Definition at line 15747 of file MIMXRT1052.h.

ENET_FTRL_TRUNC_FL

#define ENET_FTRL_TRUNC_FL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TRUNC_FL - Frame Truncation Length

Definition at line 16459 of file MIMXRT1052.h.

ENET_FTRL_TRUNC_FL_MASK

#define ENET_FTRL_TRUNC_FL_MASK   (0x3FFFU)

Definition at line 16455 of file MIMXRT1052.h.

ENET_FTRL_TRUNC_FL_SHIFT

#define ENET_FTRL_TRUNC_FL_SHIFT   (0U)

Definition at line 16456 of file MIMXRT1052.h.

ENET_GALR_GADDR2

#define ENET_GALR_GADDR2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)

Definition at line 16331 of file MIMXRT1052.h.

ENET_GALR_GADDR2_MASK

#define ENET_GALR_GADDR2_MASK   (0xFFFFFFFFU)

Definition at line 16329 of file MIMXRT1052.h.

ENET_GALR_GADDR2_SHIFT

#define ENET_GALR_GADDR2_SHIFT   (0U)

Definition at line 16330 of file MIMXRT1052.h.

ENET_GAUR_GADDR1

#define ENET_GAUR_GADDR1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)

Definition at line 16324 of file MIMXRT1052.h.

ENET_GAUR_GADDR1_MASK

#define ENET_GAUR_GADDR1_MASK   (0xFFFFFFFFU)

Definition at line 16322 of file MIMXRT1052.h.

ENET_GAUR_GADDR1_SHIFT

#define ENET_GAUR_GADDR1_SHIFT   (0U)

Definition at line 16323 of file MIMXRT1052.h.

ENET_IALR_IADDR2

#define ENET_IALR_IADDR2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)

Definition at line 16317 of file MIMXRT1052.h.

ENET_IALR_IADDR2_MASK

#define ENET_IALR_IADDR2_MASK   (0xFFFFFFFFU)

Definition at line 16315 of file MIMXRT1052.h.

ENET_IALR_IADDR2_SHIFT

#define ENET_IALR_IADDR2_SHIFT   (0U)

Definition at line 16316 of file MIMXRT1052.h.

ENET_IAUR_IADDR1

#define ENET_IAUR_IADDR1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)

Definition at line 16310 of file MIMXRT1052.h.

ENET_IAUR_IADDR1_MASK

#define ENET_IAUR_IADDR1_MASK   (0xFFFFFFFFU)

Definition at line 16308 of file MIMXRT1052.h.

ENET_IAUR_IADDR1_SHIFT

#define ENET_IAUR_IADDR1_SHIFT   (0U)

Definition at line 16309 of file MIMXRT1052.h.

ENET_IEEE_R_ALIGN_COUNT

#define ENET_IEEE_R_ALIGN_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

COUNT - Number of frames received with alignment error

Definition at line 16962 of file MIMXRT1052.h.

ENET_IEEE_R_ALIGN_COUNT_MASK

#define ENET_IEEE_R_ALIGN_COUNT_MASK   (0xFFFFU)

Definition at line 16958 of file MIMXRT1052.h.

ENET_IEEE_R_ALIGN_COUNT_SHIFT

#define ENET_IEEE_R_ALIGN_COUNT_SHIFT   (0U)

Definition at line 16959 of file MIMXRT1052.h.

ENET_IEEE_R_CRC_COUNT

#define ENET_IEEE_R_CRC_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

COUNT - Number of frames received with CRC error

Definition at line 16953 of file MIMXRT1052.h.

ENET_IEEE_R_CRC_COUNT_MASK

#define ENET_IEEE_R_CRC_COUNT_MASK   (0xFFFFU)

Definition at line 16949 of file MIMXRT1052.h.

ENET_IEEE_R_CRC_COUNT_SHIFT

#define ENET_IEEE_R_CRC_COUNT_SHIFT   (0U)

Definition at line 16950 of file MIMXRT1052.h.

ENET_IEEE_R_DROP_COUNT

#define ENET_IEEE_R_DROP_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

COUNT - Frame count

Definition at line 16935 of file MIMXRT1052.h.

ENET_IEEE_R_DROP_COUNT_MASK

#define ENET_IEEE_R_DROP_COUNT_MASK   (0xFFFFU)

Definition at line 16931 of file MIMXRT1052.h.

ENET_IEEE_R_DROP_COUNT_SHIFT

#define ENET_IEEE_R_DROP_COUNT_SHIFT   (0U)

Definition at line 16932 of file MIMXRT1052.h.

ENET_IEEE_R_FDXFC_COUNT

#define ENET_IEEE_R_FDXFC_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

COUNT - Number of flow-control pause frames received

Definition at line 16980 of file MIMXRT1052.h.

ENET_IEEE_R_FDXFC_COUNT_MASK

#define ENET_IEEE_R_FDXFC_COUNT_MASK   (0xFFFFU)

Definition at line 16976 of file MIMXRT1052.h.

ENET_IEEE_R_FDXFC_COUNT_SHIFT

#define ENET_IEEE_R_FDXFC_COUNT_SHIFT   (0U)

Definition at line 16977 of file MIMXRT1052.h.

ENET_IEEE_R_FRAME_OK_COUNT

#define ENET_IEEE_R_FRAME_OK_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

COUNT - Number of frames received OK

Definition at line 16944 of file MIMXRT1052.h.

ENET_IEEE_R_FRAME_OK_COUNT_MASK

#define ENET_IEEE_R_FRAME_OK_COUNT_MASK   (0xFFFFU)

Definition at line 16940 of file MIMXRT1052.h.

ENET_IEEE_R_FRAME_OK_COUNT_SHIFT

#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT   (0U)

Definition at line 16941 of file MIMXRT1052.h.

ENET_IEEE_R_MACERR_COUNT

#define ENET_IEEE_R_MACERR_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

COUNT - Receive FIFO overflow count

Definition at line 16971 of file MIMXRT1052.h.

ENET_IEEE_R_MACERR_COUNT_MASK

#define ENET_IEEE_R_MACERR_COUNT_MASK   (0xFFFFU)

Definition at line 16967 of file MIMXRT1052.h.

ENET_IEEE_R_MACERR_COUNT_SHIFT

#define ENET_IEEE_R_MACERR_COUNT_SHIFT   (0U)

Definition at line 16968 of file MIMXRT1052.h.

ENET_IEEE_R_OCTETS_OK_COUNT

#define ENET_IEEE_R_OCTETS_OK_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

COUNT - Number of octets for frames received without error

Definition at line 16989 of file MIMXRT1052.h.

ENET_IEEE_R_OCTETS_OK_COUNT_MASK

#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)

Definition at line 16985 of file MIMXRT1052.h.

ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT

#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT   (0U)

Definition at line 16986 of file MIMXRT1052.h.

ENET_IEEE_T_1COL_COUNT

#define ENET_IEEE_T_1COL_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

COUNT - Number of frames transmitted with one collision

Definition at line 16703 of file MIMXRT1052.h.

ENET_IEEE_T_1COL_COUNT_MASK

#define ENET_IEEE_T_1COL_COUNT_MASK   (0xFFFFU)

Definition at line 16699 of file MIMXRT1052.h.

ENET_IEEE_T_1COL_COUNT_SHIFT

#define ENET_IEEE_T_1COL_COUNT_SHIFT   (0U)

Definition at line 16700 of file MIMXRT1052.h.

ENET_IEEE_T_CSERR_COUNT

#define ENET_IEEE_T_CSERR_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

COUNT - Number of frames transmitted with carrier sense error

Definition at line 16757 of file MIMXRT1052.h.

ENET_IEEE_T_CSERR_COUNT_MASK

#define ENET_IEEE_T_CSERR_COUNT_MASK   (0xFFFFU)

Definition at line 16753 of file MIMXRT1052.h.

ENET_IEEE_T_CSERR_COUNT_SHIFT

#define ENET_IEEE_T_CSERR_COUNT_SHIFT   (0U)

Definition at line 16754 of file MIMXRT1052.h.

ENET_IEEE_T_DEF_COUNT

#define ENET_IEEE_T_DEF_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

COUNT - Number of frames transmitted with deferral delay

Definition at line 16721 of file MIMXRT1052.h.

ENET_IEEE_T_DEF_COUNT_MASK

#define ENET_IEEE_T_DEF_COUNT_MASK   (0xFFFFU)

Definition at line 16717 of file MIMXRT1052.h.

ENET_IEEE_T_DEF_COUNT_SHIFT

#define ENET_IEEE_T_DEF_COUNT_SHIFT   (0U)

Definition at line 16718 of file MIMXRT1052.h.

ENET_IEEE_T_EXCOL_COUNT

#define ENET_IEEE_T_EXCOL_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

COUNT - Number of frames transmitted with excessive collisions

Definition at line 16739 of file MIMXRT1052.h.

ENET_IEEE_T_EXCOL_COUNT_MASK

#define ENET_IEEE_T_EXCOL_COUNT_MASK   (0xFFFFU)

Definition at line 16735 of file MIMXRT1052.h.

ENET_IEEE_T_EXCOL_COUNT_SHIFT

#define ENET_IEEE_T_EXCOL_COUNT_SHIFT   (0U)

Definition at line 16736 of file MIMXRT1052.h.

ENET_IEEE_T_FDXFC_COUNT

#define ENET_IEEE_T_FDXFC_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

COUNT - Number of flow-control pause frames transmitted

Definition at line 16773 of file MIMXRT1052.h.

ENET_IEEE_T_FDXFC_COUNT_MASK

#define ENET_IEEE_T_FDXFC_COUNT_MASK   (0xFFFFU)

Definition at line 16769 of file MIMXRT1052.h.

ENET_IEEE_T_FDXFC_COUNT_SHIFT

#define ENET_IEEE_T_FDXFC_COUNT_SHIFT   (0U)

Definition at line 16770 of file MIMXRT1052.h.

ENET_IEEE_T_FRAME_OK_COUNT

#define ENET_IEEE_T_FRAME_OK_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

COUNT - Number of frames transmitted OK

Definition at line 16694 of file MIMXRT1052.h.

ENET_IEEE_T_FRAME_OK_COUNT_MASK

#define ENET_IEEE_T_FRAME_OK_COUNT_MASK   (0xFFFFU)

Definition at line 16690 of file MIMXRT1052.h.

ENET_IEEE_T_FRAME_OK_COUNT_SHIFT

#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT   (0U)

Definition at line 16691 of file MIMXRT1052.h.

ENET_IEEE_T_LCOL_COUNT

#define ENET_IEEE_T_LCOL_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

COUNT - Number of frames transmitted with late collision

Definition at line 16730 of file MIMXRT1052.h.

ENET_IEEE_T_LCOL_COUNT_MASK

#define ENET_IEEE_T_LCOL_COUNT_MASK   (0xFFFFU)

Definition at line 16726 of file MIMXRT1052.h.

ENET_IEEE_T_LCOL_COUNT_SHIFT

#define ENET_IEEE_T_LCOL_COUNT_SHIFT   (0U)

Definition at line 16727 of file MIMXRT1052.h.

ENET_IEEE_T_MACERR_COUNT

#define ENET_IEEE_T_MACERR_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

COUNT - Number of frames transmitted with transmit FIFO underrun

Definition at line 16748 of file MIMXRT1052.h.

ENET_IEEE_T_MACERR_COUNT_MASK

#define ENET_IEEE_T_MACERR_COUNT_MASK   (0xFFFFU)

Definition at line 16744 of file MIMXRT1052.h.

ENET_IEEE_T_MACERR_COUNT_SHIFT

#define ENET_IEEE_T_MACERR_COUNT_SHIFT   (0U)

Definition at line 16745 of file MIMXRT1052.h.

ENET_IEEE_T_MCOL_COUNT

#define ENET_IEEE_T_MCOL_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

COUNT - Number of frames transmitted with multiple collisions

Definition at line 16712 of file MIMXRT1052.h.

ENET_IEEE_T_MCOL_COUNT_MASK

#define ENET_IEEE_T_MCOL_COUNT_MASK   (0xFFFFU)

Definition at line 16708 of file MIMXRT1052.h.

ENET_IEEE_T_MCOL_COUNT_SHIFT

#define ENET_IEEE_T_MCOL_COUNT_SHIFT   (0U)

Definition at line 16709 of file MIMXRT1052.h.

ENET_IEEE_T_OCTETS_OK_COUNT

#define ENET_IEEE_T_OCTETS_OK_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).

Definition at line 16782 of file MIMXRT1052.h.

ENET_IEEE_T_OCTETS_OK_COUNT_MASK

#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)

Definition at line 16778 of file MIMXRT1052.h.

ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT

#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT   (0U)

Definition at line 16779 of file MIMXRT1052.h.

ENET_IEEE_T_SQE_COUNT

#define ENET_IEEE_T_SQE_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

Definition at line 16764 of file MIMXRT1052.h.

ENET_IEEE_T_SQE_COUNT_MASK

#define ENET_IEEE_T_SQE_COUNT_MASK   (0xFFFFU)

Definition at line 16762 of file MIMXRT1052.h.

ENET_IEEE_T_SQE_COUNT_SHIFT

#define ENET_IEEE_T_SQE_COUNT_SHIFT   (0U)

Definition at line 16763 of file MIMXRT1052.h.

ENET_MIBC_MIB_CLEAR

#define ENET_MIBC_MIB_CLEAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

Definition at line 16048 of file MIMXRT1052.h.

ENET_MIBC_MIB_CLEAR_MASK

#define ENET_MIBC_MIB_CLEAR_MASK   (0x20000000U)

Definition at line 16042 of file MIMXRT1052.h.

ENET_MIBC_MIB_CLEAR_SHIFT

#define ENET_MIBC_MIB_CLEAR_SHIFT   (29U)

Definition at line 16043 of file MIMXRT1052.h.

ENET_MIBC_MIB_DIS

#define ENET_MIBC_MIB_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

Definition at line 16062 of file MIMXRT1052.h.

ENET_MIBC_MIB_DIS_MASK

#define ENET_MIBC_MIB_DIS_MASK   (0x80000000U)

Definition at line 16056 of file MIMXRT1052.h.

ENET_MIBC_MIB_DIS_SHIFT

#define ENET_MIBC_MIB_DIS_SHIFT   (31U)

Definition at line 16057 of file MIMXRT1052.h.

ENET_MIBC_MIB_IDLE

#define ENET_MIBC_MIB_IDLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

Definition at line 16055 of file MIMXRT1052.h.

ENET_MIBC_MIB_IDLE_MASK

#define ENET_MIBC_MIB_IDLE_MASK   (0x40000000U)

Definition at line 16049 of file MIMXRT1052.h.

ENET_MIBC_MIB_IDLE_SHIFT

#define ENET_MIBC_MIB_IDLE_SHIFT   (30U)

Definition at line 16050 of file MIMXRT1052.h.

ENET_MMFR_DATA

#define ENET_MMFR_DATA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)

DATA - Management Frame Data

Definition at line 15987 of file MIMXRT1052.h.

ENET_MMFR_DATA_MASK

#define ENET_MMFR_DATA_MASK   (0xFFFFU)

Definition at line 15983 of file MIMXRT1052.h.

ENET_MMFR_DATA_SHIFT

#define ENET_MMFR_DATA_SHIFT   (0U)

Definition at line 15984 of file MIMXRT1052.h.

ENET_MMFR_OP

#define ENET_MMFR_OP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

OP - Operation Code

Definition at line 16007 of file MIMXRT1052.h.

ENET_MMFR_OP_MASK

#define ENET_MMFR_OP_MASK   (0x30000000U)

Definition at line 16003 of file MIMXRT1052.h.

ENET_MMFR_OP_SHIFT

#define ENET_MMFR_OP_SHIFT   (28U)

Definition at line 16004 of file MIMXRT1052.h.

ENET_MMFR_PA

#define ENET_MMFR_PA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)

PA - PHY Address

Definition at line 16002 of file MIMXRT1052.h.

ENET_MMFR_PA_MASK

#define ENET_MMFR_PA_MASK   (0xF800000U)

Definition at line 15998 of file MIMXRT1052.h.

ENET_MMFR_PA_SHIFT

#define ENET_MMFR_PA_SHIFT   (23U)

Definition at line 15999 of file MIMXRT1052.h.

ENET_MMFR_RA

#define ENET_MMFR_RA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)

RA - Register Address

Definition at line 15997 of file MIMXRT1052.h.

ENET_MMFR_RA_MASK

#define ENET_MMFR_RA_MASK   (0x7C0000U)

Definition at line 15993 of file MIMXRT1052.h.

ENET_MMFR_RA_SHIFT

#define ENET_MMFR_RA_SHIFT   (18U)

Definition at line 15994 of file MIMXRT1052.h.

ENET_MMFR_ST

#define ENET_MMFR_ST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

ST - Start Of Frame Delimiter

Definition at line 16012 of file MIMXRT1052.h.

ENET_MMFR_ST_MASK

#define ENET_MMFR_ST_MASK   (0xC0000000U)

Definition at line 16008 of file MIMXRT1052.h.

ENET_MMFR_ST_SHIFT

#define ENET_MMFR_ST_SHIFT   (30U)

Definition at line 16009 of file MIMXRT1052.h.

ENET_MMFR_TA

#define ENET_MMFR_TA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)

TA - Turn Around

Definition at line 15992 of file MIMXRT1052.h.

ENET_MMFR_TA_MASK

#define ENET_MMFR_TA_MASK   (0x30000U)

Definition at line 15988 of file MIMXRT1052.h.

ENET_MMFR_TA_SHIFT

#define ENET_MMFR_TA_SHIFT   (16U)

Definition at line 15989 of file MIMXRT1052.h.

ENET_MRBR_R_BUF_SIZE

#define ENET_MRBR_R_BUF_SIZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)

Definition at line 16373 of file MIMXRT1052.h.

ENET_MRBR_R_BUF_SIZE_MASK

#define ENET_MRBR_R_BUF_SIZE_MASK   (0x3FF0U)

Definition at line 16371 of file MIMXRT1052.h.

ENET_MRBR_R_BUF_SIZE_SHIFT

#define ENET_MRBR_R_BUF_SIZE_SHIFT   (4U)

Definition at line 16372 of file MIMXRT1052.h.

ENET_MSCR_DIS_PRE

#define ENET_MSCR_DIS_PRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

Definition at line 16028 of file MIMXRT1052.h.

ENET_MSCR_DIS_PRE_MASK

#define ENET_MSCR_DIS_PRE_MASK   (0x80U)

Definition at line 16022 of file MIMXRT1052.h.

ENET_MSCR_DIS_PRE_SHIFT

#define ENET_MSCR_DIS_PRE_SHIFT   (7U)

Definition at line 16023 of file MIMXRT1052.h.

ENET_MSCR_HOLDTIME

#define ENET_MSCR_HOLDTIME

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

Definition at line 16037 of file MIMXRT1052.h.

ENET_MSCR_HOLDTIME_MASK

#define ENET_MSCR_HOLDTIME_MASK   (0x700U)

Definition at line 16029 of file MIMXRT1052.h.

ENET_MSCR_HOLDTIME_SHIFT

#define ENET_MSCR_HOLDTIME_SHIFT   (8U)

Definition at line 16030 of file MIMXRT1052.h.

ENET_MSCR_MII_SPEED

#define ENET_MSCR_MII_SPEED

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)

MII_SPEED - MII Speed

Definition at line 16021 of file MIMXRT1052.h.

ENET_MSCR_MII_SPEED_MASK

#define ENET_MSCR_MII_SPEED_MASK   (0x7EU)

Definition at line 16017 of file MIMXRT1052.h.

ENET_MSCR_MII_SPEED_SHIFT

#define ENET_MSCR_MII_SPEED_SHIFT   (1U)

Definition at line 16018 of file MIMXRT1052.h.

ENET_OPD_OPCODE

#define ENET_OPD_OPCODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

OPCODE - Opcode Field In PAUSE Frames

Definition at line 16247 of file MIMXRT1052.h.

ENET_OPD_OPCODE_MASK

#define ENET_OPD_OPCODE_MASK   (0xFFFF0000U)

Definition at line 16243 of file MIMXRT1052.h.

ENET_OPD_OPCODE_SHIFT

#define ENET_OPD_OPCODE_SHIFT   (16U)

Definition at line 16244 of file MIMXRT1052.h.

ENET_OPD_PAUSE_DUR

#define ENET_OPD_PAUSE_DUR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)

PAUSE_DUR - Pause Duration

Definition at line 16242 of file MIMXRT1052.h.

ENET_OPD_PAUSE_DUR_MASK

#define ENET_OPD_PAUSE_DUR_MASK   (0xFFFFU)

Definition at line 16238 of file MIMXRT1052.h.

ENET_OPD_PAUSE_DUR_SHIFT

#define ENET_OPD_PAUSE_DUR_SHIFT   (0U)

Definition at line 16239 of file MIMXRT1052.h.

ENET_PALR_PADDR1

#define ENET_PALR_PADDR1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PADDR1 - Pause Address

Definition at line 16221 of file MIMXRT1052.h.

ENET_PALR_PADDR1_MASK

#define ENET_PALR_PADDR1_MASK   (0xFFFFFFFFU)

Definition at line 16217 of file MIMXRT1052.h.

ENET_PALR_PADDR1_SHIFT

#define ENET_PALR_PADDR1_SHIFT   (0U)

Definition at line 16218 of file MIMXRT1052.h.

ENET_PAUR_PADDR2

#define ENET_PAUR_PADDR2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)

Definition at line 16233 of file MIMXRT1052.h.

ENET_PAUR_PADDR2_MASK

#define ENET_PAUR_PADDR2_MASK   (0xFFFF0000U)

Definition at line 16231 of file MIMXRT1052.h.

ENET_PAUR_PADDR2_SHIFT

#define ENET_PAUR_PADDR2_SHIFT   (16U)

Definition at line 16232 of file MIMXRT1052.h.

ENET_PAUR_TYPE

#define ENET_PAUR_TYPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)

TYPE - Type Field In PAUSE Frames

Definition at line 16230 of file MIMXRT1052.h.

ENET_PAUR_TYPE_MASK

#define ENET_PAUR_TYPE_MASK   (0xFFFFU)

Definition at line 16226 of file MIMXRT1052.h.

ENET_PAUR_TYPE_SHIFT

#define ENET_PAUR_TYPE_SHIFT   (0U)

Definition at line 16227 of file MIMXRT1052.h.

ENET_RACC_IPDIS

#define ENET_RACC_IPDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

Definition at line 16509 of file MIMXRT1052.h.

ENET_RACC_IPDIS_MASK

#define ENET_RACC_IPDIS_MASK   (0x2U)

Definition at line 16501 of file MIMXRT1052.h.

ENET_RACC_IPDIS_SHIFT

#define ENET_RACC_IPDIS_SHIFT   (1U)

Definition at line 16502 of file MIMXRT1052.h.

ENET_RACC_LINEDIS

#define ENET_RACC_LINEDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

Definition at line 16525 of file MIMXRT1052.h.

ENET_RACC_LINEDIS_MASK

#define ENET_RACC_LINEDIS_MASK   (0x40U)

Definition at line 16519 of file MIMXRT1052.h.

ENET_RACC_LINEDIS_SHIFT

#define ENET_RACC_LINEDIS_SHIFT   (6U)

Definition at line 16520 of file MIMXRT1052.h.

ENET_RACC_PADREM

#define ENET_RACC_PADREM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

Definition at line 16500 of file MIMXRT1052.h.

ENET_RACC_PADREM_MASK

#define ENET_RACC_PADREM_MASK   (0x1U)

Definition at line 16494 of file MIMXRT1052.h.

ENET_RACC_PADREM_SHIFT

#define ENET_RACC_PADREM_SHIFT   (0U)

Definition at line 16495 of file MIMXRT1052.h.

ENET_RACC_PRODIS

#define ENET_RACC_PRODIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

Definition at line 16518 of file MIMXRT1052.h.

ENET_RACC_PRODIS_MASK

#define ENET_RACC_PRODIS_MASK   (0x4U)

Definition at line 16510 of file MIMXRT1052.h.

ENET_RACC_PRODIS_SHIFT

#define ENET_RACC_PRODIS_SHIFT   (2U)

Definition at line 16511 of file MIMXRT1052.h.

ENET_RACC_SHIFT16

#define ENET_RACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

Definition at line 16532 of file MIMXRT1052.h.

ENET_RACC_SHIFT16_MASK

#define ENET_RACC_SHIFT16_MASK   (0x80U)

Definition at line 16526 of file MIMXRT1052.h.

ENET_RACC_SHIFT16_SHIFT

#define ENET_RACC_SHIFT16_SHIFT   (7U)

Definition at line 16527 of file MIMXRT1052.h.

ENET_RAEM_RX_ALMOST_EMPTY

#define ENET_RAEM_RX_ALMOST_EMPTY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)

RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold

Definition at line 16405 of file MIMXRT1052.h.

ENET_RAEM_RX_ALMOST_EMPTY_MASK

#define ENET_RAEM_RX_ALMOST_EMPTY_MASK   (0xFFU)

Definition at line 16401 of file MIMXRT1052.h.

ENET_RAEM_RX_ALMOST_EMPTY_SHIFT

#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   (0U)

Definition at line 16402 of file MIMXRT1052.h.

ENET_RAFL_RX_ALMOST_FULL

#define ENET_RAFL_RX_ALMOST_FULL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)

RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold

Definition at line 16414 of file MIMXRT1052.h.

ENET_RAFL_RX_ALMOST_FULL_MASK

#define ENET_RAFL_RX_ALMOST_FULL_MASK   (0xFFU)

Definition at line 16410 of file MIMXRT1052.h.

ENET_RAFL_RX_ALMOST_FULL_SHIFT

#define ENET_RAFL_RX_ALMOST_FULL_SHIFT   (0U)

Definition at line 16411 of file MIMXRT1052.h.

ENET_RCR_BC_REJ

#define ENET_RCR_BC_REJ

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)

BC_REJ - Broadcast Frame Reject

Definition at line 16099 of file MIMXRT1052.h.

ENET_RCR_BC_REJ_MASK

#define ENET_RCR_BC_REJ_MASK   (0x10U)

Definition at line 16095 of file MIMXRT1052.h.

ENET_RCR_BC_REJ_SHIFT

#define ENET_RCR_BC_REJ_SHIFT   (4U)

Definition at line 16096 of file MIMXRT1052.h.

ENET_RCR_CFEN

#define ENET_RCR_CFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

Definition at line 16146 of file MIMXRT1052.h.

ENET_RCR_CFEN_MASK

#define ENET_RCR_CFEN_MASK   (0x8000U)

Definition at line 16140 of file MIMXRT1052.h.

ENET_RCR_CFEN_SHIFT

#define ENET_RCR_CFEN_SHIFT   (15U)

Definition at line 16141 of file MIMXRT1052.h.

ENET_RCR_CRCFWD

#define ENET_RCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

Definition at line 16139 of file MIMXRT1052.h.

ENET_RCR_CRCFWD_MASK

#define ENET_RCR_CRCFWD_MASK   (0x4000U)

Definition at line 16133 of file MIMXRT1052.h.

ENET_RCR_CRCFWD_SHIFT

#define ENET_RCR_CRCFWD_SHIFT   (14U)

Definition at line 16134 of file MIMXRT1052.h.

ENET_RCR_DRT

#define ENET_RCR_DRT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

Definition at line 16080 of file MIMXRT1052.h.

ENET_RCR_DRT_MASK

#define ENET_RCR_DRT_MASK   (0x2U)

Definition at line 16074 of file MIMXRT1052.h.

ENET_RCR_DRT_SHIFT

#define ENET_RCR_DRT_SHIFT   (1U)

Definition at line 16075 of file MIMXRT1052.h.

ENET_RCR_FCE

#define ENET_RCR_FCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)

FCE - Flow Control Enable

Definition at line 16104 of file MIMXRT1052.h.

ENET_RCR_FCE_MASK

#define ENET_RCR_FCE_MASK   (0x20U)

Definition at line 16100 of file MIMXRT1052.h.

ENET_RCR_FCE_SHIFT

#define ENET_RCR_FCE_SHIFT   (5U)

Definition at line 16101 of file MIMXRT1052.h.

ENET_RCR_GRS

#define ENET_RCR_GRS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

GRS - Graceful Receive Stopped

Definition at line 16163 of file MIMXRT1052.h.

ENET_RCR_GRS_MASK

#define ENET_RCR_GRS_MASK   (0x80000000U)

Definition at line 16159 of file MIMXRT1052.h.

ENET_RCR_GRS_SHIFT

#define ENET_RCR_GRS_SHIFT   (31U)

Definition at line 16160 of file MIMXRT1052.h.

ENET_RCR_LOOP

#define ENET_RCR_LOOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

Definition at line 16073 of file MIMXRT1052.h.

ENET_RCR_LOOP_MASK

#define ENET_RCR_LOOP_MASK   (0x1U)

Definition at line 16067 of file MIMXRT1052.h.

ENET_RCR_LOOP_SHIFT

#define ENET_RCR_LOOP_SHIFT   (0U)

Definition at line 16068 of file MIMXRT1052.h.

ENET_RCR_MAX_FL

#define ENET_RCR_MAX_FL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)

MAX_FL - Maximum Frame Length

Definition at line 16151 of file MIMXRT1052.h.

ENET_RCR_MAX_FL_MASK

#define ENET_RCR_MAX_FL_MASK   (0x3FFF0000U)

Definition at line 16147 of file MIMXRT1052.h.

ENET_RCR_MAX_FL_SHIFT

#define ENET_RCR_MAX_FL_SHIFT   (16U)

Definition at line 16148 of file MIMXRT1052.h.

ENET_RCR_MII_MODE

#define ENET_RCR_MII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

Definition at line 16087 of file MIMXRT1052.h.

ENET_RCR_MII_MODE_MASK

#define ENET_RCR_MII_MODE_MASK   (0x4U)

Definition at line 16081 of file MIMXRT1052.h.

ENET_RCR_MII_MODE_SHIFT

#define ENET_RCR_MII_MODE_SHIFT   (2U)

Definition at line 16082 of file MIMXRT1052.h.

ENET_RCR_NLC

#define ENET_RCR_NLC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.

Definition at line 16158 of file MIMXRT1052.h.

ENET_RCR_NLC_MASK

#define ENET_RCR_NLC_MASK   (0x40000000U)

Definition at line 16152 of file MIMXRT1052.h.

ENET_RCR_NLC_SHIFT

#define ENET_RCR_NLC_SHIFT   (30U)

Definition at line 16153 of file MIMXRT1052.h.

ENET_RCR_PADEN

#define ENET_RCR_PADEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

Definition at line 16125 of file MIMXRT1052.h.

ENET_RCR_PADEN_MASK

#define ENET_RCR_PADEN_MASK   (0x1000U)

Definition at line 16119 of file MIMXRT1052.h.

ENET_RCR_PADEN_SHIFT

#define ENET_RCR_PADEN_SHIFT   (12U)

Definition at line 16120 of file MIMXRT1052.h.

ENET_RCR_PAUFWD

#define ENET_RCR_PAUFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

Definition at line 16132 of file MIMXRT1052.h.

ENET_RCR_PAUFWD_MASK

#define ENET_RCR_PAUFWD_MASK   (0x2000U)

Definition at line 16126 of file MIMXRT1052.h.

ENET_RCR_PAUFWD_SHIFT

#define ENET_RCR_PAUFWD_SHIFT   (13U)

Definition at line 16127 of file MIMXRT1052.h.

ENET_RCR_PROM

#define ENET_RCR_PROM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

Definition at line 16094 of file MIMXRT1052.h.

ENET_RCR_PROM_MASK

#define ENET_RCR_PROM_MASK   (0x8U)

Definition at line 16088 of file MIMXRT1052.h.

ENET_RCR_PROM_SHIFT

#define ENET_RCR_PROM_SHIFT   (3U)

Definition at line 16089 of file MIMXRT1052.h.

ENET_RCR_RMII_10T

#define ENET_RCR_RMII_10T

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.

Definition at line 16118 of file MIMXRT1052.h.

ENET_RCR_RMII_10T_MASK

#define ENET_RCR_RMII_10T_MASK   (0x200U)

Definition at line 16112 of file MIMXRT1052.h.

ENET_RCR_RMII_10T_SHIFT

#define ENET_RCR_RMII_10T_SHIFT   (9U)

Definition at line 16113 of file MIMXRT1052.h.

ENET_RCR_RMII_MODE

#define ENET_RCR_RMII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

Definition at line 16111 of file MIMXRT1052.h.

ENET_RCR_RMII_MODE_MASK

#define ENET_RCR_RMII_MODE_MASK   (0x100U)

Definition at line 16105 of file MIMXRT1052.h.

ENET_RCR_RMII_MODE_SHIFT

#define ENET_RCR_RMII_MODE_SHIFT   (8U)

Definition at line 16106 of file MIMXRT1052.h.

ENET_RDAR_RDAR

#define ENET_RDAR_RDAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

RDAR - Receive Descriptor Active

Definition at line 15918 of file MIMXRT1052.h.

ENET_RDAR_RDAR_MASK

#define ENET_RDAR_RDAR_MASK   (0x1000000U)

Definition at line 15914 of file MIMXRT1052.h.

ENET_RDAR_RDAR_SHIFT

#define ENET_RDAR_RDAR_SHIFT   (24U)

Definition at line 15915 of file MIMXRT1052.h.

ENET_RDSR_R_DES_START

#define ENET_RDSR_R_DES_START

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)

Definition at line 16359 of file MIMXRT1052.h.

ENET_RDSR_R_DES_START_MASK

#define ENET_RDSR_R_DES_START_MASK   (0xFFFFFFF8U)

Definition at line 16357 of file MIMXRT1052.h.

ENET_RDSR_R_DES_START_SHIFT

#define ENET_RDSR_R_DES_START_SHIFT   (3U)

Definition at line 16358 of file MIMXRT1052.h.

ENET_RMON_R_BC_PKT_COUNT

#define ENET_RMON_R_BC_PKT_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

COUNT - Number of receive broadcast packets

Definition at line 16800 of file MIMXRT1052.h.

ENET_RMON_R_BC_PKT_COUNT_MASK

#define ENET_RMON_R_BC_PKT_COUNT_MASK   (0xFFFFU)

Definition at line 16796 of file MIMXRT1052.h.

ENET_RMON_R_BC_PKT_COUNT_SHIFT

#define ENET_RMON_R_BC_PKT_COUNT_SHIFT   (0U)

Definition at line 16797 of file MIMXRT1052.h.

ENET_RMON_R_CRC_ALIGN_COUNT

#define ENET_RMON_R_CRC_ALIGN_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

COUNT - Number of receive packets with CRC or align error

Definition at line 16818 of file MIMXRT1052.h.

ENET_RMON_R_CRC_ALIGN_COUNT_MASK

#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK   (0xFFFFU)

Definition at line 16814 of file MIMXRT1052.h.

ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT

#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT   (0U)

Definition at line 16815 of file MIMXRT1052.h.

ENET_RMON_R_FRAG_COUNT

#define ENET_RMON_R_FRAG_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

COUNT - Number of receive packets with less than 64 bytes and bad CRC

Definition at line 16845 of file MIMXRT1052.h.

ENET_RMON_R_FRAG_COUNT_MASK

#define ENET_RMON_R_FRAG_COUNT_MASK   (0xFFFFU)

Definition at line 16841 of file MIMXRT1052.h.

ENET_RMON_R_FRAG_COUNT_SHIFT

#define ENET_RMON_R_FRAG_COUNT_SHIFT   (0U)

Definition at line 16842 of file MIMXRT1052.h.

ENET_RMON_R_JAB_COUNT

#define ENET_RMON_R_JAB_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

COUNT - Number of receive packets greater than MAX_FL and bad CRC

Definition at line 16854 of file MIMXRT1052.h.

ENET_RMON_R_JAB_COUNT_MASK

#define ENET_RMON_R_JAB_COUNT_MASK   (0xFFFFU)

Definition at line 16850 of file MIMXRT1052.h.

ENET_RMON_R_JAB_COUNT_SHIFT

#define ENET_RMON_R_JAB_COUNT_SHIFT   (0U)

Definition at line 16851 of file MIMXRT1052.h.

ENET_RMON_R_MC_PKT_COUNT

#define ENET_RMON_R_MC_PKT_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

COUNT - Number of receive multicast packets

Definition at line 16809 of file MIMXRT1052.h.

ENET_RMON_R_MC_PKT_COUNT_MASK

#define ENET_RMON_R_MC_PKT_COUNT_MASK   (0xFFFFU)

Definition at line 16805 of file MIMXRT1052.h.

ENET_RMON_R_MC_PKT_COUNT_SHIFT

#define ENET_RMON_R_MC_PKT_COUNT_SHIFT   (0U)

Definition at line 16806 of file MIMXRT1052.h.

ENET_RMON_R_OCTETS_COUNT

#define ENET_RMON_R_OCTETS_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

COUNT - Number of receive octets

Definition at line 16926 of file MIMXRT1052.h.

ENET_RMON_R_OCTETS_COUNT_MASK

#define ENET_RMON_R_OCTETS_COUNT_MASK   (0xFFFFFFFFU)

Definition at line 16922 of file MIMXRT1052.h.

ENET_RMON_R_OCTETS_COUNT_SHIFT

#define ENET_RMON_R_OCTETS_COUNT_SHIFT   (0U)

Definition at line 16923 of file MIMXRT1052.h.

ENET_RMON_R_OVERSIZE_COUNT

#define ENET_RMON_R_OVERSIZE_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

COUNT - Number of receive packets greater than MAX_FL and good CRC

Definition at line 16836 of file MIMXRT1052.h.

ENET_RMON_R_OVERSIZE_COUNT_MASK

#define ENET_RMON_R_OVERSIZE_COUNT_MASK   (0xFFFFU)

Definition at line 16832 of file MIMXRT1052.h.

ENET_RMON_R_OVERSIZE_COUNT_SHIFT

#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT   (0U)

Definition at line 16833 of file MIMXRT1052.h.

ENET_RMON_R_P1024TO2047_COUNT

#define ENET_RMON_R_P1024TO2047_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

COUNT - Number of 1024- to 2047-byte recieve packets

Definition at line 16908 of file MIMXRT1052.h.

ENET_RMON_R_P1024TO2047_COUNT_MASK

#define ENET_RMON_R_P1024TO2047_COUNT_MASK   (0xFFFFU)

Definition at line 16904 of file MIMXRT1052.h.

ENET_RMON_R_P1024TO2047_COUNT_SHIFT

#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT   (0U)

Definition at line 16905 of file MIMXRT1052.h.

ENET_RMON_R_P128TO255_COUNT

#define ENET_RMON_R_P128TO255_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

COUNT - Number of 128- to 255-byte recieve packets

Definition at line 16881 of file MIMXRT1052.h.

ENET_RMON_R_P128TO255_COUNT_MASK

#define ENET_RMON_R_P128TO255_COUNT_MASK   (0xFFFFU)

Definition at line 16877 of file MIMXRT1052.h.

ENET_RMON_R_P128TO255_COUNT_SHIFT

#define ENET_RMON_R_P128TO255_COUNT_SHIFT   (0U)

Definition at line 16878 of file MIMXRT1052.h.

ENET_RMON_R_P256TO511_COUNT

#define ENET_RMON_R_P256TO511_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

COUNT - Number of 256- to 511-byte recieve packets

Definition at line 16890 of file MIMXRT1052.h.

ENET_RMON_R_P256TO511_COUNT_MASK

#define ENET_RMON_R_P256TO511_COUNT_MASK   (0xFFFFU)

Definition at line 16886 of file MIMXRT1052.h.

ENET_RMON_R_P256TO511_COUNT_SHIFT

#define ENET_RMON_R_P256TO511_COUNT_SHIFT   (0U)

Definition at line 16887 of file MIMXRT1052.h.

ENET_RMON_R_P512TO1023_COUNT

#define ENET_RMON_R_P512TO1023_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

COUNT - Number of 512- to 1023-byte recieve packets

Definition at line 16899 of file MIMXRT1052.h.

ENET_RMON_R_P512TO1023_COUNT_MASK

#define ENET_RMON_R_P512TO1023_COUNT_MASK   (0xFFFFU)

Definition at line 16895 of file MIMXRT1052.h.

ENET_RMON_R_P512TO1023_COUNT_SHIFT

#define ENET_RMON_R_P512TO1023_COUNT_SHIFT   (0U)

Definition at line 16896 of file MIMXRT1052.h.

ENET_RMON_R_P64_COUNT

#define ENET_RMON_R_P64_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

COUNT - Number of 64-byte receive packets

Definition at line 16863 of file MIMXRT1052.h.

ENET_RMON_R_P64_COUNT_MASK

#define ENET_RMON_R_P64_COUNT_MASK   (0xFFFFU)

Definition at line 16859 of file MIMXRT1052.h.

ENET_RMON_R_P64_COUNT_SHIFT

#define ENET_RMON_R_P64_COUNT_SHIFT   (0U)

Definition at line 16860 of file MIMXRT1052.h.

ENET_RMON_R_P65TO127_COUNT

#define ENET_RMON_R_P65TO127_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

COUNT - Number of 65- to 127-byte recieve packets

Definition at line 16872 of file MIMXRT1052.h.

ENET_RMON_R_P65TO127_COUNT_MASK

#define ENET_RMON_R_P65TO127_COUNT_MASK   (0xFFFFU)

Definition at line 16868 of file MIMXRT1052.h.

ENET_RMON_R_P65TO127_COUNT_SHIFT

#define ENET_RMON_R_P65TO127_COUNT_SHIFT   (0U)

Definition at line 16869 of file MIMXRT1052.h.

ENET_RMON_R_P_GTE2048_COUNT

#define ENET_RMON_R_P_GTE2048_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

COUNT - Number of greater-than-2048-byte recieve packets

Definition at line 16917 of file MIMXRT1052.h.

ENET_RMON_R_P_GTE2048_COUNT_MASK

#define ENET_RMON_R_P_GTE2048_COUNT_MASK   (0xFFFFU)

Definition at line 16913 of file MIMXRT1052.h.

ENET_RMON_R_P_GTE2048_COUNT_SHIFT

#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT   (0U)

Definition at line 16914 of file MIMXRT1052.h.

ENET_RMON_R_PACKETS_COUNT

#define ENET_RMON_R_PACKETS_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

COUNT - Number of packets received

Definition at line 16791 of file MIMXRT1052.h.

ENET_RMON_R_PACKETS_COUNT_MASK

#define ENET_RMON_R_PACKETS_COUNT_MASK   (0xFFFFU)

Definition at line 16787 of file MIMXRT1052.h.

ENET_RMON_R_PACKETS_COUNT_SHIFT

#define ENET_RMON_R_PACKETS_COUNT_SHIFT   (0U)

Definition at line 16788 of file MIMXRT1052.h.

ENET_RMON_R_UNDERSIZE_COUNT

#define ENET_RMON_R_UNDERSIZE_COUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

COUNT - Number of receive packets with less than 64 bytes and good CRC

Definition at line 16827 of file MIMXRT1052.h.

ENET_RMON_R_UNDERSIZE_COUNT_MASK

#define ENET_RMON_R_UNDERSIZE_COUNT_MASK   (0xFFFFU)

Definition at line 16823 of file MIMXRT1052.h.

ENET_RMON_R_UNDERSIZE_COUNT_SHIFT

#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT   (0U)

Definition at line 16824 of file MIMXRT1052.h.

ENET_RMON_T_BC_PKT_TXPKTS

#define ENET_RMON_T_BC_PKT_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

TXPKTS - Broadcast packets

Definition at line 16550 of file MIMXRT1052.h.

ENET_RMON_T_BC_PKT_TXPKTS_MASK

#define ENET_RMON_T_BC_PKT_TXPKTS_MASK   (0xFFFFU)

Definition at line 16546 of file MIMXRT1052.h.

ENET_RMON_T_BC_PKT_TXPKTS_SHIFT

#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT   (0U)

Definition at line 16547 of file MIMXRT1052.h.

ENET_RMON_T_COL_TXPKTS

#define ENET_RMON_T_COL_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

TXPKTS - Number of transmit collisions

Definition at line 16613 of file MIMXRT1052.h.

ENET_RMON_T_COL_TXPKTS_MASK

#define ENET_RMON_T_COL_TXPKTS_MASK   (0xFFFFU)

Definition at line 16609 of file MIMXRT1052.h.

ENET_RMON_T_COL_TXPKTS_SHIFT

#define ENET_RMON_T_COL_TXPKTS_SHIFT   (0U)

Definition at line 16610 of file MIMXRT1052.h.

ENET_RMON_T_CRC_ALIGN_TXPKTS

#define ENET_RMON_T_CRC_ALIGN_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

TXPKTS - Packets with CRC/align error

Definition at line 16568 of file MIMXRT1052.h.

ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK

#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK   (0xFFFFU)

Definition at line 16564 of file MIMXRT1052.h.

ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT

#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT   (0U)

Definition at line 16565 of file MIMXRT1052.h.

ENET_RMON_T_FRAG_TXPKTS

#define ENET_RMON_T_FRAG_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

TXPKTS - Number of packets less than 64 bytes with bad CRC

Definition at line 16595 of file MIMXRT1052.h.

ENET_RMON_T_FRAG_TXPKTS_MASK

#define ENET_RMON_T_FRAG_TXPKTS_MASK   (0xFFFFU)

Definition at line 16591 of file MIMXRT1052.h.

ENET_RMON_T_FRAG_TXPKTS_SHIFT

#define ENET_RMON_T_FRAG_TXPKTS_SHIFT   (0U)

Definition at line 16592 of file MIMXRT1052.h.

ENET_RMON_T_JAB_TXPKTS

#define ENET_RMON_T_JAB_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC

Definition at line 16604 of file MIMXRT1052.h.

ENET_RMON_T_JAB_TXPKTS_MASK

#define ENET_RMON_T_JAB_TXPKTS_MASK   (0xFFFFU)

Definition at line 16600 of file MIMXRT1052.h.

ENET_RMON_T_JAB_TXPKTS_SHIFT

#define ENET_RMON_T_JAB_TXPKTS_SHIFT   (0U)

Definition at line 16601 of file MIMXRT1052.h.

ENET_RMON_T_MC_PKT_TXPKTS

#define ENET_RMON_T_MC_PKT_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

TXPKTS - Multicast packets

Definition at line 16559 of file MIMXRT1052.h.

ENET_RMON_T_MC_PKT_TXPKTS_MASK

#define ENET_RMON_T_MC_PKT_TXPKTS_MASK   (0xFFFFU)

Definition at line 16555 of file MIMXRT1052.h.

ENET_RMON_T_MC_PKT_TXPKTS_SHIFT

#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT   (0U)

Definition at line 16556 of file MIMXRT1052.h.

ENET_RMON_T_OCTETS_TXOCTS

#define ENET_RMON_T_OCTETS_TXOCTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

TXOCTS - Number of transmit octets

Definition at line 16685 of file MIMXRT1052.h.

ENET_RMON_T_OCTETS_TXOCTS_MASK

#define ENET_RMON_T_OCTETS_TXOCTS_MASK   (0xFFFFFFFFU)

Definition at line 16681 of file MIMXRT1052.h.

ENET_RMON_T_OCTETS_TXOCTS_SHIFT

#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT   (0U)

Definition at line 16682 of file MIMXRT1052.h.

ENET_RMON_T_OVERSIZE_TXPKTS

#define ENET_RMON_T_OVERSIZE_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC

Definition at line 16586 of file MIMXRT1052.h.

ENET_RMON_T_OVERSIZE_TXPKTS_MASK

#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK   (0xFFFFU)

Definition at line 16582 of file MIMXRT1052.h.

ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT

#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT   (0U)

Definition at line 16583 of file MIMXRT1052.h.

ENET_RMON_T_P1024TO2047_TXPKTS

#define ENET_RMON_T_P1024TO2047_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

TXPKTS - Number of 1024- to 2047-byte transmit packets

Definition at line 16667 of file MIMXRT1052.h.

ENET_RMON_T_P1024TO2047_TXPKTS_MASK

#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK   (0xFFFFU)

Definition at line 16663 of file MIMXRT1052.h.

ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT

#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT   (0U)

Definition at line 16664 of file MIMXRT1052.h.

ENET_RMON_T_P128TO255_TXPKTS

#define ENET_RMON_T_P128TO255_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

TXPKTS - Number of 128- to 255-byte transmit packets

Definition at line 16640 of file MIMXRT1052.h.

ENET_RMON_T_P128TO255_TXPKTS_MASK

#define ENET_RMON_T_P128TO255_TXPKTS_MASK   (0xFFFFU)

Definition at line 16636 of file MIMXRT1052.h.

ENET_RMON_T_P128TO255_TXPKTS_SHIFT

#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT   (0U)

Definition at line 16637 of file MIMXRT1052.h.

ENET_RMON_T_P256TO511_TXPKTS

#define ENET_RMON_T_P256TO511_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

TXPKTS - Number of 256- to 511-byte transmit packets

Definition at line 16649 of file MIMXRT1052.h.

ENET_RMON_T_P256TO511_TXPKTS_MASK

#define ENET_RMON_T_P256TO511_TXPKTS_MASK   (0xFFFFU)

Definition at line 16645 of file MIMXRT1052.h.

ENET_RMON_T_P256TO511_TXPKTS_SHIFT

#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT   (0U)

Definition at line 16646 of file MIMXRT1052.h.

ENET_RMON_T_P512TO1023_TXPKTS

#define ENET_RMON_T_P512TO1023_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

TXPKTS - Number of 512- to 1023-byte transmit packets

Definition at line 16658 of file MIMXRT1052.h.

ENET_RMON_T_P512TO1023_TXPKTS_MASK

#define ENET_RMON_T_P512TO1023_TXPKTS_MASK   (0xFFFFU)

Definition at line 16654 of file MIMXRT1052.h.

ENET_RMON_T_P512TO1023_TXPKTS_SHIFT

#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT   (0U)

Definition at line 16655 of file MIMXRT1052.h.

ENET_RMON_T_P64_TXPKTS

#define ENET_RMON_T_P64_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

TXPKTS - Number of 64-byte transmit packets

Definition at line 16622 of file MIMXRT1052.h.

ENET_RMON_T_P64_TXPKTS_MASK

#define ENET_RMON_T_P64_TXPKTS_MASK   (0xFFFFU)

Definition at line 16618 of file MIMXRT1052.h.

ENET_RMON_T_P64_TXPKTS_SHIFT

#define ENET_RMON_T_P64_TXPKTS_SHIFT   (0U)

Definition at line 16619 of file MIMXRT1052.h.

ENET_RMON_T_P65TO127_TXPKTS

#define ENET_RMON_T_P65TO127_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

TXPKTS - Number of 65- to 127-byte transmit packets

Definition at line 16631 of file MIMXRT1052.h.

ENET_RMON_T_P65TO127_TXPKTS_MASK

#define ENET_RMON_T_P65TO127_TXPKTS_MASK   (0xFFFFU)

Definition at line 16627 of file MIMXRT1052.h.

ENET_RMON_T_P65TO127_TXPKTS_SHIFT

#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT   (0U)

Definition at line 16628 of file MIMXRT1052.h.

ENET_RMON_T_P_GTE2048_TXPKTS

#define ENET_RMON_T_P_GTE2048_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than 2048 bytes

Definition at line 16676 of file MIMXRT1052.h.

ENET_RMON_T_P_GTE2048_TXPKTS_MASK

#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK   (0xFFFFU)

Definition at line 16672 of file MIMXRT1052.h.

ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT

#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT   (0U)

Definition at line 16673 of file MIMXRT1052.h.

ENET_RMON_T_PACKETS_TXPKTS

#define ENET_RMON_T_PACKETS_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

TXPKTS - Packet count

Definition at line 16541 of file MIMXRT1052.h.

ENET_RMON_T_PACKETS_TXPKTS_MASK

#define ENET_RMON_T_PACKETS_TXPKTS_MASK   (0xFFFFU)

Definition at line 16537 of file MIMXRT1052.h.

ENET_RMON_T_PACKETS_TXPKTS_SHIFT

#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT   (0U)

Definition at line 16538 of file MIMXRT1052.h.

ENET_RMON_T_UNDERSIZE_TXPKTS

#define ENET_RMON_T_UNDERSIZE_TXPKTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

TXPKTS - Number of transmit packets less than 64 bytes with good CRC

Definition at line 16577 of file MIMXRT1052.h.

ENET_RMON_T_UNDERSIZE_TXPKTS_MASK

#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK   (0xFFFFU)

Definition at line 16573 of file MIMXRT1052.h.

ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT

#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT   (0U)

Definition at line 16574 of file MIMXRT1052.h.

ENET_RSEM_RX_SECTION_EMPTY

#define ENET_RSEM_RX_SECTION_EMPTY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)

RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold

Definition at line 16391 of file MIMXRT1052.h.

ENET_RSEM_RX_SECTION_EMPTY_MASK

#define ENET_RSEM_RX_SECTION_EMPTY_MASK   (0xFFU)

Definition at line 16387 of file MIMXRT1052.h.

ENET_RSEM_RX_SECTION_EMPTY_SHIFT

#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT   (0U)

Definition at line 16388 of file MIMXRT1052.h.

ENET_RSEM_STAT_SECTION_EMPTY

#define ENET_RSEM_STAT_SECTION_EMPTY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold

Definition at line 16396 of file MIMXRT1052.h.

ENET_RSEM_STAT_SECTION_EMPTY_MASK

#define ENET_RSEM_STAT_SECTION_EMPTY_MASK   (0x1F0000U)

Definition at line 16392 of file MIMXRT1052.h.

ENET_RSEM_STAT_SECTION_EMPTY_SHIFT

#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT   (16U)

Definition at line 16393 of file MIMXRT1052.h.

ENET_RSFL_RX_SECTION_FULL

#define ENET_RSFL_RX_SECTION_FULL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)

RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold

Definition at line 16382 of file MIMXRT1052.h.

ENET_RSFL_RX_SECTION_FULL_MASK

#define ENET_RSFL_RX_SECTION_FULL_MASK   (0xFFU)

Definition at line 16378 of file MIMXRT1052.h.

ENET_RSFL_RX_SECTION_FULL_SHIFT

#define ENET_RSFL_RX_SECTION_FULL_SHIFT   (0U)

Definition at line 16379 of file MIMXRT1052.h.

ENET_RXIC_ICCS

#define ENET_RXIC_ICCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)

ICCS - Interrupt Coalescing Timer Clock Source Select 0b0..Use MII/GMII TX clocks. 0b1..Use ENET system clock.

Definition at line 16296 of file MIMXRT1052.h.

ENET_RXIC_ICCS_MASK

#define ENET_RXIC_ICCS_MASK   (0x40000000U)

Definition at line 16290 of file MIMXRT1052.h.

ENET_RXIC_ICCS_SHIFT

#define ENET_RXIC_ICCS_SHIFT   (30U)

Definition at line 16291 of file MIMXRT1052.h.

ENET_RXIC_ICEN

#define ENET_RXIC_ICEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)

ICEN - Interrupt Coalescing Enable 0b0..Disable Interrupt coalescing. 0b1..Enable Interrupt coalescing.

Definition at line 16303 of file MIMXRT1052.h.

ENET_RXIC_ICEN_MASK

#define ENET_RXIC_ICEN_MASK   (0x80000000U)

Definition at line 16297 of file MIMXRT1052.h.

ENET_RXIC_ICEN_SHIFT

#define ENET_RXIC_ICEN_SHIFT   (31U)

Definition at line 16298 of file MIMXRT1052.h.

ENET_RXIC_ICFT

#define ENET_RXIC_ICFT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)

ICFT - Interrupt coalescing frame count threshold

Definition at line 16289 of file MIMXRT1052.h.

ENET_RXIC_ICFT_MASK

#define ENET_RXIC_ICFT_MASK   (0xFF00000U)

Definition at line 16285 of file MIMXRT1052.h.

ENET_RXIC_ICFT_SHIFT

#define ENET_RXIC_ICFT_SHIFT   (20U)

Definition at line 16286 of file MIMXRT1052.h.

ENET_RXIC_ICTT

#define ENET_RXIC_ICTT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)

ICTT - Interrupt coalescing timer threshold

Definition at line 16284 of file MIMXRT1052.h.

ENET_RXIC_ICTT_MASK

#define ENET_RXIC_ICTT_MASK   (0xFFFFU)

Definition at line 16280 of file MIMXRT1052.h.

ENET_RXIC_ICTT_SHIFT

#define ENET_RXIC_ICTT_SHIFT   (0U)

Definition at line 16281 of file MIMXRT1052.h.

ENET_TACC_IPCHK

#define ENET_TACC_IPCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

Definition at line 16481 of file MIMXRT1052.h.

ENET_TACC_IPCHK_MASK

#define ENET_TACC_IPCHK_MASK   (0x8U)

Definition at line 16474 of file MIMXRT1052.h.

ENET_TACC_IPCHK_SHIFT

#define ENET_TACC_IPCHK_SHIFT   (3U)

Definition at line 16475 of file MIMXRT1052.h.

ENET_TACC_PROCHK

#define ENET_TACC_PROCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

Definition at line 16489 of file MIMXRT1052.h.

ENET_TACC_PROCHK_MASK

#define ENET_TACC_PROCHK_MASK   (0x10U)

Definition at line 16482 of file MIMXRT1052.h.

ENET_TACC_PROCHK_SHIFT

#define ENET_TACC_PROCHK_SHIFT   (4U)

Definition at line 16483 of file MIMXRT1052.h.

ENET_TACC_SHIFT16

#define ENET_TACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

Definition at line 16473 of file MIMXRT1052.h.

ENET_TACC_SHIFT16_MASK

#define ENET_TACC_SHIFT16_MASK   (0x1U)

Definition at line 16464 of file MIMXRT1052.h.

ENET_TACC_SHIFT16_SHIFT

#define ENET_TACC_SHIFT16_SHIFT   (0U)

Definition at line 16465 of file MIMXRT1052.h.

ENET_TAEM_TX_ALMOST_EMPTY

#define ENET_TAEM_TX_ALMOST_EMPTY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)

TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold

Definition at line 16432 of file MIMXRT1052.h.

ENET_TAEM_TX_ALMOST_EMPTY_MASK

#define ENET_TAEM_TX_ALMOST_EMPTY_MASK   (0xFFU)

Definition at line 16428 of file MIMXRT1052.h.

ENET_TAEM_TX_ALMOST_EMPTY_SHIFT

#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   (0U)

Definition at line 16429 of file MIMXRT1052.h.

ENET_TAFL_TX_ALMOST_FULL

#define ENET_TAFL_TX_ALMOST_FULL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)

TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold

Definition at line 16441 of file MIMXRT1052.h.

ENET_TAFL_TX_ALMOST_FULL_MASK

#define ENET_TAFL_TX_ALMOST_FULL_MASK   (0xFFU)

Definition at line 16437 of file MIMXRT1052.h.

ENET_TAFL_TX_ALMOST_FULL_SHIFT

#define ENET_TAFL_TX_ALMOST_FULL_SHIFT   (0U)

Definition at line 16438 of file MIMXRT1052.h.

ENET_TCCR_COUNT

#define ENET_TCCR_COUNT   (4U)

Definition at line 17205 of file MIMXRT1052.h.

ENET_TCCR_TCC

#define ENET_TCCR_TCC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

TCC - Timer Capture Compare

Definition at line 17201 of file MIMXRT1052.h.

ENET_TCCR_TCC_MASK

#define ENET_TCCR_TCC_MASK   (0xFFFFFFFFU)

Definition at line 17197 of file MIMXRT1052.h.

ENET_TCCR_TCC_SHIFT

#define ENET_TCCR_TCC_SHIFT   (0U)

Definition at line 17198 of file MIMXRT1052.h.

ENET_TCR_ADDINS

#define ENET_TCR_ADDINS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

Definition at line 16205 of file MIMXRT1052.h.

ENET_TCR_ADDINS_MASK

#define ENET_TCR_ADDINS_MASK   (0x100U)

Definition at line 16199 of file MIMXRT1052.h.

ENET_TCR_ADDINS_SHIFT

#define ENET_TCR_ADDINS_SHIFT   (8U)

Definition at line 16200 of file MIMXRT1052.h.

ENET_TCR_ADDSEL

#define ENET_TCR_ADDSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

Definition at line 16198 of file MIMXRT1052.h.

ENET_TCR_ADDSEL_MASK

#define ENET_TCR_ADDSEL_MASK   (0xE0U)

Definition at line 16190 of file MIMXRT1052.h.

ENET_TCR_ADDSEL_SHIFT

#define ENET_TCR_ADDSEL_SHIFT   (5U)

Definition at line 16191 of file MIMXRT1052.h.

ENET_TCR_CRCFWD

#define ENET_TCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

Definition at line 16212 of file MIMXRT1052.h.

ENET_TCR_CRCFWD_MASK

#define ENET_TCR_CRCFWD_MASK   (0x200U)

Definition at line 16206 of file MIMXRT1052.h.

ENET_TCR_CRCFWD_SHIFT

#define ENET_TCR_CRCFWD_SHIFT   (9U)

Definition at line 16207 of file MIMXRT1052.h.

ENET_TCR_FDEN

#define ENET_TCR_FDEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)

FDEN - Full-Duplex Enable

Definition at line 16177 of file MIMXRT1052.h.

ENET_TCR_FDEN_MASK

#define ENET_TCR_FDEN_MASK   (0x4U)

Definition at line 16173 of file MIMXRT1052.h.

ENET_TCR_FDEN_SHIFT

#define ENET_TCR_FDEN_SHIFT   (2U)

Definition at line 16174 of file MIMXRT1052.h.

ENET_TCR_GTS

#define ENET_TCR_GTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)

GTS - Graceful Transmit Stop

Definition at line 16172 of file MIMXRT1052.h.

ENET_TCR_GTS_MASK

#define ENET_TCR_GTS_MASK   (0x1U)

Definition at line 16168 of file MIMXRT1052.h.

ENET_TCR_GTS_SHIFT

#define ENET_TCR_GTS_SHIFT   (0U)

Definition at line 16169 of file MIMXRT1052.h.

ENET_TCR_RFC_PAUSE

#define ENET_TCR_RFC_PAUSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)

RFC_PAUSE - Receive Frame Control Pause

Definition at line 16189 of file MIMXRT1052.h.

ENET_TCR_RFC_PAUSE_MASK

#define ENET_TCR_RFC_PAUSE_MASK   (0x10U)

Definition at line 16185 of file MIMXRT1052.h.

ENET_TCR_RFC_PAUSE_SHIFT

#define ENET_TCR_RFC_PAUSE_SHIFT   (4U)

Definition at line 16186 of file MIMXRT1052.h.

ENET_TCR_TFC_PAUSE

#define ENET_TCR_TFC_PAUSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

Definition at line 16184 of file MIMXRT1052.h.

ENET_TCR_TFC_PAUSE_MASK

#define ENET_TCR_TFC_PAUSE_MASK   (0x8U)

Definition at line 16178 of file MIMXRT1052.h.

ENET_TCR_TFC_PAUSE_SHIFT

#define ENET_TCR_TFC_PAUSE_SHIFT   (3U)

Definition at line 16179 of file MIMXRT1052.h.

ENET_TCSR_COUNT

#define ENET_TCSR_COUNT   (4U)

Definition at line 17193 of file MIMXRT1052.h.

ENET_TCSR_TDRE

#define ENET_TCSR_TDRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

Definition at line 17146 of file MIMXRT1052.h.

ENET_TCSR_TDRE_MASK

#define ENET_TCSR_TDRE_MASK   (0x1U)

Definition at line 17140 of file MIMXRT1052.h.

ENET_TCSR_TDRE_SHIFT

#define ENET_TCSR_TDRE_SHIFT   (0U)

Definition at line 17141 of file MIMXRT1052.h.

ENET_TCSR_TF

#define ENET_TCSR_TF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

Definition at line 17179 of file MIMXRT1052.h.

ENET_TCSR_TF_MASK

#define ENET_TCSR_TF_MASK   (0x80U)

Definition at line 17173 of file MIMXRT1052.h.

ENET_TCSR_TF_SHIFT

#define ENET_TCSR_TF_SHIFT   (7U)

Definition at line 17174 of file MIMXRT1052.h.

ENET_TCSR_TIE

#define ENET_TCSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

Definition at line 17172 of file MIMXRT1052.h.

ENET_TCSR_TIE_MASK

#define ENET_TCSR_TIE_MASK   (0x40U)

Definition at line 17166 of file MIMXRT1052.h.

ENET_TCSR_TIE_SHIFT

#define ENET_TCSR_TIE_SHIFT   (6U)

Definition at line 17167 of file MIMXRT1052.h.

ENET_TCSR_TMODE

#define ENET_TCSR_TMODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.

Definition at line 17165 of file MIMXRT1052.h.

ENET_TCSR_TMODE_MASK

#define ENET_TCSR_TMODE_MASK   (0x3CU)

Definition at line 17147 of file MIMXRT1052.h.

ENET_TCSR_TMODE_SHIFT

#define ENET_TCSR_TMODE_SHIFT   (2U)

Definition at line 17148 of file MIMXRT1052.h.

ENET_TCSR_TPWC

#define ENET_TCSR_TPWC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)

TPWC - Timer PulseWidth Control 0b00000..Pulse width is one 1588-clock cycle. 0b00001..Pulse width is two 1588-clock cycles. 0b00010..Pulse width is three 1588-clock cycles. 0b00011..Pulse width is four 1588-clock cycles. 0b11111..Pulse width is 32 1588-clock cycles.

Definition at line 17189 of file MIMXRT1052.h.

ENET_TCSR_TPWC_MASK

#define ENET_TCSR_TPWC_MASK   (0xF800U)

Definition at line 17180 of file MIMXRT1052.h.

ENET_TCSR_TPWC_SHIFT

#define ENET_TCSR_TPWC_SHIFT   (11U)

Definition at line 17181 of file MIMXRT1052.h.

ENET_TDAR_TDAR

#define ENET_TDAR_TDAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)

TDAR - Transmit Descriptor Active

Definition at line 15927 of file MIMXRT1052.h.

ENET_TDAR_TDAR_MASK

#define ENET_TDAR_TDAR_MASK   (0x1000000U)

Definition at line 15923 of file MIMXRT1052.h.

ENET_TDAR_TDAR_SHIFT

#define ENET_TDAR_TDAR_SHIFT   (24U)

Definition at line 15924 of file MIMXRT1052.h.

ENET_TDSR_X_DES_START

#define ENET_TDSR_X_DES_START

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)

Definition at line 16366 of file MIMXRT1052.h.

ENET_TDSR_X_DES_START_MASK

#define ENET_TDSR_X_DES_START_MASK   (0xFFFFFFF8U)

Definition at line 16364 of file MIMXRT1052.h.

ENET_TDSR_X_DES_START_SHIFT

#define ENET_TDSR_X_DES_START_SHIFT   (3U)

Definition at line 16365 of file MIMXRT1052.h.

ENET_TFWR_STRFWD

#define ENET_TFWR_STRFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.

Definition at line 16352 of file MIMXRT1052.h.

ENET_TFWR_STRFWD_MASK

#define ENET_TFWR_STRFWD_MASK   (0x100U)

Definition at line 16346 of file MIMXRT1052.h.

ENET_TFWR_STRFWD_SHIFT

#define ENET_TFWR_STRFWD_SHIFT   (8U)

Definition at line 16347 of file MIMXRT1052.h.

ENET_TFWR_TFWR

#define ENET_TFWR_TFWR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.

Definition at line 16345 of file MIMXRT1052.h.

ENET_TFWR_TFWR_MASK

#define ENET_TFWR_TFWR_MASK   (0x3FU)

Definition at line 16336 of file MIMXRT1052.h.

ENET_TFWR_TFWR_SHIFT

#define ENET_TFWR_TFWR_SHIFT   (0U)

Definition at line 16337 of file MIMXRT1052.h.

ENET_TGSR_TF0

#define ENET_TGSR_TF0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set

Definition at line 17114 of file MIMXRT1052.h.

ENET_TGSR_TF0_MASK

#define ENET_TGSR_TF0_MASK   (0x1U)

Definition at line 17108 of file MIMXRT1052.h.

ENET_TGSR_TF0_SHIFT

#define ENET_TGSR_TF0_SHIFT   (0U)

Definition at line 17109 of file MIMXRT1052.h.

ENET_TGSR_TF1

#define ENET_TGSR_TF1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set

Definition at line 17121 of file MIMXRT1052.h.

ENET_TGSR_TF1_MASK

#define ENET_TGSR_TF1_MASK   (0x2U)

Definition at line 17115 of file MIMXRT1052.h.

ENET_TGSR_TF1_SHIFT

#define ENET_TGSR_TF1_SHIFT   (1U)

Definition at line 17116 of file MIMXRT1052.h.

ENET_TGSR_TF2

#define ENET_TGSR_TF2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set

Definition at line 17128 of file MIMXRT1052.h.

ENET_TGSR_TF2_MASK

#define ENET_TGSR_TF2_MASK   (0x4U)

Definition at line 17122 of file MIMXRT1052.h.

ENET_TGSR_TF2_SHIFT

#define ENET_TGSR_TF2_SHIFT   (2U)

Definition at line 17123 of file MIMXRT1052.h.

ENET_TGSR_TF3

#define ENET_TGSR_TF3

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set

Definition at line 17135 of file MIMXRT1052.h.

ENET_TGSR_TF3_MASK

#define ENET_TGSR_TF3_MASK   (0x8U)

Definition at line 17129 of file MIMXRT1052.h.

ENET_TGSR_TF3_SHIFT

#define ENET_TGSR_TF3_SHIFT   (3U)

Definition at line 17130 of file MIMXRT1052.h.

ENET_TIPG_IPG

#define ENET_TIPG_IPG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)

IPG - Transmit Inter-Packet Gap

Definition at line 16450 of file MIMXRT1052.h.

ENET_TIPG_IPG_MASK

#define ENET_TIPG_IPG_MASK   (0x1FU)

Definition at line 16446 of file MIMXRT1052.h.

ENET_TIPG_IPG_SHIFT

#define ENET_TIPG_IPG_SHIFT   (0U)

Definition at line 16447 of file MIMXRT1052.h.

ENET_TSEM_TX_SECTION_EMPTY

#define ENET_TSEM_TX_SECTION_EMPTY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)

TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold

Definition at line 16423 of file MIMXRT1052.h.

ENET_TSEM_TX_SECTION_EMPTY_MASK

#define ENET_TSEM_TX_SECTION_EMPTY_MASK   (0xFFU)

Definition at line 16419 of file MIMXRT1052.h.

ENET_TSEM_TX_SECTION_EMPTY_SHIFT

#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT   (0U)

Definition at line 16420 of file MIMXRT1052.h.

ENET_TXIC_ICCS

#define ENET_TXIC_ICCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)

ICCS - Interrupt Coalescing Timer Clock Source Select 0b0..Use MII/GMII TX clocks. 0b1..Use ENET system clock.

Definition at line 16268 of file MIMXRT1052.h.

ENET_TXIC_ICCS_MASK

#define ENET_TXIC_ICCS_MASK   (0x40000000U)

Definition at line 16262 of file MIMXRT1052.h.

ENET_TXIC_ICCS_SHIFT

#define ENET_TXIC_ICCS_SHIFT   (30U)

Definition at line 16263 of file MIMXRT1052.h.

ENET_TXIC_ICEN

#define ENET_TXIC_ICEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)

ICEN - Interrupt Coalescing Enable 0b0..Disable Interrupt coalescing. 0b1..Enable Interrupt coalescing.

Definition at line 16275 of file MIMXRT1052.h.

ENET_TXIC_ICEN_MASK

#define ENET_TXIC_ICEN_MASK   (0x80000000U)

Definition at line 16269 of file MIMXRT1052.h.

ENET_TXIC_ICEN_SHIFT

#define ENET_TXIC_ICEN_SHIFT   (31U)

Definition at line 16270 of file MIMXRT1052.h.

ENET_TXIC_ICFT

#define ENET_TXIC_ICFT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)

ICFT - Interrupt coalescing frame count threshold

Definition at line 16261 of file MIMXRT1052.h.

ENET_TXIC_ICFT_MASK

#define ENET_TXIC_ICFT_MASK   (0xFF00000U)

Definition at line 16257 of file MIMXRT1052.h.

ENET_TXIC_ICFT_SHIFT

#define ENET_TXIC_ICFT_SHIFT   (20U)

Definition at line 16258 of file MIMXRT1052.h.

ENET_TXIC_ICTT

#define ENET_TXIC_ICTT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)

ICTT - Interrupt coalescing timer threshold

Definition at line 16256 of file MIMXRT1052.h.

ENET_TXIC_ICTT_MASK

#define ENET_TXIC_ICTT_MASK   (0xFFFFU)

Definition at line 16252 of file MIMXRT1052.h.

ENET_TXIC_ICTT_SHIFT

#define ENET_TXIC_ICTT_SHIFT   (0U)

Definition at line 16253 of file MIMXRT1052.h.