Collaboration diagram for ADC_ETC Register Masks:

Macros
#define	ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)

#define	ADC_ETC_TRIGn_COUNTER_COUNT (8U)

#define	ADC_ETC_TRIGn_CTRL_COUNT (8U)

#define	ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)

#define	ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)

#define	ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)

#define	ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)

CTRL - ADC_ETC Global Control Register
#define	ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)

#define	ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)

#define	ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)

#define	ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)

#define	ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)

#define	ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)

#define	ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)

#define	ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)

#define	ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)

#define	ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)

#define	ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)

#define	ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)

#define	ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)

#define	ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)

#define	ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)

#define	ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)

#define	ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)

#define	ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)

#define	ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)

#define	ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)

#define	ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)

#define	ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)

#define	ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)

#define	ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)

#define	ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)

#define	ADC_ETC_CTRL_SOFTRST_SHIFT (31U)

#define	ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)

DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register
#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)

#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)

#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)

DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register
#define	ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)

#define	ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)

DMA_CTRL - ETC DMA control Register
#define	ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)

#define	ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)

#define	ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)

#define	ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)

#define	ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)

#define	ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)

#define	ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)

#define	ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)

#define	ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)

#define	ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)

#define	ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)

#define	ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)

#define	ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)

#define	ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)

#define	ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)

#define	ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)

#define	ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)

#define	ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)

#define	ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)

#define	ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)

#define	ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)

#define	ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)

#define	ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)

#define	ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)

#define	ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)

#define	ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)

#define	ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)

#define	ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)

#define	ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)

#define	ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)

#define	ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)

#define	ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)

#define	ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)

#define	ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)

TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register
#define	ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)

#define	ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)

#define	ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)

#define	ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)

#define	ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)

#define	ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)

#define	ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)

#define	ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)

#define	ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)

#define	ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)

#define	ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)

#define	ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)

#define	ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)

#define	ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)

#define	ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)

TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register
#define	ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)

#define	ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)

#define	ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)

#define	ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)

#define	ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)

#define	ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)

TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register
#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)

#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)

#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)

#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)

#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)

#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)

#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)

#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)

#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)

#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)

TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register
#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)

#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)

#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)

#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)

#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)

#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)

#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)

#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)

#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)

#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)

TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register
#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)

#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)

#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)

#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)

#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)

#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)

#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)

#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)

#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)

#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)

TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register
#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)

#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)

#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)

#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)

#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)

#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)

#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)

#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)

#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)

#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)

TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register
#define	ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)

#define	ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)

#define	ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)

#define	ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)

#define	ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)

#define	ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)

TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register
#define	ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)

#define	ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)

#define	ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)

#define	ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)

#define	ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)

#define	ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)

TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register
#define	ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)

#define	ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)

#define	ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)

#define	ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)

#define	ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)

#define	ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)

TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register
#define	ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)

#define	ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)

#define	ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)

#define	ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)

#define	ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)

#define	ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)

Detailed Description

Macro Definition Documentation

◆ ADC_ETC_CTRL_DMA_MODE_SEL

#define ADC_ETC_CTRL_DMA_MODE_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)

Definition at line 1667 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_DMA_MODE_SEL_MASK

#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)

Definition at line 1665 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT

#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)

Definition at line 1666 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT0_TRIG_ENABLE

#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)

Definition at line 1652 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK

#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)

Definition at line 1650 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT

#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)

Definition at line 1651 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT0_TRIG_PRIORITY

#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)

Definition at line 1655 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK

#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)

Definition at line 1653 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT

#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)

Definition at line 1654 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT1_TRIG_ENABLE

#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)

Definition at line 1658 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK

#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)

Definition at line 1656 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT

#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)

Definition at line 1657 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT1_TRIG_PRIORITY

#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)

Definition at line 1661 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK

#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)

Definition at line 1659 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT

#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)

Definition at line 1660 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_PRE_DIVIDER

#define ADC_ETC_CTRL_PRE_DIVIDER ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)

Definition at line 1664 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_PRE_DIVIDER_MASK

#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)

Definition at line 1662 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_PRE_DIVIDER_SHIFT

#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)

Definition at line 1663 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_SOFTRST

#define ADC_ETC_CTRL_SOFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)

Definition at line 1673 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_SOFTRST_MASK

#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)

Definition at line 1671 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_SOFTRST_SHIFT

#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)

Definition at line 1672 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_TRIG_ENABLE

#define ADC_ETC_CTRL_TRIG_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)

Definition at line 1649 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_TRIG_ENABLE_MASK

#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)

Definition at line 1647 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_TRIG_ENABLE_SHIFT

#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)

Definition at line 1648 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_TSC_BYPASS

#define ADC_ETC_CTRL_TSC_BYPASS ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)

Definition at line 1670 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_TSC_BYPASS_MASK

#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)

Definition at line 1668 of file MIMXRT1052.h.

◆ ADC_ETC_CTRL_TSC_BYPASS_SHIFT

#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)

Definition at line 1669 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG0_ENABLE

#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)

Definition at line 1784 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK

#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)

Definition at line 1782 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)

Definition at line 1783 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG0_REQ

#define ADC_ETC_DMA_CTRL_TRIG0_REQ ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)

Definition at line 1808 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK

#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)

Definition at line 1806 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)

Definition at line 1807 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG1_ENABLE

#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)

Definition at line 1787 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK

#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)

Definition at line 1785 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)

Definition at line 1786 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG1_REQ

#define ADC_ETC_DMA_CTRL_TRIG1_REQ ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)

Definition at line 1811 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK

#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)

Definition at line 1809 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)

Definition at line 1810 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG2_ENABLE

#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)

Definition at line 1790 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK

#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)

Definition at line 1788 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)

Definition at line 1789 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG2_REQ

#define ADC_ETC_DMA_CTRL_TRIG2_REQ ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)

Definition at line 1814 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK

#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)

Definition at line 1812 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)

Definition at line 1813 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG3_ENABLE

#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)

Definition at line 1793 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK

#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)

Definition at line 1791 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)

Definition at line 1792 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG3_REQ

#define ADC_ETC_DMA_CTRL_TRIG3_REQ ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)

Definition at line 1817 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK

#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)

Definition at line 1815 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)

Definition at line 1816 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG4_ENABLE

#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)

Definition at line 1796 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK

#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)

Definition at line 1794 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)

Definition at line 1795 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG4_REQ

#define ADC_ETC_DMA_CTRL_TRIG4_REQ ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)

Definition at line 1820 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK

#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)

Definition at line 1818 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)

Definition at line 1819 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG5_ENABLE

#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)

Definition at line 1799 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK

#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)

Definition at line 1797 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)

Definition at line 1798 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG5_REQ

#define ADC_ETC_DMA_CTRL_TRIG5_REQ ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)

Definition at line 1823 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK

#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)

Definition at line 1821 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)

Definition at line 1822 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG6_ENABLE

#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)

Definition at line 1802 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK

#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)

Definition at line 1800 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)

Definition at line 1801 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG6_REQ

#define ADC_ETC_DMA_CTRL_TRIG6_REQ ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)

Definition at line 1826 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK

#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)

Definition at line 1824 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)

Definition at line 1825 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG7_ENABLE

#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)

Definition at line 1805 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK

#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)

Definition at line 1803 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)

Definition at line 1804 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG7_REQ

#define ADC_ETC_DMA_CTRL_TRIG7_REQ ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)

Definition at line 1829 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK

#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)

Definition at line 1827 of file MIMXRT1052.h.

◆ ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT

#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)

Definition at line 1828 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0

#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)

Definition at line 1680 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)

Definition at line 1678 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)

Definition at line 1679 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1

#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)

Definition at line 1704 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)

Definition at line 1702 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)

Definition at line 1703 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0

#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)

Definition at line 1683 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)

Definition at line 1681 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)

Definition at line 1682 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1

#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)

Definition at line 1707 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)

Definition at line 1705 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)

Definition at line 1706 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0

#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)

Definition at line 1686 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)

Definition at line 1684 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)

Definition at line 1685 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1

#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)

Definition at line 1710 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)

Definition at line 1708 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)

Definition at line 1709 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0

#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)

Definition at line 1689 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)

Definition at line 1687 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)

Definition at line 1688 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1

#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)

Definition at line 1713 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)

Definition at line 1711 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)

Definition at line 1712 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0

#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)

Definition at line 1692 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)

Definition at line 1690 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)

Definition at line 1691 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1

#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)

Definition at line 1716 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)

Definition at line 1714 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)

Definition at line 1715 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0

#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)

Definition at line 1695 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)

Definition at line 1693 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)

Definition at line 1694 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1

#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)

Definition at line 1719 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)

Definition at line 1717 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)

Definition at line 1718 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0

#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)

Definition at line 1698 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)

Definition at line 1696 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)

Definition at line 1697 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1

#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)

Definition at line 1722 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)

Definition at line 1720 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)

Definition at line 1721 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0

#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)

Definition at line 1701 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)

Definition at line 1699 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)

Definition at line 1700 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1

#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)

Definition at line 1725 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK

#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)

Definition at line 1723 of file MIMXRT1052.h.

◆ ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT

#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)

Definition at line 1724 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2

#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)

Definition at line 1732 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)

Definition at line 1730 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)

Definition at line 1731 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR

#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)

Definition at line 1756 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)

Definition at line 1754 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)

Definition at line 1755 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2

#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)

Definition at line 1735 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)

Definition at line 1733 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)

Definition at line 1734 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR

#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)

Definition at line 1759 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)

Definition at line 1757 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)

Definition at line 1758 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2

#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)

Definition at line 1738 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)

Definition at line 1736 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)

Definition at line 1737 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR

#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)

Definition at line 1762 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)

Definition at line 1760 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)

Definition at line 1761 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2

#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)

Definition at line 1741 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)

Definition at line 1739 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)

Definition at line 1740 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR

#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)

Definition at line 1765 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)

Definition at line 1763 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)

Definition at line 1764 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2

#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)

Definition at line 1744 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)

Definition at line 1742 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)

Definition at line 1743 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR

#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)

Definition at line 1768 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)

Definition at line 1766 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)

Definition at line 1767 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2

#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)

Definition at line 1747 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)

Definition at line 1745 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)

Definition at line 1746 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR

#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)

Definition at line 1771 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)

Definition at line 1769 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)

Definition at line 1770 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2

#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)

Definition at line 1750 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)

Definition at line 1748 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)

Definition at line 1749 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR

#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)

Definition at line 1774 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)

Definition at line 1772 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)

Definition at line 1773 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2

#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)

Definition at line 1753 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)

Definition at line 1751 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)

Definition at line 1752 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR

#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)

Definition at line 1777 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK

#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)

Definition at line 1775 of file MIMXRT1052.h.

◆ ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT

#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)

Definition at line 1776 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_B2B0

#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)

Definition at line 1877 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK

#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)

Definition at line 1875 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT

#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)

Definition at line 1876 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_B2B1

#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)

Definition at line 1889 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK

#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)

Definition at line 1887 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT

#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)

Definition at line 1888 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_COUNT

#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)

Definition at line 1896 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_CSEL0

#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)

Definition at line 1871 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK

#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)

Definition at line 1869 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT

#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)

Definition at line 1870 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_CSEL1

#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)

Definition at line 1883 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK

#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)

Definition at line 1881 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT

#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)

Definition at line 1882 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_HWTS0

#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)

Definition at line 1874 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK

#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)

Definition at line 1872 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT

#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)

Definition at line 1873 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_HWTS1

#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)

Definition at line 1886 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK

#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)

Definition at line 1884 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT

#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)

Definition at line 1885 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_IE0

#define ADC_ETC_TRIGn_CHAIN_1_0_IE0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)

Definition at line 1880 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK

#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)

Definition at line 1878 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT

#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)

Definition at line 1879 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_IE1

#define ADC_ETC_TRIGn_CHAIN_1_0_IE1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)

Definition at line 1892 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK

#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)

Definition at line 1890 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT

#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)

Definition at line 1891 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_B2B2

#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)

Definition at line 1908 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK

#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)

Definition at line 1906 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT

#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)

Definition at line 1907 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_B2B3

#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)

Definition at line 1920 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK

#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)

Definition at line 1918 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT

#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)

Definition at line 1919 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_COUNT

#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)

Definition at line 1927 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_CSEL2

#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)

Definition at line 1902 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK

#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)

Definition at line 1900 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT

#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)

Definition at line 1901 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_CSEL3

#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)

Definition at line 1914 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK

#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)

Definition at line 1912 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT

#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)

Definition at line 1913 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_HWTS2

#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)

Definition at line 1905 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK

#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)

Definition at line 1903 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT

#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)

Definition at line 1904 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_HWTS3

#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)

Definition at line 1917 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK

#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)

Definition at line 1915 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT

#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)

Definition at line 1916 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_IE2

#define ADC_ETC_TRIGn_CHAIN_3_2_IE2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)

Definition at line 1911 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK

#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)

Definition at line 1909 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT

#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)

Definition at line 1910 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_IE3

#define ADC_ETC_TRIGn_CHAIN_3_2_IE3 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)

Definition at line 1923 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK

#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)

Definition at line 1921 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT

#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)

Definition at line 1922 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_B2B4

#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)

Definition at line 1939 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK

#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)

Definition at line 1937 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT

#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)

Definition at line 1938 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_B2B5

#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)

Definition at line 1951 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK

#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)

Definition at line 1949 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT

#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)

Definition at line 1950 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_COUNT

#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)

Definition at line 1958 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_CSEL4

#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)

Definition at line 1933 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK

#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)

Definition at line 1931 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT

#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)

Definition at line 1932 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_CSEL5

#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)

Definition at line 1945 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK

#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)

Definition at line 1943 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT

#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)

Definition at line 1944 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_HWTS4

#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)

Definition at line 1936 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK

#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)

Definition at line 1934 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT

#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)

Definition at line 1935 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_HWTS5

#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)

Definition at line 1948 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK

#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)

Definition at line 1946 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT

#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)

Definition at line 1947 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_IE4

#define ADC_ETC_TRIGn_CHAIN_5_4_IE4 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)

Definition at line 1942 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK

#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)

Definition at line 1940 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT

#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)

Definition at line 1941 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_IE5

#define ADC_ETC_TRIGn_CHAIN_5_4_IE5 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)

Definition at line 1954 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK

#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)

Definition at line 1952 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT

#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)

Definition at line 1953 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_B2B6

#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)

Definition at line 1970 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK

#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)

Definition at line 1968 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT

#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)

Definition at line 1969 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_B2B7

#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)

Definition at line 1982 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK

#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)

Definition at line 1980 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT

#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)

Definition at line 1981 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_COUNT

#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)

Definition at line 1989 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_CSEL6

#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)

Definition at line 1964 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK

#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)

Definition at line 1962 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT

#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)

Definition at line 1963 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_CSEL7

#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)

Definition at line 1976 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK

#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)

Definition at line 1974 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT

#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)

Definition at line 1975 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_HWTS6

#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)

Definition at line 1967 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK

#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)

Definition at line 1965 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT

#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)

Definition at line 1966 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_HWTS7

#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)

Definition at line 1979 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK

#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)

Definition at line 1977 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT

#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)

Definition at line 1978 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_IE6

#define ADC_ETC_TRIGn_CHAIN_7_6_IE6 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)

Definition at line 1973 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK

#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)

Definition at line 1971 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT

#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)

Definition at line 1972 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_IE7

#define ADC_ETC_TRIGn_CHAIN_7_6_IE7 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)

Definition at line 1985 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK

#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)

Definition at line 1983 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT

#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)

Definition at line 1984 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_COUNTER_COUNT

#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)

Definition at line 1865 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_COUNTER_INIT_DELAY

#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)

Definition at line 1858 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK

#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)

Definition at line 1856 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT

#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)

Definition at line 1857 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL

#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)

Definition at line 1861 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK

#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)

Definition at line 1859 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT

#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)

Definition at line 1860 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_COUNT

#define ADC_ETC_TRIGn_CTRL_COUNT (8U)

Definition at line 1852 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_SW_TRIG

#define ADC_ETC_TRIGn_CTRL_SW_TRIG ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)

Definition at line 1836 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK

#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)

Definition at line 1834 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT

#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)

Definition at line 1835 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_SYNC_MODE

#define ADC_ETC_TRIGn_CTRL_SYNC_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)

Definition at line 1848 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK

#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)

Definition at line 1846 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT

#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)

Definition at line 1847 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_CHAIN

#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)

Definition at line 1842 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK

#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)

Definition at line 1840 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT

#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)

Definition at line 1841 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_MODE

#define ADC_ETC_TRIGn_CTRL_TRIG_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)

Definition at line 1839 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK

#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)

Definition at line 1837 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT

#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)

Definition at line 1838 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY

#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)

Definition at line 1845 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK

#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)

Definition at line 1843 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT

#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)

Definition at line 1844 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_1_0_COUNT

#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)

Definition at line 2002 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_1_0_DATA0

#define ADC_ETC_TRIGn_RESULT_1_0_DATA0 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)

Definition at line 1995 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK

#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)

Definition at line 1993 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT

#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)

Definition at line 1994 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_1_0_DATA1

#define ADC_ETC_TRIGn_RESULT_1_0_DATA1 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)

Definition at line 1998 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK

#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)

Definition at line 1996 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT

#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)

Definition at line 1997 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_3_2_COUNT

#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)

Definition at line 2015 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_3_2_DATA2

#define ADC_ETC_TRIGn_RESULT_3_2_DATA2 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)

Definition at line 2008 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK

#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)

Definition at line 2006 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT

#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)

Definition at line 2007 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_3_2_DATA3

#define ADC_ETC_TRIGn_RESULT_3_2_DATA3 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)

Definition at line 2011 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK

#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)

Definition at line 2009 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT

#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)

Definition at line 2010 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_5_4_COUNT

#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)

Definition at line 2028 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_5_4_DATA4

#define ADC_ETC_TRIGn_RESULT_5_4_DATA4 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)

Definition at line 2021 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK

#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)

Definition at line 2019 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT

#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)

Definition at line 2020 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_5_4_DATA5

#define ADC_ETC_TRIGn_RESULT_5_4_DATA5 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)

Definition at line 2024 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK

#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)

Definition at line 2022 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT

#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)

Definition at line 2023 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_7_6_COUNT

#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)

Definition at line 2041 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_7_6_DATA6

#define ADC_ETC_TRIGn_RESULT_7_6_DATA6 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)

Definition at line 2034 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK

#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)

Definition at line 2032 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT

#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)

Definition at line 2033 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_7_6_DATA7

#define ADC_ETC_TRIGn_RESULT_7_6_DATA7 ( x ) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)

Definition at line 2037 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK

#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)

Definition at line 2035 of file MIMXRT1052.h.

◆ ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT

#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)

Definition at line 2036 of file MIMXRT1052.h.

Macros

CTRL - ADC_ETC Global Control Register

DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register

DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register

DMA_CTRL - ETC DMA control Register

TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register

TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register

TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register

TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register

TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register

TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register

TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register

TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register

TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register

TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register