Macros
SEMC Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » SEMC Peripheral Access Layer
Collaboration diagram for SEMC Register Masks:

Macros

#define SEMC_BR_COUNT   (9U)
 

INTEN - Interrupt Enable Register

#define SEMC_INTEN_IPCMDDONEEN_MASK   (0x1U)
 
#define SEMC_INTEN_IPCMDDONEEN_SHIFT   (0U)
 
#define SEMC_INTEN_IPCMDDONEEN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
 
#define SEMC_INTEN_IPCMDERREN_MASK   (0x2U)
 
#define SEMC_INTEN_IPCMDERREN_SHIFT   (1U)
 
#define SEMC_INTEN_IPCMDERREN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
 
#define SEMC_INTEN_AXICMDERREN_MASK   (0x4U)
 
#define SEMC_INTEN_AXICMDERREN_SHIFT   (2U)
 
#define SEMC_INTEN_AXICMDERREN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
 
#define SEMC_INTEN_AXIBUSERREN_MASK   (0x8U)
 
#define SEMC_INTEN_AXIBUSERREN_SHIFT   (3U)
 
#define SEMC_INTEN_AXIBUSERREN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
 
#define SEMC_INTEN_NDPAGEENDEN_MASK   (0x10U)
 
#define SEMC_INTEN_NDPAGEENDEN_SHIFT   (4U)
 
#define SEMC_INTEN_NDPAGEENDEN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
 
#define SEMC_INTEN_NDNOPENDEN_MASK   (0x20U)
 
#define SEMC_INTEN_NDNOPENDEN_SHIFT   (5U)
 
#define SEMC_INTEN_NDNOPENDEN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
 

IPCMD - IP Command register

#define SEMC_IPCMD_CMD_MASK   (0xFFFFU)
 
#define SEMC_IPCMD_CMD_SHIFT   (0U)
 
#define SEMC_IPCMD_CMD(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
 
#define SEMC_IPCMD_KEY_MASK   (0xFFFF0000U)
 
#define SEMC_IPCMD_KEY_SHIFT   (16U)
 
#define SEMC_IPCMD_KEY(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
 

STS0 - Status register 0

#define SEMC_STS0_IDLE_MASK   (0x1U)
 
#define SEMC_STS0_IDLE_SHIFT   (0U)
 
#define SEMC_STS0_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
 
#define SEMC_STS0_NARDY_MASK   (0x2U)
 
#define SEMC_STS0_NARDY_SHIFT   (1U)
 
#define SEMC_STS0_NARDY(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
 

STS2 - Status register 2

#define SEMC_STS2_NDWRPEND_MASK   (0x8U)
 
#define SEMC_STS2_NDWRPEND_SHIFT   (3U)
 
#define SEMC_STS2_NDWRPEND(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
 

MCR - Module Control Register

#define SEMC_MCR_SWRST_MASK   (0x1U)
 
#define SEMC_MCR_SWRST_SHIFT   (0U)
 
#define SEMC_MCR_SWRST(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
 
#define SEMC_MCR_MDIS_MASK   (0x2U)
 
#define SEMC_MCR_MDIS_SHIFT   (1U)
 
#define SEMC_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
 
#define SEMC_MCR_DQSMD_MASK   (0x4U)
 
#define SEMC_MCR_DQSMD_SHIFT   (2U)
 
#define SEMC_MCR_DQSMD(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
 
#define SEMC_MCR_WPOL0_MASK   (0x40U)
 
#define SEMC_MCR_WPOL0_SHIFT   (6U)
 
#define SEMC_MCR_WPOL0(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
 
#define SEMC_MCR_WPOL1_MASK   (0x80U)
 
#define SEMC_MCR_WPOL1_SHIFT   (7U)
 
#define SEMC_MCR_WPOL1(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
 
#define SEMC_MCR_CTO_MASK   (0xFF0000U)
 
#define SEMC_MCR_CTO_SHIFT   (16U)
 
#define SEMC_MCR_CTO(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
 
#define SEMC_MCR_BTO_MASK   (0x1F000000U)
 
#define SEMC_MCR_BTO_SHIFT   (24U)
 
#define SEMC_MCR_BTO(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
 

IOCR - IO Mux Control Register

#define SEMC_IOCR_MUX_A8_MASK   (0x7U)
 
#define SEMC_IOCR_MUX_A8_SHIFT   (0U)
 
#define SEMC_IOCR_MUX_A8(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
 
#define SEMC_IOCR_MUX_CSX0_MASK   (0x38U)
 
#define SEMC_IOCR_MUX_CSX0_SHIFT   (3U)
 
#define SEMC_IOCR_MUX_CSX0(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
 
#define SEMC_IOCR_MUX_CSX1_MASK   (0x1C0U)
 
#define SEMC_IOCR_MUX_CSX1_SHIFT   (6U)
 
#define SEMC_IOCR_MUX_CSX1(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
 
#define SEMC_IOCR_MUX_CSX2_MASK   (0xE00U)
 
#define SEMC_IOCR_MUX_CSX2_SHIFT   (9U)
 
#define SEMC_IOCR_MUX_CSX2(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
 
#define SEMC_IOCR_MUX_CSX3_MASK   (0x7000U)
 
#define SEMC_IOCR_MUX_CSX3_SHIFT   (12U)
 
#define SEMC_IOCR_MUX_CSX3(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
 
#define SEMC_IOCR_MUX_RDY_MASK   (0x38000U)
 
#define SEMC_IOCR_MUX_RDY_SHIFT   (15U)
 
#define SEMC_IOCR_MUX_RDY(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
 

BMCR0 - Master Bus (AXI) Control Register 0

#define SEMC_BMCR0_WQOS_MASK   (0xFU)
 
#define SEMC_BMCR0_WQOS_SHIFT   (0U)
 
#define SEMC_BMCR0_WQOS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
 
#define SEMC_BMCR0_WAGE_MASK   (0xF0U)
 
#define SEMC_BMCR0_WAGE_SHIFT   (4U)
 
#define SEMC_BMCR0_WAGE(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
 
#define SEMC_BMCR0_WSH_MASK   (0xFF00U)
 
#define SEMC_BMCR0_WSH_SHIFT   (8U)
 
#define SEMC_BMCR0_WSH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
 
#define SEMC_BMCR0_WRWS_MASK   (0xFF0000U)
 
#define SEMC_BMCR0_WRWS_SHIFT   (16U)
 
#define SEMC_BMCR0_WRWS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
 

BMCR1 - Master Bus (AXI) Control Register 1

#define SEMC_BMCR1_WQOS_MASK   (0xFU)
 
#define SEMC_BMCR1_WQOS_SHIFT   (0U)
 
#define SEMC_BMCR1_WQOS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
 
#define SEMC_BMCR1_WAGE_MASK   (0xF0U)
 
#define SEMC_BMCR1_WAGE_SHIFT   (4U)
 
#define SEMC_BMCR1_WAGE(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
 
#define SEMC_BMCR1_WPH_MASK   (0xFF00U)
 
#define SEMC_BMCR1_WPH_SHIFT   (8U)
 
#define SEMC_BMCR1_WPH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
 
#define SEMC_BMCR1_WRWS_MASK   (0xFF0000U)
 
#define SEMC_BMCR1_WRWS_SHIFT   (16U)
 
#define SEMC_BMCR1_WRWS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
 
#define SEMC_BMCR1_WBR_MASK   (0xFF000000U)
 
#define SEMC_BMCR1_WBR_SHIFT   (24U)
 
#define SEMC_BMCR1_WBR(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
 

BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device)

#define SEMC_BR_VLD_MASK   (0x1U)
 
#define SEMC_BR_VLD_SHIFT   (0U)
 
#define SEMC_BR_VLD(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
 
#define SEMC_BR_MS_MASK   (0x3EU)
 
#define SEMC_BR_MS_SHIFT   (1U)
 
#define SEMC_BR_MS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
 
#define SEMC_BR_BA_MASK   (0xFFFFF000U)
 
#define SEMC_BR_BA_SHIFT   (12U)
 
#define SEMC_BR_BA(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
 

INTR - Interrupt Enable Register

#define SEMC_INTR_IPCMDDONE_MASK   (0x1U)
 
#define SEMC_INTR_IPCMDDONE_SHIFT   (0U)
 
#define SEMC_INTR_IPCMDDONE(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
 
#define SEMC_INTR_IPCMDERR_MASK   (0x2U)
 
#define SEMC_INTR_IPCMDERR_SHIFT   (1U)
 
#define SEMC_INTR_IPCMDERR(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
 
#define SEMC_INTR_AXICMDERR_MASK   (0x4U)
 
#define SEMC_INTR_AXICMDERR_SHIFT   (2U)
 
#define SEMC_INTR_AXICMDERR(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
 
#define SEMC_INTR_AXIBUSERR_MASK   (0x8U)
 
#define SEMC_INTR_AXIBUSERR_SHIFT   (3U)
 
#define SEMC_INTR_AXIBUSERR(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
 
#define SEMC_INTR_NDPAGEEND_MASK   (0x10U)
 
#define SEMC_INTR_NDPAGEEND_SHIFT   (4U)
 
#define SEMC_INTR_NDPAGEEND(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
 
#define SEMC_INTR_NDNOPEND_MASK   (0x20U)
 
#define SEMC_INTR_NDNOPEND_SHIFT   (5U)
 
#define SEMC_INTR_NDNOPEND(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
 

SDRAMCR0 - SDRAM control register 0

#define SEMC_SDRAMCR0_PS_MASK   (0x1U)
 
#define SEMC_SDRAMCR0_PS_SHIFT   (0U)
 
#define SEMC_SDRAMCR0_PS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
 
#define SEMC_SDRAMCR0_BL_MASK   (0x70U)
 
#define SEMC_SDRAMCR0_BL_SHIFT   (4U)
 
#define SEMC_SDRAMCR0_BL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
 
#define SEMC_SDRAMCR0_COL_MASK   (0x300U)
 
#define SEMC_SDRAMCR0_COL_SHIFT   (8U)
 
#define SEMC_SDRAMCR0_COL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
 
#define SEMC_SDRAMCR0_CL_MASK   (0xC00U)
 
#define SEMC_SDRAMCR0_CL_SHIFT   (10U)
 
#define SEMC_SDRAMCR0_CL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
 

SDRAMCR1 - SDRAM control register 1

#define SEMC_SDRAMCR1_PRE2ACT_MASK   (0xFU)
 
#define SEMC_SDRAMCR1_PRE2ACT_SHIFT   (0U)
 
#define SEMC_SDRAMCR1_PRE2ACT(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
 
#define SEMC_SDRAMCR1_ACT2RW_MASK   (0xF0U)
 
#define SEMC_SDRAMCR1_ACT2RW_SHIFT   (4U)
 
#define SEMC_SDRAMCR1_ACT2RW(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
 
#define SEMC_SDRAMCR1_RFRC_MASK   (0x1F00U)
 
#define SEMC_SDRAMCR1_RFRC_SHIFT   (8U)
 
#define SEMC_SDRAMCR1_RFRC(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
 
#define SEMC_SDRAMCR1_WRC_MASK   (0xE000U)
 
#define SEMC_SDRAMCR1_WRC_SHIFT   (13U)
 
#define SEMC_SDRAMCR1_WRC(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
 
#define SEMC_SDRAMCR1_CKEOFF_MASK   (0xF0000U)
 
#define SEMC_SDRAMCR1_CKEOFF_SHIFT   (16U)
 
#define SEMC_SDRAMCR1_CKEOFF(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
 
#define SEMC_SDRAMCR1_ACT2PRE_MASK   (0xF00000U)
 
#define SEMC_SDRAMCR1_ACT2PRE_SHIFT   (20U)
 
#define SEMC_SDRAMCR1_ACT2PRE(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
 

SDRAMCR2 - SDRAM control register 2

#define SEMC_SDRAMCR2_SRRC_MASK   (0xFFU)
 
#define SEMC_SDRAMCR2_SRRC_SHIFT   (0U)
 
#define SEMC_SDRAMCR2_SRRC(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
 
#define SEMC_SDRAMCR2_REF2REF_MASK   (0xFF00U)
 
#define SEMC_SDRAMCR2_REF2REF_SHIFT   (8U)
 
#define SEMC_SDRAMCR2_REF2REF(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
 
#define SEMC_SDRAMCR2_ACT2ACT_MASK   (0xFF0000U)
 
#define SEMC_SDRAMCR2_ACT2ACT_SHIFT   (16U)
 
#define SEMC_SDRAMCR2_ACT2ACT(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
 
#define SEMC_SDRAMCR2_ITO_MASK   (0xFF000000U)
 
#define SEMC_SDRAMCR2_ITO_SHIFT   (24U)
 
#define SEMC_SDRAMCR2_ITO(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
 

SDRAMCR3 - SDRAM control register 3

#define SEMC_SDRAMCR3_REN_MASK   (0x1U)
 
#define SEMC_SDRAMCR3_REN_SHIFT   (0U)
 
#define SEMC_SDRAMCR3_REN(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
 
#define SEMC_SDRAMCR3_REBL_MASK   (0xEU)
 
#define SEMC_SDRAMCR3_REBL_SHIFT   (1U)
 
#define SEMC_SDRAMCR3_REBL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
 
#define SEMC_SDRAMCR3_PRESCALE_MASK   (0xFF00U)
 
#define SEMC_SDRAMCR3_PRESCALE_SHIFT   (8U)
 
#define SEMC_SDRAMCR3_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
 
#define SEMC_SDRAMCR3_RT_MASK   (0xFF0000U)
 
#define SEMC_SDRAMCR3_RT_SHIFT   (16U)
 
#define SEMC_SDRAMCR3_RT(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
 
#define SEMC_SDRAMCR3_UT_MASK   (0xFF000000U)
 
#define SEMC_SDRAMCR3_UT_SHIFT   (24U)
 
#define SEMC_SDRAMCR3_UT(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
 

NANDCR0 - NAND control register 0

#define SEMC_NANDCR0_PS_MASK   (0x1U)
 
#define SEMC_NANDCR0_PS_SHIFT   (0U)
 
#define SEMC_NANDCR0_PS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
 
#define SEMC_NANDCR0_BL_MASK   (0x70U)
 
#define SEMC_NANDCR0_BL_SHIFT   (4U)
 
#define SEMC_NANDCR0_BL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
 
#define SEMC_NANDCR0_EDO_MASK   (0x80U)
 
#define SEMC_NANDCR0_EDO_SHIFT   (7U)
 
#define SEMC_NANDCR0_EDO(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
 
#define SEMC_NANDCR0_COL_MASK   (0x700U)
 
#define SEMC_NANDCR0_COL_SHIFT   (8U)
 
#define SEMC_NANDCR0_COL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
 

NANDCR1 - NAND control register 1

#define SEMC_NANDCR1_CES_MASK   (0xFU)
 
#define SEMC_NANDCR1_CES_SHIFT   (0U)
 
#define SEMC_NANDCR1_CES(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
 
#define SEMC_NANDCR1_CEH_MASK   (0xF0U)
 
#define SEMC_NANDCR1_CEH_SHIFT   (4U)
 
#define SEMC_NANDCR1_CEH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
 
#define SEMC_NANDCR1_WEL_MASK   (0xF00U)
 
#define SEMC_NANDCR1_WEL_SHIFT   (8U)
 
#define SEMC_NANDCR1_WEL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
 
#define SEMC_NANDCR1_WEH_MASK   (0xF000U)
 
#define SEMC_NANDCR1_WEH_SHIFT   (12U)
 
#define SEMC_NANDCR1_WEH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
 
#define SEMC_NANDCR1_REL_MASK   (0xF0000U)
 
#define SEMC_NANDCR1_REL_SHIFT   (16U)
 
#define SEMC_NANDCR1_REL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
 
#define SEMC_NANDCR1_REH_MASK   (0xF00000U)
 
#define SEMC_NANDCR1_REH_SHIFT   (20U)
 
#define SEMC_NANDCR1_REH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
 
#define SEMC_NANDCR1_TA_MASK   (0xF000000U)
 
#define SEMC_NANDCR1_TA_SHIFT   (24U)
 
#define SEMC_NANDCR1_TA(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
 
#define SEMC_NANDCR1_CEITV_MASK   (0xF0000000U)
 
#define SEMC_NANDCR1_CEITV_SHIFT   (28U)
 
#define SEMC_NANDCR1_CEITV(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
 

NANDCR2 - NAND control register 2

#define SEMC_NANDCR2_TWHR_MASK   (0x3FU)
 
#define SEMC_NANDCR2_TWHR_SHIFT   (0U)
 
#define SEMC_NANDCR2_TWHR(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
 
#define SEMC_NANDCR2_TRHW_MASK   (0xFC0U)
 
#define SEMC_NANDCR2_TRHW_SHIFT   (6U)
 
#define SEMC_NANDCR2_TRHW(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
 
#define SEMC_NANDCR2_TADL_MASK   (0x3F000U)
 
#define SEMC_NANDCR2_TADL_SHIFT   (12U)
 
#define SEMC_NANDCR2_TADL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
 
#define SEMC_NANDCR2_TRR_MASK   (0xFC0000U)
 
#define SEMC_NANDCR2_TRR_SHIFT   (18U)
 
#define SEMC_NANDCR2_TRR(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
 
#define SEMC_NANDCR2_TWB_MASK   (0x3F000000U)
 
#define SEMC_NANDCR2_TWB_SHIFT   (24U)
 
#define SEMC_NANDCR2_TWB(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
 

NANDCR3 - NAND control register 3

#define SEMC_NANDCR3_NDOPT1_MASK   (0x1U)
 
#define SEMC_NANDCR3_NDOPT1_SHIFT   (0U)
 
#define SEMC_NANDCR3_NDOPT1(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
 
#define SEMC_NANDCR3_NDOPT2_MASK   (0x2U)
 
#define SEMC_NANDCR3_NDOPT2_SHIFT   (1U)
 
#define SEMC_NANDCR3_NDOPT2(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
 
#define SEMC_NANDCR3_NDOPT3_MASK   (0x4U)
 
#define SEMC_NANDCR3_NDOPT3_SHIFT   (2U)
 
#define SEMC_NANDCR3_NDOPT3(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
 

NORCR0 - NOR control register 0

#define SEMC_NORCR0_PS_MASK   (0x1U)
 
#define SEMC_NORCR0_PS_SHIFT   (0U)
 
#define SEMC_NORCR0_PS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
 
#define SEMC_NORCR0_BL_MASK   (0x70U)
 
#define SEMC_NORCR0_BL_SHIFT   (4U)
 
#define SEMC_NORCR0_BL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
 
#define SEMC_NORCR0_AM_MASK   (0x300U)
 
#define SEMC_NORCR0_AM_SHIFT   (8U)
 
#define SEMC_NORCR0_AM(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
 
#define SEMC_NORCR0_ADVP_MASK   (0x400U)
 
#define SEMC_NORCR0_ADVP_SHIFT   (10U)
 
#define SEMC_NORCR0_ADVP(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
 
#define SEMC_NORCR0_COL_MASK   (0xF000U)
 
#define SEMC_NORCR0_COL_SHIFT   (12U)
 
#define SEMC_NORCR0_COL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
 

NORCR1 - NOR control register 1

#define SEMC_NORCR1_CES_MASK   (0xFU)
 
#define SEMC_NORCR1_CES_SHIFT   (0U)
 
#define SEMC_NORCR1_CES(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
 
#define SEMC_NORCR1_CEH_MASK   (0xF0U)
 
#define SEMC_NORCR1_CEH_SHIFT   (4U)
 
#define SEMC_NORCR1_CEH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
 
#define SEMC_NORCR1_AS_MASK   (0xF00U)
 
#define SEMC_NORCR1_AS_SHIFT   (8U)
 
#define SEMC_NORCR1_AS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
 
#define SEMC_NORCR1_AH_MASK   (0xF000U)
 
#define SEMC_NORCR1_AH_SHIFT   (12U)
 
#define SEMC_NORCR1_AH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
 
#define SEMC_NORCR1_WEL_MASK   (0xF0000U)
 
#define SEMC_NORCR1_WEL_SHIFT   (16U)
 
#define SEMC_NORCR1_WEL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
 
#define SEMC_NORCR1_WEH_MASK   (0xF00000U)
 
#define SEMC_NORCR1_WEH_SHIFT   (20U)
 
#define SEMC_NORCR1_WEH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
 
#define SEMC_NORCR1_REL_MASK   (0xF000000U)
 
#define SEMC_NORCR1_REL_SHIFT   (24U)
 
#define SEMC_NORCR1_REL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
 
#define SEMC_NORCR1_REH_MASK   (0xF0000000U)
 
#define SEMC_NORCR1_REH_SHIFT   (28U)
 
#define SEMC_NORCR1_REH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
 

NORCR2 - NOR control register 2

#define SEMC_NORCR2_WDS_MASK   (0xFU)
 
#define SEMC_NORCR2_WDS_SHIFT   (0U)
 
#define SEMC_NORCR2_WDS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)
 
#define SEMC_NORCR2_WDH_MASK   (0xF0U)
 
#define SEMC_NORCR2_WDH_SHIFT   (4U)
 
#define SEMC_NORCR2_WDH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)
 
#define SEMC_NORCR2_TA_MASK   (0xF00U)
 
#define SEMC_NORCR2_TA_SHIFT   (8U)
 
#define SEMC_NORCR2_TA(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
 
#define SEMC_NORCR2_AWDH_MASK   (0xF000U)
 
#define SEMC_NORCR2_AWDH_SHIFT   (12U)
 
#define SEMC_NORCR2_AWDH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
 
#define SEMC_NORCR2_LC_MASK   (0xF0000U)
 
#define SEMC_NORCR2_LC_SHIFT   (16U)
 
#define SEMC_NORCR2_LC(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
 
#define SEMC_NORCR2_RD_MASK   (0xF00000U)
 
#define SEMC_NORCR2_RD_SHIFT   (20U)
 
#define SEMC_NORCR2_RD(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
 
#define SEMC_NORCR2_CEITV_MASK   (0xF000000U)
 
#define SEMC_NORCR2_CEITV_SHIFT   (24U)
 
#define SEMC_NORCR2_CEITV(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
 

SRAMCR0 - SRAM control register 0

#define SEMC_SRAMCR0_PS_MASK   (0x1U)
 
#define SEMC_SRAMCR0_PS_SHIFT   (0U)
 
#define SEMC_SRAMCR0_PS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
 
#define SEMC_SRAMCR0_BL_MASK   (0x70U)
 
#define SEMC_SRAMCR0_BL_SHIFT   (4U)
 
#define SEMC_SRAMCR0_BL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
 
#define SEMC_SRAMCR0_AM_MASK   (0x300U)
 
#define SEMC_SRAMCR0_AM_SHIFT   (8U)
 
#define SEMC_SRAMCR0_AM(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
 
#define SEMC_SRAMCR0_ADVP_MASK   (0x400U)
 
#define SEMC_SRAMCR0_ADVP_SHIFT   (10U)
 
#define SEMC_SRAMCR0_ADVP(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
 
#define SEMC_SRAMCR0_COL_MASK   (0xF000U)
 
#define SEMC_SRAMCR0_COL_SHIFT   (12U)
 
#define SEMC_SRAMCR0_COL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
 

SRAMCR1 - SRAM control register 1

#define SEMC_SRAMCR1_CES_MASK   (0xFU)
 
#define SEMC_SRAMCR1_CES_SHIFT   (0U)
 
#define SEMC_SRAMCR1_CES(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
 
#define SEMC_SRAMCR1_CEH_MASK   (0xF0U)
 
#define SEMC_SRAMCR1_CEH_SHIFT   (4U)
 
#define SEMC_SRAMCR1_CEH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
 
#define SEMC_SRAMCR1_AS_MASK   (0xF00U)
 
#define SEMC_SRAMCR1_AS_SHIFT   (8U)
 
#define SEMC_SRAMCR1_AS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
 
#define SEMC_SRAMCR1_AH_MASK   (0xF000U)
 
#define SEMC_SRAMCR1_AH_SHIFT   (12U)
 
#define SEMC_SRAMCR1_AH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
 
#define SEMC_SRAMCR1_WEL_MASK   (0xF0000U)
 
#define SEMC_SRAMCR1_WEL_SHIFT   (16U)
 
#define SEMC_SRAMCR1_WEL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
 
#define SEMC_SRAMCR1_WEH_MASK   (0xF00000U)
 
#define SEMC_SRAMCR1_WEH_SHIFT   (20U)
 
#define SEMC_SRAMCR1_WEH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
 
#define SEMC_SRAMCR1_REL_MASK   (0xF000000U)
 
#define SEMC_SRAMCR1_REL_SHIFT   (24U)
 
#define SEMC_SRAMCR1_REL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
 
#define SEMC_SRAMCR1_REH_MASK   (0xF0000000U)
 
#define SEMC_SRAMCR1_REH_SHIFT   (28U)
 
#define SEMC_SRAMCR1_REH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
 

SRAMCR2 - SRAM control register 2

#define SEMC_SRAMCR2_WDS_MASK   (0xFU)
 
#define SEMC_SRAMCR2_WDS_SHIFT   (0U)
 
#define SEMC_SRAMCR2_WDS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
 
#define SEMC_SRAMCR2_WDH_MASK   (0xF0U)
 
#define SEMC_SRAMCR2_WDH_SHIFT   (4U)
 
#define SEMC_SRAMCR2_WDH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
 
#define SEMC_SRAMCR2_TA_MASK   (0xF00U)
 
#define SEMC_SRAMCR2_TA_SHIFT   (8U)
 
#define SEMC_SRAMCR2_TA(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
 
#define SEMC_SRAMCR2_AWDH_MASK   (0xF000U)
 
#define SEMC_SRAMCR2_AWDH_SHIFT   (12U)
 
#define SEMC_SRAMCR2_AWDH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
 
#define SEMC_SRAMCR2_LC_MASK   (0xF0000U)
 
#define SEMC_SRAMCR2_LC_SHIFT   (16U)
 
#define SEMC_SRAMCR2_LC(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
 
#define SEMC_SRAMCR2_RD_MASK   (0xF00000U)
 
#define SEMC_SRAMCR2_RD_SHIFT   (20U)
 
#define SEMC_SRAMCR2_RD(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
 
#define SEMC_SRAMCR2_CEITV_MASK   (0xF000000U)
 
#define SEMC_SRAMCR2_CEITV_SHIFT   (24U)
 
#define SEMC_SRAMCR2_CEITV(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
 

DBICR0 - DBI-B control register 0

#define SEMC_DBICR0_PS_MASK   (0x1U)
 
#define SEMC_DBICR0_PS_SHIFT   (0U)
 
#define SEMC_DBICR0_PS(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
 
#define SEMC_DBICR0_BL_MASK   (0x70U)
 
#define SEMC_DBICR0_BL_SHIFT   (4U)
 
#define SEMC_DBICR0_BL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
 
#define SEMC_DBICR0_COL_MASK   (0xF000U)
 
#define SEMC_DBICR0_COL_SHIFT   (12U)
 
#define SEMC_DBICR0_COL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
 

DBICR1 - DBI-B control register 1

#define SEMC_DBICR1_CES_MASK   (0xFU)
 
#define SEMC_DBICR1_CES_SHIFT   (0U)
 
#define SEMC_DBICR1_CES(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
 
#define SEMC_DBICR1_CEH_MASK   (0xF0U)
 
#define SEMC_DBICR1_CEH_SHIFT   (4U)
 
#define SEMC_DBICR1_CEH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
 
#define SEMC_DBICR1_WEL_MASK   (0xF00U)
 
#define SEMC_DBICR1_WEL_SHIFT   (8U)
 
#define SEMC_DBICR1_WEL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
 
#define SEMC_DBICR1_WEH_MASK   (0xF000U)
 
#define SEMC_DBICR1_WEH_SHIFT   (12U)
 
#define SEMC_DBICR1_WEH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
 
#define SEMC_DBICR1_REL_MASK   (0xF0000U)
 
#define SEMC_DBICR1_REL_SHIFT   (16U)
 
#define SEMC_DBICR1_REL(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
 
#define SEMC_DBICR1_REH_MASK   (0xF00000U)
 
#define SEMC_DBICR1_REH_SHIFT   (20U)
 
#define SEMC_DBICR1_REH(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
 
#define SEMC_DBICR1_CEITV_MASK   (0xF000000U)
 
#define SEMC_DBICR1_CEITV_SHIFT   (24U)
 
#define SEMC_DBICR1_CEITV(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
 
#define SEMC_DBICR1_REL2_MASK   (0x30000000U)
 
#define SEMC_DBICR1_REL2_SHIFT   (28U)
 
#define SEMC_DBICR1_REL2(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK)
 
#define SEMC_DBICR1_REH2_MASK   (0xC0000000U)
 
#define SEMC_DBICR1_REH2_SHIFT   (30U)
 
#define SEMC_DBICR1_REH2(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK)
 

IPCR0 - IP Command control register 0

#define SEMC_IPCR0_SA_MASK   (0xFFFFFFFFU)
 
#define SEMC_IPCR0_SA_SHIFT   (0U)
 
#define SEMC_IPCR0_SA(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
 

IPCR1 - IP Command control register 1

#define SEMC_IPCR1_DATSZ_MASK   (0x7U)
 
#define SEMC_IPCR1_DATSZ_SHIFT   (0U)
 
#define SEMC_IPCR1_DATSZ(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
 

IPCR2 - IP Command control register 2

#define SEMC_IPCR2_BM0_MASK   (0x1U)
 
#define SEMC_IPCR2_BM0_SHIFT   (0U)
 
#define SEMC_IPCR2_BM0(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
 
#define SEMC_IPCR2_BM1_MASK   (0x2U)
 
#define SEMC_IPCR2_BM1_SHIFT   (1U)
 
#define SEMC_IPCR2_BM1(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
 
#define SEMC_IPCR2_BM2_MASK   (0x4U)
 
#define SEMC_IPCR2_BM2_SHIFT   (2U)
 
#define SEMC_IPCR2_BM2(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
 
#define SEMC_IPCR2_BM3_MASK   (0x8U)
 
#define SEMC_IPCR2_BM3_SHIFT   (3U)
 
#define SEMC_IPCR2_BM3(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
 

IPTXDAT - TX DATA register (for IP Command)

#define SEMC_IPTXDAT_DAT_MASK   (0xFFFFFFFFU)
 
#define SEMC_IPTXDAT_DAT_SHIFT   (0U)
 
#define SEMC_IPTXDAT_DAT(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
 

IPRXDAT - RX DATA register (for IP Command)

#define SEMC_IPRXDAT_DAT_MASK   (0xFFFFFFFFU)
 
#define SEMC_IPRXDAT_DAT_SHIFT   (0U)
 
#define SEMC_IPRXDAT_DAT(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
 

STS12 - Status register 12

#define SEMC_STS12_NDADDR_MASK   (0xFFFFFFFFU)
 
#define SEMC_STS12_NDADDR_SHIFT   (0U)
 
#define SEMC_STS12_NDADDR(x)   (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
 

Detailed Description

Macro Definition Documentation

◆ SEMC_BMCR0_WAGE

#define SEMC_BMCR0_WAGE (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)

WAGE - Weight of Aging

Definition at line 34335 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WAGE_MASK

#define SEMC_BMCR0_WAGE_MASK   (0xF0U)

Definition at line 34331 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WAGE_SHIFT

#define SEMC_BMCR0_WAGE_SHIFT   (4U)

Definition at line 34332 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WQOS

#define SEMC_BMCR0_WQOS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)

WQOS - Weight of QoS

Definition at line 34330 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WQOS_MASK

#define SEMC_BMCR0_WQOS_MASK   (0xFU)

Definition at line 34326 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WQOS_SHIFT

#define SEMC_BMCR0_WQOS_SHIFT   (0U)

Definition at line 34327 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WRWS

#define SEMC_BMCR0_WRWS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)

WRWS - Weight of Slave Hit (Read/Write switch)

Definition at line 34345 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WRWS_MASK

#define SEMC_BMCR0_WRWS_MASK   (0xFF0000U)

Definition at line 34341 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WRWS_SHIFT

#define SEMC_BMCR0_WRWS_SHIFT   (16U)

Definition at line 34342 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WSH

#define SEMC_BMCR0_WSH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)

WSH - Weight of Slave Hit (no read/write switch)

Definition at line 34340 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WSH_MASK

#define SEMC_BMCR0_WSH_MASK   (0xFF00U)

Definition at line 34336 of file MIMXRT1052.h.

◆ SEMC_BMCR0_WSH_SHIFT

#define SEMC_BMCR0_WSH_SHIFT   (8U)

Definition at line 34337 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WAGE

#define SEMC_BMCR1_WAGE (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)

WAGE - Weight of Aging

Definition at line 34359 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WAGE_MASK

#define SEMC_BMCR1_WAGE_MASK   (0xF0U)

Definition at line 34355 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WAGE_SHIFT

#define SEMC_BMCR1_WAGE_SHIFT   (4U)

Definition at line 34356 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WBR

#define SEMC_BMCR1_WBR (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)

WBR - Weight of Bank Rotation

Definition at line 34374 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WBR_MASK

#define SEMC_BMCR1_WBR_MASK   (0xFF000000U)

Definition at line 34370 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WBR_SHIFT

#define SEMC_BMCR1_WBR_SHIFT   (24U)

Definition at line 34371 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WPH

#define SEMC_BMCR1_WPH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)

WPH - Weight of Page Hit

Definition at line 34364 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WPH_MASK

#define SEMC_BMCR1_WPH_MASK   (0xFF00U)

Definition at line 34360 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WPH_SHIFT

#define SEMC_BMCR1_WPH_SHIFT   (8U)

Definition at line 34361 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WQOS

#define SEMC_BMCR1_WQOS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)

WQOS - Weight of QoS

Definition at line 34354 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WQOS_MASK

#define SEMC_BMCR1_WQOS_MASK   (0xFU)

Definition at line 34350 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WQOS_SHIFT

#define SEMC_BMCR1_WQOS_SHIFT   (0U)

Definition at line 34351 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WRWS

#define SEMC_BMCR1_WRWS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)

WRWS - Weight of Read/Write switch

Definition at line 34369 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WRWS_MASK

#define SEMC_BMCR1_WRWS_MASK   (0xFF0000U)

Definition at line 34365 of file MIMXRT1052.h.

◆ SEMC_BMCR1_WRWS_SHIFT

#define SEMC_BMCR1_WRWS_SHIFT   (16U)

Definition at line 34366 of file MIMXRT1052.h.

◆ SEMC_BR_BA

#define SEMC_BR_BA (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)

BA - Base Address

Definition at line 34425 of file MIMXRT1052.h.

◆ SEMC_BR_BA_MASK

#define SEMC_BR_BA_MASK   (0xFFFFF000U)

Definition at line 34421 of file MIMXRT1052.h.

◆ SEMC_BR_BA_SHIFT

#define SEMC_BR_BA_SHIFT   (12U)

Definition at line 34422 of file MIMXRT1052.h.

◆ SEMC_BR_COUNT

#define SEMC_BR_COUNT   (9U)

Definition at line 34429 of file MIMXRT1052.h.

◆ SEMC_BR_MS

#define SEMC_BR_MS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)

MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100..4GB 0b10101..4GB 0b10110..4GB 0b10111..4GB 0b11000..4GB 0b11001..4GB 0b11010..4GB 0b11011..4GB 0b11100..4GB 0b11101..4GB 0b11110..4GB 0b11111..4GB

Definition at line 34420 of file MIMXRT1052.h.

◆ SEMC_BR_MS_MASK

#define SEMC_BR_MS_MASK   (0x3EU)

Definition at line 34384 of file MIMXRT1052.h.

◆ SEMC_BR_MS_SHIFT

#define SEMC_BR_MS_SHIFT   (1U)

Definition at line 34385 of file MIMXRT1052.h.

◆ SEMC_BR_VLD

#define SEMC_BR_VLD (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)

VLD - Valid

Definition at line 34383 of file MIMXRT1052.h.

◆ SEMC_BR_VLD_MASK

#define SEMC_BR_VLD_MASK   (0x1U)

Definition at line 34379 of file MIMXRT1052.h.

◆ SEMC_BR_VLD_SHIFT

#define SEMC_BR_VLD_SHIFT   (0U)

Definition at line 34380 of file MIMXRT1052.h.

◆ SEMC_DBICR0_BL

#define SEMC_DBICR0_BL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64

Definition at line 35093 of file MIMXRT1052.h.

◆ SEMC_DBICR0_BL_MASK

#define SEMC_DBICR0_BL_MASK   (0x70U)

Definition at line 35081 of file MIMXRT1052.h.

◆ SEMC_DBICR0_BL_SHIFT

#define SEMC_DBICR0_BL_SHIFT   (4U)

Definition at line 35082 of file MIMXRT1052.h.

◆ SEMC_DBICR0_COL

#define SEMC_DBICR0_COL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)

COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits

Definition at line 35114 of file MIMXRT1052.h.

◆ SEMC_DBICR0_COL_MASK

#define SEMC_DBICR0_COL_MASK   (0xF000U)

Definition at line 35094 of file MIMXRT1052.h.

◆ SEMC_DBICR0_COL_SHIFT

#define SEMC_DBICR0_COL_SHIFT   (12U)

Definition at line 35095 of file MIMXRT1052.h.

◆ SEMC_DBICR0_PS

#define SEMC_DBICR0_PS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 35080 of file MIMXRT1052.h.

◆ SEMC_DBICR0_PS_MASK

#define SEMC_DBICR0_PS_MASK   (0x1U)

Definition at line 35074 of file MIMXRT1052.h.

◆ SEMC_DBICR0_PS_SHIFT

#define SEMC_DBICR0_PS_SHIFT   (0U)

Definition at line 35075 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CEH

#define SEMC_DBICR1_CEH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)

CEH - CSX Hold Time

Definition at line 35128 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CEH_MASK

#define SEMC_DBICR1_CEH_MASK   (0xF0U)

Definition at line 35124 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CEH_SHIFT

#define SEMC_DBICR1_CEH_SHIFT   (4U)

Definition at line 35125 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CEITV

#define SEMC_DBICR1_CEITV (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)

CEITV - CSX interval min time

Definition at line 35153 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CEITV_MASK

#define SEMC_DBICR1_CEITV_MASK   (0xF000000U)

Definition at line 35149 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CEITV_SHIFT

#define SEMC_DBICR1_CEITV_SHIFT   (24U)

Definition at line 35150 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CES

#define SEMC_DBICR1_CES (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)

CES - CSX Setup Time

Definition at line 35123 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CES_MASK

#define SEMC_DBICR1_CES_MASK   (0xFU)

Definition at line 35119 of file MIMXRT1052.h.

◆ SEMC_DBICR1_CES_SHIFT

#define SEMC_DBICR1_CES_SHIFT   (0U)

Definition at line 35120 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REH

#define SEMC_DBICR1_REH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)

REH - RDX High Time bit [3:0]

Definition at line 35148 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REH2

#define SEMC_DBICR1_REH2 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK)

REH2 - RDX High Time bit [5:4]

Definition at line 35163 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REH2_MASK

#define SEMC_DBICR1_REH2_MASK   (0xC0000000U)

Definition at line 35159 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REH2_SHIFT

#define SEMC_DBICR1_REH2_SHIFT   (30U)

Definition at line 35160 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REH_MASK

#define SEMC_DBICR1_REH_MASK   (0xF00000U)

Definition at line 35144 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REH_SHIFT

#define SEMC_DBICR1_REH_SHIFT   (20U)

Definition at line 35145 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REL

#define SEMC_DBICR1_REL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)

REL - RDX Low Time bit [3:0]

Definition at line 35143 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REL2

#define SEMC_DBICR1_REL2 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK)

REL2 - RDX Low Time bit [5:4]

Definition at line 35158 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REL2_MASK

#define SEMC_DBICR1_REL2_MASK   (0x30000000U)

Definition at line 35154 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REL2_SHIFT

#define SEMC_DBICR1_REL2_SHIFT   (28U)

Definition at line 35155 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REL_MASK

#define SEMC_DBICR1_REL_MASK   (0xF0000U)

Definition at line 35139 of file MIMXRT1052.h.

◆ SEMC_DBICR1_REL_SHIFT

#define SEMC_DBICR1_REL_SHIFT   (16U)

Definition at line 35140 of file MIMXRT1052.h.

◆ SEMC_DBICR1_WEH

#define SEMC_DBICR1_WEH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)

WEH - WRX High Time

Definition at line 35138 of file MIMXRT1052.h.

◆ SEMC_DBICR1_WEH_MASK

#define SEMC_DBICR1_WEH_MASK   (0xF000U)

Definition at line 35134 of file MIMXRT1052.h.

◆ SEMC_DBICR1_WEH_SHIFT

#define SEMC_DBICR1_WEH_SHIFT   (12U)

Definition at line 35135 of file MIMXRT1052.h.

◆ SEMC_DBICR1_WEL

#define SEMC_DBICR1_WEL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)

WEL - WRX Low Time

Definition at line 35133 of file MIMXRT1052.h.

◆ SEMC_DBICR1_WEL_MASK

#define SEMC_DBICR1_WEL_MASK   (0xF00U)

Definition at line 35129 of file MIMXRT1052.h.

◆ SEMC_DBICR1_WEL_SHIFT

#define SEMC_DBICR1_WEL_SHIFT   (8U)

Definition at line 35130 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXIBUSERREN

#define SEMC_INTEN_AXIBUSERREN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)

AXIBUSERREN - AXI bus error interrupt enable

Definition at line 34452 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXIBUSERREN_MASK

#define SEMC_INTEN_AXIBUSERREN_MASK   (0x8U)

Definition at line 34448 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXIBUSERREN_SHIFT

#define SEMC_INTEN_AXIBUSERREN_SHIFT   (3U)

Definition at line 34449 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXICMDERREN

#define SEMC_INTEN_AXICMDERREN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)

AXICMDERREN - AXI command error interrupt enable

Definition at line 34447 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXICMDERREN_MASK

#define SEMC_INTEN_AXICMDERREN_MASK   (0x4U)

Definition at line 34443 of file MIMXRT1052.h.

◆ SEMC_INTEN_AXICMDERREN_SHIFT

#define SEMC_INTEN_AXICMDERREN_SHIFT   (2U)

Definition at line 34444 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDDONEEN

#define SEMC_INTEN_IPCMDDONEEN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)

IPCMDDONEEN - IP command done interrupt enable

Definition at line 34437 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDDONEEN_MASK

#define SEMC_INTEN_IPCMDDONEEN_MASK   (0x1U)

Definition at line 34433 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDDONEEN_SHIFT

#define SEMC_INTEN_IPCMDDONEEN_SHIFT   (0U)

Definition at line 34434 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDERREN

#define SEMC_INTEN_IPCMDERREN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)

IPCMDERREN - IP command error interrupt enable

Definition at line 34442 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDERREN_MASK

#define SEMC_INTEN_IPCMDERREN_MASK   (0x2U)

Definition at line 34438 of file MIMXRT1052.h.

◆ SEMC_INTEN_IPCMDERREN_SHIFT

#define SEMC_INTEN_IPCMDERREN_SHIFT   (1U)

Definition at line 34439 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDNOPENDEN

#define SEMC_INTEN_NDNOPENDEN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)

NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation. 0b0..Disable 0b1..Enable

Definition at line 34466 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDNOPENDEN_MASK

#define SEMC_INTEN_NDNOPENDEN_MASK   (0x20U)

Definition at line 34460 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDNOPENDEN_SHIFT

#define SEMC_INTEN_NDNOPENDEN_SHIFT   (5U)

Definition at line 34461 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDPAGEENDEN

#define SEMC_INTEN_NDPAGEENDEN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)

NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation. 0b0..Disable 0b1..Enable

Definition at line 34459 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDPAGEENDEN_MASK

#define SEMC_INTEN_NDPAGEENDEN_MASK   (0x10U)

Definition at line 34453 of file MIMXRT1052.h.

◆ SEMC_INTEN_NDPAGEENDEN_SHIFT

#define SEMC_INTEN_NDPAGEENDEN_SHIFT   (4U)

Definition at line 34454 of file MIMXRT1052.h.

◆ SEMC_INTR_AXIBUSERR

#define SEMC_INTR_AXIBUSERR (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)

AXIBUSERR - AXI bus error interrupt

Definition at line 34490 of file MIMXRT1052.h.

◆ SEMC_INTR_AXIBUSERR_MASK

#define SEMC_INTR_AXIBUSERR_MASK   (0x8U)

Definition at line 34486 of file MIMXRT1052.h.

◆ SEMC_INTR_AXIBUSERR_SHIFT

#define SEMC_INTR_AXIBUSERR_SHIFT   (3U)

Definition at line 34487 of file MIMXRT1052.h.

◆ SEMC_INTR_AXICMDERR

#define SEMC_INTR_AXICMDERR (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)

AXICMDERR - AXI command error interrupt

Definition at line 34485 of file MIMXRT1052.h.

◆ SEMC_INTR_AXICMDERR_MASK

#define SEMC_INTR_AXICMDERR_MASK   (0x4U)

Definition at line 34481 of file MIMXRT1052.h.

◆ SEMC_INTR_AXICMDERR_SHIFT

#define SEMC_INTR_AXICMDERR_SHIFT   (2U)

Definition at line 34482 of file MIMXRT1052.h.

◆ SEMC_INTR_IPCMDDONE

#define SEMC_INTR_IPCMDDONE (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)

IPCMDDONE - IP command normal done interrupt

Definition at line 34475 of file MIMXRT1052.h.

◆ SEMC_INTR_IPCMDDONE_MASK

#define SEMC_INTR_IPCMDDONE_MASK   (0x1U)

Definition at line 34471 of file MIMXRT1052.h.

◆ SEMC_INTR_IPCMDDONE_SHIFT

#define SEMC_INTR_IPCMDDONE_SHIFT   (0U)

Definition at line 34472 of file MIMXRT1052.h.

◆ SEMC_INTR_IPCMDERR

#define SEMC_INTR_IPCMDERR (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)

IPCMDERR - IP command error done interrupt

Definition at line 34480 of file MIMXRT1052.h.

◆ SEMC_INTR_IPCMDERR_MASK

#define SEMC_INTR_IPCMDERR_MASK   (0x2U)

Definition at line 34476 of file MIMXRT1052.h.

◆ SEMC_INTR_IPCMDERR_SHIFT

#define SEMC_INTR_IPCMDERR_SHIFT   (1U)

Definition at line 34477 of file MIMXRT1052.h.

◆ SEMC_INTR_NDNOPEND

#define SEMC_INTR_NDNOPEND (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)

NDNOPEND - This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface.

Definition at line 34500 of file MIMXRT1052.h.

◆ SEMC_INTR_NDNOPEND_MASK

#define SEMC_INTR_NDNOPEND_MASK   (0x20U)

Definition at line 34496 of file MIMXRT1052.h.

◆ SEMC_INTR_NDNOPEND_SHIFT

#define SEMC_INTR_NDNOPEND_SHIFT   (5U)

Definition at line 34497 of file MIMXRT1052.h.

◆ SEMC_INTR_NDPAGEEND

#define SEMC_INTR_NDPAGEEND (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)

NDPAGEEND - This interrupt is generated when the last address of one page in NAND device is written by AXI command

Definition at line 34495 of file MIMXRT1052.h.

◆ SEMC_INTR_NDPAGEEND_MASK

#define SEMC_INTR_NDPAGEEND_MASK   (0x10U)

Definition at line 34491 of file MIMXRT1052.h.

◆ SEMC_INTR_NDPAGEEND_SHIFT

#define SEMC_INTR_NDPAGEEND_SHIFT   (4U)

Definition at line 34492 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_A8

#define SEMC_IOCR_MUX_A8 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)

MUX_A8 - SEMC_A8 output selection 0b000..SDRAM Address bit (A8) 0b001..NAND CE# 0b010..NOR CE# 0b011..PSRAM CE# 0b100..DBI CSX 0b101..SDRAM Address bit (A8) 0b110..SDRAM Address bit (A8) 0b111..SDRAM Address bit (A8)

Definition at line 34256 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_A8_MASK

#define SEMC_IOCR_MUX_A8_MASK   (0x7U)

Definition at line 34244 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_A8_SHIFT

#define SEMC_IOCR_MUX_A8_SHIFT   (0U)

Definition at line 34245 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX0

#define SEMC_IOCR_MUX_CSX0 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)

MUX_CSX0 - SEMC_CSX0 output selection 0b000..NOR/PSRAM Address bit 24 (A24) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX

Definition at line 34269 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX0_MASK

#define SEMC_IOCR_MUX_CSX0_MASK   (0x38U)

Definition at line 34257 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX0_SHIFT

#define SEMC_IOCR_MUX_CSX0_SHIFT   (3U)

Definition at line 34258 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX1

#define SEMC_IOCR_MUX_CSX1 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)

MUX_CSX1 - SEMC_CSX1 output selection 0b000..NOR/PSRAM Address bit 25 (A25) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX

Definition at line 34282 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX1_MASK

#define SEMC_IOCR_MUX_CSX1_MASK   (0x1C0U)

Definition at line 34270 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX1_SHIFT

#define SEMC_IOCR_MUX_CSX1_SHIFT   (6U)

Definition at line 34271 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX2

#define SEMC_IOCR_MUX_CSX2 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)

MUX_CSX2 - SEMC_CSX2 output selection 0b000..NOR/PSRAM Address bit 26 (A26) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX

Definition at line 34295 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX2_MASK

#define SEMC_IOCR_MUX_CSX2_MASK   (0xE00U)

Definition at line 34283 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX2_SHIFT

#define SEMC_IOCR_MUX_CSX2_SHIFT   (9U)

Definition at line 34284 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX3

#define SEMC_IOCR_MUX_CSX3 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)

MUX_CSX3 - SEMC_CSX3 output selection 0b000..NOR/PSRAM Address bit 27 (A27) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX

Definition at line 34308 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX3_MASK

#define SEMC_IOCR_MUX_CSX3_MASK   (0x7000U)

Definition at line 34296 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_CSX3_SHIFT

#define SEMC_IOCR_MUX_CSX3_SHIFT   (12U)

Definition at line 34297 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_RDY

#define SEMC_IOCR_MUX_RDY (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)

MUX_RDY - SEMC_RDY function selection 0b000..NAND Ready/Wait# input 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NOR CE# 0b101..PSRAM CE# 0b110..DBI CSX 0b111..NOR/PSRAM Address bit 27

Definition at line 34321 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_RDY_MASK

#define SEMC_IOCR_MUX_RDY_MASK   (0x38000U)

Definition at line 34309 of file MIMXRT1052.h.

◆ SEMC_IOCR_MUX_RDY_SHIFT

#define SEMC_IOCR_MUX_RDY_SHIFT   (15U)

Definition at line 34310 of file MIMXRT1052.h.

◆ SEMC_IPCMD_CMD

#define SEMC_IPCMD_CMD (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)

Definition at line 35228 of file MIMXRT1052.h.

◆ SEMC_IPCMD_CMD_MASK

#define SEMC_IPCMD_CMD_MASK   (0xFFFFU)

Definition at line 35226 of file MIMXRT1052.h.

◆ SEMC_IPCMD_CMD_SHIFT

#define SEMC_IPCMD_CMD_SHIFT   (0U)

Definition at line 35227 of file MIMXRT1052.h.

◆ SEMC_IPCMD_KEY

#define SEMC_IPCMD_KEY (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)

KEY - This field should be written with 0xA55A when trigging an IP command.

Definition at line 35233 of file MIMXRT1052.h.

◆ SEMC_IPCMD_KEY_MASK

#define SEMC_IPCMD_KEY_MASK   (0xFFFF0000U)

Definition at line 35229 of file MIMXRT1052.h.

◆ SEMC_IPCMD_KEY_SHIFT

#define SEMC_IPCMD_KEY_SHIFT   (16U)

Definition at line 35230 of file MIMXRT1052.h.

◆ SEMC_IPCR0_SA

#define SEMC_IPCR0_SA (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)

SA - Slave address

Definition at line 35172 of file MIMXRT1052.h.

◆ SEMC_IPCR0_SA_MASK

#define SEMC_IPCR0_SA_MASK   (0xFFFFFFFFU)

Definition at line 35168 of file MIMXRT1052.h.

◆ SEMC_IPCR0_SA_SHIFT

#define SEMC_IPCR0_SA_SHIFT   (0U)

Definition at line 35169 of file MIMXRT1052.h.

◆ SEMC_IPCR1_DATSZ

#define SEMC_IPCR1_DATSZ (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)

DATSZ - Data Size in Byte 0b000..4 0b001..1 0b010..2 0b011..3 0b100..4 0b101..4 0b110..4 0b111..4

Definition at line 35189 of file MIMXRT1052.h.

◆ SEMC_IPCR1_DATSZ_MASK

#define SEMC_IPCR1_DATSZ_MASK   (0x7U)

Definition at line 35177 of file MIMXRT1052.h.

◆ SEMC_IPCR1_DATSZ_SHIFT

#define SEMC_IPCR1_DATSZ_SHIFT   (0U)

Definition at line 35178 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM0

#define SEMC_IPCR2_BM0 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)

BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) 0b0..Byte Unmasked 0b1..Byte Masked

Definition at line 35200 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM0_MASK

#define SEMC_IPCR2_BM0_MASK   (0x1U)

Definition at line 35194 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM0_SHIFT

#define SEMC_IPCR2_BM0_SHIFT   (0U)

Definition at line 35195 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM1

#define SEMC_IPCR2_BM1 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)

BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) 0b0..Byte Unmasked 0b1..Byte Masked

Definition at line 35207 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM1_MASK

#define SEMC_IPCR2_BM1_MASK   (0x2U)

Definition at line 35201 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM1_SHIFT

#define SEMC_IPCR2_BM1_SHIFT   (1U)

Definition at line 35202 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM2

#define SEMC_IPCR2_BM2 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)

BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) 0b0..Byte Unmasked 0b1..Byte Masked

Definition at line 35214 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM2_MASK

#define SEMC_IPCR2_BM2_MASK   (0x4U)

Definition at line 35208 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM2_SHIFT

#define SEMC_IPCR2_BM2_SHIFT   (2U)

Definition at line 35209 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM3

#define SEMC_IPCR2_BM3 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)

BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) 0b0..Byte Unmasked 0b1..Byte Masked

Definition at line 35221 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM3_MASK

#define SEMC_IPCR2_BM3_MASK   (0x8U)

Definition at line 35215 of file MIMXRT1052.h.

◆ SEMC_IPCR2_BM3_SHIFT

#define SEMC_IPCR2_BM3_SHIFT   (3U)

Definition at line 35216 of file MIMXRT1052.h.

◆ SEMC_IPRXDAT_DAT

#define SEMC_IPRXDAT_DAT (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)

Definition at line 35247 of file MIMXRT1052.h.

◆ SEMC_IPRXDAT_DAT_MASK

#define SEMC_IPRXDAT_DAT_MASK   (0xFFFFFFFFU)

Definition at line 35245 of file MIMXRT1052.h.

◆ SEMC_IPRXDAT_DAT_SHIFT

#define SEMC_IPRXDAT_DAT_SHIFT   (0U)

Definition at line 35246 of file MIMXRT1052.h.

◆ SEMC_IPTXDAT_DAT

#define SEMC_IPTXDAT_DAT (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)

Definition at line 35240 of file MIMXRT1052.h.

◆ SEMC_IPTXDAT_DAT_MASK

#define SEMC_IPTXDAT_DAT_MASK   (0xFFFFFFFFU)

Definition at line 35238 of file MIMXRT1052.h.

◆ SEMC_IPTXDAT_DAT_SHIFT

#define SEMC_IPTXDAT_DAT_SHIFT   (0U)

Definition at line 35239 of file MIMXRT1052.h.

◆ SEMC_MCR_BTO

#define SEMC_MCR_BTO (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)

BTO - Bus timeout cycles 0b00000..255*1 0b00001-0b11110..255*2 - 255*2^30 0b11111..255*2^31

Definition at line 34239 of file MIMXRT1052.h.

◆ SEMC_MCR_BTO_MASK

#define SEMC_MCR_BTO_MASK   (0x1F000000U)

Definition at line 34232 of file MIMXRT1052.h.

◆ SEMC_MCR_BTO_SHIFT

#define SEMC_MCR_BTO_SHIFT   (24U)

Definition at line 34233 of file MIMXRT1052.h.

◆ SEMC_MCR_CTO

#define SEMC_MCR_CTO (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)

CTO - Command Execution timeout cycles

Definition at line 34231 of file MIMXRT1052.h.

◆ SEMC_MCR_CTO_MASK

#define SEMC_MCR_CTO_MASK   (0xFF0000U)

Definition at line 34227 of file MIMXRT1052.h.

◆ SEMC_MCR_CTO_SHIFT

#define SEMC_MCR_CTO_SHIFT   (16U)

Definition at line 34228 of file MIMXRT1052.h.

◆ SEMC_MCR_DQSMD

#define SEMC_MCR_DQSMD (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)

DQSMD - DQS (read strobe) mode 0b0..Dummy read strobe loopbacked internally 0b1..Dummy read strobe loopbacked from DQS pad

Definition at line 34212 of file MIMXRT1052.h.

◆ SEMC_MCR_DQSMD_MASK

#define SEMC_MCR_DQSMD_MASK   (0x4U)

Definition at line 34206 of file MIMXRT1052.h.

◆ SEMC_MCR_DQSMD_SHIFT

#define SEMC_MCR_DQSMD_SHIFT   (2U)

Definition at line 34207 of file MIMXRT1052.h.

◆ SEMC_MCR_MDIS

#define SEMC_MCR_MDIS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Module enabled 0b1..Module disabled.

Definition at line 34205 of file MIMXRT1052.h.

◆ SEMC_MCR_MDIS_MASK

#define SEMC_MCR_MDIS_MASK   (0x2U)

Definition at line 34199 of file MIMXRT1052.h.

◆ SEMC_MCR_MDIS_SHIFT

#define SEMC_MCR_MDIS_SHIFT   (1U)

Definition at line 34200 of file MIMXRT1052.h.

◆ SEMC_MCR_SWRST

#define SEMC_MCR_SWRST (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)

SWRST - Software Reset

Definition at line 34198 of file MIMXRT1052.h.

◆ SEMC_MCR_SWRST_MASK

#define SEMC_MCR_SWRST_MASK   (0x1U)

Definition at line 34194 of file MIMXRT1052.h.

◆ SEMC_MCR_SWRST_SHIFT

#define SEMC_MCR_SWRST_SHIFT   (0U)

Definition at line 34195 of file MIMXRT1052.h.

◆ SEMC_MCR_WPOL0

#define SEMC_MCR_WPOL0 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)

WPOL0 - WAIT/RDY# polarity for NOR/PSRAM 0b0..Low active 0b1..High active

Definition at line 34219 of file MIMXRT1052.h.

◆ SEMC_MCR_WPOL0_MASK

#define SEMC_MCR_WPOL0_MASK   (0x40U)

Definition at line 34213 of file MIMXRT1052.h.

◆ SEMC_MCR_WPOL0_SHIFT

#define SEMC_MCR_WPOL0_SHIFT   (6U)

Definition at line 34214 of file MIMXRT1052.h.

◆ SEMC_MCR_WPOL1

#define SEMC_MCR_WPOL1 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)

WPOL1 - WAIT/RDY# polarity for NAND 0b0..Low active 0b1..High active

Definition at line 34226 of file MIMXRT1052.h.

◆ SEMC_MCR_WPOL1_MASK

#define SEMC_MCR_WPOL1_MASK   (0x80U)

Definition at line 34220 of file MIMXRT1052.h.

◆ SEMC_MCR_WPOL1_SHIFT

#define SEMC_MCR_WPOL1_SHIFT   (7U)

Definition at line 34221 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_BL

#define SEMC_NANDCR0_BL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64

Definition at line 34669 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_BL_MASK

#define SEMC_NANDCR0_BL_MASK   (0x70U)

Definition at line 34657 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_BL_SHIFT

#define SEMC_NANDCR0_BL_SHIFT   (4U)

Definition at line 34658 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_COL

#define SEMC_NANDCR0_COL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)

COL - Column address bit number 0b000..16 0b001..15 0b010..14 0b011..13 0b100..12 0b101..11 0b110..10 0b111..9

Definition at line 34689 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_COL_MASK

#define SEMC_NANDCR0_COL_MASK   (0x700U)

Definition at line 34677 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_COL_SHIFT

#define SEMC_NANDCR0_COL_SHIFT   (8U)

Definition at line 34678 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_EDO

#define SEMC_NANDCR0_EDO (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)

EDO - EDO mode enabled 0b0..EDO mode disabled 0b1..EDO mode enabled

Definition at line 34676 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_EDO_MASK

#define SEMC_NANDCR0_EDO_MASK   (0x80U)

Definition at line 34670 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_EDO_SHIFT

#define SEMC_NANDCR0_EDO_SHIFT   (7U)

Definition at line 34671 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_PS

#define SEMC_NANDCR0_PS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 34656 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_PS_MASK

#define SEMC_NANDCR0_PS_MASK   (0x1U)

Definition at line 34650 of file MIMXRT1052.h.

◆ SEMC_NANDCR0_PS_SHIFT

#define SEMC_NANDCR0_PS_SHIFT   (0U)

Definition at line 34651 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CEH

#define SEMC_NANDCR1_CEH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)

CEH - CE hold time

Definition at line 34703 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CEH_MASK

#define SEMC_NANDCR1_CEH_MASK   (0xF0U)

Definition at line 34699 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CEH_SHIFT

#define SEMC_NANDCR1_CEH_SHIFT   (4U)

Definition at line 34700 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CEITV

#define SEMC_NANDCR1_CEITV (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)

CEITV - CE# interval time

Definition at line 34733 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CEITV_MASK

#define SEMC_NANDCR1_CEITV_MASK   (0xF0000000U)

Definition at line 34729 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CEITV_SHIFT

#define SEMC_NANDCR1_CEITV_SHIFT   (28U)

Definition at line 34730 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CES

#define SEMC_NANDCR1_CES (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)

CES - CE setup time

Definition at line 34698 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CES_MASK

#define SEMC_NANDCR1_CES_MASK   (0xFU)

Definition at line 34694 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_CES_SHIFT

#define SEMC_NANDCR1_CES_SHIFT   (0U)

Definition at line 34695 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_REH

#define SEMC_NANDCR1_REH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)

REH - RE# HIGH time

Definition at line 34723 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_REH_MASK

#define SEMC_NANDCR1_REH_MASK   (0xF00000U)

Definition at line 34719 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_REH_SHIFT

#define SEMC_NANDCR1_REH_SHIFT   (20U)

Definition at line 34720 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_REL

#define SEMC_NANDCR1_REL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)

REL - RE# LOW time

Definition at line 34718 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_REL_MASK

#define SEMC_NANDCR1_REL_MASK   (0xF0000U)

Definition at line 34714 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_REL_SHIFT

#define SEMC_NANDCR1_REL_SHIFT   (16U)

Definition at line 34715 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_TA

#define SEMC_NANDCR1_TA (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)

TA - Turnaround time

Definition at line 34728 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_TA_MASK

#define SEMC_NANDCR1_TA_MASK   (0xF000000U)

Definition at line 34724 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_TA_SHIFT

#define SEMC_NANDCR1_TA_SHIFT   (24U)

Definition at line 34725 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_WEH

#define SEMC_NANDCR1_WEH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)

WEH - WE# HIGH time

Definition at line 34713 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_WEH_MASK

#define SEMC_NANDCR1_WEH_MASK   (0xF000U)

Definition at line 34709 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_WEH_SHIFT

#define SEMC_NANDCR1_WEH_SHIFT   (12U)

Definition at line 34710 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_WEL

#define SEMC_NANDCR1_WEL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)

WEL - WE# LOW time

Definition at line 34708 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_WEL_MASK

#define SEMC_NANDCR1_WEL_MASK   (0xF00U)

Definition at line 34704 of file MIMXRT1052.h.

◆ SEMC_NANDCR1_WEL_SHIFT

#define SEMC_NANDCR1_WEL_SHIFT   (8U)

Definition at line 34705 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TADL

#define SEMC_NANDCR2_TADL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)

TADL - ALE to WRITE Data start wait time

Definition at line 34752 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TADL_MASK

#define SEMC_NANDCR2_TADL_MASK   (0x3F000U)

Definition at line 34748 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TADL_SHIFT

#define SEMC_NANDCR2_TADL_SHIFT   (12U)

Definition at line 34749 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TRHW

#define SEMC_NANDCR2_TRHW (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)

TRHW - RE# HIGH to WE# LOW wait time

Definition at line 34747 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TRHW_MASK

#define SEMC_NANDCR2_TRHW_MASK   (0xFC0U)

Definition at line 34743 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TRHW_SHIFT

#define SEMC_NANDCR2_TRHW_SHIFT   (6U)

Definition at line 34744 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TRR

#define SEMC_NANDCR2_TRR (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)

TRR - Ready to RE# LOW min wait time

Definition at line 34757 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TRR_MASK

#define SEMC_NANDCR2_TRR_MASK   (0xFC0000U)

Definition at line 34753 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TRR_SHIFT

#define SEMC_NANDCR2_TRR_SHIFT   (18U)

Definition at line 34754 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TWB

#define SEMC_NANDCR2_TWB (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)

TWB - WE# HIGH to busy wait time

Definition at line 34762 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TWB_MASK

#define SEMC_NANDCR2_TWB_MASK   (0x3F000000U)

Definition at line 34758 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TWB_SHIFT

#define SEMC_NANDCR2_TWB_SHIFT   (24U)

Definition at line 34759 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TWHR

#define SEMC_NANDCR2_TWHR (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)

TWHR - WE# HIGH to RE# LOW wait time

Definition at line 34742 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TWHR_MASK

#define SEMC_NANDCR2_TWHR_MASK   (0x3FU)

Definition at line 34738 of file MIMXRT1052.h.

◆ SEMC_NANDCR2_TWHR_SHIFT

#define SEMC_NANDCR2_TWHR_SHIFT   (0U)

Definition at line 34739 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT1

#define SEMC_NANDCR3_NDOPT1 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)

NDOPT1 - NAND option bit 1

Definition at line 34771 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT1_MASK

#define SEMC_NANDCR3_NDOPT1_MASK   (0x1U)

Definition at line 34767 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT1_SHIFT

#define SEMC_NANDCR3_NDOPT1_SHIFT   (0U)

Definition at line 34768 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT2

#define SEMC_NANDCR3_NDOPT2 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)

NDOPT2 - NAND option bit 2

Definition at line 34776 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT2_MASK

#define SEMC_NANDCR3_NDOPT2_MASK   (0x2U)

Definition at line 34772 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT2_SHIFT

#define SEMC_NANDCR3_NDOPT2_SHIFT   (1U)

Definition at line 34773 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT3

#define SEMC_NANDCR3_NDOPT3 (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)

NDOPT3 - NAND option bit 3

Definition at line 34781 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT3_MASK

#define SEMC_NANDCR3_NDOPT3_MASK   (0x4U)

Definition at line 34777 of file MIMXRT1052.h.

◆ SEMC_NANDCR3_NDOPT3_SHIFT

#define SEMC_NANDCR3_NDOPT3_SHIFT   (2U)

Definition at line 34778 of file MIMXRT1052.h.

◆ SEMC_NORCR0_ADVP

#define SEMC_NORCR0_ADVP (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)

ADVP - ADV# polarity 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.

Definition at line 34821 of file MIMXRT1052.h.

◆ SEMC_NORCR0_ADVP_MASK

#define SEMC_NORCR0_ADVP_MASK   (0x400U)

Definition at line 34815 of file MIMXRT1052.h.

◆ SEMC_NORCR0_ADVP_SHIFT

#define SEMC_NORCR0_ADVP_SHIFT   (10U)

Definition at line 34816 of file MIMXRT1052.h.

◆ SEMC_NORCR0_AM

#define SEMC_NORCR0_AM (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)

AM - Address Mode 0b00..Address/Data MUX mode 0b01..Advanced Address/Data MUX mode 0b10..Address/Data non-MUX mode 0b11..Address/Data non-MUX mode

Definition at line 34814 of file MIMXRT1052.h.

◆ SEMC_NORCR0_AM_MASK

#define SEMC_NORCR0_AM_MASK   (0x300U)

Definition at line 34806 of file MIMXRT1052.h.

◆ SEMC_NORCR0_AM_SHIFT

#define SEMC_NORCR0_AM_SHIFT   (8U)

Definition at line 34807 of file MIMXRT1052.h.

◆ SEMC_NORCR0_BL

#define SEMC_NORCR0_BL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64

Definition at line 34805 of file MIMXRT1052.h.

◆ SEMC_NORCR0_BL_MASK

#define SEMC_NORCR0_BL_MASK   (0x70U)

Definition at line 34793 of file MIMXRT1052.h.

◆ SEMC_NORCR0_BL_SHIFT

#define SEMC_NORCR0_BL_SHIFT   (4U)

Definition at line 34794 of file MIMXRT1052.h.

◆ SEMC_NORCR0_COL

#define SEMC_NORCR0_COL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)

COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits

Definition at line 34842 of file MIMXRT1052.h.

◆ SEMC_NORCR0_COL_MASK

#define SEMC_NORCR0_COL_MASK   (0xF000U)

Definition at line 34822 of file MIMXRT1052.h.

◆ SEMC_NORCR0_COL_SHIFT

#define SEMC_NORCR0_COL_SHIFT   (12U)

Definition at line 34823 of file MIMXRT1052.h.

◆ SEMC_NORCR0_PS

#define SEMC_NORCR0_PS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 34792 of file MIMXRT1052.h.

◆ SEMC_NORCR0_PS_MASK

#define SEMC_NORCR0_PS_MASK   (0x1U)

Definition at line 34786 of file MIMXRT1052.h.

◆ SEMC_NORCR0_PS_SHIFT

#define SEMC_NORCR0_PS_SHIFT   (0U)

Definition at line 34787 of file MIMXRT1052.h.

◆ SEMC_NORCR1_AH

#define SEMC_NORCR1_AH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)

AH - Address hold time

Definition at line 34866 of file MIMXRT1052.h.

◆ SEMC_NORCR1_AH_MASK

#define SEMC_NORCR1_AH_MASK   (0xF000U)

Definition at line 34862 of file MIMXRT1052.h.

◆ SEMC_NORCR1_AH_SHIFT

#define SEMC_NORCR1_AH_SHIFT   (12U)

Definition at line 34863 of file MIMXRT1052.h.

◆ SEMC_NORCR1_AS

#define SEMC_NORCR1_AS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)

AS - Address setup time

Definition at line 34861 of file MIMXRT1052.h.

◆ SEMC_NORCR1_AS_MASK

#define SEMC_NORCR1_AS_MASK   (0xF00U)

Definition at line 34857 of file MIMXRT1052.h.

◆ SEMC_NORCR1_AS_SHIFT

#define SEMC_NORCR1_AS_SHIFT   (8U)

Definition at line 34858 of file MIMXRT1052.h.

◆ SEMC_NORCR1_CEH

#define SEMC_NORCR1_CEH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)

CEH - CE hold min time (CEH+1) cycle

Definition at line 34856 of file MIMXRT1052.h.

◆ SEMC_NORCR1_CEH_MASK

#define SEMC_NORCR1_CEH_MASK   (0xF0U)

Definition at line 34852 of file MIMXRT1052.h.

◆ SEMC_NORCR1_CEH_SHIFT

#define SEMC_NORCR1_CEH_SHIFT   (4U)

Definition at line 34853 of file MIMXRT1052.h.

◆ SEMC_NORCR1_CES

#define SEMC_NORCR1_CES (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)

CES - CE setup time cycle

Definition at line 34851 of file MIMXRT1052.h.

◆ SEMC_NORCR1_CES_MASK

#define SEMC_NORCR1_CES_MASK   (0xFU)

Definition at line 34847 of file MIMXRT1052.h.

◆ SEMC_NORCR1_CES_SHIFT

#define SEMC_NORCR1_CES_SHIFT   (0U)

Definition at line 34848 of file MIMXRT1052.h.

◆ SEMC_NORCR1_REH

#define SEMC_NORCR1_REH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)

REH - RE HIGH time (REH+1) cycle

Definition at line 34886 of file MIMXRT1052.h.

◆ SEMC_NORCR1_REH_MASK

#define SEMC_NORCR1_REH_MASK   (0xF0000000U)

Definition at line 34882 of file MIMXRT1052.h.

◆ SEMC_NORCR1_REH_SHIFT

#define SEMC_NORCR1_REH_SHIFT   (28U)

Definition at line 34883 of file MIMXRT1052.h.

◆ SEMC_NORCR1_REL

#define SEMC_NORCR1_REL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)

REL - RE LOW time (REL+1) cycle

Definition at line 34881 of file MIMXRT1052.h.

◆ SEMC_NORCR1_REL_MASK

#define SEMC_NORCR1_REL_MASK   (0xF000000U)

Definition at line 34877 of file MIMXRT1052.h.

◆ SEMC_NORCR1_REL_SHIFT

#define SEMC_NORCR1_REL_SHIFT   (24U)

Definition at line 34878 of file MIMXRT1052.h.

◆ SEMC_NORCR1_WEH

#define SEMC_NORCR1_WEH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)

WEH - WE HIGH time (WEH+1) cycle

Definition at line 34876 of file MIMXRT1052.h.

◆ SEMC_NORCR1_WEH_MASK

#define SEMC_NORCR1_WEH_MASK   (0xF00000U)

Definition at line 34872 of file MIMXRT1052.h.

◆ SEMC_NORCR1_WEH_SHIFT

#define SEMC_NORCR1_WEH_SHIFT   (20U)

Definition at line 34873 of file MIMXRT1052.h.

◆ SEMC_NORCR1_WEL

#define SEMC_NORCR1_WEL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)

WEL - WE LOW time (WEL+1) cycle

Definition at line 34871 of file MIMXRT1052.h.

◆ SEMC_NORCR1_WEL_MASK

#define SEMC_NORCR1_WEL_MASK   (0xF0000U)

Definition at line 34867 of file MIMXRT1052.h.

◆ SEMC_NORCR1_WEL_SHIFT

#define SEMC_NORCR1_WEL_SHIFT   (16U)

Definition at line 34868 of file MIMXRT1052.h.

◆ SEMC_NORCR2_AWDH

#define SEMC_NORCR2_AWDH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)

AWDH - Address to write data hold time cycle

Definition at line 34910 of file MIMXRT1052.h.

◆ SEMC_NORCR2_AWDH_MASK

#define SEMC_NORCR2_AWDH_MASK   (0xF000U)

Definition at line 34906 of file MIMXRT1052.h.

◆ SEMC_NORCR2_AWDH_SHIFT

#define SEMC_NORCR2_AWDH_SHIFT   (12U)

Definition at line 34907 of file MIMXRT1052.h.

◆ SEMC_NORCR2_CEITV

#define SEMC_NORCR2_CEITV (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)

CEITV - CE# interval min time

Definition at line 34925 of file MIMXRT1052.h.

◆ SEMC_NORCR2_CEITV_MASK

#define SEMC_NORCR2_CEITV_MASK   (0xF000000U)

Definition at line 34921 of file MIMXRT1052.h.

◆ SEMC_NORCR2_CEITV_SHIFT

#define SEMC_NORCR2_CEITV_SHIFT   (24U)

Definition at line 34922 of file MIMXRT1052.h.

◆ SEMC_NORCR2_LC

#define SEMC_NORCR2_LC (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)

LC - Latency count

Definition at line 34915 of file MIMXRT1052.h.

◆ SEMC_NORCR2_LC_MASK

#define SEMC_NORCR2_LC_MASK   (0xF0000U)

Definition at line 34911 of file MIMXRT1052.h.

◆ SEMC_NORCR2_LC_SHIFT

#define SEMC_NORCR2_LC_SHIFT   (16U)

Definition at line 34912 of file MIMXRT1052.h.

◆ SEMC_NORCR2_RD

#define SEMC_NORCR2_RD (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)

RD - Read cycle time

Definition at line 34920 of file MIMXRT1052.h.

◆ SEMC_NORCR2_RD_MASK

#define SEMC_NORCR2_RD_MASK   (0xF00000U)

Definition at line 34916 of file MIMXRT1052.h.

◆ SEMC_NORCR2_RD_SHIFT

#define SEMC_NORCR2_RD_SHIFT   (20U)

Definition at line 34917 of file MIMXRT1052.h.

◆ SEMC_NORCR2_TA

#define SEMC_NORCR2_TA (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)

TA - Turnaround time cycle

Definition at line 34905 of file MIMXRT1052.h.

◆ SEMC_NORCR2_TA_MASK

#define SEMC_NORCR2_TA_MASK   (0xF00U)

Definition at line 34901 of file MIMXRT1052.h.

◆ SEMC_NORCR2_TA_SHIFT

#define SEMC_NORCR2_TA_SHIFT   (8U)

Definition at line 34902 of file MIMXRT1052.h.

◆ SEMC_NORCR2_WDH

#define SEMC_NORCR2_WDH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)

WDH - Write Data hold time (WDH+1) cycle

Definition at line 34900 of file MIMXRT1052.h.

◆ SEMC_NORCR2_WDH_MASK

#define SEMC_NORCR2_WDH_MASK   (0xF0U)

Definition at line 34896 of file MIMXRT1052.h.

◆ SEMC_NORCR2_WDH_SHIFT

#define SEMC_NORCR2_WDH_SHIFT   (4U)

Definition at line 34897 of file MIMXRT1052.h.

◆ SEMC_NORCR2_WDS

#define SEMC_NORCR2_WDS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)

WDS - Write Data setup time (WDS+1) cycle

Definition at line 34895 of file MIMXRT1052.h.

◆ SEMC_NORCR2_WDS_MASK

#define SEMC_NORCR2_WDS_MASK   (0xFU)

Definition at line 34891 of file MIMXRT1052.h.

◆ SEMC_NORCR2_WDS_SHIFT

#define SEMC_NORCR2_WDS_SHIFT   (0U)

Definition at line 34892 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_BL

#define SEMC_SDRAMCR0_BL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..8 0b101..8 0b110..8 0b111..8

Definition at line 34524 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_BL_MASK

#define SEMC_SDRAMCR0_BL_MASK   (0x70U)

Definition at line 34512 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_BL_SHIFT

#define SEMC_SDRAMCR0_BL_SHIFT   (4U)

Definition at line 34513 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_CL

#define SEMC_SDRAMCR0_CL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)

CL - CAS Latency 0b00..1 0b01..1 0b10..2 0b11..3

Definition at line 34542 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_CL_MASK

#define SEMC_SDRAMCR0_CL_MASK   (0xC00U)

Definition at line 34534 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_CL_SHIFT

#define SEMC_SDRAMCR0_CL_SHIFT   (10U)

Definition at line 34535 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_COL

#define SEMC_SDRAMCR0_COL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)

COL - Column address bit number 0b00..12 bit 0b01..11 bit 0b10..10 bit 0b11..9 bit

Definition at line 34533 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_COL_MASK

#define SEMC_SDRAMCR0_COL_MASK   (0x300U)

Definition at line 34525 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_COL_SHIFT

#define SEMC_SDRAMCR0_COL_SHIFT   (8U)

Definition at line 34526 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_PS

#define SEMC_SDRAMCR0_PS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 34511 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_PS_MASK

#define SEMC_SDRAMCR0_PS_MASK   (0x1U)

Definition at line 34505 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR0_PS_SHIFT

#define SEMC_SDRAMCR0_PS_SHIFT   (0U)

Definition at line 34506 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_ACT2PRE

#define SEMC_SDRAMCR1_ACT2PRE (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)

ACT2PRE - ACT to Precharge minimum time

Definition at line 34576 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_ACT2PRE_MASK

#define SEMC_SDRAMCR1_ACT2PRE_MASK   (0xF00000U)

Definition at line 34572 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_ACT2PRE_SHIFT

#define SEMC_SDRAMCR1_ACT2PRE_SHIFT   (20U)

Definition at line 34573 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_ACT2RW

#define SEMC_SDRAMCR1_ACT2RW (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)

ACT2RW - ACT to Read/Write wait time

Definition at line 34556 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_ACT2RW_MASK

#define SEMC_SDRAMCR1_ACT2RW_MASK   (0xF0U)

Definition at line 34552 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_ACT2RW_SHIFT

#define SEMC_SDRAMCR1_ACT2RW_SHIFT   (4U)

Definition at line 34553 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_CKEOFF

#define SEMC_SDRAMCR1_CKEOFF (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)

CKEOFF - CKE OFF minimum time

Definition at line 34571 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_CKEOFF_MASK

#define SEMC_SDRAMCR1_CKEOFF_MASK   (0xF0000U)

Definition at line 34567 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_CKEOFF_SHIFT

#define SEMC_SDRAMCR1_CKEOFF_SHIFT   (16U)

Definition at line 34568 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_PRE2ACT

#define SEMC_SDRAMCR1_PRE2ACT (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)

PRE2ACT - PRECHARGE to ACT/Refresh wait time

Definition at line 34551 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_PRE2ACT_MASK

#define SEMC_SDRAMCR1_PRE2ACT_MASK   (0xFU)

Definition at line 34547 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_PRE2ACT_SHIFT

#define SEMC_SDRAMCR1_PRE2ACT_SHIFT   (0U)

Definition at line 34548 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_RFRC

#define SEMC_SDRAMCR1_RFRC (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)

RFRC - Refresh recovery time

Definition at line 34561 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_RFRC_MASK

#define SEMC_SDRAMCR1_RFRC_MASK   (0x1F00U)

Definition at line 34557 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_RFRC_SHIFT

#define SEMC_SDRAMCR1_RFRC_SHIFT   (8U)

Definition at line 34558 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_WRC

#define SEMC_SDRAMCR1_WRC (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)

WRC - Write recovery time

Definition at line 34566 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_WRC_MASK

#define SEMC_SDRAMCR1_WRC_MASK   (0xE000U)

Definition at line 34562 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR1_WRC_SHIFT

#define SEMC_SDRAMCR1_WRC_SHIFT   (13U)

Definition at line 34563 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_ACT2ACT

#define SEMC_SDRAMCR2_ACT2ACT (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)

ACT2ACT - ACT to ACT wait time

Definition at line 34595 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_ACT2ACT_MASK

#define SEMC_SDRAMCR2_ACT2ACT_MASK   (0xFF0000U)

Definition at line 34591 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_ACT2ACT_SHIFT

#define SEMC_SDRAMCR2_ACT2ACT_SHIFT   (16U)

Definition at line 34592 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_ITO

#define SEMC_SDRAMCR2_ITO (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)

ITO - SDRAM Idle timeout 0b00000000..IDLE timeout period is 256*Prescale period. 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.

Definition at line 34602 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_ITO_MASK

#define SEMC_SDRAMCR2_ITO_MASK   (0xFF000000U)

Definition at line 34596 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_ITO_SHIFT

#define SEMC_SDRAMCR2_ITO_SHIFT   (24U)

Definition at line 34597 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_REF2REF

#define SEMC_SDRAMCR2_REF2REF (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)

REF2REF - Refresh to Refresh wait time

Definition at line 34590 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_REF2REF_MASK

#define SEMC_SDRAMCR2_REF2REF_MASK   (0xFF00U)

Definition at line 34586 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_REF2REF_SHIFT

#define SEMC_SDRAMCR2_REF2REF_SHIFT   (8U)

Definition at line 34587 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_SRRC

#define SEMC_SDRAMCR2_SRRC (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)

SRRC - Self Refresh Recovery time

Definition at line 34585 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_SRRC_MASK

#define SEMC_SDRAMCR2_SRRC_MASK   (0xFFU)

Definition at line 34581 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR2_SRRC_SHIFT

#define SEMC_SDRAMCR2_SRRC_SHIFT   (0U)

Definition at line 34582 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_PRESCALE

#define SEMC_SDRAMCR3_PRESCALE (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)

PRESCALE - Prescaler timer period 0b00000000..256*16 cycle 0b00000001-0b11111111..PRESCALE*16 cycle

Definition at line 34631 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_PRESCALE_MASK

#define SEMC_SDRAMCR3_PRESCALE_MASK   (0xFF00U)

Definition at line 34625 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_PRESCALE_SHIFT

#define SEMC_SDRAMCR3_PRESCALE_SHIFT   (8U)

Definition at line 34626 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_REBL

#define SEMC_SDRAMCR3_REBL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)

REBL - Refresh burst length 0b000..1 0b001..2 0b010..3 0b011..4 0b100..5 0b101..6 0b110..7 0b111..8

Definition at line 34624 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_REBL_MASK

#define SEMC_SDRAMCR3_REBL_MASK   (0xEU)

Definition at line 34612 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_REBL_SHIFT

#define SEMC_SDRAMCR3_REBL_SHIFT   (1U)

Definition at line 34613 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_REN

#define SEMC_SDRAMCR3_REN (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)

REN - Refresh enable

Definition at line 34611 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_REN_MASK

#define SEMC_SDRAMCR3_REN_MASK   (0x1U)

Definition at line 34607 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_REN_SHIFT

#define SEMC_SDRAMCR3_REN_SHIFT   (0U)

Definition at line 34608 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_RT

#define SEMC_SDRAMCR3_RT (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)

RT - Refresh timer period 0b00000000..256*Prescaler period 0b00000001-0b11111111..RT*Prescaler period

Definition at line 34638 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_RT_MASK

#define SEMC_SDRAMCR3_RT_MASK   (0xFF0000U)

Definition at line 34632 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_RT_SHIFT

#define SEMC_SDRAMCR3_RT_SHIFT   (16U)

Definition at line 34633 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_UT

#define SEMC_SDRAMCR3_UT (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)

UT - Refresh urgent threshold 0b00000000..256*Prescaler period 0b00000001-0b11111111..UT*Prescaler period

Definition at line 34645 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_UT_MASK

#define SEMC_SDRAMCR3_UT_MASK   (0xFF000000U)

Definition at line 34639 of file MIMXRT1052.h.

◆ SEMC_SDRAMCR3_UT_SHIFT

#define SEMC_SDRAMCR3_UT_SHIFT   (24U)

Definition at line 34640 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_ADVP

#define SEMC_SRAMCR0_ADVP (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)

ADVP - ADV# polarity 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.

Definition at line 34965 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_ADVP_MASK

#define SEMC_SRAMCR0_ADVP_MASK   (0x400U)

Definition at line 34959 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_ADVP_SHIFT

#define SEMC_SRAMCR0_ADVP_SHIFT   (10U)

Definition at line 34960 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_AM

#define SEMC_SRAMCR0_AM (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)

AM - Address Mode 0b00..Address/Data MUX mode 0b01..Advanced Address/Data MUX mode 0b10..Address/Data non-MUX mode 0b11..Address/Data non-MUX mode

Definition at line 34958 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_AM_MASK

#define SEMC_SRAMCR0_AM_MASK   (0x300U)

Definition at line 34950 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_AM_SHIFT

#define SEMC_SRAMCR0_AM_SHIFT   (8U)

Definition at line 34951 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_BL

#define SEMC_SRAMCR0_BL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64

Definition at line 34949 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_BL_MASK

#define SEMC_SRAMCR0_BL_MASK   (0x70U)

Definition at line 34937 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_BL_SHIFT

#define SEMC_SRAMCR0_BL_SHIFT   (4U)

Definition at line 34938 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_COL

#define SEMC_SRAMCR0_COL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)

COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits

Definition at line 34986 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_COL_MASK

#define SEMC_SRAMCR0_COL_MASK   (0xF000U)

Definition at line 34966 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_COL_SHIFT

#define SEMC_SRAMCR0_COL_SHIFT   (12U)

Definition at line 34967 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_PS

#define SEMC_SRAMCR0_PS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 34936 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_PS_MASK

#define SEMC_SRAMCR0_PS_MASK   (0x1U)

Definition at line 34930 of file MIMXRT1052.h.

◆ SEMC_SRAMCR0_PS_SHIFT

#define SEMC_SRAMCR0_PS_SHIFT   (0U)

Definition at line 34931 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_AH

#define SEMC_SRAMCR1_AH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)

AH - Address hold time

Definition at line 35010 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_AH_MASK

#define SEMC_SRAMCR1_AH_MASK   (0xF000U)

Definition at line 35006 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_AH_SHIFT

#define SEMC_SRAMCR1_AH_SHIFT   (12U)

Definition at line 35007 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_AS

#define SEMC_SRAMCR1_AS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)

AS - Address setup time

Definition at line 35005 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_AS_MASK

#define SEMC_SRAMCR1_AS_MASK   (0xF00U)

Definition at line 35001 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_AS_SHIFT

#define SEMC_SRAMCR1_AS_SHIFT   (8U)

Definition at line 35002 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_CEH

#define SEMC_SRAMCR1_CEH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)

CEH - CE hold min time (CEH+1) cycle

Definition at line 35000 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_CEH_MASK

#define SEMC_SRAMCR1_CEH_MASK   (0xF0U)

Definition at line 34996 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_CEH_SHIFT

#define SEMC_SRAMCR1_CEH_SHIFT   (4U)

Definition at line 34997 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_CES

#define SEMC_SRAMCR1_CES (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)

CES - CE setup time cycle

Definition at line 34995 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_CES_MASK

#define SEMC_SRAMCR1_CES_MASK   (0xFU)

Definition at line 34991 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_CES_SHIFT

#define SEMC_SRAMCR1_CES_SHIFT   (0U)

Definition at line 34992 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_REH

#define SEMC_SRAMCR1_REH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)

REH - RE HIGH time (REH+1) cycle

Definition at line 35030 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_REH_MASK

#define SEMC_SRAMCR1_REH_MASK   (0xF0000000U)

Definition at line 35026 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_REH_SHIFT

#define SEMC_SRAMCR1_REH_SHIFT   (28U)

Definition at line 35027 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_REL

#define SEMC_SRAMCR1_REL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)

REL - RE LOW time (REL+1) cycle

Definition at line 35025 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_REL_MASK

#define SEMC_SRAMCR1_REL_MASK   (0xF000000U)

Definition at line 35021 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_REL_SHIFT

#define SEMC_SRAMCR1_REL_SHIFT   (24U)

Definition at line 35022 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_WEH

#define SEMC_SRAMCR1_WEH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)

WEH - WE HIGH time (WEH+1) cycle

Definition at line 35020 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_WEH_MASK

#define SEMC_SRAMCR1_WEH_MASK   (0xF00000U)

Definition at line 35016 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_WEH_SHIFT

#define SEMC_SRAMCR1_WEH_SHIFT   (20U)

Definition at line 35017 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_WEL

#define SEMC_SRAMCR1_WEL (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)

WEL - WE LOW time (WEL+1) cycle

Definition at line 35015 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_WEL_MASK

#define SEMC_SRAMCR1_WEL_MASK   (0xF0000U)

Definition at line 35011 of file MIMXRT1052.h.

◆ SEMC_SRAMCR1_WEL_SHIFT

#define SEMC_SRAMCR1_WEL_SHIFT   (16U)

Definition at line 35012 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_AWDH

#define SEMC_SRAMCR2_AWDH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)

AWDH - Address to write data hold time cycle

Definition at line 35054 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_AWDH_MASK

#define SEMC_SRAMCR2_AWDH_MASK   (0xF000U)

Definition at line 35050 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_AWDH_SHIFT

#define SEMC_SRAMCR2_AWDH_SHIFT   (12U)

Definition at line 35051 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_CEITV

#define SEMC_SRAMCR2_CEITV (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)

CEITV - CE# interval min time

Definition at line 35069 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_CEITV_MASK

#define SEMC_SRAMCR2_CEITV_MASK   (0xF000000U)

Definition at line 35065 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_CEITV_SHIFT

#define SEMC_SRAMCR2_CEITV_SHIFT   (24U)

Definition at line 35066 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_LC

#define SEMC_SRAMCR2_LC (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)

LC - Latency count

Definition at line 35059 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_LC_MASK

#define SEMC_SRAMCR2_LC_MASK   (0xF0000U)

Definition at line 35055 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_LC_SHIFT

#define SEMC_SRAMCR2_LC_SHIFT   (16U)

Definition at line 35056 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_RD

#define SEMC_SRAMCR2_RD (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)

RD - Read cycle time

Definition at line 35064 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_RD_MASK

#define SEMC_SRAMCR2_RD_MASK   (0xF00000U)

Definition at line 35060 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_RD_SHIFT

#define SEMC_SRAMCR2_RD_SHIFT   (20U)

Definition at line 35061 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_TA

#define SEMC_SRAMCR2_TA (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)

TA - Turnaround time cycle

Definition at line 35049 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_TA_MASK

#define SEMC_SRAMCR2_TA_MASK   (0xF00U)

Definition at line 35045 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_TA_SHIFT

#define SEMC_SRAMCR2_TA_SHIFT   (8U)

Definition at line 35046 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_WDH

#define SEMC_SRAMCR2_WDH (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)

WDH - Write Data hold time (WDH+1) cycle

Definition at line 35044 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_WDH_MASK

#define SEMC_SRAMCR2_WDH_MASK   (0xF0U)

Definition at line 35040 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_WDH_SHIFT

#define SEMC_SRAMCR2_WDH_SHIFT   (4U)

Definition at line 35041 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_WDS

#define SEMC_SRAMCR2_WDS (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)

WDS - Write Data setup time (WDS+1) cycle

Definition at line 35039 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_WDS_MASK

#define SEMC_SRAMCR2_WDS_MASK   (0xFU)

Definition at line 35035 of file MIMXRT1052.h.

◆ SEMC_SRAMCR2_WDS_SHIFT

#define SEMC_SRAMCR2_WDS_SHIFT   (0U)

Definition at line 35036 of file MIMXRT1052.h.

◆ SEMC_STS0_IDLE

#define SEMC_STS0_IDLE (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)

IDLE - Indicating whether SEMC is in IDLE state.

Definition at line 35256 of file MIMXRT1052.h.

◆ SEMC_STS0_IDLE_MASK

#define SEMC_STS0_IDLE_MASK   (0x1U)

Definition at line 35252 of file MIMXRT1052.h.

◆ SEMC_STS0_IDLE_SHIFT

#define SEMC_STS0_IDLE_SHIFT   (0U)

Definition at line 35253 of file MIMXRT1052.h.

◆ SEMC_STS0_NARDY

#define SEMC_STS0_NARDY (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)

NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready

Definition at line 35263 of file MIMXRT1052.h.

◆ SEMC_STS0_NARDY_MASK

#define SEMC_STS0_NARDY_MASK   (0x2U)

Definition at line 35257 of file MIMXRT1052.h.

◆ SEMC_STS0_NARDY_SHIFT

#define SEMC_STS0_NARDY_SHIFT   (1U)

Definition at line 35258 of file MIMXRT1052.h.

◆ SEMC_STS12_NDADDR

#define SEMC_STS12_NDADDR (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)

NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).

Definition at line 35283 of file MIMXRT1052.h.

◆ SEMC_STS12_NDADDR_MASK

#define SEMC_STS12_NDADDR_MASK   (0xFFFFFFFFU)

Definition at line 35279 of file MIMXRT1052.h.

◆ SEMC_STS12_NDADDR_SHIFT

#define SEMC_STS12_NDADDR_SHIFT   (0U)

Definition at line 35280 of file MIMXRT1052.h.

◆ SEMC_STS2_NDWRPEND

#define SEMC_STS2_NDWRPEND (   x)    (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)

NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending

Definition at line 35274 of file MIMXRT1052.h.

◆ SEMC_STS2_NDWRPEND_MASK

#define SEMC_STS2_NDWRPEND_MASK   (0x8U)

Definition at line 35268 of file MIMXRT1052.h.

◆ SEMC_STS2_NDWRPEND_SHIFT

#define SEMC_STS2_NDWRPEND_SHIFT   (3U)

Definition at line 35269 of file MIMXRT1052.h.


picovoice_driver
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autogenerated on Fri Apr 1 2022 02:15:10