Macros | |
| #define | I2S_RDR_COUNT (4U) |
| #define | I2S_RFR_COUNT (4U) |
| #define | I2S_TDR_COUNT (4U) |
| #define | I2S_TFR_COUNT (4U) |
VERID - Version ID Register | |
| #define | I2S_VERID_FEATURE_MASK (0xFFFFU) |
| #define | I2S_VERID_FEATURE_SHIFT (0U) |
| #define | I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) |
| #define | I2S_VERID_MINOR_MASK (0xFF0000U) |
| #define | I2S_VERID_MINOR_SHIFT (16U) |
| #define | I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) |
| #define | I2S_VERID_MAJOR_MASK (0xFF000000U) |
| #define | I2S_VERID_MAJOR_SHIFT (24U) |
| #define | I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) |
PARAM - Parameter Register | |
| #define | I2S_PARAM_DATALINE_MASK (0xFU) |
| #define | I2S_PARAM_DATALINE_SHIFT (0U) |
| #define | I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) |
| #define | I2S_PARAM_FIFO_MASK (0xF00U) |
| #define | I2S_PARAM_FIFO_SHIFT (8U) |
| #define | I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) |
| #define | I2S_PARAM_FRAME_MASK (0xF0000U) |
| #define | I2S_PARAM_FRAME_SHIFT (16U) |
| #define | I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) |
TCSR - SAI Transmit Control Register | |
| #define | I2S_TCSR_FRDE_MASK (0x1U) |
| #define | I2S_TCSR_FRDE_SHIFT (0U) |
| #define | I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) |
| #define | I2S_TCSR_FWDE_MASK (0x2U) |
| #define | I2S_TCSR_FWDE_SHIFT (1U) |
| #define | I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) |
| #define | I2S_TCSR_FRIE_MASK (0x100U) |
| #define | I2S_TCSR_FRIE_SHIFT (8U) |
| #define | I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) |
| #define | I2S_TCSR_FWIE_MASK (0x200U) |
| #define | I2S_TCSR_FWIE_SHIFT (9U) |
| #define | I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) |
| #define | I2S_TCSR_FEIE_MASK (0x400U) |
| #define | I2S_TCSR_FEIE_SHIFT (10U) |
| #define | I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) |
| #define | I2S_TCSR_SEIE_MASK (0x800U) |
| #define | I2S_TCSR_SEIE_SHIFT (11U) |
| #define | I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) |
| #define | I2S_TCSR_WSIE_MASK (0x1000U) |
| #define | I2S_TCSR_WSIE_SHIFT (12U) |
| #define | I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) |
| #define | I2S_TCSR_FRF_MASK (0x10000U) |
| #define | I2S_TCSR_FRF_SHIFT (16U) |
| #define | I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) |
| #define | I2S_TCSR_FWF_MASK (0x20000U) |
| #define | I2S_TCSR_FWF_SHIFT (17U) |
| #define | I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) |
| #define | I2S_TCSR_FEF_MASK (0x40000U) |
| #define | I2S_TCSR_FEF_SHIFT (18U) |
| #define | I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) |
| #define | I2S_TCSR_SEF_MASK (0x80000U) |
| #define | I2S_TCSR_SEF_SHIFT (19U) |
| #define | I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) |
| #define | I2S_TCSR_WSF_MASK (0x100000U) |
| #define | I2S_TCSR_WSF_SHIFT (20U) |
| #define | I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) |
| #define | I2S_TCSR_SR_MASK (0x1000000U) |
| #define | I2S_TCSR_SR_SHIFT (24U) |
| #define | I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) |
| #define | I2S_TCSR_FR_MASK (0x2000000U) |
| #define | I2S_TCSR_FR_SHIFT (25U) |
| #define | I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) |
| #define | I2S_TCSR_BCE_MASK (0x10000000U) |
| #define | I2S_TCSR_BCE_SHIFT (28U) |
| #define | I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) |
| #define | I2S_TCSR_DBGE_MASK (0x20000000U) |
| #define | I2S_TCSR_DBGE_SHIFT (29U) |
| #define | I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) |
| #define | I2S_TCSR_STOPE_MASK (0x40000000U) |
| #define | I2S_TCSR_STOPE_SHIFT (30U) |
| #define | I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) |
| #define | I2S_TCSR_TE_MASK (0x80000000U) |
| #define | I2S_TCSR_TE_SHIFT (31U) |
| #define | I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) |
TCR1 - SAI Transmit Configuration 1 Register | |
| #define | I2S_TCR1_TFW_MASK (0x1FU) |
| #define | I2S_TCR1_TFW_SHIFT (0U) |
| #define | I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) |
TCR2 - SAI Transmit Configuration 2 Register | |
| #define | I2S_TCR2_DIV_MASK (0xFFU) |
| #define | I2S_TCR2_DIV_SHIFT (0U) |
| #define | I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) |
| #define | I2S_TCR2_BCD_MASK (0x1000000U) |
| #define | I2S_TCR2_BCD_SHIFT (24U) |
| #define | I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) |
| #define | I2S_TCR2_BCP_MASK (0x2000000U) |
| #define | I2S_TCR2_BCP_SHIFT (25U) |
| #define | I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) |
| #define | I2S_TCR2_MSEL_MASK (0xC000000U) |
| #define | I2S_TCR2_MSEL_SHIFT (26U) |
| #define | I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) |
| #define | I2S_TCR2_BCI_MASK (0x10000000U) |
| #define | I2S_TCR2_BCI_SHIFT (28U) |
| #define | I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) |
| #define | I2S_TCR2_BCS_MASK (0x20000000U) |
| #define | I2S_TCR2_BCS_SHIFT (29U) |
| #define | I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) |
| #define | I2S_TCR2_SYNC_MASK (0xC0000000U) |
| #define | I2S_TCR2_SYNC_SHIFT (30U) |
| #define | I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) |
TCR3 - SAI Transmit Configuration 3 Register | |
| #define | I2S_TCR3_WDFL_MASK (0x1FU) |
| #define | I2S_TCR3_WDFL_SHIFT (0U) |
| #define | I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) |
| #define | I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
| #define | I2S_TCR3_TCE_SHIFT (16U) |
| #define | I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
| #define | I2S_TCR3_CFR_MASK (0xF000000U) |
| #define | I2S_TCR3_CFR_SHIFT (24U) |
| #define | I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) |
TCR4 - SAI Transmit Configuration 4 Register | |
| #define | I2S_TCR4_FSD_MASK (0x1U) |
| #define | I2S_TCR4_FSD_SHIFT (0U) |
| #define | I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) |
| #define | I2S_TCR4_FSP_MASK (0x2U) |
| #define | I2S_TCR4_FSP_SHIFT (1U) |
| #define | I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) |
| #define | I2S_TCR4_ONDEM_MASK (0x4U) |
| #define | I2S_TCR4_ONDEM_SHIFT (2U) |
| #define | I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) |
| #define | I2S_TCR4_FSE_MASK (0x8U) |
| #define | I2S_TCR4_FSE_SHIFT (3U) |
| #define | I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) |
| #define | I2S_TCR4_MF_MASK (0x10U) |
| #define | I2S_TCR4_MF_SHIFT (4U) |
| #define | I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) |
| #define | I2S_TCR4_CHMOD_MASK (0x20U) |
| #define | I2S_TCR4_CHMOD_SHIFT (5U) |
| #define | I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) |
| #define | I2S_TCR4_SYWD_MASK (0x1F00U) |
| #define | I2S_TCR4_SYWD_SHIFT (8U) |
| #define | I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) |
| #define | I2S_TCR4_FRSZ_MASK (0x1F0000U) |
| #define | I2S_TCR4_FRSZ_SHIFT (16U) |
| #define | I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) |
| #define | I2S_TCR4_FPACK_MASK (0x3000000U) |
| #define | I2S_TCR4_FPACK_SHIFT (24U) |
| #define | I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) |
| #define | I2S_TCR4_FCOMB_MASK (0xC000000U) |
| #define | I2S_TCR4_FCOMB_SHIFT (26U) |
| #define | I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) |
| #define | I2S_TCR4_FCONT_MASK (0x10000000U) |
| #define | I2S_TCR4_FCONT_SHIFT (28U) |
| #define | I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) |
TCR5 - SAI Transmit Configuration 5 Register | |
| #define | I2S_TCR5_FBT_MASK (0x1F00U) |
| #define | I2S_TCR5_FBT_SHIFT (8U) |
| #define | I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) |
| #define | I2S_TCR5_W0W_MASK (0x1F0000U) |
| #define | I2S_TCR5_W0W_SHIFT (16U) |
| #define | I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) |
| #define | I2S_TCR5_WNW_MASK (0x1F000000U) |
| #define | I2S_TCR5_WNW_SHIFT (24U) |
| #define | I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) |
TDR - SAI Transmit Data Register | |
| #define | I2S_TDR_TDR_MASK (0xFFFFFFFFU) |
| #define | I2S_TDR_TDR_SHIFT (0U) |
| #define | I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) |
TFR - SAI Transmit FIFO Register | |
| #define | I2S_TFR_RFP_MASK (0x3FU) |
| #define | I2S_TFR_RFP_SHIFT (0U) |
| #define | I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) |
| #define | I2S_TFR_WFP_MASK (0x3F0000U) |
| #define | I2S_TFR_WFP_SHIFT (16U) |
| #define | I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) |
| #define | I2S_TFR_WCP_MASK (0x80000000U) |
| #define | I2S_TFR_WCP_SHIFT (31U) |
| #define | I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) |
TMR - SAI Transmit Mask Register | |
| #define | I2S_TMR_TWM_MASK (0xFFFFFFFFU) |
| #define | I2S_TMR_TWM_SHIFT (0U) |
| #define | I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) |
RCSR - SAI Receive Control Register | |
| #define | I2S_RCSR_FRDE_MASK (0x1U) |
| #define | I2S_RCSR_FRDE_SHIFT (0U) |
| #define | I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) |
| #define | I2S_RCSR_FWDE_MASK (0x2U) |
| #define | I2S_RCSR_FWDE_SHIFT (1U) |
| #define | I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) |
| #define | I2S_RCSR_FRIE_MASK (0x100U) |
| #define | I2S_RCSR_FRIE_SHIFT (8U) |
| #define | I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) |
| #define | I2S_RCSR_FWIE_MASK (0x200U) |
| #define | I2S_RCSR_FWIE_SHIFT (9U) |
| #define | I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) |
| #define | I2S_RCSR_FEIE_MASK (0x400U) |
| #define | I2S_RCSR_FEIE_SHIFT (10U) |
| #define | I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) |
| #define | I2S_RCSR_SEIE_MASK (0x800U) |
| #define | I2S_RCSR_SEIE_SHIFT (11U) |
| #define | I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) |
| #define | I2S_RCSR_WSIE_MASK (0x1000U) |
| #define | I2S_RCSR_WSIE_SHIFT (12U) |
| #define | I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) |
| #define | I2S_RCSR_FRF_MASK (0x10000U) |
| #define | I2S_RCSR_FRF_SHIFT (16U) |
| #define | I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) |
| #define | I2S_RCSR_FWF_MASK (0x20000U) |
| #define | I2S_RCSR_FWF_SHIFT (17U) |
| #define | I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) |
| #define | I2S_RCSR_FEF_MASK (0x40000U) |
| #define | I2S_RCSR_FEF_SHIFT (18U) |
| #define | I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) |
| #define | I2S_RCSR_SEF_MASK (0x80000U) |
| #define | I2S_RCSR_SEF_SHIFT (19U) |
| #define | I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) |
| #define | I2S_RCSR_WSF_MASK (0x100000U) |
| #define | I2S_RCSR_WSF_SHIFT (20U) |
| #define | I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) |
| #define | I2S_RCSR_SR_MASK (0x1000000U) |
| #define | I2S_RCSR_SR_SHIFT (24U) |
| #define | I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) |
| #define | I2S_RCSR_FR_MASK (0x2000000U) |
| #define | I2S_RCSR_FR_SHIFT (25U) |
| #define | I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) |
| #define | I2S_RCSR_BCE_MASK (0x10000000U) |
| #define | I2S_RCSR_BCE_SHIFT (28U) |
| #define | I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) |
| #define | I2S_RCSR_DBGE_MASK (0x20000000U) |
| #define | I2S_RCSR_DBGE_SHIFT (29U) |
| #define | I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) |
| #define | I2S_RCSR_STOPE_MASK (0x40000000U) |
| #define | I2S_RCSR_STOPE_SHIFT (30U) |
| #define | I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) |
| #define | I2S_RCSR_RE_MASK (0x80000000U) |
| #define | I2S_RCSR_RE_SHIFT (31U) |
| #define | I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) |
RCR1 - SAI Receive Configuration 1 Register | |
| #define | I2S_RCR1_RFW_MASK (0x1FU) |
| #define | I2S_RCR1_RFW_SHIFT (0U) |
| #define | I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) |
RCR2 - SAI Receive Configuration 2 Register | |
| #define | I2S_RCR2_DIV_MASK (0xFFU) |
| #define | I2S_RCR2_DIV_SHIFT (0U) |
| #define | I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) |
| #define | I2S_RCR2_BCD_MASK (0x1000000U) |
| #define | I2S_RCR2_BCD_SHIFT (24U) |
| #define | I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) |
| #define | I2S_RCR2_BCP_MASK (0x2000000U) |
| #define | I2S_RCR2_BCP_SHIFT (25U) |
| #define | I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) |
| #define | I2S_RCR2_MSEL_MASK (0xC000000U) |
| #define | I2S_RCR2_MSEL_SHIFT (26U) |
| #define | I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) |
| #define | I2S_RCR2_BCI_MASK (0x10000000U) |
| #define | I2S_RCR2_BCI_SHIFT (28U) |
| #define | I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) |
| #define | I2S_RCR2_BCS_MASK (0x20000000U) |
| #define | I2S_RCR2_BCS_SHIFT (29U) |
| #define | I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) |
| #define | I2S_RCR2_SYNC_MASK (0xC0000000U) |
| #define | I2S_RCR2_SYNC_SHIFT (30U) |
| #define | I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) |
RCR3 - SAI Receive Configuration 3 Register | |
| #define | I2S_RCR3_WDFL_MASK (0x1FU) |
| #define | I2S_RCR3_WDFL_SHIFT (0U) |
| #define | I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) |
| #define | I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
| #define | I2S_RCR3_RCE_SHIFT (16U) |
| #define | I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
| #define | I2S_RCR3_CFR_MASK (0xF000000U) |
| #define | I2S_RCR3_CFR_SHIFT (24U) |
| #define | I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) |
RCR4 - SAI Receive Configuration 4 Register | |
| #define | I2S_RCR4_FSD_MASK (0x1U) |
| #define | I2S_RCR4_FSD_SHIFT (0U) |
| #define | I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) |
| #define | I2S_RCR4_FSP_MASK (0x2U) |
| #define | I2S_RCR4_FSP_SHIFT (1U) |
| #define | I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) |
| #define | I2S_RCR4_ONDEM_MASK (0x4U) |
| #define | I2S_RCR4_ONDEM_SHIFT (2U) |
| #define | I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) |
| #define | I2S_RCR4_FSE_MASK (0x8U) |
| #define | I2S_RCR4_FSE_SHIFT (3U) |
| #define | I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) |
| #define | I2S_RCR4_MF_MASK (0x10U) |
| #define | I2S_RCR4_MF_SHIFT (4U) |
| #define | I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) |
| #define | I2S_RCR4_SYWD_MASK (0x1F00U) |
| #define | I2S_RCR4_SYWD_SHIFT (8U) |
| #define | I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) |
| #define | I2S_RCR4_FRSZ_MASK (0x1F0000U) |
| #define | I2S_RCR4_FRSZ_SHIFT (16U) |
| #define | I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) |
| #define | I2S_RCR4_FPACK_MASK (0x3000000U) |
| #define | I2S_RCR4_FPACK_SHIFT (24U) |
| #define | I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) |
| #define | I2S_RCR4_FCOMB_MASK (0xC000000U) |
| #define | I2S_RCR4_FCOMB_SHIFT (26U) |
| #define | I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) |
| #define | I2S_RCR4_FCONT_MASK (0x10000000U) |
| #define | I2S_RCR4_FCONT_SHIFT (28U) |
| #define | I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) |
RCR5 - SAI Receive Configuration 5 Register | |
| #define | I2S_RCR5_FBT_MASK (0x1F00U) |
| #define | I2S_RCR5_FBT_SHIFT (8U) |
| #define | I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) |
| #define | I2S_RCR5_W0W_MASK (0x1F0000U) |
| #define | I2S_RCR5_W0W_SHIFT (16U) |
| #define | I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) |
| #define | I2S_RCR5_WNW_MASK (0x1F000000U) |
| #define | I2S_RCR5_WNW_SHIFT (24U) |
| #define | I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) |
RDR - SAI Receive Data Register | |
| #define | I2S_RDR_RDR_MASK (0xFFFFFFFFU) |
| #define | I2S_RDR_RDR_SHIFT (0U) |
| #define | I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) |
RFR - SAI Receive FIFO Register | |
| #define | I2S_RFR_RFP_MASK (0x3FU) |
| #define | I2S_RFR_RFP_SHIFT (0U) |
| #define | I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) |
| #define | I2S_RFR_RCP_MASK (0x8000U) |
| #define | I2S_RFR_RCP_SHIFT (15U) |
| #define | I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) |
| #define | I2S_RFR_WFP_MASK (0x3F0000U) |
| #define | I2S_RFR_WFP_SHIFT (16U) |
| #define | I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) |
RMR - SAI Receive Mask Register | |
| #define | I2S_RMR_RWM_MASK (0xFFFFFFFFU) |
| #define | I2S_RMR_RWM_SHIFT (0U) |
| #define | I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) |
Detailed Description
Macro Definition Documentation
◆ I2S_PARAM_DATALINE
| #define I2S_PARAM_DATALINE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) |
DATALINE - Number of Datalines
Definition at line 19930 of file MIMXRT1052.h.
◆ I2S_PARAM_DATALINE_MASK
| #define I2S_PARAM_DATALINE_MASK (0xFU) |
Definition at line 19926 of file MIMXRT1052.h.
◆ I2S_PARAM_DATALINE_SHIFT
| #define I2S_PARAM_DATALINE_SHIFT (0U) |
Definition at line 19927 of file MIMXRT1052.h.
◆ I2S_PARAM_FIFO
| #define I2S_PARAM_FIFO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) |
FIFO - FIFO Size
Definition at line 19935 of file MIMXRT1052.h.
◆ I2S_PARAM_FIFO_MASK
| #define I2S_PARAM_FIFO_MASK (0xF00U) |
Definition at line 19931 of file MIMXRT1052.h.
◆ I2S_PARAM_FIFO_SHIFT
| #define I2S_PARAM_FIFO_SHIFT (8U) |
Definition at line 19932 of file MIMXRT1052.h.
◆ I2S_PARAM_FRAME
| #define I2S_PARAM_FRAME | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) |
FRAME - Frame Size
Definition at line 19940 of file MIMXRT1052.h.
◆ I2S_PARAM_FRAME_MASK
| #define I2S_PARAM_FRAME_MASK (0xF0000U) |
Definition at line 19936 of file MIMXRT1052.h.
◆ I2S_PARAM_FRAME_SHIFT
| #define I2S_PARAM_FRAME_SHIFT (16U) |
Definition at line 19937 of file MIMXRT1052.h.
◆ I2S_RCR1_RFW
| #define I2S_RCR1_RFW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) |
RFW - Receive FIFO Watermark
Definition at line 20439 of file MIMXRT1052.h.
◆ I2S_RCR1_RFW_MASK
| #define I2S_RCR1_RFW_MASK (0x1FU) |
Definition at line 20435 of file MIMXRT1052.h.
◆ I2S_RCR1_RFW_SHIFT
| #define I2S_RCR1_RFW_SHIFT (0U) |
Definition at line 20436 of file MIMXRT1052.h.
◆ I2S_RCR2_BCD
| #define I2S_RCR2_BCD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) |
BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.
Definition at line 20455 of file MIMXRT1052.h.
◆ I2S_RCR2_BCD_MASK
| #define I2S_RCR2_BCD_MASK (0x1000000U) |
Definition at line 20449 of file MIMXRT1052.h.
◆ I2S_RCR2_BCD_SHIFT
| #define I2S_RCR2_BCD_SHIFT (24U) |
Definition at line 20450 of file MIMXRT1052.h.
◆ I2S_RCR2_BCI
| #define I2S_RCR2_BCI | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) |
BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.
Definition at line 20478 of file MIMXRT1052.h.
◆ I2S_RCR2_BCI_MASK
| #define I2S_RCR2_BCI_MASK (0x10000000U) |
Definition at line 20472 of file MIMXRT1052.h.
◆ I2S_RCR2_BCI_SHIFT
| #define I2S_RCR2_BCI_SHIFT (28U) |
Definition at line 20473 of file MIMXRT1052.h.
◆ I2S_RCR2_BCP
| #define I2S_RCR2_BCP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) |
BCP - Bit Clock Polarity 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
Definition at line 20462 of file MIMXRT1052.h.
◆ I2S_RCR2_BCP_MASK
| #define I2S_RCR2_BCP_MASK (0x2000000U) |
Definition at line 20456 of file MIMXRT1052.h.
◆ I2S_RCR2_BCP_SHIFT
| #define I2S_RCR2_BCP_SHIFT (25U) |
Definition at line 20457 of file MIMXRT1052.h.
◆ I2S_RCR2_BCS
| #define I2S_RCR2_BCS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) |
BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.
Definition at line 20485 of file MIMXRT1052.h.
◆ I2S_RCR2_BCS_MASK
| #define I2S_RCR2_BCS_MASK (0x20000000U) |
Definition at line 20479 of file MIMXRT1052.h.
◆ I2S_RCR2_BCS_SHIFT
| #define I2S_RCR2_BCS_SHIFT (29U) |
Definition at line 20480 of file MIMXRT1052.h.
◆ I2S_RCR2_DIV
| #define I2S_RCR2_DIV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) |
DIV - Bit Clock Divide
Definition at line 20448 of file MIMXRT1052.h.
◆ I2S_RCR2_DIV_MASK
| #define I2S_RCR2_DIV_MASK (0xFFU) |
Definition at line 20444 of file MIMXRT1052.h.
◆ I2S_RCR2_DIV_SHIFT
| #define I2S_RCR2_DIV_SHIFT (0U) |
Definition at line 20445 of file MIMXRT1052.h.
◆ I2S_RCR2_MSEL
| #define I2S_RCR2_MSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) |
MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.
Definition at line 20471 of file MIMXRT1052.h.
◆ I2S_RCR2_MSEL_MASK
| #define I2S_RCR2_MSEL_MASK (0xC000000U) |
Definition at line 20463 of file MIMXRT1052.h.
◆ I2S_RCR2_MSEL_SHIFT
| #define I2S_RCR2_MSEL_SHIFT (26U) |
Definition at line 20464 of file MIMXRT1052.h.
◆ I2S_RCR2_SYNC
| #define I2S_RCR2_SYNC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) |
SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with transmitter. 0b10..Reserved. 0b11..Reserved.
Definition at line 20494 of file MIMXRT1052.h.
◆ I2S_RCR2_SYNC_MASK
| #define I2S_RCR2_SYNC_MASK (0xC0000000U) |
Definition at line 20486 of file MIMXRT1052.h.
◆ I2S_RCR2_SYNC_SHIFT
| #define I2S_RCR2_SYNC_SHIFT (30U) |
Definition at line 20487 of file MIMXRT1052.h.
◆ I2S_RCR3_CFR
| #define I2S_RCR3_CFR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) |
CFR - Channel FIFO Reset
Definition at line 20513 of file MIMXRT1052.h.
◆ I2S_RCR3_CFR_MASK
| #define I2S_RCR3_CFR_MASK (0xF000000U) |
Definition at line 20509 of file MIMXRT1052.h.
◆ I2S_RCR3_CFR_SHIFT
| #define I2S_RCR3_CFR_SHIFT (24U) |
Definition at line 20510 of file MIMXRT1052.h.
◆ I2S_RCR3_RCE
| #define I2S_RCR3_RCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
RCE - Receive Channel Enable
Definition at line 20508 of file MIMXRT1052.h.
◆ I2S_RCR3_RCE_MASK
| #define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
Definition at line 20504 of file MIMXRT1052.h.
◆ I2S_RCR3_RCE_SHIFT
| #define I2S_RCR3_RCE_SHIFT (16U) |
Definition at line 20505 of file MIMXRT1052.h.
◆ I2S_RCR3_WDFL
| #define I2S_RCR3_WDFL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) |
WDFL - Word Flag Configuration
Definition at line 20503 of file MIMXRT1052.h.
◆ I2S_RCR3_WDFL_MASK
| #define I2S_RCR3_WDFL_MASK (0x1FU) |
Definition at line 20499 of file MIMXRT1052.h.
◆ I2S_RCR3_WDFL_SHIFT
| #define I2S_RCR3_WDFL_SHIFT (0U) |
Definition at line 20500 of file MIMXRT1052.h.
◆ I2S_RCR4_FCOMB
| #define I2S_RCR4_FCOMB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) |
FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). 0b10..FIFO combine mode enabled on FIFO reads (by software). 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
Definition at line 20580 of file MIMXRT1052.h.
◆ I2S_RCR4_FCOMB_MASK
| #define I2S_RCR4_FCOMB_MASK (0xC000000U) |
Definition at line 20572 of file MIMXRT1052.h.
◆ I2S_RCR4_FCOMB_SHIFT
| #define I2S_RCR4_FCOMB_SHIFT (26U) |
Definition at line 20573 of file MIMXRT1052.h.
◆ I2S_RCR4_FCONT
| #define I2S_RCR4_FCONT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) |
FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
Definition at line 20587 of file MIMXRT1052.h.
◆ I2S_RCR4_FCONT_MASK
| #define I2S_RCR4_FCONT_MASK (0x10000000U) |
Definition at line 20581 of file MIMXRT1052.h.
◆ I2S_RCR4_FCONT_SHIFT
| #define I2S_RCR4_FCONT_SHIFT (28U) |
Definition at line 20582 of file MIMXRT1052.h.
◆ I2S_RCR4_FPACK
| #define I2S_RCR4_FPACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) |
FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved. 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled
Definition at line 20571 of file MIMXRT1052.h.
◆ I2S_RCR4_FPACK_MASK
| #define I2S_RCR4_FPACK_MASK (0x3000000U) |
Definition at line 20563 of file MIMXRT1052.h.
◆ I2S_RCR4_FPACK_SHIFT
| #define I2S_RCR4_FPACK_SHIFT (24U) |
Definition at line 20564 of file MIMXRT1052.h.
◆ I2S_RCR4_FRSZ
| #define I2S_RCR4_FRSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) |
FRSZ - Frame Size
Definition at line 20562 of file MIMXRT1052.h.
◆ I2S_RCR4_FRSZ_MASK
| #define I2S_RCR4_FRSZ_MASK (0x1F0000U) |
Definition at line 20558 of file MIMXRT1052.h.
◆ I2S_RCR4_FRSZ_SHIFT
| #define I2S_RCR4_FRSZ_SHIFT (16U) |
Definition at line 20559 of file MIMXRT1052.h.
◆ I2S_RCR4_FSD
| #define I2S_RCR4_FSD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) |
FSD - Frame Sync Direction 0b0..Frame Sync is generated externally in Slave mode. 0b1..Frame Sync is generated internally in Master mode.
Definition at line 20524 of file MIMXRT1052.h.
◆ I2S_RCR4_FSD_MASK
| #define I2S_RCR4_FSD_MASK (0x1U) |
Definition at line 20518 of file MIMXRT1052.h.
◆ I2S_RCR4_FSD_SHIFT
| #define I2S_RCR4_FSD_SHIFT (0U) |
Definition at line 20519 of file MIMXRT1052.h.
◆ I2S_RCR4_FSE
| #define I2S_RCR4_FSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) |
FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.
Definition at line 20545 of file MIMXRT1052.h.
◆ I2S_RCR4_FSE_MASK
| #define I2S_RCR4_FSE_MASK (0x8U) |
Definition at line 20539 of file MIMXRT1052.h.
◆ I2S_RCR4_FSE_SHIFT
| #define I2S_RCR4_FSE_SHIFT (3U) |
Definition at line 20540 of file MIMXRT1052.h.
◆ I2S_RCR4_FSP
| #define I2S_RCR4_FSP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) |
FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.
Definition at line 20531 of file MIMXRT1052.h.
◆ I2S_RCR4_FSP_MASK
| #define I2S_RCR4_FSP_MASK (0x2U) |
Definition at line 20525 of file MIMXRT1052.h.
◆ I2S_RCR4_FSP_SHIFT
| #define I2S_RCR4_FSP_SHIFT (1U) |
Definition at line 20526 of file MIMXRT1052.h.
◆ I2S_RCR4_MF
| #define I2S_RCR4_MF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) |
MF - MSB First 0b0..LSB is received first. 0b1..MSB is received first.
Definition at line 20552 of file MIMXRT1052.h.
◆ I2S_RCR4_MF_MASK
| #define I2S_RCR4_MF_MASK (0x10U) |
Definition at line 20546 of file MIMXRT1052.h.
◆ I2S_RCR4_MF_SHIFT
| #define I2S_RCR4_MF_SHIFT (4U) |
Definition at line 20547 of file MIMXRT1052.h.
◆ I2S_RCR4_ONDEM
| #define I2S_RCR4_ONDEM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) |
ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
Definition at line 20538 of file MIMXRT1052.h.
◆ I2S_RCR4_ONDEM_MASK
| #define I2S_RCR4_ONDEM_MASK (0x4U) |
Definition at line 20532 of file MIMXRT1052.h.
◆ I2S_RCR4_ONDEM_SHIFT
| #define I2S_RCR4_ONDEM_SHIFT (2U) |
Definition at line 20533 of file MIMXRT1052.h.
◆ I2S_RCR4_SYWD
| #define I2S_RCR4_SYWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) |
SYWD - Sync Width
Definition at line 20557 of file MIMXRT1052.h.
◆ I2S_RCR4_SYWD_MASK
| #define I2S_RCR4_SYWD_MASK (0x1F00U) |
Definition at line 20553 of file MIMXRT1052.h.
◆ I2S_RCR4_SYWD_SHIFT
| #define I2S_RCR4_SYWD_SHIFT (8U) |
Definition at line 20554 of file MIMXRT1052.h.
◆ I2S_RCR5_FBT
| #define I2S_RCR5_FBT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) |
FBT - First Bit Shifted
Definition at line 20596 of file MIMXRT1052.h.
◆ I2S_RCR5_FBT_MASK
| #define I2S_RCR5_FBT_MASK (0x1F00U) |
Definition at line 20592 of file MIMXRT1052.h.
◆ I2S_RCR5_FBT_SHIFT
| #define I2S_RCR5_FBT_SHIFT (8U) |
Definition at line 20593 of file MIMXRT1052.h.
◆ I2S_RCR5_W0W
| #define I2S_RCR5_W0W | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) |
W0W - Word 0 Width
Definition at line 20601 of file MIMXRT1052.h.
◆ I2S_RCR5_W0W_MASK
| #define I2S_RCR5_W0W_MASK (0x1F0000U) |
Definition at line 20597 of file MIMXRT1052.h.
◆ I2S_RCR5_W0W_SHIFT
| #define I2S_RCR5_W0W_SHIFT (16U) |
Definition at line 20598 of file MIMXRT1052.h.
◆ I2S_RCR5_WNW
| #define I2S_RCR5_WNW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) |
WNW - Word N Width
Definition at line 20606 of file MIMXRT1052.h.
◆ I2S_RCR5_WNW_MASK
| #define I2S_RCR5_WNW_MASK (0x1F000000U) |
Definition at line 20602 of file MIMXRT1052.h.
◆ I2S_RCR5_WNW_SHIFT
| #define I2S_RCR5_WNW_SHIFT (24U) |
Definition at line 20603 of file MIMXRT1052.h.
◆ I2S_RCSR_BCE
| #define I2S_RCSR_BCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) |
BCE - Bit Clock Enable 0b0..Receive bit clock is disabled. 0b1..Receive bit clock is enabled.
Definition at line 20409 of file MIMXRT1052.h.
◆ I2S_RCSR_BCE_MASK
| #define I2S_RCSR_BCE_MASK (0x10000000U) |
Definition at line 20403 of file MIMXRT1052.h.
◆ I2S_RCSR_BCE_SHIFT
| #define I2S_RCSR_BCE_SHIFT (28U) |
Definition at line 20404 of file MIMXRT1052.h.
◆ I2S_RCSR_DBGE
| #define I2S_RCSR_DBGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) |
DBGE - Debug Enable 0b0..Receiver is disabled in Debug mode, after completing the current frame. 0b1..Receiver is enabled in Debug mode.
Definition at line 20416 of file MIMXRT1052.h.
◆ I2S_RCSR_DBGE_MASK
| #define I2S_RCSR_DBGE_MASK (0x20000000U) |
Definition at line 20410 of file MIMXRT1052.h.
◆ I2S_RCSR_DBGE_SHIFT
| #define I2S_RCSR_DBGE_SHIFT (29U) |
Definition at line 20411 of file MIMXRT1052.h.
◆ I2S_RCSR_FEF
| #define I2S_RCSR_FEF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) |
FEF - FIFO Error Flag 0b0..Receive overflow not detected. 0b1..Receive overflow detected.
Definition at line 20374 of file MIMXRT1052.h.
◆ I2S_RCSR_FEF_MASK
| #define I2S_RCSR_FEF_MASK (0x40000U) |
Definition at line 20368 of file MIMXRT1052.h.
◆ I2S_RCSR_FEF_SHIFT
| #define I2S_RCSR_FEF_SHIFT (18U) |
Definition at line 20369 of file MIMXRT1052.h.
◆ I2S_RCSR_FEIE
| #define I2S_RCSR_FEIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) |
FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.
Definition at line 20339 of file MIMXRT1052.h.
◆ I2S_RCSR_FEIE_MASK
| #define I2S_RCSR_FEIE_MASK (0x400U) |
Definition at line 20333 of file MIMXRT1052.h.
◆ I2S_RCSR_FEIE_SHIFT
| #define I2S_RCSR_FEIE_SHIFT (10U) |
Definition at line 20334 of file MIMXRT1052.h.
◆ I2S_RCSR_FR
| #define I2S_RCSR_FR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) |
FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.
Definition at line 20402 of file MIMXRT1052.h.
◆ I2S_RCSR_FR_MASK
| #define I2S_RCSR_FR_MASK (0x2000000U) |
Definition at line 20396 of file MIMXRT1052.h.
◆ I2S_RCSR_FR_SHIFT
| #define I2S_RCSR_FR_SHIFT (25U) |
Definition at line 20397 of file MIMXRT1052.h.
◆ I2S_RCSR_FRDE
| #define I2S_RCSR_FRDE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) |
FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.
Definition at line 20311 of file MIMXRT1052.h.
◆ I2S_RCSR_FRDE_MASK
| #define I2S_RCSR_FRDE_MASK (0x1U) |
Definition at line 20305 of file MIMXRT1052.h.
◆ I2S_RCSR_FRDE_SHIFT
| #define I2S_RCSR_FRDE_SHIFT (0U) |
Definition at line 20306 of file MIMXRT1052.h.
◆ I2S_RCSR_FRF
| #define I2S_RCSR_FRF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) |
FRF - FIFO Request Flag 0b0..Receive FIFO watermark not reached. 0b1..Receive FIFO watermark has been reached.
Definition at line 20360 of file MIMXRT1052.h.
◆ I2S_RCSR_FRF_MASK
| #define I2S_RCSR_FRF_MASK (0x10000U) |
Definition at line 20354 of file MIMXRT1052.h.
◆ I2S_RCSR_FRF_SHIFT
| #define I2S_RCSR_FRF_SHIFT (16U) |
Definition at line 20355 of file MIMXRT1052.h.
◆ I2S_RCSR_FRIE
| #define I2S_RCSR_FRIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) |
FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.
Definition at line 20325 of file MIMXRT1052.h.
◆ I2S_RCSR_FRIE_MASK
| #define I2S_RCSR_FRIE_MASK (0x100U) |
Definition at line 20319 of file MIMXRT1052.h.
◆ I2S_RCSR_FRIE_SHIFT
| #define I2S_RCSR_FRIE_SHIFT (8U) |
Definition at line 20320 of file MIMXRT1052.h.
◆ I2S_RCSR_FWDE
| #define I2S_RCSR_FWDE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) |
FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.
Definition at line 20318 of file MIMXRT1052.h.
◆ I2S_RCSR_FWDE_MASK
| #define I2S_RCSR_FWDE_MASK (0x2U) |
Definition at line 20312 of file MIMXRT1052.h.
◆ I2S_RCSR_FWDE_SHIFT
| #define I2S_RCSR_FWDE_SHIFT (1U) |
Definition at line 20313 of file MIMXRT1052.h.
◆ I2S_RCSR_FWF
| #define I2S_RCSR_FWF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) |
FWF - FIFO Warning Flag 0b0..No enabled receive FIFO is full. 0b1..Enabled receive FIFO is full.
Definition at line 20367 of file MIMXRT1052.h.
◆ I2S_RCSR_FWF_MASK
| #define I2S_RCSR_FWF_MASK (0x20000U) |
Definition at line 20361 of file MIMXRT1052.h.
◆ I2S_RCSR_FWF_SHIFT
| #define I2S_RCSR_FWF_SHIFT (17U) |
Definition at line 20362 of file MIMXRT1052.h.
◆ I2S_RCSR_FWIE
| #define I2S_RCSR_FWIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) |
FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.
Definition at line 20332 of file MIMXRT1052.h.
◆ I2S_RCSR_FWIE_MASK
| #define I2S_RCSR_FWIE_MASK (0x200U) |
Definition at line 20326 of file MIMXRT1052.h.
◆ I2S_RCSR_FWIE_SHIFT
| #define I2S_RCSR_FWIE_SHIFT (9U) |
Definition at line 20327 of file MIMXRT1052.h.
◆ I2S_RCSR_RE
| #define I2S_RCSR_RE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) |
RE - Receiver Enable 0b0..Receiver is disabled. 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
Definition at line 20430 of file MIMXRT1052.h.
◆ I2S_RCSR_RE_MASK
| #define I2S_RCSR_RE_MASK (0x80000000U) |
Definition at line 20424 of file MIMXRT1052.h.
◆ I2S_RCSR_RE_SHIFT
| #define I2S_RCSR_RE_SHIFT (31U) |
Definition at line 20425 of file MIMXRT1052.h.
◆ I2S_RCSR_SEF
| #define I2S_RCSR_SEF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) |
SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.
Definition at line 20381 of file MIMXRT1052.h.
◆ I2S_RCSR_SEF_MASK
| #define I2S_RCSR_SEF_MASK (0x80000U) |
Definition at line 20375 of file MIMXRT1052.h.
◆ I2S_RCSR_SEF_SHIFT
| #define I2S_RCSR_SEF_SHIFT (19U) |
Definition at line 20376 of file MIMXRT1052.h.
◆ I2S_RCSR_SEIE
| #define I2S_RCSR_SEIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) |
SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.
Definition at line 20346 of file MIMXRT1052.h.
◆ I2S_RCSR_SEIE_MASK
| #define I2S_RCSR_SEIE_MASK (0x800U) |
Definition at line 20340 of file MIMXRT1052.h.
◆ I2S_RCSR_SEIE_SHIFT
| #define I2S_RCSR_SEIE_SHIFT (11U) |
Definition at line 20341 of file MIMXRT1052.h.
◆ I2S_RCSR_SR
| #define I2S_RCSR_SR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) |
SR - Software Reset 0b0..No effect. 0b1..Software reset.
Definition at line 20395 of file MIMXRT1052.h.
◆ I2S_RCSR_SR_MASK
| #define I2S_RCSR_SR_MASK (0x1000000U) |
Definition at line 20389 of file MIMXRT1052.h.
◆ I2S_RCSR_SR_SHIFT
| #define I2S_RCSR_SR_SHIFT (24U) |
Definition at line 20390 of file MIMXRT1052.h.
◆ I2S_RCSR_STOPE
| #define I2S_RCSR_STOPE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) |
STOPE - Stop Enable 0b0..Receiver disabled in Stop mode. 0b1..Receiver enabled in Stop mode.
Definition at line 20423 of file MIMXRT1052.h.
◆ I2S_RCSR_STOPE_MASK
| #define I2S_RCSR_STOPE_MASK (0x40000000U) |
Definition at line 20417 of file MIMXRT1052.h.
◆ I2S_RCSR_STOPE_SHIFT
| #define I2S_RCSR_STOPE_SHIFT (30U) |
Definition at line 20418 of file MIMXRT1052.h.
◆ I2S_RCSR_WSF
| #define I2S_RCSR_WSF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) |
WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.
Definition at line 20388 of file MIMXRT1052.h.
◆ I2S_RCSR_WSF_MASK
| #define I2S_RCSR_WSF_MASK (0x100000U) |
Definition at line 20382 of file MIMXRT1052.h.
◆ I2S_RCSR_WSF_SHIFT
| #define I2S_RCSR_WSF_SHIFT (20U) |
Definition at line 20383 of file MIMXRT1052.h.
◆ I2S_RCSR_WSIE
| #define I2S_RCSR_WSIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) |
WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.
Definition at line 20353 of file MIMXRT1052.h.
◆ I2S_RCSR_WSIE_MASK
| #define I2S_RCSR_WSIE_MASK (0x1000U) |
Definition at line 20347 of file MIMXRT1052.h.
◆ I2S_RCSR_WSIE_SHIFT
| #define I2S_RCSR_WSIE_SHIFT (12U) |
Definition at line 20348 of file MIMXRT1052.h.
◆ I2S_RDR_COUNT
| #define I2S_RDR_COUNT (4U) |
Definition at line 20619 of file MIMXRT1052.h.
◆ I2S_RDR_RDR
| #define I2S_RDR_RDR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) |
RDR - Receive Data Register
Definition at line 20615 of file MIMXRT1052.h.
◆ I2S_RDR_RDR_MASK
| #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) |
Definition at line 20611 of file MIMXRT1052.h.
◆ I2S_RDR_RDR_SHIFT
| #define I2S_RDR_RDR_SHIFT (0U) |
Definition at line 20612 of file MIMXRT1052.h.
◆ I2S_RFR_COUNT
| #define I2S_RFR_COUNT (4U) |
Definition at line 20643 of file MIMXRT1052.h.
◆ I2S_RFR_RCP
| #define I2S_RFR_RCP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) |
RCP - Receive Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
Definition at line 20634 of file MIMXRT1052.h.
◆ I2S_RFR_RCP_MASK
| #define I2S_RFR_RCP_MASK (0x8000U) |
Definition at line 20628 of file MIMXRT1052.h.
◆ I2S_RFR_RCP_SHIFT
| #define I2S_RFR_RCP_SHIFT (15U) |
Definition at line 20629 of file MIMXRT1052.h.
◆ I2S_RFR_RFP
| #define I2S_RFR_RFP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) |
RFP - Read FIFO Pointer
Definition at line 20627 of file MIMXRT1052.h.
◆ I2S_RFR_RFP_MASK
| #define I2S_RFR_RFP_MASK (0x3FU) |
Definition at line 20623 of file MIMXRT1052.h.
◆ I2S_RFR_RFP_SHIFT
| #define I2S_RFR_RFP_SHIFT (0U) |
Definition at line 20624 of file MIMXRT1052.h.
◆ I2S_RFR_WFP
| #define I2S_RFR_WFP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) |
WFP - Write FIFO Pointer
Definition at line 20639 of file MIMXRT1052.h.
◆ I2S_RFR_WFP_MASK
| #define I2S_RFR_WFP_MASK (0x3F0000U) |
Definition at line 20635 of file MIMXRT1052.h.
◆ I2S_RFR_WFP_SHIFT
| #define I2S_RFR_WFP_SHIFT (16U) |
Definition at line 20636 of file MIMXRT1052.h.
◆ I2S_RMR_RWM
| #define I2S_RMR_RWM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) |
RWM - Receive Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked.
Definition at line 20653 of file MIMXRT1052.h.
◆ I2S_RMR_RWM_MASK
| #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) |
Definition at line 20647 of file MIMXRT1052.h.
◆ I2S_RMR_RWM_SHIFT
| #define I2S_RMR_RWM_SHIFT (0U) |
Definition at line 20648 of file MIMXRT1052.h.
◆ I2S_TCR1_TFW
| #define I2S_TCR1_TFW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) |
TFW - Transmit FIFO Watermark
Definition at line 20079 of file MIMXRT1052.h.
◆ I2S_TCR1_TFW_MASK
| #define I2S_TCR1_TFW_MASK (0x1FU) |
Definition at line 20075 of file MIMXRT1052.h.
◆ I2S_TCR1_TFW_SHIFT
| #define I2S_TCR1_TFW_SHIFT (0U) |
Definition at line 20076 of file MIMXRT1052.h.
◆ I2S_TCR2_BCD
| #define I2S_TCR2_BCD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) |
BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.
Definition at line 20095 of file MIMXRT1052.h.
◆ I2S_TCR2_BCD_MASK
| #define I2S_TCR2_BCD_MASK (0x1000000U) |
Definition at line 20089 of file MIMXRT1052.h.
◆ I2S_TCR2_BCD_SHIFT
| #define I2S_TCR2_BCD_SHIFT (24U) |
Definition at line 20090 of file MIMXRT1052.h.
◆ I2S_TCR2_BCI
| #define I2S_TCR2_BCI | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) |
BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.
Definition at line 20118 of file MIMXRT1052.h.
◆ I2S_TCR2_BCI_MASK
| #define I2S_TCR2_BCI_MASK (0x10000000U) |
Definition at line 20112 of file MIMXRT1052.h.
◆ I2S_TCR2_BCI_SHIFT
| #define I2S_TCR2_BCI_SHIFT (28U) |
Definition at line 20113 of file MIMXRT1052.h.
◆ I2S_TCR2_BCP
| #define I2S_TCR2_BCP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) |
BCP - Bit Clock Polarity 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
Definition at line 20102 of file MIMXRT1052.h.
◆ I2S_TCR2_BCP_MASK
| #define I2S_TCR2_BCP_MASK (0x2000000U) |
Definition at line 20096 of file MIMXRT1052.h.
◆ I2S_TCR2_BCP_SHIFT
| #define I2S_TCR2_BCP_SHIFT (25U) |
Definition at line 20097 of file MIMXRT1052.h.
◆ I2S_TCR2_BCS
| #define I2S_TCR2_BCS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) |
BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.
Definition at line 20125 of file MIMXRT1052.h.
◆ I2S_TCR2_BCS_MASK
| #define I2S_TCR2_BCS_MASK (0x20000000U) |
Definition at line 20119 of file MIMXRT1052.h.
◆ I2S_TCR2_BCS_SHIFT
| #define I2S_TCR2_BCS_SHIFT (29U) |
Definition at line 20120 of file MIMXRT1052.h.
◆ I2S_TCR2_DIV
| #define I2S_TCR2_DIV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) |
DIV - Bit Clock Divide
Definition at line 20088 of file MIMXRT1052.h.
◆ I2S_TCR2_DIV_MASK
| #define I2S_TCR2_DIV_MASK (0xFFU) |
Definition at line 20084 of file MIMXRT1052.h.
◆ I2S_TCR2_DIV_SHIFT
| #define I2S_TCR2_DIV_SHIFT (0U) |
Definition at line 20085 of file MIMXRT1052.h.
◆ I2S_TCR2_MSEL
| #define I2S_TCR2_MSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) |
MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.
Definition at line 20111 of file MIMXRT1052.h.
◆ I2S_TCR2_MSEL_MASK
| #define I2S_TCR2_MSEL_MASK (0xC000000U) |
Definition at line 20103 of file MIMXRT1052.h.
◆ I2S_TCR2_MSEL_SHIFT
| #define I2S_TCR2_MSEL_SHIFT (26U) |
Definition at line 20104 of file MIMXRT1052.h.
◆ I2S_TCR2_SYNC
| #define I2S_TCR2_SYNC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) |
SYNC - Synchronous Mode 0b00..Asynchronous mode. 0b01..Synchronous with receiver. 0b10..Reserved. 0b11..Reserved.
Definition at line 20134 of file MIMXRT1052.h.
◆ I2S_TCR2_SYNC_MASK
| #define I2S_TCR2_SYNC_MASK (0xC0000000U) |
Definition at line 20126 of file MIMXRT1052.h.
◆ I2S_TCR2_SYNC_SHIFT
| #define I2S_TCR2_SYNC_SHIFT (30U) |
Definition at line 20127 of file MIMXRT1052.h.
◆ I2S_TCR3_CFR
| #define I2S_TCR3_CFR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) |
CFR - Channel FIFO Reset
Definition at line 20153 of file MIMXRT1052.h.
◆ I2S_TCR3_CFR_MASK
| #define I2S_TCR3_CFR_MASK (0xF000000U) |
Definition at line 20149 of file MIMXRT1052.h.
◆ I2S_TCR3_CFR_SHIFT
| #define I2S_TCR3_CFR_SHIFT (24U) |
Definition at line 20150 of file MIMXRT1052.h.
◆ I2S_TCR3_TCE
| #define I2S_TCR3_TCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
TCE - Transmit Channel Enable
Definition at line 20148 of file MIMXRT1052.h.
◆ I2S_TCR3_TCE_MASK
| #define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
Definition at line 20144 of file MIMXRT1052.h.
◆ I2S_TCR3_TCE_SHIFT
| #define I2S_TCR3_TCE_SHIFT (16U) |
Definition at line 20145 of file MIMXRT1052.h.
◆ I2S_TCR3_WDFL
| #define I2S_TCR3_WDFL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) |
WDFL - Word Flag Configuration
Definition at line 20143 of file MIMXRT1052.h.
◆ I2S_TCR3_WDFL_MASK
| #define I2S_TCR3_WDFL_MASK (0x1FU) |
Definition at line 20139 of file MIMXRT1052.h.
◆ I2S_TCR3_WDFL_SHIFT
| #define I2S_TCR3_WDFL_SHIFT (0U) |
Definition at line 20140 of file MIMXRT1052.h.
◆ I2S_TCR4_CHMOD
| #define I2S_TCR4_CHMOD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) |
CHMOD - Channel Mode 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
Definition at line 20199 of file MIMXRT1052.h.
◆ I2S_TCR4_CHMOD_MASK
| #define I2S_TCR4_CHMOD_MASK (0x20U) |
Definition at line 20193 of file MIMXRT1052.h.
◆ I2S_TCR4_CHMOD_SHIFT
| #define I2S_TCR4_CHMOD_SHIFT (5U) |
Definition at line 20194 of file MIMXRT1052.h.
◆ I2S_TCR4_FCOMB
| #define I2S_TCR4_FCOMB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) |
FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0b10..FIFO combine mode enabled on FIFO writes (by software). 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
Definition at line 20227 of file MIMXRT1052.h.
◆ I2S_TCR4_FCOMB_MASK
| #define I2S_TCR4_FCOMB_MASK (0xC000000U) |
Definition at line 20219 of file MIMXRT1052.h.
◆ I2S_TCR4_FCOMB_SHIFT
| #define I2S_TCR4_FCOMB_SHIFT (26U) |
Definition at line 20220 of file MIMXRT1052.h.
◆ I2S_TCR4_FCONT
| #define I2S_TCR4_FCONT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) |
FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
Definition at line 20234 of file MIMXRT1052.h.
◆ I2S_TCR4_FCONT_MASK
| #define I2S_TCR4_FCONT_MASK (0x10000000U) |
Definition at line 20228 of file MIMXRT1052.h.
◆ I2S_TCR4_FCONT_SHIFT
| #define I2S_TCR4_FCONT_SHIFT (28U) |
Definition at line 20229 of file MIMXRT1052.h.
◆ I2S_TCR4_FPACK
| #define I2S_TCR4_FPACK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) |
FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled
Definition at line 20218 of file MIMXRT1052.h.
◆ I2S_TCR4_FPACK_MASK
| #define I2S_TCR4_FPACK_MASK (0x3000000U) |
Definition at line 20210 of file MIMXRT1052.h.
◆ I2S_TCR4_FPACK_SHIFT
| #define I2S_TCR4_FPACK_SHIFT (24U) |
Definition at line 20211 of file MIMXRT1052.h.
◆ I2S_TCR4_FRSZ
| #define I2S_TCR4_FRSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) |
FRSZ - Frame size
Definition at line 20209 of file MIMXRT1052.h.
◆ I2S_TCR4_FRSZ_MASK
| #define I2S_TCR4_FRSZ_MASK (0x1F0000U) |
Definition at line 20205 of file MIMXRT1052.h.
◆ I2S_TCR4_FRSZ_SHIFT
| #define I2S_TCR4_FRSZ_SHIFT (16U) |
Definition at line 20206 of file MIMXRT1052.h.
◆ I2S_TCR4_FSD
| #define I2S_TCR4_FSD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) |
FSD - Frame Sync Direction 0b0..Frame sync is generated externally in Slave mode. 0b1..Frame sync is generated internally in Master mode.
Definition at line 20164 of file MIMXRT1052.h.
◆ I2S_TCR4_FSD_MASK
| #define I2S_TCR4_FSD_MASK (0x1U) |
Definition at line 20158 of file MIMXRT1052.h.
◆ I2S_TCR4_FSD_SHIFT
| #define I2S_TCR4_FSD_SHIFT (0U) |
Definition at line 20159 of file MIMXRT1052.h.
◆ I2S_TCR4_FSE
| #define I2S_TCR4_FSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) |
FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.
Definition at line 20185 of file MIMXRT1052.h.
◆ I2S_TCR4_FSE_MASK
| #define I2S_TCR4_FSE_MASK (0x8U) |
Definition at line 20179 of file MIMXRT1052.h.
◆ I2S_TCR4_FSE_SHIFT
| #define I2S_TCR4_FSE_SHIFT (3U) |
Definition at line 20180 of file MIMXRT1052.h.
◆ I2S_TCR4_FSP
| #define I2S_TCR4_FSP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) |
FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.
Definition at line 20171 of file MIMXRT1052.h.
◆ I2S_TCR4_FSP_MASK
| #define I2S_TCR4_FSP_MASK (0x2U) |
Definition at line 20165 of file MIMXRT1052.h.
◆ I2S_TCR4_FSP_SHIFT
| #define I2S_TCR4_FSP_SHIFT (1U) |
Definition at line 20166 of file MIMXRT1052.h.
◆ I2S_TCR4_MF
| #define I2S_TCR4_MF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) |
MF - MSB First 0b0..LSB is transmitted first. 0b1..MSB is transmitted first.
Definition at line 20192 of file MIMXRT1052.h.
◆ I2S_TCR4_MF_MASK
| #define I2S_TCR4_MF_MASK (0x10U) |
Definition at line 20186 of file MIMXRT1052.h.
◆ I2S_TCR4_MF_SHIFT
| #define I2S_TCR4_MF_SHIFT (4U) |
Definition at line 20187 of file MIMXRT1052.h.
◆ I2S_TCR4_ONDEM
| #define I2S_TCR4_ONDEM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) |
ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
Definition at line 20178 of file MIMXRT1052.h.
◆ I2S_TCR4_ONDEM_MASK
| #define I2S_TCR4_ONDEM_MASK (0x4U) |
Definition at line 20172 of file MIMXRT1052.h.
◆ I2S_TCR4_ONDEM_SHIFT
| #define I2S_TCR4_ONDEM_SHIFT (2U) |
Definition at line 20173 of file MIMXRT1052.h.
◆ I2S_TCR4_SYWD
| #define I2S_TCR4_SYWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) |
SYWD - Sync Width
Definition at line 20204 of file MIMXRT1052.h.
◆ I2S_TCR4_SYWD_MASK
| #define I2S_TCR4_SYWD_MASK (0x1F00U) |
Definition at line 20200 of file MIMXRT1052.h.
◆ I2S_TCR4_SYWD_SHIFT
| #define I2S_TCR4_SYWD_SHIFT (8U) |
Definition at line 20201 of file MIMXRT1052.h.
◆ I2S_TCR5_FBT
| #define I2S_TCR5_FBT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) |
FBT - First Bit Shifted
Definition at line 20243 of file MIMXRT1052.h.
◆ I2S_TCR5_FBT_MASK
| #define I2S_TCR5_FBT_MASK (0x1F00U) |
Definition at line 20239 of file MIMXRT1052.h.
◆ I2S_TCR5_FBT_SHIFT
| #define I2S_TCR5_FBT_SHIFT (8U) |
Definition at line 20240 of file MIMXRT1052.h.
◆ I2S_TCR5_W0W
| #define I2S_TCR5_W0W | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) |
W0W - Word 0 Width
Definition at line 20248 of file MIMXRT1052.h.
◆ I2S_TCR5_W0W_MASK
| #define I2S_TCR5_W0W_MASK (0x1F0000U) |
Definition at line 20244 of file MIMXRT1052.h.
◆ I2S_TCR5_W0W_SHIFT
| #define I2S_TCR5_W0W_SHIFT (16U) |
Definition at line 20245 of file MIMXRT1052.h.
◆ I2S_TCR5_WNW
| #define I2S_TCR5_WNW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) |
WNW - Word N Width
Definition at line 20253 of file MIMXRT1052.h.
◆ I2S_TCR5_WNW_MASK
| #define I2S_TCR5_WNW_MASK (0x1F000000U) |
Definition at line 20249 of file MIMXRT1052.h.
◆ I2S_TCR5_WNW_SHIFT
| #define I2S_TCR5_WNW_SHIFT (24U) |
Definition at line 20250 of file MIMXRT1052.h.
◆ I2S_TCSR_BCE
| #define I2S_TCSR_BCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) |
BCE - Bit Clock Enable 0b0..Transmit bit clock is disabled. 0b1..Transmit bit clock is enabled.
Definition at line 20049 of file MIMXRT1052.h.
◆ I2S_TCSR_BCE_MASK
| #define I2S_TCSR_BCE_MASK (0x10000000U) |
Definition at line 20043 of file MIMXRT1052.h.
◆ I2S_TCSR_BCE_SHIFT
| #define I2S_TCSR_BCE_SHIFT (28U) |
Definition at line 20044 of file MIMXRT1052.h.
◆ I2S_TCSR_DBGE
| #define I2S_TCSR_DBGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) |
DBGE - Debug Enable 0b0..Transmitter is disabled in Debug mode, after completing the current frame. 0b1..Transmitter is enabled in Debug mode.
Definition at line 20056 of file MIMXRT1052.h.
◆ I2S_TCSR_DBGE_MASK
| #define I2S_TCSR_DBGE_MASK (0x20000000U) |
Definition at line 20050 of file MIMXRT1052.h.
◆ I2S_TCSR_DBGE_SHIFT
| #define I2S_TCSR_DBGE_SHIFT (29U) |
Definition at line 20051 of file MIMXRT1052.h.
◆ I2S_TCSR_FEF
| #define I2S_TCSR_FEF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) |
FEF - FIFO Error Flag 0b0..Transmit underrun not detected. 0b1..Transmit underrun detected.
Definition at line 20014 of file MIMXRT1052.h.
◆ I2S_TCSR_FEF_MASK
| #define I2S_TCSR_FEF_MASK (0x40000U) |
Definition at line 20008 of file MIMXRT1052.h.
◆ I2S_TCSR_FEF_SHIFT
| #define I2S_TCSR_FEF_SHIFT (18U) |
Definition at line 20009 of file MIMXRT1052.h.
◆ I2S_TCSR_FEIE
| #define I2S_TCSR_FEIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) |
FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.
Definition at line 19979 of file MIMXRT1052.h.
◆ I2S_TCSR_FEIE_MASK
| #define I2S_TCSR_FEIE_MASK (0x400U) |
Definition at line 19973 of file MIMXRT1052.h.
◆ I2S_TCSR_FEIE_SHIFT
| #define I2S_TCSR_FEIE_SHIFT (10U) |
Definition at line 19974 of file MIMXRT1052.h.
◆ I2S_TCSR_FR
| #define I2S_TCSR_FR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) |
FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.
Definition at line 20042 of file MIMXRT1052.h.
◆ I2S_TCSR_FR_MASK
| #define I2S_TCSR_FR_MASK (0x2000000U) |
Definition at line 20036 of file MIMXRT1052.h.
◆ I2S_TCSR_FR_SHIFT
| #define I2S_TCSR_FR_SHIFT (25U) |
Definition at line 20037 of file MIMXRT1052.h.
◆ I2S_TCSR_FRDE
| #define I2S_TCSR_FRDE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) |
FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.
Definition at line 19951 of file MIMXRT1052.h.
◆ I2S_TCSR_FRDE_MASK
| #define I2S_TCSR_FRDE_MASK (0x1U) |
Definition at line 19945 of file MIMXRT1052.h.
◆ I2S_TCSR_FRDE_SHIFT
| #define I2S_TCSR_FRDE_SHIFT (0U) |
Definition at line 19946 of file MIMXRT1052.h.
◆ I2S_TCSR_FRF
| #define I2S_TCSR_FRF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) |
FRF - FIFO Request Flag 0b0..Transmit FIFO watermark has not been reached. 0b1..Transmit FIFO watermark has been reached.
Definition at line 20000 of file MIMXRT1052.h.
◆ I2S_TCSR_FRF_MASK
| #define I2S_TCSR_FRF_MASK (0x10000U) |
Definition at line 19994 of file MIMXRT1052.h.
◆ I2S_TCSR_FRF_SHIFT
| #define I2S_TCSR_FRF_SHIFT (16U) |
Definition at line 19995 of file MIMXRT1052.h.
◆ I2S_TCSR_FRIE
| #define I2S_TCSR_FRIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) |
FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.
Definition at line 19965 of file MIMXRT1052.h.
◆ I2S_TCSR_FRIE_MASK
| #define I2S_TCSR_FRIE_MASK (0x100U) |
Definition at line 19959 of file MIMXRT1052.h.
◆ I2S_TCSR_FRIE_SHIFT
| #define I2S_TCSR_FRIE_SHIFT (8U) |
Definition at line 19960 of file MIMXRT1052.h.
◆ I2S_TCSR_FWDE
| #define I2S_TCSR_FWDE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) |
FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.
Definition at line 19958 of file MIMXRT1052.h.
◆ I2S_TCSR_FWDE_MASK
| #define I2S_TCSR_FWDE_MASK (0x2U) |
Definition at line 19952 of file MIMXRT1052.h.
◆ I2S_TCSR_FWDE_SHIFT
| #define I2S_TCSR_FWDE_SHIFT (1U) |
Definition at line 19953 of file MIMXRT1052.h.
◆ I2S_TCSR_FWF
| #define I2S_TCSR_FWF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) |
FWF - FIFO Warning Flag 0b0..No enabled transmit FIFO is empty. 0b1..Enabled transmit FIFO is empty.
Definition at line 20007 of file MIMXRT1052.h.
◆ I2S_TCSR_FWF_MASK
| #define I2S_TCSR_FWF_MASK (0x20000U) |
Definition at line 20001 of file MIMXRT1052.h.
◆ I2S_TCSR_FWF_SHIFT
| #define I2S_TCSR_FWF_SHIFT (17U) |
Definition at line 20002 of file MIMXRT1052.h.
◆ I2S_TCSR_FWIE
| #define I2S_TCSR_FWIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) |
FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.
Definition at line 19972 of file MIMXRT1052.h.
◆ I2S_TCSR_FWIE_MASK
| #define I2S_TCSR_FWIE_MASK (0x200U) |
Definition at line 19966 of file MIMXRT1052.h.
◆ I2S_TCSR_FWIE_SHIFT
| #define I2S_TCSR_FWIE_SHIFT (9U) |
Definition at line 19967 of file MIMXRT1052.h.
◆ I2S_TCSR_SEF
| #define I2S_TCSR_SEF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) |
SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.
Definition at line 20021 of file MIMXRT1052.h.
◆ I2S_TCSR_SEF_MASK
| #define I2S_TCSR_SEF_MASK (0x80000U) |
Definition at line 20015 of file MIMXRT1052.h.
◆ I2S_TCSR_SEF_SHIFT
| #define I2S_TCSR_SEF_SHIFT (19U) |
Definition at line 20016 of file MIMXRT1052.h.
◆ I2S_TCSR_SEIE
| #define I2S_TCSR_SEIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) |
SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.
Definition at line 19986 of file MIMXRT1052.h.
◆ I2S_TCSR_SEIE_MASK
| #define I2S_TCSR_SEIE_MASK (0x800U) |
Definition at line 19980 of file MIMXRT1052.h.
◆ I2S_TCSR_SEIE_SHIFT
| #define I2S_TCSR_SEIE_SHIFT (11U) |
Definition at line 19981 of file MIMXRT1052.h.
◆ I2S_TCSR_SR
| #define I2S_TCSR_SR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) |
SR - Software Reset 0b0..No effect. 0b1..Software reset.
Definition at line 20035 of file MIMXRT1052.h.
◆ I2S_TCSR_SR_MASK
| #define I2S_TCSR_SR_MASK (0x1000000U) |
Definition at line 20029 of file MIMXRT1052.h.
◆ I2S_TCSR_SR_SHIFT
| #define I2S_TCSR_SR_SHIFT (24U) |
Definition at line 20030 of file MIMXRT1052.h.
◆ I2S_TCSR_STOPE
| #define I2S_TCSR_STOPE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) |
STOPE - Stop Enable 0b0..Transmitter disabled in Stop mode. 0b1..Transmitter enabled in Stop mode.
Definition at line 20063 of file MIMXRT1052.h.
◆ I2S_TCSR_STOPE_MASK
| #define I2S_TCSR_STOPE_MASK (0x40000000U) |
Definition at line 20057 of file MIMXRT1052.h.
◆ I2S_TCSR_STOPE_SHIFT
| #define I2S_TCSR_STOPE_SHIFT (30U) |
Definition at line 20058 of file MIMXRT1052.h.
◆ I2S_TCSR_TE
| #define I2S_TCSR_TE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) |
TE - Transmitter Enable 0b0..Transmitter is disabled. 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
Definition at line 20070 of file MIMXRT1052.h.
◆ I2S_TCSR_TE_MASK
| #define I2S_TCSR_TE_MASK (0x80000000U) |
Definition at line 20064 of file MIMXRT1052.h.
◆ I2S_TCSR_TE_SHIFT
| #define I2S_TCSR_TE_SHIFT (31U) |
Definition at line 20065 of file MIMXRT1052.h.
◆ I2S_TCSR_WSF
| #define I2S_TCSR_WSF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) |
WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.
Definition at line 20028 of file MIMXRT1052.h.
◆ I2S_TCSR_WSF_MASK
| #define I2S_TCSR_WSF_MASK (0x100000U) |
Definition at line 20022 of file MIMXRT1052.h.
◆ I2S_TCSR_WSF_SHIFT
| #define I2S_TCSR_WSF_SHIFT (20U) |
Definition at line 20023 of file MIMXRT1052.h.
◆ I2S_TCSR_WSIE
| #define I2S_TCSR_WSIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) |
WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.
Definition at line 19993 of file MIMXRT1052.h.
◆ I2S_TCSR_WSIE_MASK
| #define I2S_TCSR_WSIE_MASK (0x1000U) |
Definition at line 19987 of file MIMXRT1052.h.
◆ I2S_TCSR_WSIE_SHIFT
| #define I2S_TCSR_WSIE_SHIFT (12U) |
Definition at line 19988 of file MIMXRT1052.h.
◆ I2S_TDR_COUNT
| #define I2S_TDR_COUNT (4U) |
Definition at line 20266 of file MIMXRT1052.h.
◆ I2S_TDR_TDR
| #define I2S_TDR_TDR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) |
TDR - Transmit Data Register
Definition at line 20262 of file MIMXRT1052.h.
◆ I2S_TDR_TDR_MASK
| #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) |
Definition at line 20258 of file MIMXRT1052.h.
◆ I2S_TDR_TDR_SHIFT
| #define I2S_TDR_TDR_SHIFT (0U) |
Definition at line 20259 of file MIMXRT1052.h.
◆ I2S_TFR_COUNT
| #define I2S_TFR_COUNT (4U) |
Definition at line 20290 of file MIMXRT1052.h.
◆ I2S_TFR_RFP
| #define I2S_TFR_RFP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) |
RFP - Read FIFO Pointer
Definition at line 20274 of file MIMXRT1052.h.
◆ I2S_TFR_RFP_MASK
| #define I2S_TFR_RFP_MASK (0x3FU) |
Definition at line 20270 of file MIMXRT1052.h.
◆ I2S_TFR_RFP_SHIFT
| #define I2S_TFR_RFP_SHIFT (0U) |
Definition at line 20271 of file MIMXRT1052.h.
◆ I2S_TFR_WCP
| #define I2S_TFR_WCP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) |
WCP - Write Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
Definition at line 20286 of file MIMXRT1052.h.
◆ I2S_TFR_WCP_MASK
| #define I2S_TFR_WCP_MASK (0x80000000U) |
Definition at line 20280 of file MIMXRT1052.h.
◆ I2S_TFR_WCP_SHIFT
| #define I2S_TFR_WCP_SHIFT (31U) |
Definition at line 20281 of file MIMXRT1052.h.
◆ I2S_TFR_WFP
| #define I2S_TFR_WFP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) |
WFP - Write FIFO Pointer
Definition at line 20279 of file MIMXRT1052.h.
◆ I2S_TFR_WFP_MASK
| #define I2S_TFR_WFP_MASK (0x3F0000U) |
Definition at line 20275 of file MIMXRT1052.h.
◆ I2S_TFR_WFP_SHIFT
| #define I2S_TFR_WFP_SHIFT (16U) |
Definition at line 20276 of file MIMXRT1052.h.
◆ I2S_TMR_TWM
| #define I2S_TMR_TWM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) |
TWM - Transmit Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
Definition at line 20300 of file MIMXRT1052.h.
◆ I2S_TMR_TWM_MASK
| #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) |
Definition at line 20294 of file MIMXRT1052.h.
◆ I2S_TMR_TWM_SHIFT
| #define I2S_TMR_TWM_SHIFT (0U) |
Definition at line 20295 of file MIMXRT1052.h.
◆ I2S_VERID_FEATURE
| #define I2S_VERID_FEATURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) |
FEATURE - Feature Specification Number 0b0000000000000000..Standard feature set.
Definition at line 19911 of file MIMXRT1052.h.
◆ I2S_VERID_FEATURE_MASK
| #define I2S_VERID_FEATURE_MASK (0xFFFFU) |
Definition at line 19906 of file MIMXRT1052.h.
◆ I2S_VERID_FEATURE_SHIFT
| #define I2S_VERID_FEATURE_SHIFT (0U) |
Definition at line 19907 of file MIMXRT1052.h.
◆ I2S_VERID_MAJOR
| #define I2S_VERID_MAJOR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) |
MAJOR - Major Version Number
Definition at line 19921 of file MIMXRT1052.h.
◆ I2S_VERID_MAJOR_MASK
| #define I2S_VERID_MAJOR_MASK (0xFF000000U) |
Definition at line 19917 of file MIMXRT1052.h.
◆ I2S_VERID_MAJOR_SHIFT
| #define I2S_VERID_MAJOR_SHIFT (24U) |
Definition at line 19918 of file MIMXRT1052.h.
◆ I2S_VERID_MINOR
| #define I2S_VERID_MINOR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) |
MINOR - Minor Version Number
Definition at line 19916 of file MIMXRT1052.h.
◆ I2S_VERID_MINOR_MASK
| #define I2S_VERID_MINOR_MASK (0xFF0000U) |
Definition at line 19912 of file MIMXRT1052.h.
◆ I2S_VERID_MINOR_SHIFT
| #define I2S_VERID_MINOR_SHIFT (16U) |
Definition at line 19913 of file MIMXRT1052.h.