IOMUXC_GPR Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » IOMUXC_GPR Peripheral Access Layer
Collaboration diagram for IOMUXC_GPR Register Masks:

GPR1 - GPR1 General Purpose Register

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK   (0x7U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK   (0x38U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK   (0xC0U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK   (0x300U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK   (0xC00U)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_GINT_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR1_GINT_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR1_GINT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
 
#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
 
#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_EXC_MON_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR1_EXC_MON(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
 
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
 
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
 

GPR2 - GPR2 General Purpose Register

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
 
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
 
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK   (0xFF0000U)
 
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
 
#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR2_MQS_SW_RST(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
 
#define IOMUXC_GPR_GPR2_MQS_EN_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR2_MQS_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
 
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
 
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
 

GPR3 - GPR3 General Purpose Register

#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK   (0xFU)
 
#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR3_OCRAM_CTL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
 
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
 
#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK   (0xF0000U)
 
#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK   (0x1U)
 
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT   (0U)
 
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK   (0x2U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK   (0xCU)
 
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT   (2U)
 
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK   (0x10000U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK   (0x20000U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT   (17U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK   (0x40000U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT   (18U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK   (0x80000U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT   (19U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
 

GPR4 - GPR4 General Purpose Register

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
 

GPR5 - GPR5 General Purpose Register

#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR5_WDOG1_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
 
#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR5_WDOG2_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
 
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
 

GPR6 - GPR6 General Purpose Register

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
 

GPR7 - GPR7 General Purpose Register

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
 

GPR8 - GPR8 General Purpose Register

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
 

GPR10 - GPR10 General Purpose Register

#define IOMUXC_GPR_GPR10_NIDEN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR10_NIDEN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR10_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
 
#define IOMUXC_GPR_GPR10_DBG_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR10_DBG_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
 
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
 
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK   (0xFE00U)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK   (0xFE000000U)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
 

GPR11 - GPR11 General Purpose Register

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK   (0x3U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK   (0xCU)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK   (0x30U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK   (0xC0U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK   (0x30000U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK   (0xC0000U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK   (0x300000U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK   (0xC00000U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK   (0xF000000U)
 
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)
 

GPR12 - GPR12 General Purpose Register

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
 

GPR13 - GPR13 General Purpose Register

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
 
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
 
#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR13_CACHE_ENET(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
 
#define IOMUXC_GPR_GPR13_CACHE_USB_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR13_CACHE_USB(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
 

GPR14 - GPR14 General Purpose Register

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
 
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK   (0xF0000U)
 
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
 
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK   (0xF00000U)
 
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
 

GPR16 - GPR16 General Purpose Register

#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
 
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
 

GPR17 - GPR17 General Purpose Register

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK   (0xFFFFFFFFU)
 
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
 

GPR18 - GPR18 General Purpose Register

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
 
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
 

GPR19 - GPR19 General Purpose Register

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
 
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
 

GPR20 - GPR20 General Purpose Register

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
 
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
 

GPR21 - GPR21 General Purpose Register

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
 
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
 

GPR22 - GPR22 General Purpose Register

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
 
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
 

GPR23 - GPR23 General Purpose Register

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
 
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
 

GPR24 - GPR24 General Purpose Register

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
 
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
 

GPR25 - GPR25 General Purpose Register

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
 
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
 

Detailed Description

Macro Definition Documentation

◆ IOMUXC_GPR_GPR10_DBG_EN

#define IOMUXC_GPR_GPR10_DBG_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)

DBG_EN 0b0..Debug turned off. 0b1..Debug enabled (default).

Definition at line 22303 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_DBG_EN_MASK

#define IOMUXC_GPR_GPR10_DBG_EN_MASK   (0x2U)

Definition at line 22297 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_DBG_EN_SHIFT

#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT   (1U)

Definition at line 22298 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX

#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)

DCPKEY_OCOTP_OR_KEYMUX 0b0..Select key from Key MUX (SNVS/OTPMK). 0b1..Select key from OCOTP (SW_GP2).

Definition at line 22317 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK

#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK   (0x10U)

Definition at line 22311 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT

#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT   (4U)

Definition at line 22312 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_DBG_EN

#define IOMUXC_GPR_GPR10_LOCK_DBG_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)

LOCK_DBG_EN 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 22342 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK

#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK   (0x20000U)

Definition at line 22336 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT   (17U)

Definition at line 22337 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX

#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)

LOCK_DCPKEY_OCOTP_OR_KEYMUX 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 22356 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK

#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK   (0x100000U)

Definition at line 22350 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT   (20U)

Definition at line 22351 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_NIDEN

#define IOMUXC_GPR_GPR10_LOCK_NIDEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)

LOCK_NIDEN 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 22335 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK

#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK   (0x10000U)

Definition at line 22329 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT   (16U)

Definition at line 22330 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)

LOCK_OCRAM_TZ_ADDR 0b0000000..Field is not locked 0b0000001..Field is locked (read access only)

Definition at line 22370 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK   (0xFE000000U)

Definition at line 22364 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT   (25U)

Definition at line 22365 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)

LOCK_OCRAM_TZ_EN 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 22363 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK   (0x1000000U)

Definition at line 22357 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT   (24U)

Definition at line 22358 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP

#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)

LOCK_SEC_ERR_RESP 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 22349 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK

#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK   (0x40000U)

Definition at line 22343 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT   (18U)

Definition at line 22344 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_NIDEN

#define IOMUXC_GPR_GPR10_NIDEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)

NIDEN 0b0..Debug turned off. 0b1..Debug enabled (default).

Definition at line 22296 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_NIDEN_MASK

#define IOMUXC_GPR_GPR10_NIDEN_MASK   (0x1U)

Definition at line 22290 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_NIDEN_SHIFT

#define IOMUXC_GPR_GPR10_NIDEN_SHIFT   (0U)

Definition at line 22291 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR

#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)

Definition at line 22328 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK

#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK   (0xFE00U)

Definition at line 22326 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT

#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT   (9U)

Definition at line 22327 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_OCRAM_TZ_EN

#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)

OCRAM_TZ_EN 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.

Definition at line 22325 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK

#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK   (0x100U)

Definition at line 22318 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT

#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT   (8U)

Definition at line 22319 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_SEC_ERR_RESP

#define IOMUXC_GPR_GPR10_SEC_ERR_RESP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)

SEC_ERR_RESP 0b0..OKEY response 0b1..SLVError (default)

Definition at line 22310 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK

#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK   (0x4U)

Definition at line 22304 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT

#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT   (2U)

Definition at line 22305 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_BEE_DE_RX_EN

#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)

Definition at line 22413 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK

#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK   (0xF00U)

Definition at line 22411 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT

#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT   (8U)

Definition at line 22412 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN

#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)

Definition at line 22428 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK

#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK   (0xF000000U)

Definition at line 22426 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT

#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT   (24U)

Definition at line 22427 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)

Definition at line 22416 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK   (0x30000U)

Definition at line 22414 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT   (16U)

Definition at line 22415 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)

Definition at line 22419 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK   (0xC0000U)

Definition at line 22417 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT   (18U)

Definition at line 22418 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)

Definition at line 22422 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK   (0x300000U)

Definition at line 22420 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT   (20U)

Definition at line 22421 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)

Definition at line 22425 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK   (0xC00000U)

Definition at line 22423 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT   (22U)

Definition at line 22424 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)

M7_APC_AC_R0_CTRL 0b00..No access protection 0b01..M7 debug protection enabled 0b10..FlexSPI access protection 0b11..Both M7 debug and FlexSPI access are protected

Definition at line 22383 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK   (0x3U)

Definition at line 22375 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT   (0U)

Definition at line 22376 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)

M7_APC_AC_R1_CTRL 0b00..No access protection 0b01..M7 debug protection enabled 0b10..FlexSPI access protection 0b11..Both M7 debug and FlexSPI access are protected

Definition at line 22392 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK

#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK   (0xCU)

Definition at line 22384 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT   (2U)

Definition at line 22385 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)

M7_APC_AC_R2_CTRL 0b00..No access protection 0b01..M7 debug protection enabled 0b10..FlexSPI access protection 0b11..Both M7 debug and FlexSPI access are protected

Definition at line 22401 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK

#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK   (0x30U)

Definition at line 22393 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT   (4U)

Definition at line 22394 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)

M7_APC_AC_R3_CTRL 0b00..No access protection 0b01..M7 debug protection enabled 0b10..FlexSPI access protection 0b11..Both M7 debug and FlexSPI access are protected

Definition at line 22410 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK

#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK   (0xC0U)

Definition at line 22402 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT   (6U)

Definition at line 22403 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)

ACMP_IPG_STOP_MODE 0b0..ACMP is functional in Stop mode. 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode.

Definition at line 22467 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK   (0x10U)

Definition at line 22461 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT   (4U)

Definition at line 22462 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)

FLEXIO1_IPG_DOZE 0b0..FLEXIO1 is not in doze mode 0b1..FLEXIO1 is in doze mode

Definition at line 22446 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK   (0x2U)

Definition at line 22440 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT   (1U)

Definition at line 22441 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)

FLEXIO1_IPG_STOP_MODE 0b0..FlexIO1 is functional in Stop mode. 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode.

Definition at line 22439 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK   (0x1U)

Definition at line 22433 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT   (0U)

Definition at line 22434 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)

FLEXIO2_IPG_DOZE 0b0..FLEXIO2 is not in doze mode 0b1..FLEXIO2 is in doze mode

Definition at line 22460 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK   (0x8U)

Definition at line 22454 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT   (3U)

Definition at line 22455 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)

FLEXIO2_IPG_STOP_MODE 0b0..FlexIO2 is functional in Stop mode. 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode.

Definition at line 22453 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK   (0x4U)

Definition at line 22447 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT   (2U)

Definition at line 22448 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_ARCACHE_USDHC

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)

ARCACHE_USDHC 0b0..Cacheable attribute is off for read transactions. 0b1..Cacheable attribute is on for read transactions.

Definition at line 22478 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK   (0x1U)

Definition at line 22472 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT   (0U)

Definition at line 22473 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_AWCACHE_USDHC

#define IOMUXC_GPR_GPR13_AWCACHE_USDHC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)

AWCACHE_USDHC 0b0..Cacheable attribute is off for write transactions. 0b1..Cacheable attribute is on for write transactions.

Definition at line 22485 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK

#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK   (0x2U)

Definition at line 22479 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT

#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT   (1U)

Definition at line 22480 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_CACHE_ENET

#define IOMUXC_GPR_GPR13_CACHE_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)

CACHE_ENET 0b0..Cacheable attribute is off for read/write transactions. 0b1..Cacheable attribute is on for read/write transactions.

Definition at line 22492 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_CACHE_ENET_MASK

#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK   (0x80U)

Definition at line 22486 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT

#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT   (7U)

Definition at line 22487 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_CACHE_USB

#define IOMUXC_GPR_GPR13_CACHE_USB (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)

CACHE_USB 0b0..Cacheable attribute is off for read/write transactions. 0b1..Cacheable attribute is on for read/write transactions.

Definition at line 22499 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_CACHE_USB_MASK

#define IOMUXC_GPR_GPR13_CACHE_USB_MASK   (0x2000U)

Definition at line 22493 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR13_CACHE_USB_SHIFT

#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT   (13U)

Definition at line 22494 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)

ACMP1_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

Definition at line 22510 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK   (0x1U)

Definition at line 22504 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT   (0U)

Definition at line 22505 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)

ACMP1_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

Definition at line 22538 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK   (0x10U)

Definition at line 22532 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT   (4U)

Definition at line 22533 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)

ACMP1_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

Definition at line 22566 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK

#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK   (0x100U)

Definition at line 22560 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT   (8U)

Definition at line 22561 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)

ACMP2_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

Definition at line 22517 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK   (0x2U)

Definition at line 22511 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT   (1U)

Definition at line 22512 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)

ACMP2_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

Definition at line 22545 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK   (0x20U)

Definition at line 22539 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT   (5U)

Definition at line 22540 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)

ACMP2_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

Definition at line 22573 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK

#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK   (0x200U)

Definition at line 22567 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT   (9U)

Definition at line 22568 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)

ACMP3_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

Definition at line 22524 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK   (0x4U)

Definition at line 22518 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT   (2U)

Definition at line 22519 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)

ACMP3_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

Definition at line 22552 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK   (0x40U)

Definition at line 22546 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT   (6U)

Definition at line 22547 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)

ACMP3_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

Definition at line 22580 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK

#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK   (0x400U)

Definition at line 22574 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT   (10U)

Definition at line 22575 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)

ACMP4_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

Definition at line 22531 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK   (0x8U)

Definition at line 22525 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT   (3U)

Definition at line 22526 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)

ACMP4_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

Definition at line 22559 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK   (0x80U)

Definition at line 22553 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT   (7U)

Definition at line 22554 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)

ACMP4_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

Definition at line 22587 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK

#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK   (0x800U)

Definition at line 22581 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT   (11U)

Definition at line 22582 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ

#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)

CM7_CFGDTCMSZ 0b0000..0 KB (No DTCM) 0b0011..4 KB 0b0100..8 KB 0b0101..16 KB 0b0110..32 KB 0b0111..64 KB 0b1000..128 KB 0b1001..256 KB 0b1010..512 KB

Definition at line 22615 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK

#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK   (0xF00000U)

Definition at line 22602 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT

#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT   (20U)

Definition at line 22603 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_CM7_CFGITCMSZ

#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)

CM7_CFGITCMSZ 0b0000..0 KB (No ITCM) 0b0011..4 KB 0b0100..8 KB 0b0101..16 KB 0b0110..32 KB 0b0111..64 KB 0b1000..128 KB 0b1001..256 KB 0b1010..512 KB

Definition at line 22601 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK

#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK   (0xF0000U)

Definition at line 22588 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT

#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT   (16U)

Definition at line 22589 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)

FLEXRAM_BANK_CFG_SEL 0b0..use fuse value to config 0b1..use FLEXRAM_BANK_CFG to config

Definition at line 22640 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK   (0x4U)

Definition at line 22634 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT   (2U)

Definition at line 22635 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_INIT_DTCM_EN

#define IOMUXC_GPR_GPR16_INIT_DTCM_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)

INIT_DTCM_EN 0b0..DTCM is disabled 0b1..DTCM is enabled

Definition at line 22633 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK

#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK   (0x2U)

Definition at line 22627 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT

#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT   (1U)

Definition at line 22628 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_INIT_ITCM_EN

#define IOMUXC_GPR_GPR16_INIT_ITCM_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)

INIT_ITCM_EN 0b0..ITCM is disabled 0b1..ITCM is enabled

Definition at line 22626 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK

#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK   (0x1U)

Definition at line 22620 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT

#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT   (0U)

Definition at line 22621 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)

FLEXRAM_BANK_CFG - FlexRAM bank config value

Definition at line 22649 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK   (0xFFFFFFFFU)

Definition at line 22645 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT   (0U)

Definition at line 22646 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)

LOCK_M7_APC_AC_R0_BOT 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 22660 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK   (0x1U)

Definition at line 22654 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT   (0U)

Definition at line 22655 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT

#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)

Definition at line 22663 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK

#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK   (0xFFFFFFF8U)

Definition at line 22661 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT

#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT   (3U)

Definition at line 22662 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)

LOCK_M7_APC_AC_R0_TOP 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 22674 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK   (0x1U)

Definition at line 22668 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT   (0U)

Definition at line 22669 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP

#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)

Definition at line 22677 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK

#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK   (0xFFFFFFF8U)

Definition at line 22675 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT

#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT   (3U)

Definition at line 22676 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN

#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)

CM7_FORCE_HCLK_EN 0b0..AHB clock is not running (gated) 0b1..AHB clock is running (enabled)

Definition at line 21020 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK

#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK   (0x80000000U)

Definition at line 21014 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT

#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT   (31U)

Definition at line 21015 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET1_CLK_SEL

#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)

ENET1_CLK_SEL 0b0..ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller.

Definition at line 20964 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK

#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK   (0x2000U)

Definition at line 20957 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT

#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT   (13U)

Definition at line 20958 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR

#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)

ENET1_TX_CLK_DIR 0b0..ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input. 0b1..ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0.

Definition at line 20978 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK

#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK   (0x20000U)

Definition at line 20972 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT   (17U)

Definition at line 20973 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN

#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)

ENET_IPG_CLK_S_EN 0b0..ipg_clk_s is gated when there is no IPS access 0b1..ipg_clk_s is always on

Definition at line 21013 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK

#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK   (0x800000U)

Definition at line 21007 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT

#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT   (23U)

Definition at line 21008 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_EXC_MON

#define IOMUXC_GPR_GPR1_EXC_MON (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)

EXC_MON 0b0..OKAY response 0b1..SLVError response

Definition at line 21006 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_EXC_MON_MASK

#define IOMUXC_GPR_GPR1_EXC_MON_MASK   (0x400000U)

Definition at line 21000 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_EXC_MON_SHIFT

#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT   (22U)

Definition at line 21001 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_GINT

#define IOMUXC_GPR_GPR1_GINT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)

GINT 0b0..Global interrupt request is not asserted. 0b1..Global interrupt request is asserted.

Definition at line 20956 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_GINT_MASK

#define IOMUXC_GPR_GPR1_GINT_MASK   (0x1000U)

Definition at line 20950 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_GINT_SHIFT

#define IOMUXC_GPR_GPR1_GINT_SHIFT   (12U)

Definition at line 20951 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)

SAI1_MCLK1_SEL 0b000..ccm.ssi1_clk_root 0b001..ccm.ssi2_clk_root 0b010..ccm.ssi3_clk_root 0b011..iomux.sai1_ipg_clk_sai_mclk 0b100..iomux.sai2_ipg_clk_sai_mclk 0b101..iomux.sai3_ipg_clk_sai_mclk 0b110..Reserved 0b111..Reserved

Definition at line 20909 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK   (0x7U)

Definition at line 20897 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT   (0U)

Definition at line 20898 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)

SAI1_MCLK2_SEL 0b000..ccm.ssi1_clk_root 0b001..ccm.ssi2_clk_root 0b010..ccm.ssi3_clk_root 0b011..iomux.sai1_ipg_clk_sai_mclk 0b100..iomux.sai2_ipg_clk_sai_mclk 0b101..iomux.sai3_ipg_clk_sai_mclk 0b110..Reserved 0b111..Reserved

Definition at line 20922 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK   (0x38U)

Definition at line 20910 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT   (3U)

Definition at line 20911 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)

SAI1_MCLK3_SEL 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

Definition at line 20931 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK   (0xC0U)

Definition at line 20923 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT   (6U)

Definition at line 20924 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK_DIR

#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)

SAI1_MCLK_DIR 0b0..sai1.MCLK is input signal 0b1..sai1.MCLK is output signal

Definition at line 20985 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK

#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK   (0x80000U)

Definition at line 20979 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT   (19U)

Definition at line 20980 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)

SAI2_MCLK3_SEL 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

Definition at line 20940 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK   (0x300U)

Definition at line 20932 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT   (8U)

Definition at line 20933 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)

SAI2_MCLK_DIR 0b0..sai2.MCLK is input signal 0b1..sai2.MCLK is output signal

Definition at line 20992 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK   (0x100000U)

Definition at line 20986 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT   (20U)

Definition at line 20987 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL

#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)

SAI3_MCLK3_SEL 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

Definition at line 20949 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK   (0xC00U)

Definition at line 20941 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT   (10U)

Definition at line 20942 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI3_MCLK_DIR

#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)

SAI3_MCLK_DIR 0b0..sai3.MCLK is input signal 0b1..sai3.MCLK is output signal

Definition at line 20999 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK

#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK   (0x200000U)

Definition at line 20993 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT   (21U)

Definition at line 20994 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_USB_EXP_MODE

#define IOMUXC_GPR_GPR1_USB_EXP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)

USB_EXP_MODE 0b0..Exposure mode is disabled. 0b1..Exposure mode is enabled.

Definition at line 20971 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK

#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK   (0x8000U)

Definition at line 20965 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT

#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT   (15U)

Definition at line 20966 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)

LOCK_M7_APC_AC_R1_BOT 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 22688 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK   (0x1U)

Definition at line 22682 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT   (0U)

Definition at line 22683 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT

#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)

Definition at line 22691 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK

#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK   (0xFFFFFFF8U)

Definition at line 22689 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT

#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT   (3U)

Definition at line 22690 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)

LOCK_M7_APC_AC_R1_TOP 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 22702 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK   (0x1U)

Definition at line 22696 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT   (0U)

Definition at line 22697 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP

#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)

Definition at line 22705 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK

#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK   (0xFFFFFFF8U)

Definition at line 22703 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT

#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT   (3U)

Definition at line 22704 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)

LOCK_M7_APC_AC_R2_BOT 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 22716 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK   (0x1U)

Definition at line 22710 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT   (0U)

Definition at line 22711 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT

#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)

Definition at line 22719 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK

#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK   (0xFFFFFFF8U)

Definition at line 22717 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT

#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT   (3U)

Definition at line 22718 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)

LOCK_M7_APC_AC_R2_TOP 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 22730 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK   (0x1U)

Definition at line 22724 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT   (0U)

Definition at line 22725 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP

#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)

Definition at line 22733 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK

#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK   (0xFFFFFFF8U)

Definition at line 22731 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT

#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT   (3U)

Definition at line 22732 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)

LOCK_M7_APC_AC_R3_BOT 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 22744 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK   (0x1U)

Definition at line 22738 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT   (0U)

Definition at line 22739 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT

#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)

Definition at line 22747 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK

#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK   (0xFFFFFFF8U)

Definition at line 22745 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT

#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT   (3U)

Definition at line 22746 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)

LOCK_M7_APC_AC_R3_TOP 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 22758 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK   (0x1U)

Definition at line 22752 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT   (0U)

Definition at line 22753 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP

#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)

Definition at line 22761 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK

#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK   (0xFFFFFFF8U)

Definition at line 22759 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT

#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT   (3U)

Definition at line 22760 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP

#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)

L2_MEM_DEEPSLEEP 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode 0b1..force memory into deep sleep mode

Definition at line 21038 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK

#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK   (0x4000U)

Definition at line 21032 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT

#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT   (14U)

Definition at line 21033 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)

L2_MEM_EN_POWERSAVING 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels

Definition at line 21031 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK   (0x1000U)

Definition at line 21025 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT   (12U)

Definition at line 21026 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_CLK_DIV

#define IOMUXC_GPR_GPR2_MQS_CLK_DIV (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)

MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. 0b00000000..mclk frequency = 1/1 * hmclk frequency 0b00000001..mclk frequency = 1/2 * hmclk frequency 0b00000010..mclk frequency = 1/3 * hmclk frequency 0b00000011..mclk frequency = 1/4 * hmclk frequency 0b00000100..mclk frequency = 1/5 * hmclk frequency 0b00000101..mclk frequency = 1/6 * hmclk frequency 0b00000110..mclk frequency = 1/7 * hmclk frequency 0b00000111..mclk frequency = 1/8 * hmclk frequency 0b00001000..mclk frequency = 1/9 * hmclk frequency 0b00001001..mclk frequency = 1/10 * hmclk frequency 0b00001010..mclk frequency = 1/11 * hmclk frequency 0b00001011..mclk frequency = 1/12 * hmclk frequency 0b00001100..mclk frequency = 1/13 * hmclk frequency 0b00001101..mclk frequency = 1/14 * hmclk frequency 0b00001110..mclk frequency = 1/15 * hmclk frequency 0b00001111..mclk frequency = 1/16 * hmclk frequency 0b00010000..mclk frequency = 1/17 * hmclk frequency 0b00010001..mclk frequency = 1/18 * hmclk frequency 0b00010010..mclk frequency = 1/19 * hmclk frequency 0b00010011..mclk frequency = 1/20 * hmclk frequency 0b00010100..mclk frequency = 1/21 * hmclk frequency 0b00010101..mclk frequency = 1/22 * hmclk frequency 0b00010110..mclk frequency = 1/23 * hmclk frequency 0b00010111..mclk frequency = 1/24 * hmclk frequency 0b00011000..mclk frequency = 1/25 * hmclk frequency 0b00011001..mclk frequency = 1/26 * hmclk frequency 0b00011010..mclk frequency = 1/27 * hmclk frequency 0b00011011..mclk frequency = 1/28 * hmclk frequency 0b00011100..mclk frequency = 1/29 * hmclk frequency 0b00011101..mclk frequency = 1/30 * hmclk frequency 0b00011110..mclk frequency = 1/31 * hmclk frequency 0b00011111..mclk frequency = 1/32 * hmclk frequency 0b00100000..mclk frequency = 1/33 * hmclk frequency 0b00100001..mclk frequency = 1/34 * hmclk frequency 0b00100010..mclk frequency = 1/35 * hmclk frequency 0b00100011..mclk frequency = 1/36 * hmclk frequency 0b00100100..mclk frequency = 1/37 * hmclk frequency 0b00100101..mclk frequency = 1/38 * hmclk frequency 0b00100110..mclk frequency = 1/39 * hmclk frequency 0b00100111..mclk frequency = 1/40 * hmclk frequency 0b00101000..mclk frequency = 1/41 * hmclk frequency 0b00101001..mclk frequency = 1/42 * hmclk frequency 0b00101010..mclk frequency = 1/43 * hmclk frequency 0b00101011..mclk frequency = 1/44 * hmclk frequency 0b00101100..mclk frequency = 1/45 * hmclk frequency 0b00101101..mclk frequency = 1/46 * hmclk frequency 0b00101110..mclk frequency = 1/47 * hmclk frequency 0b00101111..mclk frequency = 1/48 * hmclk frequency 0b00110000..mclk frequency = 1/49 * hmclk frequency 0b00110001..mclk frequency = 1/50 * hmclk frequency 0b00110010..mclk frequency = 1/51 * hmclk frequency 0b00110011..mclk frequency = 1/52 * hmclk frequency 0b00110100..mclk frequency = 1/53 * hmclk frequency 0b00110101..mclk frequency = 1/54 * hmclk frequency 0b00110110..mclk frequency = 1/55 * hmclk frequency 0b00110111..mclk frequency = 1/56 * hmclk frequency 0b00111000..mclk frequency = 1/57 * hmclk frequency 0b00111001..mclk frequency = 1/58 * hmclk frequency 0b00111010..mclk frequency = 1/59 * hmclk frequency 0b00111011..mclk frequency = 1/60 * hmclk frequency 0b00111100..mclk frequency = 1/61 * hmclk frequency 0b00111101..mclk frequency = 1/62 * hmclk frequency 0b00111110..mclk frequency = 1/63 * hmclk frequency 0b00111111..mclk frequency = 1/64 * hmclk frequency 0b01000000..mclk frequency = 1/65 * hmclk frequency 0b01000001..mclk frequency = 1/66 * hmclk frequency 0b01000010..mclk frequency = 1/67 * hmclk frequency 0b01000011..mclk frequency = 1/68 * hmclk frequency 0b01000100..mclk frequency = 1/69 * hmclk frequency 0b01000101..mclk frequency = 1/70 * hmclk frequency 0b01000110..mclk frequency = 1/71 * hmclk frequency 0b01000111..mclk frequency = 1/72 * hmclk frequency 0b01001000..mclk frequency = 1/73 * hmclk frequency 0b01001001..mclk frequency = 1/74 * hmclk frequency 0b01001010..mclk frequency = 1/75 * hmclk frequency 0b01001011..mclk frequency = 1/76 * hmclk frequency 0b01001100..mclk frequency = 1/77 * hmclk frequency 0b01001101..mclk frequency = 1/78 * hmclk frequency 0b01001110..mclk frequency = 1/79 * hmclk frequency 0b01001111..mclk frequency = 1/80 * hmclk frequency 0b01010000..mclk frequency = 1/81 * hmclk frequency 0b01010001..mclk frequency = 1/82 * hmclk frequency 0b01010010..mclk frequency = 1/83 * hmclk frequency 0b01010011..mclk frequency = 1/84 * hmclk frequency 0b01010100..mclk frequency = 1/85 * hmclk frequency 0b01010101..mclk frequency = 1/86 * hmclk frequency 0b01010110..mclk frequency = 1/87 * hmclk frequency 0b01010111..mclk frequency = 1/88 * hmclk frequency 0b01011000..mclk frequency = 1/89 * hmclk frequency 0b01011001..mclk frequency = 1/90 * hmclk frequency 0b01011010..mclk frequency = 1/91 * hmclk frequency 0b01011011..mclk frequency = 1/92 * hmclk frequency 0b01011100..mclk frequency = 1/93 * hmclk frequency 0b01011101..mclk frequency = 1/94 * hmclk frequency 0b01011110..mclk frequency = 1/95 * hmclk frequency 0b01011111..mclk frequency = 1/96 * hmclk frequency 0b01100000..mclk frequency = 1/97 * hmclk frequency 0b01100001..mclk frequency = 1/98 * hmclk frequency 0b01100010..mclk frequency = 1/99 * hmclk frequency 0b01100011..mclk frequency = 1/100 * hmclk frequency 0b01100100..mclk frequency = 1/101 * hmclk frequency 0b01100101..mclk frequency = 1/102 * hmclk frequency 0b01100110..mclk frequency = 1/103 * hmclk frequency 0b01100111..mclk frequency = 1/104 * hmclk frequency 0b01101000..mclk frequency = 1/105 * hmclk frequency 0b01101001..mclk frequency = 1/106 * hmclk frequency 0b01101010..mclk frequency = 1/107 * hmclk frequency 0b01101011..mclk frequency = 1/108 * hmclk frequency 0b01101100..mclk frequency = 1/109 * hmclk frequency 0b01101101..mclk frequency = 1/110 * hmclk frequency 0b01101110..mclk frequency = 1/111 * hmclk frequency 0b01101111..mclk frequency = 1/112 * hmclk frequency 0b01110000..mclk frequency = 1/113 * hmclk frequency 0b01110001..mclk frequency = 1/114 * hmclk frequency 0b01110010..mclk frequency = 1/115 * hmclk frequency 0b01110011..mclk frequency = 1/116 * hmclk frequency 0b01110100..mclk frequency = 1/117 * hmclk frequency 0b01110101..mclk frequency = 1/118 * hmclk frequency 0b01110110..mclk frequency = 1/119 * hmclk frequency 0b01110111..mclk frequency = 1/120 * hmclk frequency 0b01111000..mclk frequency = 1/121 * hmclk frequency 0b01111001..mclk frequency = 1/122 * hmclk frequency 0b01111010..mclk frequency = 1/123 * hmclk frequency 0b01111011..mclk frequency = 1/124 * hmclk frequency 0b01111100..mclk frequency = 1/125 * hmclk frequency 0b01111101..mclk frequency = 1/126 * hmclk frequency 0b01111110..mclk frequency = 1/127 * hmclk frequency 0b01111111..mclk frequency = 1/128 * hmclk frequency 0b10000000..mclk frequency = 1/129 * hmclk frequency 0b10000001..mclk frequency = 1/130 * hmclk frequency 0b10000010..mclk frequency = 1/131 * hmclk frequency 0b10000011..mclk frequency = 1/132 * hmclk frequency 0b10000100..mclk frequency = 1/133 * hmclk frequency 0b10000101..mclk frequency = 1/134 * hmclk frequency 0b10000110..mclk frequency = 1/135 * hmclk frequency 0b10000111..mclk frequency = 1/136 * hmclk frequency 0b10001000..mclk frequency = 1/137 * hmclk frequency 0b10001001..mclk frequency = 1/138 * hmclk frequency 0b10001010..mclk frequency = 1/139 * hmclk frequency 0b10001011..mclk frequency = 1/140 * hmclk frequency 0b10001100..mclk frequency = 1/141 * hmclk frequency 0b10001101..mclk frequency = 1/142 * hmclk frequency 0b10001110..mclk frequency = 1/143 * hmclk frequency 0b10001111..mclk frequency = 1/144 * hmclk frequency 0b10010000..mclk frequency = 1/145 * hmclk frequency 0b10010001..mclk frequency = 1/146 * hmclk frequency 0b10010010..mclk frequency = 1/147 * hmclk frequency 0b10010011..mclk frequency = 1/148 * hmclk frequency 0b10010100..mclk frequency = 1/149 * hmclk frequency 0b10010101..mclk frequency = 1/150 * hmclk frequency 0b10010110..mclk frequency = 1/151 * hmclk frequency 0b10010111..mclk frequency = 1/152 * hmclk frequency 0b10011000..mclk frequency = 1/153 * hmclk frequency 0b10011001..mclk frequency = 1/154 * hmclk frequency 0b10011010..mclk frequency = 1/155 * hmclk frequency 0b10011011..mclk frequency = 1/156 * hmclk frequency 0b10011100..mclk frequency = 1/157 * hmclk frequency 0b10011101..mclk frequency = 1/158 * hmclk frequency 0b10011110..mclk frequency = 1/159 * hmclk frequency 0b10011111..mclk frequency = 1/160 * hmclk frequency 0b10100000..mclk frequency = 1/161 * hmclk frequency 0b10100001..mclk frequency = 1/162 * hmclk frequency 0b10100010..mclk frequency = 1/163 * hmclk frequency 0b10100011..mclk frequency = 1/164 * hmclk frequency 0b10100100..mclk frequency = 1/165 * hmclk frequency 0b10100101..mclk frequency = 1/166 * hmclk frequency 0b10100110..mclk frequency = 1/167 * hmclk frequency 0b10100111..mclk frequency = 1/168 * hmclk frequency 0b10101000..mclk frequency = 1/169 * hmclk frequency 0b10101001..mclk frequency = 1/170 * hmclk frequency 0b10101010..mclk frequency = 1/171 * hmclk frequency 0b10101011..mclk frequency = 1/172 * hmclk frequency 0b10101100..mclk frequency = 1/173 * hmclk frequency 0b10101101..mclk frequency = 1/174 * hmclk frequency 0b10101110..mclk frequency = 1/175 * hmclk frequency 0b10101111..mclk frequency = 1/176 * hmclk frequency 0b10110000..mclk frequency = 1/177 * hmclk frequency 0b10110001..mclk frequency = 1/178 * hmclk frequency 0b10110010..mclk frequency = 1/179 * hmclk frequency 0b10110011..mclk frequency = 1/180 * hmclk frequency 0b10110100..mclk frequency = 1/181 * hmclk frequency 0b10110101..mclk frequency = 1/182 * hmclk frequency 0b10110110..mclk frequency = 1/183 * hmclk frequency 0b10110111..mclk frequency = 1/184 * hmclk frequency 0b10111000..mclk frequency = 1/185 * hmclk frequency 0b10111001..mclk frequency = 1/186 * hmclk frequency 0b10111010..mclk frequency = 1/187 * hmclk frequency 0b10111011..mclk frequency = 1/188 * hmclk frequency 0b10111100..mclk frequency = 1/189 * hmclk frequency 0b10111101..mclk frequency = 1/190 * hmclk frequency 0b10111110..mclk frequency = 1/191 * hmclk frequency 0b10111111..mclk frequency = 1/192 * hmclk frequency 0b11000000..mclk frequency = 1/193 * hmclk frequency 0b11000001..mclk frequency = 1/194 * hmclk frequency 0b11000010..mclk frequency = 1/195 * hmclk frequency 0b11000011..mclk frequency = 1/196 * hmclk frequency 0b11000100..mclk frequency = 1/197 * hmclk frequency 0b11000101..mclk frequency = 1/198 * hmclk frequency 0b11000110..mclk frequency = 1/199 * hmclk frequency 0b11000111..mclk frequency = 1/200 * hmclk frequency 0b11001000..mclk frequency = 1/201 * hmclk frequency 0b11001001..mclk frequency = 1/202 * hmclk frequency 0b11001010..mclk frequency = 1/203 * hmclk frequency 0b11001011..mclk frequency = 1/204 * hmclk frequency 0b11001100..mclk frequency = 1/205 * hmclk frequency 0b11001101..mclk frequency = 1/206 * hmclk frequency 0b11001110..mclk frequency = 1/207 * hmclk frequency 0b11001111..mclk frequency = 1/208 * hmclk frequency 0b11010000..mclk frequency = 1/209 * hmclk frequency 0b11010001..mclk frequency = 1/210 * hmclk frequency 0b11010010..mclk frequency = 1/211 * hmclk frequency 0b11010011..mclk frequency = 1/212 * hmclk frequency 0b11010100..mclk frequency = 1/213 * hmclk frequency 0b11010101..mclk frequency = 1/214 * hmclk frequency 0b11010110..mclk frequency = 1/215 * hmclk frequency 0b11010111..mclk frequency = 1/216 * hmclk frequency 0b11011000..mclk frequency = 1/217 * hmclk frequency 0b11011001..mclk frequency = 1/218 * hmclk frequency 0b11011010..mclk frequency = 1/219 * hmclk frequency 0b11011011..mclk frequency = 1/220 * hmclk frequency 0b11011100..mclk frequency = 1/221 * hmclk frequency 0b11011101..mclk frequency = 1/222 * hmclk frequency 0b11011110..mclk frequency = 1/223 * hmclk frequency 0b11011111..mclk frequency = 1/224 * hmclk frequency 0b11100000..mclk frequency = 1/225 * hmclk frequency 0b11100001..mclk frequency = 1/226 * hmclk frequency 0b11100010..mclk frequency = 1/227 * hmclk frequency 0b11100011..mclk frequency = 1/228 * hmclk frequency 0b11100100..mclk frequency = 1/229 * hmclk frequency 0b11100101..mclk frequency = 1/230 * hmclk frequency 0b11100110..mclk frequency = 1/231 * hmclk frequency 0b11100111..mclk frequency = 1/232 * hmclk frequency 0b11101000..mclk frequency = 1/233 * hmclk frequency 0b11101001..mclk frequency = 1/234 * hmclk frequency 0b11101010..mclk frequency = 1/235 * hmclk frequency 0b11101011..mclk frequency = 1/236 * hmclk frequency 0b11101100..mclk frequency = 1/237 * hmclk frequency 0b11101101..mclk frequency = 1/238 * hmclk frequency 0b11101110..mclk frequency = 1/239 * hmclk frequency 0b11101111..mclk frequency = 1/240 * hmclk frequency 0b11110000..mclk frequency = 1/241 * hmclk frequency 0b11110001..mclk frequency = 1/242 * hmclk frequency 0b11110010..mclk frequency = 1/243 * hmclk frequency 0b11110011..mclk frequency = 1/244 * hmclk frequency 0b11110100..mclk frequency = 1/245 * hmclk frequency 0b11110101..mclk frequency = 1/246 * hmclk frequency 0b11110110..mclk frequency = 1/247 * hmclk frequency 0b11110111..mclk frequency = 1/248 * hmclk frequency 0b11111000..mclk frequency = 1/249 * hmclk frequency 0b11111001..mclk frequency = 1/250 * hmclk frequency 0b11111010..mclk frequency = 1/251 * hmclk frequency 0b11111011..mclk frequency = 1/252 * hmclk frequency 0b11111100..mclk frequency = 1/253 * hmclk frequency 0b11111101..mclk frequency = 1/254 * hmclk frequency 0b11111110..mclk frequency = 1/255 * hmclk frequency 0b11111111..mclk frequency = 1/256 * hmclk frequency

Definition at line 21299 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK

#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK   (0xFF0000U)

Definition at line 21039 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT

#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT   (16U)

Definition at line 21040 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_EN

#define IOMUXC_GPR_GPR2_MQS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)

MQS_EN 0b0..Disable MQS 0b1..Enable MQS

Definition at line 21313 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_EN_MASK

#define IOMUXC_GPR_GPR2_MQS_EN_MASK   (0x2000000U)

Definition at line 21307 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_EN_SHIFT

#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT   (25U)

Definition at line 21308 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_OVERSAMPLE

#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)

MQS_OVERSAMPLE 0b0..32 0b1..64

Definition at line 21320 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK

#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK   (0x4000000U)

Definition at line 21314 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT

#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT   (26U)

Definition at line 21315 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_SW_RST

#define IOMUXC_GPR_GPR2_MQS_SW_RST (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)

MQS_SW_RST 0b0..Exit software reset for MQS 0b1..Enable software reset for MQS

Definition at line 21306 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_SW_RST_MASK

#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK   (0x1000000U)

Definition at line 21300 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT

#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT   (24U)

Definition at line 21301 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)

QTIMER1_TMR_CNTS_FREEZE 0b0..timer counter work normally 0b1..reset counter and ouput flags

Definition at line 21327 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK

#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK   (0x10000000U)

Definition at line 21321 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT

#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT   (28U)

Definition at line 21322 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)

QTIMER2_TMR_CNTS_FREEZE 0b0..timer counter work normally 0b1..reset counter and ouput flags

Definition at line 21334 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK

#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK   (0x20000000U)

Definition at line 21328 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT

#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT   (29U)

Definition at line 21329 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)

QTIMER3_TMR_CNTS_FREEZE 0b0..timer counter work normally 0b1..reset counter and ouput flags

Definition at line 21341 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK

#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK   (0x40000000U)

Definition at line 21335 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT

#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT   (30U)

Definition at line 21336 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)

QTIMER4_TMR_CNTS_FREEZE 0b0..timer counter work normally 0b1..reset counter and ouput flags

Definition at line 21348 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK

#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK   (0x80000000U)

Definition at line 21342 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT

#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT   (31U)

Definition at line 21343 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_DCP_KEY_SEL

#define IOMUXC_GPR_GPR3_DCP_KEY_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)

DCP_KEY_SEL 0b0..Select [127:0] from snvs/ocotp key as dcp key 0b1..Select [255:128] from snvs/ocotp key as dcp key

Definition at line 21362 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK

#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK   (0x10U)

Definition at line 21356 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT

#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT   (4U)

Definition at line 21357 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_OCRAM_CTL

#define IOMUXC_GPR_GPR3_OCRAM_CTL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)

Definition at line 21355 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_OCRAM_CTL_MASK

#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK   (0xFU)

Definition at line 21353 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT

#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT   (0U)

Definition at line 21354 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_OCRAM_STATUS

#define IOMUXC_GPR_GPR3_OCRAM_STATUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)

OCRAM_STATUS 0b0000..read data pipeline configuration valid 0b0001..read data pipeline control bit changed

Definition at line 21369 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK

#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK   (0xF0000U)

Definition at line 21363 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT

#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT   (16U)

Definition at line 21364 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN1_STOP_ACK

#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)

CAN1_STOP_ACK 0b0..CAN1 stop acknowledge is not asserted 0b1..CAN1 stop acknowledge is asserted

Definition at line 21478 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK   (0x20000U)

Definition at line 21472 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT   (17U)

Definition at line 21473 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN1_STOP_REQ

#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)

CAN1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21387 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK   (0x2U)

Definition at line 21381 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT   (1U)

Definition at line 21382 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN2_STOP_ACK

#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)

CAN2_STOP_ACK 0b0..CAN2 stop acknowledge is not asserted 0b1..CAN2 stop acknowledge is asserted

Definition at line 21485 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK   (0x40000U)

Definition at line 21479 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT   (18U)

Definition at line 21480 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN2_STOP_REQ

#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)

CAN2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21394 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK   (0x4U)

Definition at line 21388 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT   (2U)

Definition at line 21389 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_EDMA_STOP_ACK

#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)

EDMA_STOP_ACK 0b0..EDMA stop acknowledge is not asserted 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode).

Definition at line 21471 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK   (0x10000U)

Definition at line 21465 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT   (16U)

Definition at line 21466 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_EDMA_STOP_REQ

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)

EDMA_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21380 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK   (0x1U)

Definition at line 21374 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT   (0U)

Definition at line 21375 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_ENET_STOP_ACK

#define IOMUXC_GPR_GPR4_ENET_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)

ENET_STOP_ACK 0b0..ENET stop acknowledge is not asserted 0b1..ENET stop acknowledge is asserted

Definition at line 21499 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK   (0x100000U)

Definition at line 21493 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT   (20U)

Definition at line 21494 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_ENET_STOP_REQ

#define IOMUXC_GPR_GPR4_ENET_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)

ENET_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21408 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK   (0x10U)

Definition at line 21402 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT   (4U)

Definition at line 21403 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)

FLEXIO1_STOP_ACK 0b0..FLEXIO1 stop acknowledge is not asserted 0b1..FLEXIO1 stop acknowledge is asserted

Definition at line 21548 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK   (0x10000000U)

Definition at line 21542 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT   (28U)

Definition at line 21543 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)

FLEXIO1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21457 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK   (0x1000U)

Definition at line 21451 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT   (12U)

Definition at line 21452 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)

FLEXIO2_STOP_ACK 0b0..FLEXIO2 stop acknowledge is not asserted 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode)

Definition at line 21555 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK   (0x20000000U)

Definition at line 21549 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT   (29U)

Definition at line 21550 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)

FLEXIO2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21464 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK   (0x2000U)

Definition at line 21458 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT   (13U)

Definition at line 21459 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)

FLEXSPI_STOP_ACK 0b0..FLEXSPI stop acknowledge is not asserted 0b1..FLEXSPI stop acknowledge is asserted

Definition at line 21541 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK   (0x8000000U)

Definition at line 21535 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT   (27U)

Definition at line 21536 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)

FLEXSPI_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21450 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK   (0x800U)

Definition at line 21444 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT   (11U)

Definition at line 21445 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_PIT_STOP_ACK

#define IOMUXC_GPR_GPR4_PIT_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)

PIT_STOP_ACK 0b0..PIT stop acknowledge is not asserted 0b1..PIT stop acknowledge is asserted

Definition at line 21534 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK   (0x4000000U)

Definition at line 21528 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT   (26U)

Definition at line 21529 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_PIT_STOP_REQ

#define IOMUXC_GPR_GPR4_PIT_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)

PIT_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21443 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK   (0x400U)

Definition at line 21437 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT   (10U)

Definition at line 21438 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI1_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)

SAI1_STOP_ACK 0b0..SAI1 stop acknowledge is not asserted 0b1..SAI1 stop acknowledge is asserted

Definition at line 21506 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK   (0x200000U)

Definition at line 21500 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT   (21U)

Definition at line 21501 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI1_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)

SAI1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21415 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK   (0x20U)

Definition at line 21409 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT   (5U)

Definition at line 21410 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI2_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)

SAI2_STOP_ACK 0b0..SAI2 stop acknowledge is not asserted 0b1..SAI2 stop acknowledge is asserted

Definition at line 21513 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK   (0x400000U)

Definition at line 21507 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT   (22U)

Definition at line 21508 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI2_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)

SAI2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21422 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK   (0x40U)

Definition at line 21416 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT   (6U)

Definition at line 21417 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI3_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)

SAI3_STOP_ACK 0b0..SAI3 stop acknowledge is not asserted 0b1..SAI3 stop acknowledge is asserted

Definition at line 21520 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK   (0x800000U)

Definition at line 21514 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT   (23U)

Definition at line 21515 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI3_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)

SAI3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21429 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK   (0x80U)

Definition at line 21423 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT   (7U)

Definition at line 21424 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SEMC_STOP_ACK

#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)

SEMC_STOP_ACK 0b0..SEMC stop acknowledge is not asserted 0b1..SEMC stop acknowledge is asserted

Definition at line 21527 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK   (0x2000000U)

Definition at line 21521 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT   (25U)

Definition at line 21522 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SEMC_STOP_REQ

#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)

SEMC_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21436 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK   (0x200U)

Definition at line 21430 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT   (9U)

Definition at line 21431 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_TRNG_STOP_ACK

#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)

TRNG_STOP_ACK 0b0..TRNG stop acknowledge is not asserted 0b1..TRNG stop acknowledge is asserted

Definition at line 21492 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK   (0x80000U)

Definition at line 21486 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT   (19U)

Definition at line 21487 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_TRNG_STOP_REQ

#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)

TRNG_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21401 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK   (0x8U)

Definition at line 21395 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT   (3U)

Definition at line 21396 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL

#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)

ENET_EVENT3IN_SEL 0b0..event3 source input from pad 0b1..event3 source input from gpt2.ipp_do_cmpout1

Definition at line 21587 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK

#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK   (0x2000000U)

Definition at line 21581 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT

#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT   (25U)

Definition at line 21582 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL

#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)

GPT2_CAPIN1_SEL 0b0..source from pad 0b1..source from enet1.ipp_do_mac0_timer[3]

Definition at line 21580 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK

#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK   (0x800000U)

Definition at line 21574 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT

#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT   (23U)

Definition at line 21575 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)

VREF_1M_CLK_GPT1 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock

Definition at line 21594 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK   (0x10000000U)

Definition at line 21588 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT   (28U)

Definition at line 21589 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)

VREF_1M_CLK_GPT2 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock

Definition at line 21601 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK   (0x20000000U)

Definition at line 21595 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT   (29U)

Definition at line 21596 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_WDOG1_MASK

#define IOMUXC_GPR_GPR5_WDOG1_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)

WDOG1_MASK 0b0..WDOG1 Timeout behaves normally 0b1..WDOG1 Timeout is masked

Definition at line 21566 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_WDOG1_MASK_MASK

#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK   (0x40U)

Definition at line 21560 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT

#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT   (6U)

Definition at line 21561 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_WDOG2_MASK

#define IOMUXC_GPR_GPR5_WDOG2_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)

WDOG2_MASK 0b0..WDOG2 Timeout behaves normally 0b1..WDOG2 Timeout is masked

Definition at line 21573 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_WDOG2_MASK_MASK

#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK   (0x80U)

Definition at line 21567 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT

#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT   (7U)

Definition at line 21568 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)

IOMUXC_XBAR_DIR_SEL_10 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21766 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK   (0x400000U)

Definition at line 21760 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT   (22U)

Definition at line 21761 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)

IOMUXC_XBAR_DIR_SEL_11 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21773 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK   (0x800000U)

Definition at line 21767 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT   (23U)

Definition at line 21768 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)

IOMUXC_XBAR_DIR_SEL_12 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21780 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK   (0x1000000U)

Definition at line 21774 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT   (24U)

Definition at line 21775 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)

IOMUXC_XBAR_DIR_SEL_13 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21787 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK   (0x2000000U)

Definition at line 21781 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT   (25U)

Definition at line 21782 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)

IOMUXC_XBAR_DIR_SEL_14 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21794 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK   (0x4000000U)

Definition at line 21788 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT   (26U)

Definition at line 21789 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)

IOMUXC_XBAR_DIR_SEL_15 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21801 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK   (0x8000000U)

Definition at line 21795 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT   (27U)

Definition at line 21796 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)

IOMUXC_XBAR_DIR_SEL_16 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21808 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK   (0x10000000U)

Definition at line 21802 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT   (28U)

Definition at line 21803 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)

IOMUXC_XBAR_DIR_SEL_17 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21815 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK   (0x20000000U)

Definition at line 21809 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT   (29U)

Definition at line 21810 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)

IOMUXC_XBAR_DIR_SEL_18 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21822 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK   (0x40000000U)

Definition at line 21816 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT   (30U)

Definition at line 21817 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)

IOMUXC_XBAR_DIR_SEL_19 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21829 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK   (0x80000000U)

Definition at line 21823 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT   (31U)

Definition at line 21824 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)

IOMUXC_XBAR_DIR_SEL_4 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21724 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK   (0x10000U)

Definition at line 21718 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT   (16U)

Definition at line 21719 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)

IOMUXC_XBAR_DIR_SEL_5 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21731 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK   (0x20000U)

Definition at line 21725 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT   (17U)

Definition at line 21726 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)

IOMUXC_XBAR_DIR_SEL_6 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21738 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK   (0x40000U)

Definition at line 21732 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT   (18U)

Definition at line 21733 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)

IOMUXC_XBAR_DIR_SEL_7 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21745 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK   (0x80000U)

Definition at line 21739 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT   (19U)

Definition at line 21740 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)

IOMUXC_XBAR_DIR_SEL_8 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21752 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK   (0x100000U)

Definition at line 21746 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT   (20U)

Definition at line 21747 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)

IOMUXC_XBAR_DIR_SEL_9 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 21759 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK   (0x200000U)

Definition at line 21753 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT   (21U)

Definition at line 21754 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)

QTIMER1_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21612 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK   (0x1U)

Definition at line 21606 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT   (0U)

Definition at line 21607 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)

QTIMER1_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21619 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK   (0x2U)

Definition at line 21613 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT   (1U)

Definition at line 21614 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)

QTIMER1_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21626 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK   (0x4U)

Definition at line 21620 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT   (2U)

Definition at line 21621 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)

QTIMER1_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21633 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK   (0x8U)

Definition at line 21627 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT   (3U)

Definition at line 21628 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)

QTIMER2_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21640 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK   (0x10U)

Definition at line 21634 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT   (4U)

Definition at line 21635 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)

QTIMER2_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21647 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK   (0x20U)

Definition at line 21641 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT   (5U)

Definition at line 21642 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)

QTIMER2_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21654 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK   (0x40U)

Definition at line 21648 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT   (6U)

Definition at line 21649 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)

QTIMER2_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21661 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK   (0x80U)

Definition at line 21655 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT   (7U)

Definition at line 21656 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)

QTIMER3_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21668 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK   (0x100U)

Definition at line 21662 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT   (8U)

Definition at line 21663 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)

QTIMER3_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21675 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK   (0x200U)

Definition at line 21669 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT   (9U)

Definition at line 21670 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)

QTIMER3_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21682 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK   (0x400U)

Definition at line 21676 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT   (10U)

Definition at line 21677 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)

QTIMER3_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21689 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK   (0x800U)

Definition at line 21683 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT   (11U)

Definition at line 21684 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)

QTIMER4_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21696 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK   (0x1000U)

Definition at line 21690 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT   (12U)

Definition at line 21691 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)

QTIMER4_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21703 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK   (0x2000U)

Definition at line 21697 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT   (13U)

Definition at line 21698 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)

QTIMER4_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21710 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK   (0x4000U)

Definition at line 21704 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT   (14U)

Definition at line 21705 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)

QTIMER4_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 21717 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK   (0x8000U)

Definition at line 21711 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT   (15U)

Definition at line 21712 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)

LPI2C1_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted (the module is in Stop mode)

Definition at line 21952 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK   (0x10000U)

Definition at line 21946 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT   (16U)

Definition at line 21947 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)

LPI2C1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21840 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK   (0x1U)

Definition at line 21834 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT   (0U)

Definition at line 21835 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)

LPI2C2_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 21959 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK   (0x20000U)

Definition at line 21953 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT   (17U)

Definition at line 21954 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)

LPI2C2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21847 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK   (0x2U)

Definition at line 21841 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT   (1U)

Definition at line 21842 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)

LPI2C3_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 21966 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK   (0x40000U)

Definition at line 21960 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT   (18U)

Definition at line 21961 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)

LPI2C3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21854 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK   (0x4U)

Definition at line 21848 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT   (2U)

Definition at line 21849 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)

LPI2C4_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 21973 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK   (0x80000U)

Definition at line 21967 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT   (19U)

Definition at line 21968 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)

LPI2C4_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21861 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK   (0x8U)

Definition at line 21855 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT   (3U)

Definition at line 21856 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)

LPSPI1_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 21980 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK   (0x100000U)

Definition at line 21974 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT   (20U)

Definition at line 21975 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)

LPSPI1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21868 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK   (0x10U)

Definition at line 21862 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT   (4U)

Definition at line 21863 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)

LPSPI2_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 21987 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK   (0x200000U)

Definition at line 21981 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT   (21U)

Definition at line 21982 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)

LPSPI2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21875 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK   (0x20U)

Definition at line 21869 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT   (5U)

Definition at line 21870 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)

LPSPI3_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 21994 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK   (0x400000U)

Definition at line 21988 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT   (22U)

Definition at line 21989 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)

LPSPI3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21882 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK   (0x40U)

Definition at line 21876 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT   (6U)

Definition at line 21877 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)

LPSPI4_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 22001 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK   (0x800000U)

Definition at line 21995 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT   (23U)

Definition at line 21996 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)

LPSPI4_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21889 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK   (0x80U)

Definition at line 21883 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT   (7U)

Definition at line 21884 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)

LPUART1_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 22008 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK   (0x1000000U)

Definition at line 22002 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT   (24U)

Definition at line 22003 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)

LPUART1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21896 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK   (0x100U)

Definition at line 21890 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT   (8U)

Definition at line 21891 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)

LPUART2_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 22015 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK   (0x2000000U)

Definition at line 22009 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT   (25U)

Definition at line 22010 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)

LPUART2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21903 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK   (0x200U)

Definition at line 21897 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT   (9U)

Definition at line 21898 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)

LPUART3_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 22022 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK   (0x4000000U)

Definition at line 22016 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT   (26U)

Definition at line 22017 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)

LPUART3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21910 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK   (0x400U)

Definition at line 21904 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT   (10U)

Definition at line 21905 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)

LPUART4_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 22029 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK   (0x8000000U)

Definition at line 22023 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT   (27U)

Definition at line 22024 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)

LPUART4_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21917 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK   (0x800U)

Definition at line 21911 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT   (11U)

Definition at line 21912 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART5_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)

LPUART5_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 22036 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK   (0x10000000U)

Definition at line 22030 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT   (28U)

Definition at line 22031 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART5_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)

LPUART5_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21924 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK   (0x1000U)

Definition at line 21918 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT   (12U)

Definition at line 21919 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART6_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)

LPUART6_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 22043 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK   (0x20000000U)

Definition at line 22037 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT   (29U)

Definition at line 22038 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART6_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)

LPUART6_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21931 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK   (0x2000U)

Definition at line 21925 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT   (13U)

Definition at line 21926 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART7_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)

LPUART7_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 22050 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK   (0x40000000U)

Definition at line 22044 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT   (30U)

Definition at line 22045 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART7_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)

LPUART7_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21938 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK   (0x4000U)

Definition at line 21932 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT   (14U)

Definition at line 21933 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART8_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)

LPUART8_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted (the module is in Stop mode)

Definition at line 22057 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK   (0x80000000U)

Definition at line 22051 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT   (31U)

Definition at line 22052 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART8_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)

LPUART8_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 21945 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK   (0x8000U)

Definition at line 21939 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT   (15U)

Definition at line 21940 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)

LPI2C1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22075 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK   (0x2U)

Definition at line 22069 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT   (1U)

Definition at line 22070 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)

LPI2C1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22068 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK   (0x1U)

Definition at line 22062 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT   (0U)

Definition at line 22063 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)

LPI2C2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22089 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK   (0x8U)

Definition at line 22083 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT   (3U)

Definition at line 22084 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)

LPI2C2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22082 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK   (0x4U)

Definition at line 22076 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT   (2U)

Definition at line 22077 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)

LPI2C3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22103 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK   (0x20U)

Definition at line 22097 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT   (5U)

Definition at line 22098 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)

LPI2C3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22096 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK   (0x10U)

Definition at line 22090 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT   (4U)

Definition at line 22091 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)

LPI2C4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22117 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK   (0x80U)

Definition at line 22111 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT   (7U)

Definition at line 22112 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)

LPI2C4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22110 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK   (0x40U)

Definition at line 22104 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT   (6U)

Definition at line 22105 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)

LPSPI1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22131 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK   (0x200U)

Definition at line 22125 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT   (9U)

Definition at line 22126 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)

LPSPI1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22124 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK   (0x100U)

Definition at line 22118 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT   (8U)

Definition at line 22119 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)

LPSPI2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22145 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK   (0x800U)

Definition at line 22139 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT   (11U)

Definition at line 22140 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)

LPSPI2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22138 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK   (0x400U)

Definition at line 22132 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT   (10U)

Definition at line 22133 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)

LPSPI3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22159 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK   (0x2000U)

Definition at line 22153 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT   (13U)

Definition at line 22154 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)

LPSPI3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22152 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK   (0x1000U)

Definition at line 22146 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT   (12U)

Definition at line 22147 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)

LPSPI4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22173 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK   (0x8000U)

Definition at line 22167 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT   (15U)

Definition at line 22168 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)

LPSPI4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22166 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK   (0x4000U)

Definition at line 22160 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT   (14U)

Definition at line 22161 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)

LPUART1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22187 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK   (0x20000U)

Definition at line 22181 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT   (17U)

Definition at line 22182 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)

LPUART1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22180 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK   (0x10000U)

Definition at line 22174 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT   (16U)

Definition at line 22175 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)

LPUART2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22201 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK   (0x80000U)

Definition at line 22195 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT   (19U)

Definition at line 22196 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)

LPUART2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22194 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK   (0x40000U)

Definition at line 22188 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT   (18U)

Definition at line 22189 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)

LPUART3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22215 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK   (0x200000U)

Definition at line 22209 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT   (21U)

Definition at line 22210 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)

LPUART3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22208 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK   (0x100000U)

Definition at line 22202 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT   (20U)

Definition at line 22203 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)

LPUART4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22229 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK   (0x800000U)

Definition at line 22223 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT   (23U)

Definition at line 22224 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)

LPUART4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22222 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK   (0x400000U)

Definition at line 22216 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT   (22U)

Definition at line 22217 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)

LPUART5_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22243 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK   (0x2000000U)

Definition at line 22237 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT   (25U)

Definition at line 22238 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)

LPUART5_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22236 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK   (0x1000000U)

Definition at line 22230 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT   (24U)

Definition at line 22231 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)

LPUART6_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22257 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK   (0x8000000U)

Definition at line 22251 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT   (27U)

Definition at line 22252 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)

LPUART6_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22250 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK   (0x4000000U)

Definition at line 22244 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT   (26U)

Definition at line 22245 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)

LPUART7_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22271 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK   (0x20000000U)

Definition at line 22265 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT   (29U)

Definition at line 22266 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)

LPUART7_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22264 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK   (0x10000000U)

Definition at line 22258 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT   (28U)

Definition at line 22259 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)

LPUART8_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 22285 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK   (0x80000000U)

Definition at line 22279 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT   (31U)

Definition at line 22280 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)

LPUART8_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 22278 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK   (0x40000000U)

Definition at line 22272 of file MIMXRT1052.h.

◆ IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT   (30U)

Definition at line 22273 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL

#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)

Definition at line 23334 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK   (0x10000U)

Definition at line 23332 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT   (16U)

Definition at line 23333 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)

Definition at line 23337 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK   (0x20000U)

Definition at line 23335 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT   (17U)

Definition at line 23336 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)

Definition at line 23340 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK   (0x40000U)

Definition at line 23338 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT   (18U)

Definition at line 23339 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)

DCDC_STATUS_CAPT_CLR - DCDC captured status clear

Definition at line 23328 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK   (0x2U)

Definition at line 23324 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT   (1U)

Definition at line 23325 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)

Definition at line 23343 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK   (0x80000U)

Definition at line 23341 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT   (19U)

Definition at line 23342 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE

#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)

Definition at line 23323 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK

#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK   (0x1U)

Definition at line 23321 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT   (0U)

Definition at line 23322 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE

#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)

Definition at line 23331 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK

#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK   (0xCU)

Definition at line 23329 of file MIMXRT1052.h.

◆ IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT   (2U)

Definition at line 23330 of file MIMXRT1052.h.


picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:10