same70n20b.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70N20B_
36 #define _SAME70N20B_
37 
46 
47 #ifdef __cplusplus
48  extern "C" {
49 #endif
50 
51 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
52 #include <stdint.h>
53 #endif
54 
55 /* ************************************************************************** */
56 /* CMSIS DEFINITIONS FOR SAME70N20B */
57 /* ************************************************************************** */
60 
62 typedef enum IRQn
63 {
64 /****** Cortex-M7 Processor Exceptions Numbers ******************************/
65  NonMaskableInt_IRQn = -14,
66  HardFault_IRQn = -13,
67  MemoryManagement_IRQn = -12,
68  BusFault_IRQn = -11,
69  UsageFault_IRQn = -10,
70  SVCall_IRQn = -5,
71  DebugMonitor_IRQn = -4,
72  PendSV_IRQn = -2,
73  SysTick_IRQn = -1,
74 /****** SAME70N20B specific Interrupt Numbers *********************************/
75 
76  SUPC_IRQn = 0,
77  RSTC_IRQn = 1,
78  RTC_IRQn = 2,
79  RTT_IRQn = 3,
80  WDT_IRQn = 4,
81  PMC_IRQn = 5,
82  EFC_IRQn = 6,
83  UART0_IRQn = 7,
84  UART1_IRQn = 8,
85  PIOA_IRQn = 10,
86  PIOB_IRQn = 11,
87  USART0_IRQn = 13,
88  USART1_IRQn = 14,
89  USART2_IRQn = 15,
90  PIOD_IRQn = 16,
91  HSMCI_IRQn = 18,
92  TWIHS0_IRQn = 19,
93  TWIHS1_IRQn = 20,
94  SPI0_IRQn = 21,
95  SSC_IRQn = 22,
96  TC0_IRQn = 23,
97  TC1_IRQn = 24,
98  TC2_IRQn = 25,
99  AFEC0_IRQn = 29,
100  DACC_IRQn = 30,
101  PWM0_IRQn = 31,
102  ICM_IRQn = 32,
103  ACC_IRQn = 33,
104  USBHS_IRQn = 34,
105  MCAN0_INT0_IRQn = 35,
106  MCAN0_INT1_IRQn = 36,
107  MCAN1_INT0_IRQn = 37,
108  MCAN1_INT1_IRQn = 38,
109  GMAC_IRQn = 39,
110  AFEC1_IRQn = 40,
111  TWIHS2_IRQn = 41,
112  QSPI_IRQn = 43,
113  UART2_IRQn = 44,
114  UART3_IRQn = 45,
115  UART4_IRQn = 46,
116  TC9_IRQn = 50,
117  TC10_IRQn = 51,
118  TC11_IRQn = 52,
119  AES_IRQn = 56,
120  TRNG_IRQn = 57,
121  XDMAC_IRQn = 58,
122  ISI_IRQn = 59,
123  PWM1_IRQn = 60,
124  FPU_IRQn = 61,
125  RSWDT_IRQn = 63,
126  CCW_IRQn = 64,
127  CCF_IRQn = 65,
128  GMAC_Q1_IRQn = 66,
129  GMAC_Q2_IRQn = 67,
130  IXC_IRQn = 68,
131  I2SC0_IRQn = 69,
132  GMAC_Q3_IRQn = 71,
133  GMAC_Q4_IRQn = 72,
134  GMAC_Q5_IRQn = 73,
136  PERIPH_COUNT_IRQn = 74
137 } IRQn_Type;
138 
139 typedef struct _DeviceVectors
140 {
141  /* Stack pointer */
142  void* pvStack;
143 
144  /* Cortex-M handlers */
145  void* pfnReset_Handler;
146  void* pfnNMI_Handler;
147  void* pfnHardFault_Handler;
148  void* pfnMemManage_Handler;
149  void* pfnBusFault_Handler;
150  void* pfnUsageFault_Handler;
151  void* pfnReserved1_Handler;
152  void* pfnReserved2_Handler;
153  void* pfnReserved3_Handler;
154  void* pfnReserved4_Handler;
155  void* pfnSVC_Handler;
156  void* pfnDebugMon_Handler;
157  void* pfnReserved5_Handler;
158  void* pfnPendSV_Handler;
159  void* pfnSysTick_Handler;
160 
161  /* Peripheral handlers */
162  void* pfnSUPC_Handler; /* 0 Supply Controller */
163  void* pfnRSTC_Handler; /* 1 Reset Controller */
164  void* pfnRTC_Handler; /* 2 Real Time Clock */
165  void* pfnRTT_Handler; /* 3 Real Time Timer */
166  void* pfnWDT_Handler; /* 4 Watchdog Timer */
167  void* pfnPMC_Handler; /* 5 Power Management Controller */
168  void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
169  void* pfnUART0_Handler; /* 7 UART 0 */
170  void* pfnUART1_Handler; /* 8 UART 1 */
171  void* pvReserved9;
172  void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
173  void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
174  void* pvReserved12;
175  void* pfnUSART0_Handler; /* 13 USART 0 */
176  void* pfnUSART1_Handler; /* 14 USART 1 */
177  void* pfnUSART2_Handler; /* 15 USART 2 */
178  void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
179  void* pvReserved17;
180  void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
181  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
182  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
183  void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
184  void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
185  void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
186  void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
187  void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
188  void* pvReserved26;
189  void* pvReserved27;
190  void* pvReserved28;
191  void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
192  void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
193  void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
194  void* pfnICM_Handler; /* 32 Integrity Check Monitor */
195  void* pfnACC_Handler; /* 33 Analog Comparator */
196  void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
197  void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */
198  void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */
199  void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */
200  void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */
201  void* pfnGMAC_Handler; /* 39 Ethernet MAC */
202  void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
203  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
204  void* pvReserved42;
205  void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
206  void* pfnUART2_Handler; /* 44 UART 2 */
207  void* pfnUART3_Handler; /* 45 UART 3 */
208  void* pfnUART4_Handler; /* 46 UART 4 */
209  void* pvReserved47;
210  void* pvReserved48;
211  void* pvReserved49;
212  void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
213  void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
214  void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
215  void* pvReserved53;
216  void* pvReserved54;
217  void* pvReserved55;
218  void* pfnAES_Handler; /* 56 AES */
219  void* pfnTRNG_Handler; /* 57 True Random Generator */
220  void* pfnXDMAC_Handler; /* 58 DMA */
221  void* pfnISI_Handler; /* 59 Camera Interface */
222  void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
223  void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */
224  void* pvReserved62;
225  void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */
226  void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */
227  void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */
228  void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */
229  void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */
230  void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */
231  void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */
232  void* pvReserved70;
233  void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */
234  void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */
235  void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */
236 } DeviceVectors;
237 
238 /* Cortex-M7 core handlers */
239 void Reset_Handler ( void );
240 void NMI_Handler ( void );
241 void HardFault_Handler ( void );
242 void MemManage_Handler ( void );
243 void BusFault_Handler ( void );
244 void UsageFault_Handler ( void );
245 void SVC_Handler ( void );
246 void DebugMon_Handler ( void );
247 void PendSV_Handler ( void );
248 void SysTick_Handler ( void );
249 
250 /* Peripherals handlers */
251 void ACC_Handler ( void );
252 void AES_Handler ( void );
253 void AFEC0_Handler ( void );
254 void AFEC1_Handler ( void );
255 void CCF_Handler ( void );
256 void CCW_Handler ( void );
257 void DACC_Handler ( void );
258 void EFC_Handler ( void );
259 void FPU_Handler ( void );
260 void GMAC_Handler ( void );
261 void HSMCI_Handler ( void );
262 void ICM_Handler ( void );
263 void ISI_Handler ( void );
264 void I2SC0_Handler ( void );
265 void IXC_Handler ( void );
266 void MCAN0_INT0_Handler ( void );
267 void MCAN0_INT1_Handler ( void );
268 void MCAN1_INT0_Handler ( void );
269 void MCAN1_INT1_Handler ( void );
270 void MCAN0_Handler ( void );
271 void MCAN1_Handler ( void );
272 void PIOA_Handler ( void );
273 void PIOB_Handler ( void );
274 void PIOD_Handler ( void );
275 void PMC_Handler ( void );
276 void PWM0_Handler ( void );
277 void PWM1_Handler ( void );
278 void GMAC_Q1_Handler ( void );
279 void GMAC_Q2_Handler ( void );
280 void GMAC_Q3_Handler ( void );
281 void GMAC_Q4_Handler ( void );
282 void GMAC_Q5_Handler ( void );
283 void QSPI_Handler ( void );
284 void RSTC_Handler ( void );
285 void RSWDT_Handler ( void );
286 void RTC_Handler ( void );
287 void RTT_Handler ( void );
288 void SPI0_Handler ( void );
289 void SSC_Handler ( void );
290 void SUPC_Handler ( void );
291 void TC0_Handler ( void );
292 void TC1_Handler ( void );
293 void TC2_Handler ( void );
294 void TC9_Handler ( void );
295 void TC10_Handler ( void );
296 void TC11_Handler ( void );
297 void TRNG_Handler ( void );
298 void TWIHS0_Handler ( void );
299 void TWIHS1_Handler ( void );
300 void TWIHS2_Handler ( void );
301 void UART0_Handler ( void );
302 void UART1_Handler ( void );
303 void UART2_Handler ( void );
304 void UART3_Handler ( void );
305 void UART4_Handler ( void );
306 void USART0_Handler ( void );
307 void USART1_Handler ( void );
308 void USART2_Handler ( void );
309 void USBHS_Handler ( void );
310 void WDT_Handler ( void );
311 void XDMAC_Handler ( void );
312 
317 #define __CM7_REV 0x0000
318 #define __MPU_PRESENT 1
319 #define __NVIC_PRIO_BITS 3
320 #define __FPU_PRESENT 1
321 #define __FPU_DP 1
322 #define __ICACHE_PRESENT 1
323 #define __DCACHE_PRESENT 1
324 #define __DTCM_PRESENT 1
325 #define __ITCM_PRESENT 1
326 #define __Vendor_SysTickConfig 0
327 #define __SAM_M7_REVB 1
329 /*
330  * \brief CMSIS includes
331  */
332 
333 #include <core_cm7.h>
334 #if !defined DONT_USE_CMSIS_INIT
335 #include "system_same70.h"
336 #endif /* DONT_USE_CMSIS_INIT */
337 
340 /* ************************************************************************** */
342 /* ************************************************************************** */
345 
346 #include "component/acc.h"
347 #include "component/aes.h"
348 #include "component/afec.h"
349 #include "component/chipid.h"
350 #include "component/dacc.h"
351 #include "component/efc.h"
352 #include "component/gmac.h"
353 #include "component/gpbr.h"
354 #include "component/hsmci.h"
355 #include "component/i2sc.h"
356 #include "component/icm.h"
357 #include "component/isi.h"
358 #include "component/matrix.h"
359 #include "component/mcan.h"
360 #include "component/pio.h"
361 #include "component/pmc.h"
362 #include "component/pwm.h"
363 #include "component/qspi.h"
364 #include "component/rstc.h"
365 #include "component/rswdt.h"
366 #include "component/rtc.h"
367 #include "component/rtt.h"
368 #include "component/spi.h"
369 #include "component/ssc.h"
370 #include "component/supc.h"
371 #include "component/tc.h"
372 #include "component/trng.h"
373 #include "component/twihs.h"
374 #include "component/uart.h"
375 #include "component/usart.h"
376 #include "component/usbhs.h"
377 #include "component/utmi.h"
378 #include "component/wdt.h"
379 #include "component/xdmac.h"
382 /* ************************************************************************** */
383 /* REGISTER ACCESS DEFINITIONS FOR SAME70N20B */
384 /* ************************************************************************** */
387 
388 #include "instance/hsmci.h"
389 #include "instance/ssc.h"
390 #include "instance/spi0.h"
391 #include "instance/tc0.h"
392 #include "instance/twihs0.h"
393 #include "instance/twihs1.h"
394 #include "instance/pwm0.h"
395 #include "instance/usart0.h"
396 #include "instance/usart1.h"
397 #include "instance/usart2.h"
398 #include "instance/mcan0.h"
399 #include "instance/mcan1.h"
400 #include "instance/usbhs.h"
401 #include "instance/afec0.h"
402 #include "instance/dacc.h"
403 #include "instance/acc.h"
404 #include "instance/icm.h"
405 #include "instance/isi.h"
406 #include "instance/gmac.h"
407 #include "instance/tc3.h"
408 #include "instance/pwm1.h"
409 #include "instance/twihs2.h"
410 #include "instance/afec1.h"
411 #include "instance/aes.h"
412 #include "instance/trng.h"
413 #include "instance/xdmac.h"
414 #include "instance/qspi.h"
415 #include "instance/matrix.h"
416 #include "instance/i2sc0.h"
417 #include "instance/utmi.h"
418 #include "instance/pmc.h"
419 #include "instance/uart0.h"
420 #include "instance/chipid.h"
421 #include "instance/uart1.h"
422 #include "instance/efc.h"
423 #include "instance/pioa.h"
424 #include "instance/piob.h"
425 #include "instance/piod.h"
426 #include "instance/rstc.h"
427 #include "instance/supc.h"
428 #include "instance/rtt.h"
429 #include "instance/wdt.h"
430 #include "instance/rtc.h"
431 #include "instance/gpbr.h"
432 #include "instance/rswdt.h"
433 #include "instance/uart2.h"
434 #include "instance/uart3.h"
435 #include "instance/uart4.h"
438 /* ************************************************************************** */
439 /* PERIPHERAL ID DEFINITIONS FOR SAME70N20B */
440 /* ************************************************************************** */
443 
444 #define ID_SUPC ( 0)
445 #define ID_RSTC ( 1)
446 #define ID_RTC ( 2)
447 #define ID_RTT ( 3)
448 #define ID_WDT ( 4)
449 #define ID_PMC ( 5)
450 #define ID_EFC ( 6)
451 #define ID_UART0 ( 7)
452 #define ID_UART1 ( 8)
453 #define ID_PIOA (10)
454 #define ID_PIOB (11)
455 #define ID_USART0 (13)
456 #define ID_USART1 (14)
457 #define ID_USART2 (15)
458 #define ID_PIOD (16)
459 #define ID_HSMCI (18)
460 #define ID_TWIHS0 (19)
461 #define ID_TWIHS1 (20)
462 #define ID_SPI0 (21)
463 #define ID_SSC (22)
464 #define ID_TC0 (23)
465 #define ID_TC1 (24)
466 #define ID_TC2 (25)
467 #define ID_AFEC0 (29)
468 #define ID_DACC (30)
469 #define ID_PWM0 (31)
470 #define ID_ICM (32)
471 #define ID_ACC (33)
472 #define ID_USBHS (34)
473 #define ID_MCAN0 (35)
474 #define ID_MCAN1 (37)
475 #define ID_GMAC (39)
476 #define ID_AFEC1 (40)
477 #define ID_TWIHS2 (41)
478 #define ID_QSPI (43)
479 #define ID_UART2 (44)
480 #define ID_UART3 (45)
481 #define ID_UART4 (46)
482 #define ID_TC9 (50)
483 #define ID_TC10 (51)
484 #define ID_TC11 (52)
485 #define ID_AES (56)
486 #define ID_TRNG (57)
487 #define ID_XDMAC (58)
488 #define ID_ISI (59)
489 #define ID_PWM1 (60)
490 #define ID_RSWDT (63)
491 #define ID_IXC (68)
492 #define ID_I2SC0 (69)
494 #define ID_PERIPH_COUNT (74)
496 
497 /* ************************************************************************** */
498 /* BASE ADDRESS DEFINITIONS FOR SAME70N20B */
499 /* ************************************************************************** */
502 
503 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
504 #define HSMCI (0x40000000U)
505 #define SSC (0x40004000U)
506 #define SPI0 (0x40008000U)
507 #define TC0 (0x4000C000U)
508 #define TWIHS0 (0x40018000U)
509 #define TWIHS1 (0x4001C000U)
510 #define PWM0 (0x40020000U)
511 #define USART0 (0x40024000U)
512 #define USART1 (0x40028000U)
513 #define USART2 (0x4002C000U)
514 #define MCAN0 (0x40030000U)
515 #define MCAN1 (0x40034000U)
516 #define USBHS (0x40038000U)
517 #define AFEC0 (0x4003C000U)
518 #define DACC (0x40040000U)
519 #define ACC (0x40044000U)
520 #define ICM (0x40048000U)
521 #define ISI (0x4004C000U)
522 #define GMAC (0x40050000U)
523 #define TC3 (0x40054000U)
524 #define PWM1 (0x4005C000U)
525 #define TWIHS2 (0x40060000U)
526 #define AFEC1 (0x40064000U)
527 #define AES (0x4006C000U)
528 #define TRNG (0x40070000U)
529 #define XDMAC (0x40078000U)
530 #define QSPI (0x4007C000U)
531 #define MATRIX (0x40088000U)
532 #define I2SC0 (0x4008C000U)
533 #define UTMI (0x400E0400U)
534 #define PMC (0x400E0600U)
535 #define UART0 (0x400E0800U)
536 #define CHIPID (0x400E0940U)
537 #define UART1 (0x400E0A00U)
538 #define EFC (0x400E0C00U)
539 #define PIOA (0x400E0E00U)
540 #define PIOB (0x400E1000U)
541 #define PIOD (0x400E1400U)
542 #define RSTC (0x400E1800U)
543 #define SUPC (0x400E1810U)
544 #define RTT (0x400E1830U)
545 #define WDT (0x400E1850U)
546 #define RTC (0x400E1860U)
547 #define GPBR (0x400E1890U)
548 #define RSWDT (0x400E1900U)
549 #define UART2 (0x400E1A00U)
550 #define UART3 (0x400E1C00U)
551 #define UART4 (0x400E1E00U)
552 #else
553 #define HSMCI ((Hsmci *)0x40000000U)
554 #define SSC ((Ssc *)0x40004000U)
555 #define SPI0 ((Spi *)0x40008000U)
556 #define TC0 ((Tc *)0x4000C000U)
557 #define TWIHS0 ((Twihs *)0x40018000U)
558 #define TWIHS1 ((Twihs *)0x4001C000U)
559 #define PWM0 ((Pwm *)0x40020000U)
560 #define USART0 ((Usart *)0x40024000U)
561 #define USART1 ((Usart *)0x40028000U)
562 #define USART2 ((Usart *)0x4002C000U)
563 #define MCAN0 ((Mcan *)0x40030000U)
564 #define MCAN1 ((Mcan *)0x40034000U)
565 #define USBHS ((Usbhs *)0x40038000U)
566 #define AFEC0 ((Afec *)0x4003C000U)
567 #define DACC ((Dacc *)0x40040000U)
568 #define ACC ((Acc *)0x40044000U)
569 #define ICM ((Icm *)0x40048000U)
570 #define ISI ((Isi *)0x4004C000U)
571 #define GMAC ((Gmac *)0x40050000U)
572 #define TC3 ((Tc *)0x40054000U)
573 #define PWM1 ((Pwm *)0x4005C000U)
574 #define TWIHS2 ((Twihs *)0x40060000U)
575 #define AFEC1 ((Afec *)0x40064000U)
576 #define AES ((Aes *)0x4006C000U)
577 #define TRNG ((Trng *)0x40070000U)
578 #define XDMAC ((Xdmac *)0x40078000U)
579 #define QSPI ((Qspi *)0x4007C000U)
580 #define MATRIX ((Matrix *)0x40088000U)
581 #define I2SC0 ((I2sc *)0x4008C000U)
582 #define UTMI ((Utmi *)0x400E0400U)
583 #define PMC ((Pmc *)0x400E0600U)
584 #define UART0 ((Uart *)0x400E0800U)
585 #define CHIPID ((Chipid *)0x400E0940U)
586 #define UART1 ((Uart *)0x400E0A00U)
587 #define EFC ((Efc *)0x400E0C00U)
588 #define PIOA ((Pio *)0x400E0E00U)
589 #define PIOB ((Pio *)0x400E1000U)
590 #define PIOD ((Pio *)0x400E1400U)
591 #define RSTC ((Rstc *)0x400E1800U)
592 #define SUPC ((Supc *)0x400E1810U)
593 #define RTT ((Rtt *)0x400E1830U)
594 #define WDT ((Wdt *)0x400E1850U)
595 #define RTC ((Rtc *)0x400E1860U)
596 #define GPBR ((Gpbr *)0x400E1890U)
597 #define RSWDT ((Rswdt *)0x400E1900U)
598 #define UART2 ((Uart *)0x400E1A00U)
599 #define UART3 ((Uart *)0x400E1C00U)
600 #define UART4 ((Uart *)0x400E1E00U)
601 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
602 
604 /* ************************************************************************** */
605 /* PIO DEFINITIONS FOR SAME70N20B */
606 /* ************************************************************************** */
609 
610 #include "pio/same70n20b.h"
613 /* ************************************************************************** */
614 /* MEMORY MAPPING DEFINITIONS FOR SAME70N20 */
615 /* ************************************************************************** */
616 
617 #define IFLASH_SIZE (0x100000u)
618 #define IFLASH_PAGE_SIZE (512u)
619 #define IFLASH_LOCK_REGION_SIZE (8192u)
620 #define IFLASH_NB_OF_PAGES (2048u)
621 #define IFLASH_NB_OF_LOCK_BITS (64u)
622 #define IRAM_SIZE (0x60000u)
623 
624 #define QSPIMEM_ADDR (0x80000000u)
625 #define AXIMX_ADDR (0xA0000000u)
626 #define ITCM_ADDR (0x00000000u)
627 #define IFLASH_ADDR (0x00400000u)
628 #define IROM_ADDR (0x00800000u)
629 #define DTCM_ADDR (0x20000000u)
630 #define IRAM_ADDR (0x20400000u)
632 /* ************************************************************************** */
633 /* MISCELLANEOUS DEFINITIONS FOR SAME70N20B */
634 /* ************************************************************************** */
635 
636 #define CHIP_JTAGID (0x05B3D03FUL)
637 #define CHIP_CIDR (0xA1020C01UL)
638 #define CHIP_EXID (0x00000001UL)
639 
640 /* ************************************************************************** */
641 /* ELECTRICAL DEFINITIONS FOR SAME70N20B */
642 /* ************************************************************************** */
643 
644 /* %ATMEL_ELECTRICAL% */
645 
646 /* Device characteristics */
647 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
648 #define CHIP_FREQ_SLCK_RC (32000UL)
649 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
650 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
651 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
652 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
653 #define CHIP_FREQ_CPU_MAX (300000000UL)
654 #define CHIP_FREQ_XTAL_32K (32768UL)
655 #define CHIP_FREQ_XTAL_12M (12000000UL)
656 
657 /* Embedded Flash Read Wait State (for Worst-Case Conditions) */
658 #define CHIP_FREQ_FWS_0 (23000000UL)
659 #define CHIP_FREQ_FWS_1 (46000000UL)
660 #define CHIP_FREQ_FWS_2 (69000000UL)
661 #define CHIP_FREQ_FWS_3 (92000000UL)
662 #define CHIP_FREQ_FWS_4 (115000000UL)
663 #define CHIP_FREQ_FWS_5 (138000000UL)
664 #define CHIP_FREQ_FWS_6 (150000000UL)
666 #ifdef __cplusplus
667 }
668 #endif
669 
672 #endif /* _SAME70N20B_ */
SysTick_IRQn
Definition: same70n20b.h:73
_DeviceVectors::pvReserved62
void * pvReserved62
Definition: same70j19.h:212
_DeviceVectors::pfnAFEC1_Handler
void * pfnAFEC1_Handler
Definition: same70j19.h:190
WDT_IRQn
Definition: same70n20b.h:80
_DeviceVectors::pfnUART4_Handler
void * pfnUART4_Handler
Definition: same70n19.h:203
_DeviceVectors::pfnXDMAC_Handler
void * pfnXDMAC_Handler
Definition: same70j19.h:208
UART0_IRQn
Definition: same70n20b.h:83
FPU_IRQn
Definition: same70n20b.h:124
_DeviceVectors::pfnUART3_Handler
void * pfnUART3_Handler
Definition: same70n19.h:202
_DeviceVectors::pfnPWM1_Handler
void * pfnPWM1_Handler
Definition: same70j19.h:210
TC11_IRQn
Definition: same70n20b.h:118
CCW_IRQn
Definition: same70n20b.h:126
_DeviceVectors::pfnBusFault_Handler
void * pfnBusFault_Handler
Definition: same70j19.h:137
_DeviceVectors::pfnTWIHS1_Handler
void * pfnTWIHS1_Handler
Definition: same70j19.h:170
GMAC_Q1_IRQn
Definition: same70n20b.h:128
_DeviceVectors::pvReserved55
void * pvReserved55
Definition: same70j19.h:205
_DeviceVectors::pfnPIOB_Handler
void * pfnPIOB_Handler
Definition: same70j19.h:161
MemManage_Handler
void MemManage_Handler(void)
Definition: rtos.c:196
HardFault_Handler
void HardFault_Handler(void)
Definition: rtos.c:248
GMAC_Q3_IRQn
Definition: same70n20b.h:132
_DeviceVectors::pfnGMAC_Q5_Handler
void * pfnGMAC_Q5_Handler
Definition: same70j19b.h:226
USBHS_IRQn
Definition: same70n20b.h:104
_DeviceVectors::pfnAFEC0_Handler
void * pfnAFEC0_Handler
Definition: same70j19.h:179
_DeviceVectors::pfnTC11_Handler
void * pfnTC11_Handler
Definition: same70j19.h:202
USART1_IRQn
Definition: same70n20b.h:88
MCAN1_INT0_Handler
void MCAN1_INT0_Handler(void)
TC2_IRQn
Definition: same70n20b.h:98
BusFault_IRQn
Definition: same70n20b.h:68
TWIHS0_IRQn
Definition: same70n20b.h:92
PMC_Handler
void PMC_Handler(void)
_DeviceVectors::pfnUART2_Handler
void * pfnUART2_Handler
Definition: same70j19.h:194
_DeviceVectors::pfnSSC_Handler
void * pfnSSC_Handler
Definition: same70j19.h:172
TC0_Handler
void TC0_Handler(void)
MCAN0_INT0_IRQn
Definition: same70n20b.h:105
PWM0_Handler
void PWM0_Handler(void)
_DeviceVectors::pfnISI_Handler
void * pfnISI_Handler
Definition: same70j19.h:209
SSC_IRQn
Definition: same70n20b.h:95
NonMaskableInt_IRQn
Definition: same70n20b.h:65
HSMCI_Handler
void HSMCI_Handler(void)
_DeviceVectors::pfnHardFault_Handler
void * pfnHardFault_Handler
Definition: same70j19.h:135
USART0_Handler
void USART0_Handler(void)
Definition: d_usartDMA.c:1646
_DeviceVectors::pfnMCAN1_INT0_Handler
void * pfnMCAN1_INT0_Handler
Definition: same70n19.h:194
_DeviceVectors::pfnSVC_Handler
void * pfnSVC_Handler
Definition: same70j19.h:143
EFC_Handler
void EFC_Handler(void)
PendSV_Handler
void PendSV_Handler(void)
_DeviceVectors::pfnUSART2_Handler
void * pfnUSART2_Handler
Definition: same70n19.h:172
UART1_IRQn
Definition: same70n20b.h:84
_DeviceVectors::pfnGMAC_Q3_Handler
void * pfnGMAC_Q3_Handler
Definition: same70j19b.h:224
UsageFault_IRQn
Definition: same70n20b.h:69
_DeviceVectors::pvStack
void * pvStack
Definition: same70j19.h:130
TWIHS2_Handler
void TWIHS2_Handler(void)
_DeviceVectors::pfnRSWDT_Handler
void * pfnRSWDT_Handler
Definition: same70j19.h:213
GMAC_Handler
void GMAC_Handler(void)
EFC_IRQn
Definition: same70n20b.h:82
_DeviceVectors::pfnUSBHS_Handler
void * pfnUSBHS_Handler
Definition: same70j19.h:184
QSPI_IRQn
Definition: same70n20b.h:112
PIOD_IRQn
Definition: same70n20b.h:90
system_same70.h
MCAN0_INT1_IRQn
Definition: same70n20b.h:106
_DeviceVectors::pfnCCF_Handler
void * pfnCCF_Handler
Definition: same70j19.h:215
TWIHS0_Handler
void TWIHS0_Handler(void)
QSPI_Handler
void QSPI_Handler(void)
_DeviceVectors::pvReserved48
void * pvReserved48
Definition: same70j19.h:198
_DeviceVectors::pfnUSART0_Handler
void * pfnUSART0_Handler
Definition: same70j19.h:163
MCAN1_Handler
void MCAN1_Handler(void)
SysTick_Handler
void SysTick_Handler(void)
_DeviceVectors::pfnPWM0_Handler
void * pfnPWM0_Handler
Definition: same70j19.h:181
_DeviceVectors::pfnGMAC_Handler
void * pfnGMAC_Handler
Definition: same70j19.h:189
PWM1_IRQn
Definition: same70n20b.h:123
_DeviceVectors::pvReserved9
void * pvReserved9
Definition: same70j19.h:159
HardFault_IRQn
Definition: same70n20b.h:66
FPU_Handler
void FPU_Handler(void)
_DeviceVectors::pfnMemManage_Handler
void * pfnMemManage_Handler
Definition: same70j19.h:136
MCAN0_INT1_Handler
void MCAN0_INT1_Handler(void)
MCAN1_INT1_Handler
void MCAN1_INT1_Handler(void)
PendSV_IRQn
Definition: same70n20b.h:72
TC9_IRQn
Definition: same70n20b.h:116
PIOA_IRQn
Definition: same70n20b.h:85
PIOD_Handler
void PIOD_Handler(void)
RTC_IRQn
Definition: same70n20b.h:78
DebugMonitor_IRQn
Definition: same70n20b.h:71
_DeviceVectors::pfnDebugMon_Handler
void * pfnDebugMon_Handler
Definition: same70j19.h:144
_DeviceVectors::pvReserved26
void * pvReserved26
Definition: same70j19.h:176
TC10_Handler
void TC10_Handler(void)
DebugMon_Handler
void DebugMon_Handler(void)
TC2_Handler
void TC2_Handler(void)
UART4_IRQn
Definition: same70n20b.h:115
SVCall_IRQn
Definition: same70n20b.h:70
_DeviceVectors::pfnPIOD_Handler
void * pfnPIOD_Handler
Definition: same70j19.h:166
AFEC1_IRQn
Definition: same70n20b.h:110
TC0_IRQn
Definition: same70n20b.h:96
_DeviceVectors::pfnGMAC_Q4_Handler
void * pfnGMAC_Q4_Handler
Definition: same70j19b.h:225
ACC_Handler
void ACC_Handler(void)
TC1_Handler
void TC1_Handler(void)
_DeviceVectors::pfnTC2_Handler
void * pfnTC2_Handler
Definition: same70j19.h:175
WDT_Handler
void WDT_Handler(void)
_DeviceVectors::pfnHSMCI_Handler
void * pfnHSMCI_Handler
Definition: same70n19.h:175
ISI_Handler
void ISI_Handler(void)
TC1_IRQn
Definition: same70n20b.h:97
AFEC0_Handler
void AFEC0_Handler(void)
RSTC_Handler
void RSTC_Handler(void)
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
SUPC_Handler
void SUPC_Handler(void)
IRQn_Type
enum IRQn IRQn_Type
_DeviceVectors::pfnReset_Handler
void * pfnReset_Handler
Definition: same70j19.h:133
_DeviceVectors::pvReserved42
void * pvReserved42
Definition: same70j19.h:192
NMI_Handler
void NMI_Handler(void)
_DeviceVectors::pfnUART1_Handler
void * pfnUART1_Handler
Definition: same70j19.h:158
BusFault_Handler
void BusFault_Handler(void)
Definition: rtos.c:211
I2SC0_IRQn
Definition: same70n20b.h:131
PIOB_Handler
void PIOB_Handler(void)
usbhs.h
_DeviceVectors::pfnSysTick_Handler
void * pfnSysTick_Handler
Definition: same70j19.h:147
HSMCI_IRQn
Definition: same70n20b.h:91
_DeviceVectors::pfnACC_Handler
void * pfnACC_Handler
Definition: same70j19.h:183
UART3_IRQn
Definition: same70n20b.h:114
_DeviceVectors::pfnWDT_Handler
void * pfnWDT_Handler
Definition: same70j19.h:154
I2SC0_Handler
void I2SC0_Handler(void)
USART0_IRQn
Definition: same70n20b.h:87
_DeviceVectors::pfnICM_Handler
void * pfnICM_Handler
Definition: same70j19.h:182
RSTC_IRQn
Definition: same70n20b.h:77
SPI0_IRQn
Definition: same70n20b.h:94
MCAN0_Handler
void MCAN0_Handler(void)
_DeviceVectors::pfnCCW_Handler
void * pfnCCW_Handler
Definition: same70j19.h:214
RSWDT_IRQn
Definition: same70n20b.h:125
TWIHS1_IRQn
Definition: same70n20b.h:93
_DeviceVectors::pfnFPU_Handler
void * pfnFPU_Handler
Definition: same70j19.h:211
_DeviceVectors
Definition: same70j19.h:127
_DeviceVectors::pfnIXC_Handler
void * pfnIXC_Handler
Definition: same70j19.h:218
PWM1_Handler
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Definition: same70j19.h:140
PIOB_IRQn
Definition: same70n20b.h:86
TC9_Handler
void TC9_Handler(void)
_DeviceVectors::pfnReserved4_Handler
void * pfnReserved4_Handler
Definition: same70j19.h:142
_DeviceVectors::pvReserved47
void * pvReserved47
Definition: same70j19.h:197
UART2_IRQn
Definition: same70n20b.h:113
TWIHS2_IRQn
Definition: same70n20b.h:111
_DeviceVectors::pfnRTT_Handler
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Definition: same70j19.h:153
AES_Handler
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GMAC_Q4_IRQn
Definition: same70n20b.h:133
UART3_Handler
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Definition: d_usartDMA.c:1644
MCAN1_INT1_IRQn
Definition: same70n20b.h:108
TRNG_Handler
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_DeviceVectors::pfnUSART1_Handler
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Definition: same70j19.h:164
IXC_Handler
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ISI_IRQn
Definition: same70n20b.h:122
AES_IRQn
Definition: same70n20b.h:119
AFEC1_Handler
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CCF_IRQn
Definition: same70n20b.h:127
_DeviceVectors::pfnAES_Handler
void * pfnAES_Handler
Definition: same70j19.h:206
_DeviceVectors::pvReserved27
void * pvReserved27
Definition: same70j19.h:177
TC10_IRQn
Definition: same70n20b.h:117
GMAC_Q4_Handler
void GMAC_Q4_Handler(void)
AFEC0_IRQn
Definition: same70n20b.h:99
MCAN0_INT0_Handler
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CCW_Handler
void CCW_Handler(void)
_DeviceVectors::pfnPendSV_Handler
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Definition: same70j19.h:146
RTC_Handler
void RTC_Handler(void)
_DeviceVectors::pvReserved54
void * pvReserved54
Definition: same70j19.h:204
_DeviceVectors::pfnMCAN1_INT1_Handler
void * pfnMCAN1_INT1_Handler
Definition: same70n19.h:195
MCAN1_INT0_IRQn
Definition: same70n20b.h:107
UART0_Handler
void UART0_Handler(void)
Definition: d_usartDMA.c:1641
_DeviceVectors::pvReserved53
void * pvReserved53
Definition: same70j19.h:203
SUPC_IRQn
Definition: same70n20b.h:76
_DeviceVectors::pfnTC0_Handler
void * pfnTC0_Handler
Definition: same70j19.h:173
_DeviceVectors::pfnTWIHS0_Handler
void * pfnTWIHS0_Handler
Definition: same70j19.h:169
_DeviceVectors::pfnGMAC_Q1_Handler
void * pfnGMAC_Q1_Handler
Definition: same70j19.h:216
_DeviceVectors::pfnDACC_Handler
void * pfnDACC_Handler
Definition: same70j19.h:180
_DeviceVectors::pfnUART0_Handler
void * pfnUART0_Handler
Definition: same70j19.h:157
_DeviceVectors::pfnNMI_Handler
void * pfnNMI_Handler
Definition: same70j19.h:134
_DeviceVectors::pfnTC9_Handler
void * pfnTC9_Handler
Definition: same70j19.h:200
_DeviceVectors::pfnUsageFault_Handler
void * pfnUsageFault_Handler
Definition: same70j19.h:138
_DeviceVectors::pfnTC10_Handler
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Definition: same70j19.h:201
ICM_IRQn
Definition: same70n20b.h:102
UART2_Handler
void UART2_Handler(void)
Definition: d_usartDMA.c:1643
_DeviceVectors::pfnI2SC0_Handler
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Definition: same70n19b.h:230
GMAC_Q2_Handler
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CCF_Handler
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TWIHS1_Handler
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ACC_IRQn
Definition: same70n20b.h:103
_DeviceVectors::pfnPIOA_Handler
void * pfnPIOA_Handler
Definition: same70j19.h:160
Reset_Handler
void Reset_Handler(void)
This is the code that gets called on processor reset. To initialize the device, and call the main() r...
Definition: startup_same70.c:388
USBHS_Handler
void USBHS_Handler(void)
Definition: USBD_HAL.c:1008
IRQn
IRQn
Definition: same70j19.h:62
_DeviceVectors::pfnEFC_Handler
void * pfnEFC_Handler
Definition: same70j19.h:156
_DeviceVectors::pfnTRNG_Handler
void * pfnTRNG_Handler
Definition: same70j19.h:207
GMAC_Q2_IRQn
Definition: same70n20b.h:129
_DeviceVectors::pvReserved17
void * pvReserved17
Definition: same70j19.h:167
RTT_Handler
void RTT_Handler(void)
Definition: d_time.c:22
_DeviceVectors::pfnGMAC_Q2_Handler
void * pfnGMAC_Q2_Handler
Definition: same70j19.h:217
_DeviceVectors::pfnMCAN0_INT0_Handler
void * pfnMCAN0_INT0_Handler
Definition: same70j19.h:185
GMAC_Q3_Handler
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RSWDT_Handler
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UART4_Handler
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Definition: d_usartDMA.c:1645
PWM0_IRQn
Definition: same70n20b.h:101
MemoryManagement_IRQn
Definition: same70n20b.h:67
GMAC_IRQn
Definition: same70n20b.h:109
UART1_Handler
void UART1_Handler(void)
Definition: d_usartDMA.c:1642
_DeviceVectors::pfnMCAN0_INT1_Handler
void * pfnMCAN0_INT1_Handler
Definition: same70j19.h:186
XDMAC_Handler
void XDMAC_Handler(void)
Definition: d_usartDMA.c:704
_DeviceVectors::pfnTWIHS2_Handler
void * pfnTWIHS2_Handler
Definition: same70n19.h:198
_DeviceVectors::pfnRTC_Handler
void * pfnRTC_Handler
Definition: same70j19.h:152
USART2_Handler
void USART2_Handler(void)
Definition: d_usartDMA.c:1648
SVC_Handler
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ICM_Handler
void ICM_Handler(void)
GMAC_Q5_IRQn
Definition: same70n20b.h:134
_DeviceVectors::pfnSPI0_Handler
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Definition: same70n19.h:178
USART2_IRQn
Definition: same70n20b.h:89
GMAC_Q1_Handler
void GMAC_Q1_Handler(void)
_DeviceVectors::pfnReserved3_Handler
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Definition: same70j19.h:141
DeviceVectors
struct _DeviceVectors DeviceVectors
TRNG_IRQn
Definition: same70n20b.h:120
USART1_Handler
void USART1_Handler(void)
Definition: d_usartDMA.c:1647
TC11_Handler
void TC11_Handler(void)
_DeviceVectors::pfnReserved5_Handler
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Definition: same70j19.h:145
PIOA_Handler
void PIOA_Handler(void)
_DeviceVectors::pvReserved49
void * pvReserved49
Definition: same70j19.h:199
_DeviceVectors::pfnTC1_Handler
void * pfnTC1_Handler
Definition: same70j19.h:174
PERIPH_COUNT_IRQn
Definition: same70n20b.h:136
_DeviceVectors::pvReserved70
void * pvReserved70
Definition: same70j19.h:220
_DeviceVectors::pvReserved12
void * pvReserved12
Definition: same70j19.h:162
GMAC_Q5_Handler
void GMAC_Q5_Handler(void)
XDMAC_IRQn
Definition: same70n20b.h:121
RTT_IRQn
Definition: same70n20b.h:79
_DeviceVectors::pfnPMC_Handler
void * pfnPMC_Handler
Definition: same70j19.h:155
_DeviceVectors::pfnQSPI_Handler
void * pfnQSPI_Handler
Definition: same70j19.h:193
_DeviceVectors::pfnRSTC_Handler
void * pfnRSTC_Handler
Definition: same70j19.h:151
_DeviceVectors::pfnSUPC_Handler
void * pfnSUPC_Handler
Definition: same70j19.h:150
UsageFault_Handler
void UsageFault_Handler(void)
Definition: rtos.c:226
_DeviceVectors::pfnReserved1_Handler
void * pfnReserved1_Handler
Definition: same70j19.h:139
usbhs.h
DACC_Handler
void DACC_Handler(void)
IXC_IRQn
Definition: same70n20b.h:130
SSC_Handler
void SSC_Handler(void)
SPI0_Handler
void SPI0_Handler(void)
PMC_IRQn
Definition: same70n20b.h:81
_DeviceVectors::pvReserved28
void * pvReserved28
Definition: same70j19.h:178
DACC_IRQn
Definition: same70n20b.h:100

inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:05