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Macros | |
#define | REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) |
(UART3) Baud Rate Generator Register More... | |
#define | REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) |
(UART3) Comparison Register More... | |
#define | REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) |
(UART3) Control Register More... | |
#define | REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) |
(UART3) Interrupt Disable Register More... | |
#define | REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) |
(UART3) Interrupt Enable Register More... | |
#define | REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) |
(UART3) Interrupt Mask Register More... | |
#define | REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) |
(UART3) Mode Register More... | |
#define | REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) |
(UART3) Receive Holding Register More... | |
#define | REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) |
(UART3) Status Register More... | |
#define | REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) |
(UART3) Transmit Holding Register More... | |
#define | REG_UART3_VERSION (*(__I uint32_t*)0x400E1CFCU) |
(UART3) Version Register More... | |
#define | REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) |
(UART3) Write Protection Mode Register More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file uart3.h.
#define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) |
#define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) |
#define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) |
#define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) |
#define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) |
#define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) |
#define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) |
#define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) |
#define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) |
#define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) |
#define REG_UART3_VERSION (*(__I uint32_t*)0x400E1CFCU) |