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Macros
#define	REG_AFEC0_ACR ((__IO uint32_t)0x4003C094U)
	(AFEC0) AFEC Analog Control Register More...

#define	REG_AFEC0_CDR ((__I uint32_t)0x4003C068U)
	(AFEC0) AFEC Channel Data Register More...

#define	REG_AFEC0_CECR ((__IO uint32_t)0x4003C0D8U)
	(AFEC0) AFEC Channel Error Correction Register More...

#define	REG_AFEC0_CGR ((__IO uint32_t)0x4003C054U)
	(AFEC0) AFEC Channel Gain Register More...

#define	REG_AFEC0_CHDR ((__O uint32_t)0x4003C018U)
	(AFEC0) AFEC Channel Disable Register More...

#define	REG_AFEC0_CHER ((__O uint32_t)0x4003C014U)
	(AFEC0) AFEC Channel Enable Register More...

#define	REG_AFEC0_CHSR ((__I uint32_t)0x4003C01CU)
	(AFEC0) AFEC Channel Status Register More...

#define	REG_AFEC0_COCR ((__IO uint32_t)0x4003C06CU)
	(AFEC0) AFEC Channel Offset Compensation Register More...

#define	REG_AFEC0_COSR ((__IO uint32_t)0x4003C0D0U)
	(AFEC0) AFEC Correction Select Register More...

#define	REG_AFEC0_CR ((__O uint32_t)0x4003C000U)
	(AFEC0) AFEC Control Register More...

#define	REG_AFEC0_CSELR ((__IO uint32_t)0x4003C064U)
	(AFEC0) AFEC Channel Selection Register More...

#define	REG_AFEC0_CVR ((__IO uint32_t)0x4003C0D4U)
	(AFEC0) AFEC Correction Values Register More...

#define	REG_AFEC0_CWR ((__IO uint32_t)0x4003C050U)
	(AFEC0) AFEC Compare Window Register More...

#define	REG_AFEC0_DIFFR ((__IO uint32_t)0x4003C060U)
	(AFEC0) AFEC Channel Differential Register More...

#define	REG_AFEC0_EMR ((__IO uint32_t)0x4003C008U)
	(AFEC0) AFEC Extended Mode Register More...

#define	REG_AFEC0_IDR ((__O uint32_t)0x4003C028U)
	(AFEC0) AFEC Interrupt Disable Register More...

#define	REG_AFEC0_IER ((__O uint32_t)0x4003C024U)
	(AFEC0) AFEC Interrupt Enable Register More...

#define	REG_AFEC0_IMR ((__I uint32_t)0x4003C02CU)
	(AFEC0) AFEC Interrupt Mask Register More...

#define	REG_AFEC0_ISR ((__I uint32_t)0x4003C030U)
	(AFEC0) AFEC Interrupt Status Register More...

#define	REG_AFEC0_LCDR ((__I uint32_t)0x4003C020U)
	(AFEC0) AFEC Last Converted Data Register More...

#define	REG_AFEC0_MR ((__IO uint32_t)0x4003C004U)
	(AFEC0) AFEC Mode Register More...

#define	REG_AFEC0_OVER ((__I uint32_t)0x4003C04CU)
	(AFEC0) AFEC Overrun Status Register More...

#define	REG_AFEC0_SEQ1R ((__IO uint32_t)0x4003C00CU)
	(AFEC0) AFEC Channel Sequence 1 Register More...

#define	REG_AFEC0_SEQ2R ((__IO uint32_t)0x4003C010U)
	(AFEC0) AFEC Channel Sequence 2 Register More...

#define	REG_AFEC0_SHMR ((__IO uint32_t)0x4003C0A0U)
	(AFEC0) AFEC Sample & Hold Mode Register More...

#define	REG_AFEC0_TEMPCWR ((__IO uint32_t)0x4003C074U)
	(AFEC0) AFEC Temperature Compare Window Register More...

#define	REG_AFEC0_TEMPMR ((__IO uint32_t)0x4003C070U)
	(AFEC0) AFEC Temperature Sensor Mode Register More...

#define	REG_AFEC0_VERSION ((__I uint32_t)0x4003C0FCU)
	(AFEC0) AFEC Version Register More...

#define	REG_AFEC0_WPMR ((__IO uint32_t)0x4003C0E4U)
	(AFEC0) AFEC Write Protection Mode Register More...

#define	REG_AFEC0_WPSR ((__I uint32_t)0x4003C0E8U)
	(AFEC0) AFEC Write Protection Status Register More...

Detailed Description

Definition in file afec0.h.

Macro Definition Documentation

◆ REG_AFEC0_ACR

#define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U)

(AFEC0) AFEC Analog Control Register

Definition at line 93 of file afec0.h.

◆ REG_AFEC0_CDR

#define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U)

(AFEC0) AFEC Channel Data Register

Definition at line 89 of file afec0.h.

◆ REG_AFEC0_CECR

#define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U)

(AFEC0) AFEC Channel Error Correction Register

Definition at line 97 of file afec0.h.

◆ REG_AFEC0_CGR

#define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U)

(AFEC0) AFEC Channel Gain Register

Definition at line 86 of file afec0.h.

◆ REG_AFEC0_CHDR

#define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U)

(AFEC0) AFEC Channel Disable Register

Definition at line 77 of file afec0.h.

◆ REG_AFEC0_CHER

#define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U)

(AFEC0) AFEC Channel Enable Register

Definition at line 76 of file afec0.h.

◆ REG_AFEC0_CHSR

#define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU)

(AFEC0) AFEC Channel Status Register

Definition at line 78 of file afec0.h.

◆ REG_AFEC0_COCR

#define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU)

(AFEC0) AFEC Channel Offset Compensation Register

Definition at line 90 of file afec0.h.

◆ REG_AFEC0_COSR

#define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U)

(AFEC0) AFEC Correction Select Register

Definition at line 95 of file afec0.h.

◆ REG_AFEC0_CR

#define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U)

(AFEC0) AFEC Control Register

Definition at line 71 of file afec0.h.

◆ REG_AFEC0_CSELR

#define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U)

(AFEC0) AFEC Channel Selection Register

Definition at line 88 of file afec0.h.

◆ REG_AFEC0_CVR

#define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U)

(AFEC0) AFEC Correction Values Register

Definition at line 96 of file afec0.h.

◆ REG_AFEC0_CWR

#define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U)

(AFEC0) AFEC Compare Window Register

Definition at line 85 of file afec0.h.

◆ REG_AFEC0_DIFFR

#define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U)

(AFEC0) AFEC Channel Differential Register

Definition at line 87 of file afec0.h.

◆ REG_AFEC0_EMR

#define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U)

(AFEC0) AFEC Extended Mode Register

Definition at line 73 of file afec0.h.

◆ REG_AFEC0_IDR

#define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U)

(AFEC0) AFEC Interrupt Disable Register

Definition at line 81 of file afec0.h.

◆ REG_AFEC0_IER

#define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U)

(AFEC0) AFEC Interrupt Enable Register

Definition at line 80 of file afec0.h.

◆ REG_AFEC0_IMR

#define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU)

(AFEC0) AFEC Interrupt Mask Register

Definition at line 82 of file afec0.h.

◆ REG_AFEC0_ISR

#define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U)

(AFEC0) AFEC Interrupt Status Register

Definition at line 83 of file afec0.h.

◆ REG_AFEC0_LCDR

#define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U)

(AFEC0) AFEC Last Converted Data Register

Definition at line 79 of file afec0.h.

◆ REG_AFEC0_MR

#define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U)

(AFEC0) AFEC Mode Register

Definition at line 72 of file afec0.h.

◆ REG_AFEC0_OVER

#define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU)

(AFEC0) AFEC Overrun Status Register

Definition at line 84 of file afec0.h.

◆ REG_AFEC0_SEQ1R

#define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU)

(AFEC0) AFEC Channel Sequence 1 Register

Definition at line 74 of file afec0.h.

◆ REG_AFEC0_SEQ2R

#define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U)

(AFEC0) AFEC Channel Sequence 2 Register

Definition at line 75 of file afec0.h.

◆ REG_AFEC0_SHMR

#define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U)

(AFEC0) AFEC Sample & Hold Mode Register

Definition at line 94 of file afec0.h.

◆ REG_AFEC0_TEMPCWR

#define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U)

(AFEC0) AFEC Temperature Compare Window Register

Definition at line 92 of file afec0.h.

◆ REG_AFEC0_TEMPMR

#define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U)

(AFEC0) AFEC Temperature Sensor Mode Register

Definition at line 91 of file afec0.h.

◆ REG_AFEC0_VERSION

#define REG_AFEC0_VERSION (*(__I uint32_t*)0x4003C0FCU)

(AFEC0) AFEC Version Register

Definition at line 100 of file afec0.h.

◆ REG_AFEC0_WPMR

#define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U)

(AFEC0) AFEC Write Protection Mode Register

Definition at line 98 of file afec0.h.

◆ REG_AFEC0_WPSR

#define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U)

(AFEC0) AFEC Write Protection Status Register

Definition at line 99 of file afec0.h.

Macros