84 #ifdef _SAME70_PIOC_INSTANCE_ 87 #ifdef _SAME70_USART0_INSTANCE_ 90 #ifdef _SAME70_USART1_INSTANCE_ 93 #ifdef _SAME70_USART2_INSTANCE_ 97 #ifdef _SAME70_PIOE_INSTANCE_ 100 #ifdef _SAME70_HSMCI_INSTANCE_ 105 #ifdef _SAME70_SPI0_INSTANCE_ 112 #ifdef _SAME70_TC1_INSTANCE_ 115 #ifdef _SAME70_TC1_INSTANCE_ 118 #ifdef _SAME70_TC1_INSTANCE_ 122 #ifdef _SAME70_DACC_INSTANCE_ 131 #ifdef _SAME70_MCAN1_INSTANCE_ 137 #ifdef _SAME70_TWIHS2_INSTANCE_ 140 #ifdef _SAME70_SPI1_INSTANCE_ 145 #ifdef _SAME70_UART3_INSTANCE_ 148 #ifdef _SAME70_UART4_INSTANCE_ 151 #ifdef _SAME70_TC2_INSTANCE_ 154 #ifdef _SAME70_TC2_INSTANCE_ 157 #ifdef _SAME70_TC2_INSTANCE_ 169 #ifdef _SAME70_SDRAMC_INSTANCE_ 178 #ifdef _SAME70_I2SC0_INSTANCE_ 181 #ifdef _SAME70_I2SC1_INSTANCE_ 184 #if (__SAM_M7_REVB == 1) 202 .pfnReserved1_Handler = (
void*) (0UL),
203 .pfnReserved2_Handler = (
void*) (0UL),
204 .pfnReserved3_Handler = (
void*) (0UL),
205 .pfnReserved4_Handler = (
void*) (0UL),
208 .pfnReserved5_Handler = (
void*) (0UL),
222 .pvReserved9 = (
void*) (0UL),
225 #ifdef _SAME70_PIOC_INSTANCE_
228 .pvReserved12 = (
void*) (0UL),
230 #ifdef _SAME70_USART0_INSTANCE_ 233 .pvReserved13 = (
void*) (0UL),
235 #ifdef _SAME70_USART1_INSTANCE_
238 .pvReserved14 = (
void*) (0UL),
240 #ifdef _SAME70_USART2_INSTANCE_ 243 .pvReserved15 = (
void*) (0UL),
246 #ifdef _SAME70_PIOE_INSTANCE_ 249 .pvReserved17 = (
void*) (0UL),
251 #ifdef _SAME70_HSMCI_INSTANCE_
254 .pvReserved18 = (
void*) (0UL),
258 #ifdef _SAME70_SPI0_INSTANCE_ 261 .pvReserved21 = (
void*) (0UL),
267 #ifdef _SAME70_TC1_INSTANCE_
270 .pvReserved26 = (
void*) (0UL),
272 #ifdef _SAME70_TC1_INSTANCE_ 275 .pvReserved27 = (
void*) (0UL),
277 #ifdef _SAME70_TC1_INSTANCE_
280 .pvReserved28 = (
void*) (0UL),
283 #ifdef _SAME70_DACC_INSTANCE_
286 .pvReserved30 = (
void*) (0UL),
294 #ifdef _SAME70_MCAN1_INSTANCE_ 298 .pvReserved37 = (
void*) (0UL),
299 .pvReserved38 = (
void*) (0UL),
303 #ifdef _SAME70_TWIHS2_INSTANCE_ 306 .pvReserved41 = (
void*) (0UL),
308 #ifdef _SAME70_SPI1_INSTANCE_
311 .pvReserved42 = (
void*) (0UL),
315 #ifdef _SAME70_UART3_INSTANCE_ 318 .pvReserved45 = (
void*) (0UL),
320 #ifdef _SAME70_UART4_INSTANCE_
323 .pvReserved46 = (
void*) (0UL),
325 #ifdef _SAME70_TC2_INSTANCE_ 328 .pvReserved47 = (
void*) (0UL),
330 #ifdef _SAME70_TC2_INSTANCE_
333 .pvReserved48 = (
void*) (0UL),
335 #ifdef _SAME70_TC2_INSTANCE_ 338 .pvReserved49 = (
void*) (0UL),
343 .pvReserved53 = (
void*) (0UL),
344 .pvReserved54 = (
void*) (0UL),
345 .pvReserved55 = (
void*) (0UL),
352 #ifdef _SAME70_SDRAMC_INSTANCE_ 355 .pvReserved62 = (
void*) (0UL),
363 #ifdef _SAME70_I2SC0_INSTANCE_
366 .pvReserved69 = (
void*) (0UL),
368 #ifdef _SAME70_I2SC1_INSTANCE_ 371 .pvReserved70 = (
void*) (0UL),
378 .pvReserved71 = (
void*) (0UL),
379 .pvReserved72 = (
void*) (0UL),
380 .pvReserved73 = (
void*) (0UL)
390 uint32_t *pSrc, *pDest;
void MCAN0_INT0_Handler(void)
void MemManage_Handler(void)
void Reset_Handler(void)
This is the code that gets called on processor reset. To initialize the device, and call the main() r...
void NMI_Handler(void HardFault_Handler void)
void __libc_init_array(void)
void GMAC_Q2_Handler(void)
void USART1_Handler(void)
void GMAC_Q4_Handler(void)
void HardFault_Handler(void)
void TWIHS0_Handler(void)
void GMAC_Q5_Handler(void)
void DebugMon_Handler(void)
void MCAN0_INT1_Handler(void)
void MCAN1_INT0_Handler(void)
void TWIHS1_Handler(void)
void GMAC_Q1_Handler(void)
void SysTick_Handler(void)
void TWIHS2_Handler(void)
typedef __attribute__
USB Device LPM Descriptor structure.
void Dummy_Handler(void)
Default interrupt handler for unused IRQs.
void MCAN1_INT1_Handler(void)
void USART0_Handler(void)
void USART2_Handler(void)
void UsageFault_Handler(void)
void GMAC_Q3_Handler(void)
#define SCB_VTOR_TBLOFF_Msk
static __always_inline void fpu_enable(void)
Enable FPU.
void PendSV_Handler(void)
void SDRAMC_Handler(void)
void BusFault_Handler(void)