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Macros | |
#define | REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) |
(UART2) Baud Rate Generator Register More... | |
#define | REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) |
(UART2) Comparison Register More... | |
#define | REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) |
(UART2) Control Register More... | |
#define | REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) |
(UART2) Interrupt Disable Register More... | |
#define | REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) |
(UART2) Interrupt Enable Register More... | |
#define | REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) |
(UART2) Interrupt Mask Register More... | |
#define | REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) |
(UART2) Mode Register More... | |
#define | REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) |
(UART2) Receive Holding Register More... | |
#define | REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) |
(UART2) Status Register More... | |
#define | REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) |
(UART2) Transmit Holding Register More... | |
#define | REG_UART2_VERSION (*(__I uint32_t*)0x400E1AFCU) |
(UART2) Version Register More... | |
#define | REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) |
(UART2) Write Protection Mode Register More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file uart2.h.
#define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) |
#define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) |
#define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) |
#define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) |
#define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) |
#define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) |
#define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) |
#define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) |
#define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) |
#define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) |
#define REG_UART2_VERSION (*(__I uint32_t*)0x400E1AFCU) |