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Macros | |
#define | REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) |
(TWIHS2) Control Register More... | |
#define | REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) |
(TWIHS2) Clock Waveform Generator Register More... | |
#define | REG_TWIHS2_DR (*(__I uint32_t*)0x400600D0U) |
(TWIHS2) Debug Register More... | |
#define | REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) |
(TWIHS2) Filter Register More... | |
#define | REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) |
(TWIHS2) Internal Address Register More... | |
#define | REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) |
(TWIHS2) Interrupt Disable Register More... | |
#define | REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) |
(TWIHS2) Interrupt Enable Register More... | |
#define | REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) |
(TWIHS2) Interrupt Mask Register More... | |
#define | REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) |
(TWIHS2) Master Mode Register More... | |
#define | REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) |
(TWIHS2) Receive Holding Register More... | |
#define | REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) |
(TWIHS2) SMBus Timing Register More... | |
#define | REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) |
(TWIHS2) Slave Mode Register More... | |
#define | REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) |
(TWIHS2) Status Register More... | |
#define | REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) |
(TWIHS2) SleepWalking Matching Register More... | |
#define | REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) |
(TWIHS2) Transmit Holding Register More... | |
#define | REG_TWIHS2_VER (*(__I uint32_t*)0x400600FCU) |
(TWIHS2) Version Register More... | |
#define | REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) |
(TWIHS2) Write Protection Mode Register More... | |
#define | REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) |
(TWIHS2) Write Protection Status Register More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file twihs2.h.
#define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) |
#define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) |
#define REG_TWIHS2_DR (*(__I uint32_t*)0x400600D0U) |
#define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) |
#define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) |
#define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) |
#define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) |
#define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) |
#define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) |
#define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) |
#define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) |
#define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) |
#define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) |
#define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) |
#define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) |
#define REG_TWIHS2_VER (*(__I uint32_t*)0x400600FCU) |
#define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) |