Macros
instance/qspi.h File Reference
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Macros

#define REG_QSPI_CR   (*(__O uint32_t*)0x4007C000U)
 (QSPI) Control Register More...
 
#define REG_QSPI_IAR   (*(__IO uint32_t*)0x4007C030U)
 (QSPI) Instruction Address Register More...
 
#define REG_QSPI_ICR   (*(__IO uint32_t*)0x4007C034U)
 (QSPI) Instruction Code Register More...
 
#define REG_QSPI_IDR   (*(__O uint32_t*)0x4007C018U)
 (QSPI) Interrupt Disable Register More...
 
#define REG_QSPI_IER   (*(__O uint32_t*)0x4007C014U)
 (QSPI) Interrupt Enable Register More...
 
#define REG_QSPI_IFR   (*(__IO uint32_t*)0x4007C038U)
 (QSPI) Instruction Frame Register More...
 
#define REG_QSPI_IMR   (*(__I uint32_t*)0x4007C01CU)
 (QSPI) Interrupt Mask Register More...
 
#define REG_QSPI_MR   (*(__IO uint32_t*)0x4007C004U)
 (QSPI) Mode Register More...
 
#define REG_QSPI_RDR   (*(__I uint32_t*)0x4007C008U)
 (QSPI) Receive Data Register More...
 
#define REG_QSPI_SCR   (*(__IO uint32_t*)0x4007C020U)
 (QSPI) Serial Clock Register More...
 
#define REG_QSPI_SKR   (*(__O uint32_t*)0x4007C044U)
 (QSPI) Scrambling Key Register More...
 
#define REG_QSPI_SMR   (*(__IO uint32_t*)0x4007C040U)
 (QSPI) Scrambling Mode Register More...
 
#define REG_QSPI_SR   (*(__I uint32_t*)0x4007C010U)
 (QSPI) Status Register More...
 
#define REG_QSPI_TDR   (*(__O uint32_t*)0x4007C00CU)
 (QSPI) Transmit Data Register More...
 
#define REG_QSPI_VERSION   (*(__I uint32_t*)0x4007C0FCU)
 (QSPI) Version Register More...
 
#define REG_QSPI_WPMR   (*(__IO uint32_t*)0x4007C0E4U)
 (QSPI) Write Protection Mode Register More...
 
#define REG_QSPI_WPSR   (*(__I uint32_t*)0x4007C0E8U)
 (QSPI) Write Protection Status Register More...
 

Detailed Description

Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.

Definition in file instance/qspi.h.

Macro Definition Documentation

◆ REG_QSPI_CR

#define REG_QSPI_CR   (*(__O uint32_t*)0x4007C000U)

(QSPI) Control Register

Definition at line 58 of file instance/qspi.h.

◆ REG_QSPI_IAR

#define REG_QSPI_IAR   (*(__IO uint32_t*)0x4007C030U)

(QSPI) Instruction Address Register

Definition at line 67 of file instance/qspi.h.

◆ REG_QSPI_ICR

#define REG_QSPI_ICR   (*(__IO uint32_t*)0x4007C034U)

(QSPI) Instruction Code Register

Definition at line 68 of file instance/qspi.h.

◆ REG_QSPI_IDR

#define REG_QSPI_IDR   (*(__O uint32_t*)0x4007C018U)

(QSPI) Interrupt Disable Register

Definition at line 64 of file instance/qspi.h.

◆ REG_QSPI_IER

#define REG_QSPI_IER   (*(__O uint32_t*)0x4007C014U)

(QSPI) Interrupt Enable Register

Definition at line 63 of file instance/qspi.h.

◆ REG_QSPI_IFR

#define REG_QSPI_IFR   (*(__IO uint32_t*)0x4007C038U)

(QSPI) Instruction Frame Register

Definition at line 69 of file instance/qspi.h.

◆ REG_QSPI_IMR

#define REG_QSPI_IMR   (*(__I uint32_t*)0x4007C01CU)

(QSPI) Interrupt Mask Register

Definition at line 65 of file instance/qspi.h.

◆ REG_QSPI_MR

#define REG_QSPI_MR   (*(__IO uint32_t*)0x4007C004U)

(QSPI) Mode Register

Definition at line 59 of file instance/qspi.h.

◆ REG_QSPI_RDR

#define REG_QSPI_RDR   (*(__I uint32_t*)0x4007C008U)

(QSPI) Receive Data Register

Definition at line 60 of file instance/qspi.h.

◆ REG_QSPI_SCR

#define REG_QSPI_SCR   (*(__IO uint32_t*)0x4007C020U)

(QSPI) Serial Clock Register

Definition at line 66 of file instance/qspi.h.

◆ REG_QSPI_SKR

#define REG_QSPI_SKR   (*(__O uint32_t*)0x4007C044U)

(QSPI) Scrambling Key Register

Definition at line 71 of file instance/qspi.h.

◆ REG_QSPI_SMR

#define REG_QSPI_SMR   (*(__IO uint32_t*)0x4007C040U)

(QSPI) Scrambling Mode Register

Definition at line 70 of file instance/qspi.h.

◆ REG_QSPI_SR

#define REG_QSPI_SR   (*(__I uint32_t*)0x4007C010U)

(QSPI) Status Register

Definition at line 62 of file instance/qspi.h.

◆ REG_QSPI_TDR

#define REG_QSPI_TDR   (*(__O uint32_t*)0x4007C00CU)

(QSPI) Transmit Data Register

Definition at line 61 of file instance/qspi.h.

◆ REG_QSPI_VERSION

#define REG_QSPI_VERSION   (*(__I uint32_t*)0x4007C0FCU)

(QSPI) Version Register

Definition at line 74 of file instance/qspi.h.

◆ REG_QSPI_WPMR

#define REG_QSPI_WPMR   (*(__IO uint32_t*)0x4007C0E4U)

(QSPI) Write Protection Mode Register

Definition at line 72 of file instance/qspi.h.

◆ REG_QSPI_WPSR

#define REG_QSPI_WPSR   (*(__I uint32_t*)0x4007C0E8U)

(QSPI) Write Protection Status Register

Definition at line 73 of file instance/qspi.h.



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autogenerated on Sat Sep 19 2020 03:19:06