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Macros | |
#define | REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) |
(TWIHS1) Control Register More... | |
#define | REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) |
(TWIHS1) Clock Waveform Generator Register More... | |
#define | REG_TWIHS1_DR (*(__I uint32_t*)0x4001C0D0U) |
(TWIHS1) Debug Register More... | |
#define | REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) |
(TWIHS1) Filter Register More... | |
#define | REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) |
(TWIHS1) Internal Address Register More... | |
#define | REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) |
(TWIHS1) Interrupt Disable Register More... | |
#define | REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) |
(TWIHS1) Interrupt Enable Register More... | |
#define | REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) |
(TWIHS1) Interrupt Mask Register More... | |
#define | REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) |
(TWIHS1) Master Mode Register More... | |
#define | REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) |
(TWIHS1) Receive Holding Register More... | |
#define | REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) |
(TWIHS1) SMBus Timing Register More... | |
#define | REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) |
(TWIHS1) Slave Mode Register More... | |
#define | REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) |
(TWIHS1) Status Register More... | |
#define | REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) |
(TWIHS1) SleepWalking Matching Register More... | |
#define | REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) |
(TWIHS1) Transmit Holding Register More... | |
#define | REG_TWIHS1_VER (*(__I uint32_t*)0x4001C0FCU) |
(TWIHS1) Version Register More... | |
#define | REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) |
(TWIHS1) Write Protection Mode Register More... | |
#define | REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) |
(TWIHS1) Write Protection Status Register More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file twihs1.h.
#define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) |
#define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) |
#define REG_TWIHS1_DR (*(__I uint32_t*)0x4001C0D0U) |
#define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) |
#define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) |
#define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) |
#define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) |
#define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) |
#define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) |
#define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) |
#define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) |
#define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) |
#define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) |
#define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) |
#define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) |
#define REG_TWIHS1_VER (*(__I uint32_t*)0x4001C0FCU) |
#define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) |