same70j20.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef _SAME70J20_
#define _SAME70J20_


#ifdef __cplusplus
 extern "C" {
#endif 

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#endif

/* ************************************************************************** */
/*   CMSIS DEFINITIONS FOR SAME70J20 */
/* ************************************************************************** */

typedef enum IRQn
{
/******  Cortex-M7 Processor Exceptions Numbers ******************************/
  NonMaskableInt_IRQn   = -14, 
  HardFault_IRQn        = -13, 
  MemoryManagement_IRQn = -12, 
  BusFault_IRQn         = -11, 
  UsageFault_IRQn       = -10, 
  SVCall_IRQn           = -5,  
  DebugMonitor_IRQn     = -4,  
  PendSV_IRQn           = -2,  
  SysTick_IRQn          = -1,  
/******  SAME70J20 specific Interrupt Numbers *********************************/
  
  SUPC_IRQn            =  0, 
  RSTC_IRQn            =  1, 
  RTC_IRQn             =  2, 
  RTT_IRQn             =  3, 
  WDT_IRQn             =  4, 
  PMC_IRQn             =  5, 
  EFC_IRQn             =  6, 
  UART0_IRQn           =  7, 
  UART1_IRQn           =  8, 
  PIOA_IRQn            = 10, 
  PIOB_IRQn            = 11, 
  USART0_IRQn          = 13, 
  USART1_IRQn          = 14, 
  PIOD_IRQn            = 16, 
  TWIHS0_IRQn          = 19, 
  TWIHS1_IRQn          = 20, 
  SSC_IRQn             = 22, 
  TC0_IRQn             = 23, 
  TC1_IRQn             = 24, 
  TC2_IRQn             = 25, 
  AFEC0_IRQn           = 29, 
  DACC_IRQn            = 30, 
  PWM0_IRQn            = 31, 
  ICM_IRQn             = 32, 
  ACC_IRQn             = 33, 
  USBHS_IRQn           = 34, 
  MCAN0_INT0_IRQn      = 35, 
  MCAN0_INT1_IRQn      = 36, 
  GMAC_IRQn            = 39, 
  AFEC1_IRQn           = 40, 
  QSPI_IRQn            = 43, 
  UART2_IRQn           = 44, 
  TC9_IRQn             = 50, 
  TC10_IRQn            = 51, 
  TC11_IRQn            = 52, 
  AES_IRQn             = 56, 
  TRNG_IRQn            = 57, 
  XDMAC_IRQn           = 58, 
  ISI_IRQn             = 59, 
  PWM1_IRQn            = 60, 
  FPU_IRQn             = 61, 
  RSWDT_IRQn           = 63, 
  CCW_IRQn             = 64, 
  CCF_IRQn             = 65, 
  GMAC_Q1_IRQn         = 66, 
  GMAC_Q2_IRQn         = 67, 
  IXC_IRQn             = 68, 
  PERIPH_COUNT_IRQn    = 74  
} IRQn_Type;

typedef struct _DeviceVectors
{
  /* Stack pointer */
  void* pvStack;
  
  /* Cortex-M handlers */
  void* pfnReset_Handler;
  void* pfnNMI_Handler;
  void* pfnHardFault_Handler;
  void* pfnMemManage_Handler;
  void* pfnBusFault_Handler;
  void* pfnUsageFault_Handler;
  void* pfnReserved1_Handler;
  void* pfnReserved2_Handler;
  void* pfnReserved3_Handler;
  void* pfnReserved4_Handler;
  void* pfnSVC_Handler;
  void* pfnDebugMon_Handler;
  void* pfnReserved5_Handler;
  void* pfnPendSV_Handler;
  void* pfnSysTick_Handler;

  /* Peripheral handlers */
  void* pfnSUPC_Handler;   /*  0 Supply Controller */
  void* pfnRSTC_Handler;   /*  1 Reset Controller */
  void* pfnRTC_Handler;    /*  2 Real Time Clock */
  void* pfnRTT_Handler;    /*  3 Real Time Timer */
  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
  void* pfnPMC_Handler;    /*  5 Power Management Controller */
  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
  void* pfnUART0_Handler;  /*  7 UART 0 */
  void* pfnUART1_Handler;  /*  8 UART 1 */
  void* pvReserved9;
  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
  void* pvReserved12;
  void* pfnUSART0_Handler; /* 13 USART 0 */
  void* pfnUSART1_Handler; /* 14 USART 1 */
  void* pvReserved15;
  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
  void* pvReserved17;
  void* pvReserved18; 
  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
  void* pvReserved21;
  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
  void* pvReserved26;
  void* pvReserved27;
  void* pvReserved28;
  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
  void* pfnACC_Handler;    /* 33 Analog Comparator */
  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
  void* pfnMCAN0_INT0_Handler;      /* 35  Controller Area Network (MCAN0) */
  void* pfnMCAN0_INT1_Handler;      /* 36  Controller Area Network (MCAN0) */
  void* pvReserved37;
  void* pvReserved38;
  void* pfnGMAC_Handler;   /* 39 Ethernet MAC */
  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
  void* pvReserved41;
  void* pvReserved42; 
  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
  void* pfnUART2_Handler;  /* 44 UART 2 */
  void* pvReserved45;
  void* pvReserved46; 
  void* pvReserved47;
  void* pvReserved48;
  void* pvReserved49;
  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
  void* pvReserved53;
  void* pvReserved54;
  void* pvReserved55;
  void* pfnAES_Handler;    /* 56 AES */
  void* pfnTRNG_Handler;   /* 57 True Random Generator */
  void* pfnXDMAC_Handler;  /* 58 DMA */
  void* pfnISI_Handler;    /* 59 Camera Interface */
  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
  void* pfnFPU_Handler;    /* 61 Floating Point Unit Registers (FPU) */
  void* pvReserved62;
  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
  void* pfnCCW_Handler;    /* 64 System Control Registers (SystemControl) */
  void* pfnCCF_Handler;    /* 65 System Control Registers (SystemControl) */
  void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */
  void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */
  void* pfnIXC_Handler;    /* 68 Floating Point Unit Registers (FPU) */
  void* pvReserved69;
  void* pvReserved70;
  void* pvReserved71;
  void* pvReserved72;
  void* pvReserved73;
} DeviceVectors;

/* Cortex-M7 core handlers */
void Reset_Handler      ( void );
void NMI_Handler        ( void );
void HardFault_Handler  ( void );
void MemManage_Handler  ( void );
void BusFault_Handler   ( void );
void UsageFault_Handler ( void );
void SVC_Handler        ( void );
void DebugMon_Handler   ( void );
void PendSV_Handler     ( void );
void SysTick_Handler    ( void );

/* Peripherals handlers */
void ACC_Handler        ( void );
void AES_Handler        ( void );
void AFEC0_Handler      ( void );
void AFEC1_Handler      ( void );
void CCF_Handler        ( void );
void CCW_Handler        ( void );
void EFC_Handler        ( void );
void FPU_Handler        ( void );
void GMAC_Handler       ( void );
void ICM_Handler        ( void );
void ISI_Handler        ( void );
void IXC_Handler        ( void );
void MCAN0_INT0_Handler ( void );
void MCAN0_INT1_Handler ( void );
void PIOA_Handler       ( void );
void PIOB_Handler       ( void );
void PIOD_Handler       ( void );
void PMC_Handler        ( void );
void PWM0_Handler       ( void );
void PWM1_Handler       ( void );
void GMAC_Q1_Handler    ( void );
void GMAC_Q2_Handler    ( void );
void QSPI_Handler       ( void );
void RSTC_Handler       ( void );
void RSWDT_Handler      ( void );
void RTC_Handler        ( void );
void RTT_Handler        ( void );
void SSC_Handler        ( void );
void SUPC_Handler       ( void );
void TC0_Handler        ( void );
void TC1_Handler        ( void );
void TC2_Handler        ( void );
void TC9_Handler        ( void );
void TC10_Handler       ( void );
void TC11_Handler       ( void );
void TRNG_Handler       ( void );
void TWIHS0_Handler     ( void );
void TWIHS1_Handler     ( void );
void UART0_Handler      ( void );
void UART1_Handler      ( void );
void UART2_Handler      ( void );
void USART0_Handler     ( void );
void USART1_Handler     ( void );
void USBHS_Handler      ( void );
void WDT_Handler        ( void );
void XDMAC_Handler      ( void );

#define __CM7_REV              0x0000 
#define __MPU_PRESENT          1      
#define __NVIC_PRIO_BITS       3      
#define __FPU_PRESENT          1      
#define __FPU_DP               1      
#define __ICACHE_PRESENT       1      
#define __DCACHE_PRESENT       1      
#define __DTCM_PRESENT         1      
#define __ITCM_PRESENT         1      
#define __Vendor_SysTickConfig 0      
#define __SAM_M7_REVB              0      
/*
 * \brief CMSIS includes
 */

#include <core_cm7.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_same70.h"
#endif /* DONT_USE_CMSIS_INIT */

/* ************************************************************************** */
/* ************************************************************************** */

#include "component/acc.h"
#include "component/aes.h"
#include "component/afec.h"
#include "component/chipid.h"
#include "component/dacc.h"
#include "component/efc.h"
#include "component/gmac.h"
#include "component/gpbr.h"
#include "component/icm.h"
#include "component/isi.h"
#include "component/matrix.h"
#include "component/mcan.h"
#include "component/pio.h"
#include "component/pmc.h"
#include "component/pwm.h"
#include "component/qspi.h"
#include "component/rstc.h"
#include "component/rswdt.h"
#include "component/rtc.h"
#include "component/rtt.h"
#include "component/ssc.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/trng.h"
#include "component/twihs.h"
#include "component/uart.h"
#include "component/usart.h"
#include "component/usbhs.h"
#include "component/utmi.h"
#include "component/wdt.h"
#include "component/xdmac.h"
/* ************************************************************************** */
/*   REGISTER ACCESS DEFINITIONS FOR SAME70J20 */
/* ************************************************************************** */

#include "instance/ssc.h"
#include "instance/tc0.h"
#include "instance/twihs0.h"
#include "instance/twihs1.h"
#include "instance/pwm0.h"
#include "instance/usart0.h"
#include "instance/usart1.h"
#include "instance/mcan0.h"
#include "instance/usbhs.h"
#include "instance/afec0.h"
#include "instance/acc.h"
#include "instance/dacc.h"
#include "instance/icm.h"
#include "instance/isi.h"
#include "instance/gmac.h"
#include "instance/tc3.h"
#include "instance/pwm1.h"
#include "instance/afec1.h"
#include "instance/aes.h"
#include "instance/trng.h"
#include "instance/xdmac.h"
#include "instance/qspi.h"
#include "instance/matrix.h"
#include "instance/utmi.h"
#include "instance/pmc.h"
#include "instance/uart0.h"
#include "instance/chipid.h"
#include "instance/uart1.h"
#include "instance/efc.h"
#include "instance/pioa.h"
#include "instance/piob.h"
#include "instance/piod.h"
#include "instance/rstc.h"
#include "instance/supc.h"
#include "instance/rtt.h"
#include "instance/wdt.h"
#include "instance/rtc.h"
#include "instance/gpbr.h"
#include "instance/rswdt.h"
#include "instance/uart2.h"
/* ************************************************************************** */
/*   PERIPHERAL ID DEFINITIONS FOR SAME70J20 */
/* ************************************************************************** */

#define ID_SUPC   ( 0) 
#define ID_RSTC   ( 1) 
#define ID_RTC    ( 2) 
#define ID_RTT    ( 3) 
#define ID_WDT    ( 4) 
#define ID_PMC    ( 5) 
#define ID_EFC    ( 6) 
#define ID_UART0  ( 7) 
#define ID_UART1  ( 8) 
#define ID_PIOA   (10) 
#define ID_PIOB   (11) 
#define ID_USART0 (13) 
#define ID_USART1 (14) 
#define ID_PIOD   (16) 
#define ID_TWIHS0 (19) 
#define ID_TWIHS1 (20) 
#define ID_SSC    (22) 
#define ID_TC0    (23) 
#define ID_TC1    (24) 
#define ID_TC2    (25) 
#define ID_AFEC0  (29) 
#define ID_DACC   (30) 
#define ID_PWM0   (31) 
#define ID_ICM    (32) 
#define ID_ACC    (33) 
#define ID_USBHS  (34) 
#define ID_MCAN0  (35) 
#define ID_MCAN1  (37) 
#define ID_GMAC   (39) 
#define ID_AFEC1  (40) 
#define ID_QSPI   (43) 
#define ID_UART2  (44) 
#define ID_TC9    (50) 
#define ID_TC10   (51) 
#define ID_TC11   (52) 
#define ID_AES    (56) 
#define ID_TRNG   (57) 
#define ID_XDMAC  (58) 
#define ID_ISI    (59) 
#define ID_PWM1   (60) 
#define ID_RSWDT  (63) 
#define ID_IXC    (68) 
#define ID_PERIPH_COUNT (74) 

/* ************************************************************************** */
/*   BASE ADDRESS DEFINITIONS FOR SAME70J20 */
/* ************************************************************************** */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define SSC    (0x40004000U) 
#define TC0    (0x4000C000U) 
#define TWIHS0 (0x40018000U) 
#define TWIHS1 (0x4001C000U) 
#define PWM0   (0x40020000U) 
#define USART0 (0x40024000U) 
#define USART1 (0x40028000U) 
#define MCAN0  (0x40030000U) 
#define MCAN1  (0x40034000U) 
#define USBHS  (0x40038000U) 
#define AFEC0  (0x4003C000U) 
#define DACC   (0x40040000U) 
#define ACC    (0x40044000U) 
#define ICM    (0x40048000U) 
#define ISI    (0x4004C000U) 
#define GMAC   (0x40050000U) 
#define TC3    (0x40054000U) 
#define PWM1   (0x4005C000U) 
#define AFEC1  (0x40064000U) 
#define AES    (0x4006C000U) 
#define TRNG   (0x40070000U) 
#define XDMAC  (0x40078000U) 
#define QSPI   (0x4007C000U) 
#define MATRIX (0x40088000U) 
#define UTMI   (0x400E0400U) 
#define PMC    (0x400E0600U) 
#define UART0  (0x400E0800U) 
#define CHIPID (0x400E0940U) 
#define UART1  (0x400E0A00U) 
#define EFC    (0x400E0C00U) 
#define PIOA   (0x400E0E00U) 
#define PIOB   (0x400E1000U) 
#define PIOD   (0x400E1400U) 
#define RSTC   (0x400E1800U) 
#define SUPC   (0x400E1810U) 
#define RTT    (0x400E1830U) 
#define WDT    (0x400E1850U) 
#define RTC    (0x400E1860U) 
#define GPBR   (0x400E1890U) 
#define RSWDT  (0x400E1900U) 
#define UART2  (0x400E1A00U) 
#else
#define SSC    ((Ssc    *)0x40004000U) 
#define TC0    ((Tc     *)0x4000C000U) 
#define TWIHS0 ((Twihs  *)0x40018000U) 
#define TWIHS1 ((Twihs  *)0x4001C000U) 
#define PWM0   ((Pwm    *)0x40020000U) 
#define USART0 ((Usart  *)0x40024000U) 
#define USART1 ((Usart  *)0x40028000U) 
#define MCAN0  ((Mcan   *)0x40030000U) 
#define MCAN1  ((Mcan   *)0x40034000U) 
#define USBHS  ((Usbhs  *)0x40038000U) 
#define AFEC0  ((Afec   *)0x4003C000U) 
#define DACC   ((Dacc   *)0x40040000U) 
#define ACC    ((Acc    *)0x40044000U) 
#define ICM    ((Icm    *)0x40048000U) 
#define ISI    ((Isi    *)0x4004C000U) 
#define GMAC   ((Gmac   *)0x40050000U) 
#define TC3    ((Tc     *)0x40054000U) 
#define PWM1   ((Pwm    *)0x4005C000U) 
#define AFEC1  ((Afec   *)0x40064000U) 
#define AES    ((Aes    *)0x4006C000U) 
#define TRNG   ((Trng   *)0x40070000U) 
#define XDMAC  ((Xdmac  *)0x40078000U) 
#define QSPI   ((Qspi   *)0x4007C000U) 
#define MATRIX ((Matrix *)0x40088000U) 
#define UTMI   ((Utmi   *)0x400E0400U) 
#define PMC    ((Pmc    *)0x400E0600U) 
#define UART0  ((Uart   *)0x400E0800U) 
#define CHIPID ((Chipid *)0x400E0940U) 
#define UART1  ((Uart   *)0x400E0A00U) 
#define EFC    ((Efc    *)0x400E0C00U) 
#define PIOA   ((Pio    *)0x400E0E00U) 
#define PIOB   ((Pio    *)0x400E1000U) 
#define PIOD   ((Pio    *)0x400E1400U) 
#define RSTC   ((Rstc   *)0x400E1800U) 
#define SUPC   ((Supc   *)0x400E1810U) 
#define RTT    ((Rtt    *)0x400E1830U) 
#define WDT    ((Wdt    *)0x400E1850U) 
#define RTC    ((Rtc    *)0x400E1860U) 
#define GPBR   ((Gpbr   *)0x400E1890U) 
#define RSWDT  ((Rswdt  *)0x400E1900U) 
#define UART2  ((Uart   *)0x400E1A00U) 
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* ************************************************************************** */
/*   PIO DEFINITIONS FOR SAME70J20 */
/* ************************************************************************** */

#include "pio/same70j20.h"
/* ************************************************************************** */
/*   MEMORY MAPPING DEFINITIONS FOR SAME70J20 */
/* ************************************************************************** */

#define IFLASH_SIZE             (0x100000u)
#define IFLASH_PAGE_SIZE        (512u)
#define IFLASH_LOCK_REGION_SIZE (8192u)
#define IFLASH_NB_OF_PAGES      (2048u)
#define IFLASH_NB_OF_LOCK_BITS  (64u)
#define IRAM_SIZE               (0x60000u)

#define QSPIMEM_ADDR  (0x80000000u) 
#define AXIMX_ADDR    (0xA0000000u) 
#define ITCM_ADDR     (0x00000000u) 
#define IFLASH_ADDR   (0x00400000u) 
#define IROM_ADDR     (0x00800000u) 
#define DTCM_ADDR     (0x20000000u) 
#define IRAM_ADDR     (0x20400000u) 
/* ************************************************************************** */
/*   MISCELLANEOUS DEFINITIONS FOR SAME70J20 */
/* ************************************************************************** */

#define CHIP_JTAGID (0x05B3D03FUL)
#define CHIP_CIDR   (0xA1020C00UL)
#define CHIP_EXID   (0x00000000UL)

/* ************************************************************************** */
/*   ELECTRICAL DEFINITIONS FOR SAME70J20 */
/* ************************************************************************** */

/* %ATMEL_ELECTRICAL% */

/* Device characteristics */
#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
#define CHIP_FREQ_SLCK_RC               (32000UL)
#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
#define CHIP_FREQ_CPU_MAX               (300000000UL)
#define CHIP_FREQ_XTAL_32K              (32768UL)
#define CHIP_FREQ_XTAL_12M              (12000000UL)

/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
#define CHIP_FREQ_FWS_0                 (23000000UL)  
#define CHIP_FREQ_FWS_1                 (46000000UL)  
#define CHIP_FREQ_FWS_2                 (69000000UL)  
#define CHIP_FREQ_FWS_3                 (92000000UL)  
#define CHIP_FREQ_FWS_4                 (115000000UL) 
#define CHIP_FREQ_FWS_5                 (138000000UL) 
#define CHIP_FREQ_FWS_6                 (150000000UL) 
#ifdef __cplusplus
}
#endif

#endif /* _SAME70J20_ */