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Macros | |
#define | REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) |
(UART1) Baud Rate Generator Register More... | |
#define | REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) |
(UART1) Comparison Register More... | |
#define | REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) |
(UART1) Control Register More... | |
#define | REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) |
(UART1) Interrupt Disable Register More... | |
#define | REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) |
(UART1) Interrupt Enable Register More... | |
#define | REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) |
(UART1) Interrupt Mask Register More... | |
#define | REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) |
(UART1) Mode Register More... | |
#define | REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) |
(UART1) Receive Holding Register More... | |
#define | REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) |
(UART1) Status Register More... | |
#define | REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) |
(UART1) Transmit Holding Register More... | |
#define | REG_UART1_VERSION (*(__I uint32_t*)0x400E0AFCU) |
(UART1) Version Register More... | |
#define | REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) |
(UART1) Write Protection Mode Register More... | |
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file uart1.h.
#define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) |
#define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) |
#define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) |
#define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) |
#define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) |
#define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) |
#define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) |
#define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) |
#define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) |
#define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) |
#define REG_UART1_VERSION (*(__I uint32_t*)0x400E0AFCU) |