stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_ARMV8MML_H_GENERIC
32 #define __CORE_ARMV8MML_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 /* CMSIS Armv8MML definitions */
66 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
69  __ARMv8MML_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (81U)
76 #if defined ( __CC_ARM )
77  #if defined __TARGET_FPU_VFP
78  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79  #define __FPU_USED 1U
80  #else
81  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82  #define __FPU_USED 0U
83  #endif
84  #else
85  #define __FPU_USED 0U
86  #endif
87 
88  #if defined(__ARM_FEATURE_DSP)
89  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
90  #define __DSP_USED 1U
91  #else
92  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
93  #define __DSP_USED 0U
94  #endif
95  #else
96  #define __DSP_USED 0U
97  #endif
98 
99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
100  #if defined __ARM_PCS_VFP
101  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
102  #define __FPU_USED 1U
103  #else
104  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
105  #define __FPU_USED 0U
106  #endif
107  #else
108  #define __FPU_USED 0U
109  #endif
110 
111  #if defined(__ARM_FEATURE_DSP)
112  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
113  #define __DSP_USED 1U
114  #else
115  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
116  #define __DSP_USED 0U
117  #endif
118  #else
119  #define __DSP_USED 0U
120  #endif
121 
122 #elif defined ( __GNUC__ )
123  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
124  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
125  #define __FPU_USED 1U
126  #else
127  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128  #define __FPU_USED 0U
129  #endif
130  #else
131  #define __FPU_USED 0U
132  #endif
133 
134  #if defined(__ARM_FEATURE_DSP)
135  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
136  #define __DSP_USED 1U
137  #else
138  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
139  #define __DSP_USED 0U
140  #endif
141  #else
142  #define __DSP_USED 0U
143  #endif
144 
145 #elif defined ( __ICCARM__ )
146  #if defined __ARMVFP__
147  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
148  #define __FPU_USED 1U
149  #else
150  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
151  #define __FPU_USED 0U
152  #endif
153  #else
154  #define __FPU_USED 0U
155  #endif
156 
157  #if defined(__ARM_FEATURE_DSP)
158  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
159  #define __DSP_USED 1U
160  #else
161  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
162  #define __DSP_USED 0U
163  #endif
164  #else
165  #define __DSP_USED 0U
166  #endif
167 
168 #elif defined ( __TI_ARM__ )
169  #if defined __TI_VFP_SUPPORT__
170  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
171  #define __FPU_USED 1U
172  #else
173  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
174  #define __FPU_USED 0U
175  #endif
176  #else
177  #define __FPU_USED 0U
178  #endif
179 
180 #elif defined ( __TASKING__ )
181  #if defined __FPU_VFP__
182  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
183  #define __FPU_USED 1U
184  #else
185  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
186  #define __FPU_USED 0U
187  #endif
188  #else
189  #define __FPU_USED 0U
190  #endif
191 
192 #elif defined ( __CSMC__ )
193  #if ( __CSMC__ & 0x400U)
194  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
195  #define __FPU_USED 1U
196  #else
197  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
198  #define __FPU_USED 0U
199  #endif
200  #else
201  #define __FPU_USED 0U
202  #endif
203 
204 #endif
205 
206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
207 
208 
209 #ifdef __cplusplus
210 }
211 #endif
212 
213 #endif /* __CORE_ARMV8MML_H_GENERIC */
214 
215 #ifndef __CMSIS_GENERIC
216 
217 #ifndef __CORE_ARMV8MML_H_DEPENDANT
218 #define __CORE_ARMV8MML_H_DEPENDANT
219 
220 #ifdef __cplusplus
221  extern "C" {
222 #endif
223 
224 /* check device defines and use defaults */
225 #if defined __CHECK_DEVICE_DEFINES
226  #ifndef __ARMv8MML_REV
227  #define __ARMv8MML_REV 0x0000U
228  #warning "__ARMv8MML_REV not defined in device header file; using default!"
229  #endif
230 
231  #ifndef __FPU_PRESENT
232  #define __FPU_PRESENT 0U
233  #warning "__FPU_PRESENT not defined in device header file; using default!"
234  #endif
235 
236  #ifndef __MPU_PRESENT
237  #define __MPU_PRESENT 0U
238  #warning "__MPU_PRESENT not defined in device header file; using default!"
239  #endif
240 
241  #ifndef __SAUREGION_PRESENT
242  #define __SAUREGION_PRESENT 0U
243  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
244  #endif
245 
246  #ifndef __DSP_PRESENT
247  #define __DSP_PRESENT 0U
248  #warning "__DSP_PRESENT not defined in device header file; using default!"
249  #endif
250 
251  #ifndef __NVIC_PRIO_BITS
252  #define __NVIC_PRIO_BITS 3U
253  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
254  #endif
255 
256  #ifndef __Vendor_SysTickConfig
257  #define __Vendor_SysTickConfig 0U
258  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
259  #endif
260 #endif
261 
262 /* IO definitions (access restrictions to peripheral registers) */
270 #ifdef __cplusplus
271  #define __I volatile
272 #else
273  #define __I volatile const
274 #endif
275 #define __O volatile
276 #define __IO volatile
278 /* following defines should be used for structure members */
279 #define __IM volatile const
280 #define __OM volatile
281 #define __IOM volatile
283 
287 /*******************************************************************************
288  * Register Abstraction
289  Core Register contain:
290  - Core Register
291  - Core NVIC Register
292  - Core SCB Register
293  - Core SysTick Register
294  - Core Debug Register
295  - Core MPU Register
296  - Core SAU Register
297  - Core FPU Register
298  ******************************************************************************/
299 
314 typedef union
315 {
316  struct
317  {
318  uint32_t _reserved0:16;
319  uint32_t GE:4;
320  uint32_t _reserved1:7;
321  uint32_t Q:1;
322  uint32_t V:1;
323  uint32_t C:1;
324  uint32_t Z:1;
325  uint32_t N:1;
326  } b;
327  uint32_t w;
328 } APSR_Type;
329 
330 /* APSR Register Definitions */
331 #define APSR_N_Pos 31U
332 #define APSR_N_Msk (1UL << APSR_N_Pos)
334 #define APSR_Z_Pos 30U
335 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
337 #define APSR_C_Pos 29U
338 #define APSR_C_Msk (1UL << APSR_C_Pos)
340 #define APSR_V_Pos 28U
341 #define APSR_V_Msk (1UL << APSR_V_Pos)
343 #define APSR_Q_Pos 27U
344 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
346 #define APSR_GE_Pos 16U
347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
353 typedef union
354 {
355  struct
356  {
357  uint32_t ISR:9;
358  uint32_t _reserved0:23;
359  } b;
360  uint32_t w;
361 } IPSR_Type;
362 
363 /* IPSR Register Definitions */
364 #define IPSR_ISR_Pos 0U
365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
371 typedef union
372 {
373  struct
374  {
375  uint32_t ISR:9;
376  uint32_t _reserved0:7;
377  uint32_t GE:4;
378  uint32_t _reserved1:4;
379  uint32_t T:1;
380  uint32_t IT:2;
381  uint32_t Q:1;
382  uint32_t V:1;
383  uint32_t C:1;
384  uint32_t Z:1;
385  uint32_t N:1;
386  } b;
387  uint32_t w;
388 } xPSR_Type;
389 
390 /* xPSR Register Definitions */
391 #define xPSR_N_Pos 31U
392 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
394 #define xPSR_Z_Pos 30U
395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
397 #define xPSR_C_Pos 29U
398 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
400 #define xPSR_V_Pos 28U
401 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
403 #define xPSR_Q_Pos 27U
404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
406 #define xPSR_IT_Pos 25U
407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
409 #define xPSR_T_Pos 24U
410 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
412 #define xPSR_GE_Pos 16U
413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
415 #define xPSR_ISR_Pos 0U
416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
422 typedef union
423 {
424  struct
425  {
426  uint32_t nPRIV:1;
427  uint32_t SPSEL:1;
428  uint32_t FPCA:1;
429  uint32_t SFPA:1;
430  uint32_t _reserved1:28;
431  } b;
432  uint32_t w;
433 } CONTROL_Type;
434 
435 /* CONTROL Register Definitions */
436 #define CONTROL_SFPA_Pos 3U
437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
439 #define CONTROL_FPCA_Pos 2U
440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
442 #define CONTROL_SPSEL_Pos 1U
443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
445 #define CONTROL_nPRIV_Pos 0U
446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
448 
461 typedef struct
462 {
463  __IOM uint32_t ISER[16U];
464  uint32_t RESERVED0[16U];
465  __IOM uint32_t ICER[16U];
466  uint32_t RSERVED1[16U];
467  __IOM uint32_t ISPR[16U];
468  uint32_t RESERVED2[16U];
469  __IOM uint32_t ICPR[16U];
470  uint32_t RESERVED3[16U];
471  __IOM uint32_t IABR[16U];
472  uint32_t RESERVED4[16U];
473  __IOM uint32_t ITNS[16U];
474  uint32_t RESERVED5[16U];
475  __IOM uint8_t IPR[496U];
476  uint32_t RESERVED6[580U];
477  __OM uint32_t STIR;
478 } NVIC_Type;
479 
480 /* Software Triggered Interrupt Register Definitions */
481 #define NVIC_STIR_INTID_Pos 0U
482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
484 
497 typedef struct
498 {
499  __IM uint32_t CPUID;
500  __IOM uint32_t ICSR;
501  __IOM uint32_t VTOR;
502  __IOM uint32_t AIRCR;
503  __IOM uint32_t SCR;
504  __IOM uint32_t CCR;
505  __IOM uint8_t SHPR[12U];
506  __IOM uint32_t SHCSR;
507  __IOM uint32_t CFSR;
508  __IOM uint32_t HFSR;
509  __IOM uint32_t DFSR;
510  __IOM uint32_t MMFAR;
511  __IOM uint32_t BFAR;
512  __IOM uint32_t AFSR;
513  __IM uint32_t ID_PFR[2U];
514  __IM uint32_t ID_DFR;
515  __IM uint32_t ID_ADR;
516  __IM uint32_t ID_MMFR[4U];
517  __IM uint32_t ID_ISAR[6U];
518  __IM uint32_t CLIDR;
519  __IM uint32_t CTR;
520  __IM uint32_t CCSIDR;
521  __IOM uint32_t CSSELR;
522  __IOM uint32_t CPACR;
523  __IOM uint32_t NSACR;
524  uint32_t RESERVED3[92U];
525  __OM uint32_t STIR;
526  uint32_t RESERVED4[15U];
527  __IM uint32_t MVFR0;
528  __IM uint32_t MVFR1;
529  __IM uint32_t MVFR2;
530  uint32_t RESERVED5[1U];
531  __OM uint32_t ICIALLU;
532  uint32_t RESERVED6[1U];
533  __OM uint32_t ICIMVAU;
534  __OM uint32_t DCIMVAC;
535  __OM uint32_t DCISW;
536  __OM uint32_t DCCMVAU;
537  __OM uint32_t DCCMVAC;
538  __OM uint32_t DCCSW;
539  __OM uint32_t DCCIMVAC;
540  __OM uint32_t DCCISW;
541  uint32_t RESERVED7[6U];
542  __IOM uint32_t ITCMCR;
543  __IOM uint32_t DTCMCR;
544  __IOM uint32_t AHBPCR;
545  __IOM uint32_t CACR;
546  __IOM uint32_t AHBSCR;
547  uint32_t RESERVED8[1U];
548  __IOM uint32_t ABFSR;
549 } SCB_Type;
550 
551 /* SCB CPUID Register Definitions */
552 #define SCB_CPUID_IMPLEMENTER_Pos 24U
553 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
555 #define SCB_CPUID_VARIANT_Pos 20U
556 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
558 #define SCB_CPUID_ARCHITECTURE_Pos 16U
559 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
561 #define SCB_CPUID_PARTNO_Pos 4U
562 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
564 #define SCB_CPUID_REVISION_Pos 0U
565 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
567 /* SCB Interrupt Control State Register Definitions */
568 #define SCB_ICSR_PENDNMISET_Pos 31U
569 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
571 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
572 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
574 #define SCB_ICSR_PENDNMICLR_Pos 30U
575 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
577 #define SCB_ICSR_PENDSVSET_Pos 28U
578 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
580 #define SCB_ICSR_PENDSVCLR_Pos 27U
581 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
583 #define SCB_ICSR_PENDSTSET_Pos 26U
584 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
586 #define SCB_ICSR_PENDSTCLR_Pos 25U
587 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
589 #define SCB_ICSR_STTNS_Pos 24U
590 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
592 #define SCB_ICSR_ISRPREEMPT_Pos 23U
593 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
595 #define SCB_ICSR_ISRPENDING_Pos 22U
596 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
598 #define SCB_ICSR_VECTPENDING_Pos 12U
599 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
601 #define SCB_ICSR_RETTOBASE_Pos 11U
602 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
604 #define SCB_ICSR_VECTACTIVE_Pos 0U
605 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
607 /* SCB Vector Table Offset Register Definitions */
608 #define SCB_VTOR_TBLOFF_Pos 7U
609 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
611 /* SCB Application Interrupt and Reset Control Register Definitions */
612 #define SCB_AIRCR_VECTKEY_Pos 16U
613 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
615 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
616 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
618 #define SCB_AIRCR_ENDIANESS_Pos 15U
619 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
621 #define SCB_AIRCR_PRIS_Pos 14U
622 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
624 #define SCB_AIRCR_BFHFNMINS_Pos 13U
625 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
627 #define SCB_AIRCR_PRIGROUP_Pos 8U
628 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
630 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
631 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
633 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
634 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
636 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
637 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
639 /* SCB System Control Register Definitions */
640 #define SCB_SCR_SEVONPEND_Pos 4U
641 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
643 #define SCB_SCR_SLEEPDEEPS_Pos 3U
644 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
646 #define SCB_SCR_SLEEPDEEP_Pos 2U
647 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
649 #define SCB_SCR_SLEEPONEXIT_Pos 1U
650 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
652 /* SCB Configuration Control Register Definitions */
653 #define SCB_CCR_BP_Pos 18U
654 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
656 #define SCB_CCR_IC_Pos 17U
657 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
659 #define SCB_CCR_DC_Pos 16U
660 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
662 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
663 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
665 #define SCB_CCR_BFHFNMIGN_Pos 8U
666 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
668 #define SCB_CCR_DIV_0_TRP_Pos 4U
669 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
671 #define SCB_CCR_UNALIGN_TRP_Pos 3U
672 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
674 #define SCB_CCR_USERSETMPEND_Pos 1U
675 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
677 /* SCB System Handler Control and State Register Definitions */
678 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
679 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
681 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
682 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
684 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U
685 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
687 #define SCB_SHCSR_USGFAULTENA_Pos 18U
688 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
690 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
691 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
693 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
694 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
696 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
697 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
699 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
700 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
702 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
703 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
705 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
706 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
708 #define SCB_SHCSR_SYSTICKACT_Pos 11U
709 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
711 #define SCB_SHCSR_PENDSVACT_Pos 10U
712 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
714 #define SCB_SHCSR_MONITORACT_Pos 8U
715 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
717 #define SCB_SHCSR_SVCALLACT_Pos 7U
718 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
720 #define SCB_SHCSR_NMIACT_Pos 5U
721 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
723 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U
724 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
726 #define SCB_SHCSR_USGFAULTACT_Pos 3U
727 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
729 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
730 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
732 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
733 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
735 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
736 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
738 /* SCB Configurable Fault Status Register Definitions */
739 #define SCB_CFSR_USGFAULTSR_Pos 16U
740 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
742 #define SCB_CFSR_BUSFAULTSR_Pos 8U
743 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
745 #define SCB_CFSR_MEMFAULTSR_Pos 0U
746 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
748 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
749 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
750 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
752 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
753 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
755 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
756 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
758 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
759 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
761 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
762 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
764 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
765 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
767 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
768 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
769 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
771 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
772 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
774 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
775 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
777 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
778 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
780 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
781 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
783 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
784 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
786 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
787 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
789 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
790 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
791 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
793 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
794 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
796 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
797 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
799 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
800 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
802 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
803 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
805 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
806 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
808 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
809 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
811 /* SCB Hard Fault Status Register Definitions */
812 #define SCB_HFSR_DEBUGEVT_Pos 31U
813 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
815 #define SCB_HFSR_FORCED_Pos 30U
816 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
818 #define SCB_HFSR_VECTTBL_Pos 1U
819 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
821 /* SCB Debug Fault Status Register Definitions */
822 #define SCB_DFSR_EXTERNAL_Pos 4U
823 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
825 #define SCB_DFSR_VCATCH_Pos 3U
826 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
828 #define SCB_DFSR_DWTTRAP_Pos 2U
829 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
831 #define SCB_DFSR_BKPT_Pos 1U
832 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
834 #define SCB_DFSR_HALTED_Pos 0U
835 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
837 /* SCB Non-Secure Access Control Register Definitions */
838 #define SCB_NSACR_CP11_Pos 11U
839 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
841 #define SCB_NSACR_CP10_Pos 10U
842 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
844 #define SCB_NSACR_CPn_Pos 0U
845 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
847 /* SCB Cache Level ID Register Definitions */
848 #define SCB_CLIDR_LOUU_Pos 27U
849 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
851 #define SCB_CLIDR_LOC_Pos 24U
852 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
854 /* SCB Cache Type Register Definitions */
855 #define SCB_CTR_FORMAT_Pos 29U
856 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
858 #define SCB_CTR_CWG_Pos 24U
859 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
861 #define SCB_CTR_ERG_Pos 20U
862 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
864 #define SCB_CTR_DMINLINE_Pos 16U
865 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
867 #define SCB_CTR_IMINLINE_Pos 0U
868 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
870 /* SCB Cache Size ID Register Definitions */
871 #define SCB_CCSIDR_WT_Pos 31U
872 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
874 #define SCB_CCSIDR_WB_Pos 30U
875 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
877 #define SCB_CCSIDR_RA_Pos 29U
878 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
880 #define SCB_CCSIDR_WA_Pos 28U
881 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
883 #define SCB_CCSIDR_NUMSETS_Pos 13U
884 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
886 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
887 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
889 #define SCB_CCSIDR_LINESIZE_Pos 0U
890 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
892 /* SCB Cache Size Selection Register Definitions */
893 #define SCB_CSSELR_LEVEL_Pos 1U
894 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
896 #define SCB_CSSELR_IND_Pos 0U
897 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
899 /* SCB Software Triggered Interrupt Register Definitions */
900 #define SCB_STIR_INTID_Pos 0U
901 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
903 /* SCB D-Cache Invalidate by Set-way Register Definitions */
904 #define SCB_DCISW_WAY_Pos 30U
905 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
907 #define SCB_DCISW_SET_Pos 5U
908 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
910 /* SCB D-Cache Clean by Set-way Register Definitions */
911 #define SCB_DCCSW_WAY_Pos 30U
912 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
914 #define SCB_DCCSW_SET_Pos 5U
915 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
917 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
918 #define SCB_DCCISW_WAY_Pos 30U
919 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
921 #define SCB_DCCISW_SET_Pos 5U
922 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
924 /* Instruction Tightly-Coupled Memory Control Register Definitions */
925 #define SCB_ITCMCR_SZ_Pos 3U
926 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
928 #define SCB_ITCMCR_RETEN_Pos 2U
929 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
931 #define SCB_ITCMCR_RMW_Pos 1U
932 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
934 #define SCB_ITCMCR_EN_Pos 0U
935 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
937 /* Data Tightly-Coupled Memory Control Register Definitions */
938 #define SCB_DTCMCR_SZ_Pos 3U
939 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
941 #define SCB_DTCMCR_RETEN_Pos 2U
942 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
944 #define SCB_DTCMCR_RMW_Pos 1U
945 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
947 #define SCB_DTCMCR_EN_Pos 0U
948 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
950 /* AHBP Control Register Definitions */
951 #define SCB_AHBPCR_SZ_Pos 1U
952 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
954 #define SCB_AHBPCR_EN_Pos 0U
955 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
957 /* L1 Cache Control Register Definitions */
958 #define SCB_CACR_FORCEWT_Pos 2U
959 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
961 #define SCB_CACR_ECCEN_Pos 1U
962 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
964 #define SCB_CACR_SIWT_Pos 0U
965 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
967 /* AHBS Control Register Definitions */
968 #define SCB_AHBSCR_INITCOUNT_Pos 11U
969 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
971 #define SCB_AHBSCR_TPRI_Pos 2U
972 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
974 #define SCB_AHBSCR_CTL_Pos 0U
975 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
977 /* Auxiliary Bus Fault Status Register Definitions */
978 #define SCB_ABFSR_AXIMTYPE_Pos 8U
979 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
981 #define SCB_ABFSR_EPPB_Pos 4U
982 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
984 #define SCB_ABFSR_AXIM_Pos 3U
985 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
987 #define SCB_ABFSR_AHBP_Pos 2U
988 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
990 #define SCB_ABFSR_DTCM_Pos 1U
991 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
993 #define SCB_ABFSR_ITCM_Pos 0U
994 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
996 
1009 typedef struct
1010 {
1011  uint32_t RESERVED0[1U];
1012  __IM uint32_t ICTR;
1013  __IOM uint32_t ACTLR;
1014  __IOM uint32_t CPPWR;
1015 } SCnSCB_Type;
1016 
1017 /* Interrupt Controller Type Register Definitions */
1018 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
1019 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
1021 
1034 typedef struct
1035 {
1036  __IOM uint32_t CTRL;
1037  __IOM uint32_t LOAD;
1038  __IOM uint32_t VAL;
1039  __IM uint32_t CALIB;
1040 } SysTick_Type;
1041 
1042 /* SysTick Control / Status Register Definitions */
1043 #define SysTick_CTRL_COUNTFLAG_Pos 16U
1044 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1046 #define SysTick_CTRL_CLKSOURCE_Pos 2U
1047 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1049 #define SysTick_CTRL_TICKINT_Pos 1U
1050 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1052 #define SysTick_CTRL_ENABLE_Pos 0U
1053 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1055 /* SysTick Reload Register Definitions */
1056 #define SysTick_LOAD_RELOAD_Pos 0U
1057 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1059 /* SysTick Current Register Definitions */
1060 #define SysTick_VAL_CURRENT_Pos 0U
1061 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1063 /* SysTick Calibration Register Definitions */
1064 #define SysTick_CALIB_NOREF_Pos 31U
1065 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1067 #define SysTick_CALIB_SKEW_Pos 30U
1068 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1070 #define SysTick_CALIB_TENMS_Pos 0U
1071 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1073 
1086 typedef struct
1087 {
1088  __OM union
1089  {
1090  __OM uint8_t u8;
1091  __OM uint16_t u16;
1092  __OM uint32_t u32;
1093  } PORT [32U];
1094  uint32_t RESERVED0[864U];
1095  __IOM uint32_t TER;
1096  uint32_t RESERVED1[15U];
1097  __IOM uint32_t TPR;
1098  uint32_t RESERVED2[15U];
1099  __IOM uint32_t TCR;
1100  uint32_t RESERVED3[29U];
1101  __OM uint32_t IWR;
1102  __IM uint32_t IRR;
1103  __IOM uint32_t IMCR;
1104  uint32_t RESERVED4[43U];
1105  __OM uint32_t LAR;
1106  __IM uint32_t LSR;
1107  uint32_t RESERVED5[1U];
1108  __IM uint32_t DEVARCH;
1109  uint32_t RESERVED6[4U];
1110  __IM uint32_t PID4;
1111  __IM uint32_t PID5;
1112  __IM uint32_t PID6;
1113  __IM uint32_t PID7;
1114  __IM uint32_t PID0;
1115  __IM uint32_t PID1;
1116  __IM uint32_t PID2;
1117  __IM uint32_t PID3;
1118  __IM uint32_t CID0;
1119  __IM uint32_t CID1;
1120  __IM uint32_t CID2;
1121  __IM uint32_t CID3;
1122 } ITM_Type;
1123 
1124 /* ITM Stimulus Port Register Definitions */
1125 #define ITM_STIM_DISABLED_Pos 1U
1126 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1128 #define ITM_STIM_FIFOREADY_Pos 0U
1129 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1131 /* ITM Trace Privilege Register Definitions */
1132 #define ITM_TPR_PRIVMASK_Pos 0U
1133 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1135 /* ITM Trace Control Register Definitions */
1136 #define ITM_TCR_BUSY_Pos 23U
1137 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1139 #define ITM_TCR_TRACEBUSID_Pos 16U
1140 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1142 #define ITM_TCR_GTSFREQ_Pos 10U
1143 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1145 #define ITM_TCR_TSPRESCALE_Pos 8U
1146 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1148 #define ITM_TCR_STALLENA_Pos 5U
1149 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1151 #define ITM_TCR_SWOENA_Pos 4U
1152 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1154 #define ITM_TCR_DWTENA_Pos 3U
1155 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1157 #define ITM_TCR_SYNCENA_Pos 2U
1158 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1160 #define ITM_TCR_TSENA_Pos 1U
1161 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1163 #define ITM_TCR_ITMENA_Pos 0U
1164 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1166 /* ITM Integration Write Register Definitions */
1167 #define ITM_IWR_ATVALIDM_Pos 0U
1168 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
1170 /* ITM Integration Read Register Definitions */
1171 #define ITM_IRR_ATREADYM_Pos 0U
1172 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
1174 /* ITM Integration Mode Control Register Definitions */
1175 #define ITM_IMCR_INTEGRATION_Pos 0U
1176 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
1178 /* ITM Lock Status Register Definitions */
1179 #define ITM_LSR_ByteAcc_Pos 2U
1180 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1182 #define ITM_LSR_Access_Pos 1U
1183 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1185 #define ITM_LSR_Present_Pos 0U
1186 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1188  /* end of group CMSIS_ITM */
1189 
1190 
1201 typedef struct
1202 {
1203  __IOM uint32_t CTRL;
1204  __IOM uint32_t CYCCNT;
1205  __IOM uint32_t CPICNT;
1206  __IOM uint32_t EXCCNT;
1207  __IOM uint32_t SLEEPCNT;
1208  __IOM uint32_t LSUCNT;
1209  __IOM uint32_t FOLDCNT;
1210  __IM uint32_t PCSR;
1211  __IOM uint32_t COMP0;
1212  uint32_t RESERVED1[1U];
1213  __IOM uint32_t FUNCTION0;
1214  uint32_t RESERVED2[1U];
1215  __IOM uint32_t COMP1;
1216  uint32_t RESERVED3[1U];
1217  __IOM uint32_t FUNCTION1;
1218  uint32_t RESERVED4[1U];
1219  __IOM uint32_t COMP2;
1220  uint32_t RESERVED5[1U];
1221  __IOM uint32_t FUNCTION2;
1222  uint32_t RESERVED6[1U];
1223  __IOM uint32_t COMP3;
1224  uint32_t RESERVED7[1U];
1225  __IOM uint32_t FUNCTION3;
1226  uint32_t RESERVED8[1U];
1227  __IOM uint32_t COMP4;
1228  uint32_t RESERVED9[1U];
1229  __IOM uint32_t FUNCTION4;
1230  uint32_t RESERVED10[1U];
1231  __IOM uint32_t COMP5;
1232  uint32_t RESERVED11[1U];
1233  __IOM uint32_t FUNCTION5;
1234  uint32_t RESERVED12[1U];
1235  __IOM uint32_t COMP6;
1236  uint32_t RESERVED13[1U];
1237  __IOM uint32_t FUNCTION6;
1238  uint32_t RESERVED14[1U];
1239  __IOM uint32_t COMP7;
1240  uint32_t RESERVED15[1U];
1241  __IOM uint32_t FUNCTION7;
1242  uint32_t RESERVED16[1U];
1243  __IOM uint32_t COMP8;
1244  uint32_t RESERVED17[1U];
1245  __IOM uint32_t FUNCTION8;
1246  uint32_t RESERVED18[1U];
1247  __IOM uint32_t COMP9;
1248  uint32_t RESERVED19[1U];
1249  __IOM uint32_t FUNCTION9;
1250  uint32_t RESERVED20[1U];
1251  __IOM uint32_t COMP10;
1252  uint32_t RESERVED21[1U];
1253  __IOM uint32_t FUNCTION10;
1254  uint32_t RESERVED22[1U];
1255  __IOM uint32_t COMP11;
1256  uint32_t RESERVED23[1U];
1257  __IOM uint32_t FUNCTION11;
1258  uint32_t RESERVED24[1U];
1259  __IOM uint32_t COMP12;
1260  uint32_t RESERVED25[1U];
1261  __IOM uint32_t FUNCTION12;
1262  uint32_t RESERVED26[1U];
1263  __IOM uint32_t COMP13;
1264  uint32_t RESERVED27[1U];
1265  __IOM uint32_t FUNCTION13;
1266  uint32_t RESERVED28[1U];
1267  __IOM uint32_t COMP14;
1268  uint32_t RESERVED29[1U];
1269  __IOM uint32_t FUNCTION14;
1270  uint32_t RESERVED30[1U];
1271  __IOM uint32_t COMP15;
1272  uint32_t RESERVED31[1U];
1273  __IOM uint32_t FUNCTION15;
1274  uint32_t RESERVED32[934U];
1275  __IM uint32_t LSR;
1276  uint32_t RESERVED33[1U];
1277  __IM uint32_t DEVARCH;
1278 } DWT_Type;
1279 
1280 /* DWT Control Register Definitions */
1281 #define DWT_CTRL_NUMCOMP_Pos 28U
1282 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1284 #define DWT_CTRL_NOTRCPKT_Pos 27U
1285 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1287 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1288 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1290 #define DWT_CTRL_NOCYCCNT_Pos 25U
1291 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1293 #define DWT_CTRL_NOPRFCNT_Pos 24U
1294 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1296 #define DWT_CTRL_CYCDISS_Pos 23U
1297 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1299 #define DWT_CTRL_CYCEVTENA_Pos 22U
1300 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1302 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1303 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1305 #define DWT_CTRL_LSUEVTENA_Pos 20U
1306 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1308 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1309 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1311 #define DWT_CTRL_EXCEVTENA_Pos 18U
1312 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1314 #define DWT_CTRL_CPIEVTENA_Pos 17U
1315 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1317 #define DWT_CTRL_EXCTRCENA_Pos 16U
1318 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1320 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1321 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1323 #define DWT_CTRL_SYNCTAP_Pos 10U
1324 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1326 #define DWT_CTRL_CYCTAP_Pos 9U
1327 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1329 #define DWT_CTRL_POSTINIT_Pos 5U
1330 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1332 #define DWT_CTRL_POSTPRESET_Pos 1U
1333 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1335 #define DWT_CTRL_CYCCNTENA_Pos 0U
1336 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1338 /* DWT CPI Count Register Definitions */
1339 #define DWT_CPICNT_CPICNT_Pos 0U
1340 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1342 /* DWT Exception Overhead Count Register Definitions */
1343 #define DWT_EXCCNT_EXCCNT_Pos 0U
1344 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1346 /* DWT Sleep Count Register Definitions */
1347 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1348 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1350 /* DWT LSU Count Register Definitions */
1351 #define DWT_LSUCNT_LSUCNT_Pos 0U
1352 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1354 /* DWT Folded-instruction Count Register Definitions */
1355 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1356 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1358 /* DWT Comparator Function Register Definitions */
1359 #define DWT_FUNCTION_ID_Pos 27U
1360 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1362 #define DWT_FUNCTION_MATCHED_Pos 24U
1363 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1365 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1366 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1368 #define DWT_FUNCTION_ACTION_Pos 4U
1369 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1371 #define DWT_FUNCTION_MATCH_Pos 0U
1372 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
1374  /* end of group CMSIS_DWT */
1375 
1376 
1387 typedef struct
1388 {
1389  __IM uint32_t SSPSR;
1390  __IOM uint32_t CSPSR;
1391  uint32_t RESERVED0[2U];
1392  __IOM uint32_t ACPR;
1393  uint32_t RESERVED1[55U];
1394  __IOM uint32_t SPPR;
1395  uint32_t RESERVED2[131U];
1396  __IM uint32_t FFSR;
1397  __IOM uint32_t FFCR;
1398  __IOM uint32_t PSCR;
1399  uint32_t RESERVED3[809U];
1400  __OM uint32_t LAR;
1401  __IM uint32_t LSR;
1402  uint32_t RESERVED4[4U];
1403  __IM uint32_t TYPE;
1404  __IM uint32_t DEVTYPE;
1405 } TPI_Type;
1406 
1407 /* TPI Asynchronous Clock Prescaler Register Definitions */
1408 #define TPI_ACPR_SWOSCALER_Pos 0U
1409 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
1411 /* TPI Selected Pin Protocol Register Definitions */
1412 #define TPI_SPPR_TXMODE_Pos 0U
1413 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1415 /* TPI Formatter and Flush Status Register Definitions */
1416 #define TPI_FFSR_FtNonStop_Pos 3U
1417 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1419 #define TPI_FFSR_TCPresent_Pos 2U
1420 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1422 #define TPI_FFSR_FtStopped_Pos 1U
1423 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1425 #define TPI_FFSR_FlInProg_Pos 0U
1426 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1428 /* TPI Formatter and Flush Control Register Definitions */
1429 #define TPI_FFCR_TrigIn_Pos 8U
1430 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1432 #define TPI_FFCR_FOnMan_Pos 6U
1433 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1435 #define TPI_FFCR_EnFCont_Pos 1U
1436 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1438 /* TPI Periodic Synchronization Control Register Definitions */
1439 #define TPI_PSCR_PSCount_Pos 0U
1440 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
1442 /* TPI Software Lock Status Register Definitions */
1443 #define TPI_LSR_nTT_Pos 1U
1444 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
1446 #define TPI_LSR_SLK_Pos 1U
1447 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
1449 #define TPI_LSR_SLI_Pos 0U
1450 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
1452 /* TPI DEVID Register Definitions */
1453 #define TPI_DEVID_NRZVALID_Pos 11U
1454 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1456 #define TPI_DEVID_MANCVALID_Pos 10U
1457 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1459 #define TPI_DEVID_PTINVALID_Pos 9U
1460 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1462 #define TPI_DEVID_FIFOSZ_Pos 6U
1463 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1465 /* TPI DEVTYPE Register Definitions */
1466 #define TPI_DEVTYPE_SubType_Pos 4U
1467 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1469 #define TPI_DEVTYPE_MajorType_Pos 0U
1470 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1472  /* end of group CMSIS_TPI */
1473 
1474 
1475 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1476 
1486 typedef struct
1487 {
1488  __IM uint32_t TYPE;
1489  __IOM uint32_t CTRL;
1490  __IOM uint32_t RNR;
1491  __IOM uint32_t RBAR;
1492  __IOM uint32_t RLAR;
1493  __IOM uint32_t RBAR_A1;
1494  __IOM uint32_t RLAR_A1;
1495  __IOM uint32_t RBAR_A2;
1496  __IOM uint32_t RLAR_A2;
1497  __IOM uint32_t RBAR_A3;
1498  __IOM uint32_t RLAR_A3;
1499  uint32_t RESERVED0[1];
1500  union {
1501  __IOM uint32_t MAIR[2];
1502  struct {
1503  __IOM uint32_t MAIR0;
1504  __IOM uint32_t MAIR1;
1505  };
1506  };
1507 } MPU_Type;
1508 
1509 #define MPU_TYPE_RALIASES 4U
1510 
1511 /* MPU Type Register Definitions */
1512 #define MPU_TYPE_IREGION_Pos 16U
1513 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1515 #define MPU_TYPE_DREGION_Pos 8U
1516 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1518 #define MPU_TYPE_SEPARATE_Pos 0U
1519 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1521 /* MPU Control Register Definitions */
1522 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1523 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1525 #define MPU_CTRL_HFNMIENA_Pos 1U
1526 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1528 #define MPU_CTRL_ENABLE_Pos 0U
1529 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1531 /* MPU Region Number Register Definitions */
1532 #define MPU_RNR_REGION_Pos 0U
1533 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1535 /* MPU Region Base Address Register Definitions */
1536 #define MPU_RBAR_BASE_Pos 5U
1537 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
1539 #define MPU_RBAR_SH_Pos 3U
1540 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1542 #define MPU_RBAR_AP_Pos 1U
1543 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1545 #define MPU_RBAR_XN_Pos 0U
1546 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1548 /* MPU Region Limit Address Register Definitions */
1549 #define MPU_RLAR_LIMIT_Pos 5U
1550 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1552 #define MPU_RLAR_AttrIndx_Pos 1U
1553 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1555 #define MPU_RLAR_EN_Pos 0U
1556 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1558 /* MPU Memory Attribute Indirection Register 0 Definitions */
1559 #define MPU_MAIR0_Attr3_Pos 24U
1560 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1562 #define MPU_MAIR0_Attr2_Pos 16U
1563 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1565 #define MPU_MAIR0_Attr1_Pos 8U
1566 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1568 #define MPU_MAIR0_Attr0_Pos 0U
1569 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1571 /* MPU Memory Attribute Indirection Register 1 Definitions */
1572 #define MPU_MAIR1_Attr7_Pos 24U
1573 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1575 #define MPU_MAIR1_Attr6_Pos 16U
1576 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1578 #define MPU_MAIR1_Attr5_Pos 8U
1579 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1581 #define MPU_MAIR1_Attr4_Pos 0U
1582 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1584 
1585 #endif
1586 
1587 
1588 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1589 
1599 typedef struct
1600 {
1601  __IOM uint32_t CTRL;
1602  __IM uint32_t TYPE;
1603 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1604  __IOM uint32_t RNR;
1605  __IOM uint32_t RBAR;
1606  __IOM uint32_t RLAR;
1607 #else
1608  uint32_t RESERVED0[3];
1609 #endif
1610  __IOM uint32_t SFSR;
1611  __IOM uint32_t SFAR;
1612 } SAU_Type;
1613 
1614 /* SAU Control Register Definitions */
1615 #define SAU_CTRL_ALLNS_Pos 1U
1616 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1618 #define SAU_CTRL_ENABLE_Pos 0U
1619 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1621 /* SAU Type Register Definitions */
1622 #define SAU_TYPE_SREGION_Pos 0U
1623 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1625 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1626 /* SAU Region Number Register Definitions */
1627 #define SAU_RNR_REGION_Pos 0U
1628 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1630 /* SAU Region Base Address Register Definitions */
1631 #define SAU_RBAR_BADDR_Pos 5U
1632 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1634 /* SAU Region Limit Address Register Definitions */
1635 #define SAU_RLAR_LADDR_Pos 5U
1636 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1638 #define SAU_RLAR_NSC_Pos 1U
1639 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1641 #define SAU_RLAR_ENABLE_Pos 0U
1642 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1644 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1645 
1646 /* Secure Fault Status Register Definitions */
1647 #define SAU_SFSR_LSERR_Pos 7U
1648 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1650 #define SAU_SFSR_SFARVALID_Pos 6U
1651 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1653 #define SAU_SFSR_LSPERR_Pos 5U
1654 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1656 #define SAU_SFSR_INVTRAN_Pos 4U
1657 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1659 #define SAU_SFSR_AUVIOL_Pos 3U
1660 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1662 #define SAU_SFSR_INVER_Pos 2U
1663 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1665 #define SAU_SFSR_INVIS_Pos 1U
1666 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1668 #define SAU_SFSR_INVEP_Pos 0U
1669 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1671 
1672 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1673 
1674 
1685 typedef struct
1686 {
1687  uint32_t RESERVED0[1U];
1688  __IOM uint32_t FPCCR;
1689  __IOM uint32_t FPCAR;
1690  __IOM uint32_t FPDSCR;
1691  __IM uint32_t MVFR0;
1692  __IM uint32_t MVFR1;
1693 } FPU_Type;
1694 
1695 /* Floating-Point Context Control Register Definitions */
1696 #define FPU_FPCCR_ASPEN_Pos 31U
1697 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1699 #define FPU_FPCCR_LSPEN_Pos 30U
1700 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1702 #define FPU_FPCCR_LSPENS_Pos 29U
1703 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1705 #define FPU_FPCCR_CLRONRET_Pos 28U
1706 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1708 #define FPU_FPCCR_CLRONRETS_Pos 27U
1709 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1711 #define FPU_FPCCR_TS_Pos 26U
1712 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1714 #define FPU_FPCCR_UFRDY_Pos 10U
1715 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1717 #define FPU_FPCCR_SPLIMVIOL_Pos 9U
1718 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1720 #define FPU_FPCCR_MONRDY_Pos 8U
1721 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1723 #define FPU_FPCCR_SFRDY_Pos 7U
1724 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1726 #define FPU_FPCCR_BFRDY_Pos 6U
1727 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1729 #define FPU_FPCCR_MMRDY_Pos 5U
1730 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1732 #define FPU_FPCCR_HFRDY_Pos 4U
1733 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1735 #define FPU_FPCCR_THREAD_Pos 3U
1736 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1738 #define FPU_FPCCR_S_Pos 2U
1739 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1741 #define FPU_FPCCR_USER_Pos 1U
1742 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1744 #define FPU_FPCCR_LSPACT_Pos 0U
1745 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1747 /* Floating-Point Context Address Register Definitions */
1748 #define FPU_FPCAR_ADDRESS_Pos 3U
1749 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1751 /* Floating-Point Default Status Control Register Definitions */
1752 #define FPU_FPDSCR_AHP_Pos 26U
1753 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1755 #define FPU_FPDSCR_DN_Pos 25U
1756 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1758 #define FPU_FPDSCR_FZ_Pos 24U
1759 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1761 #define FPU_FPDSCR_RMode_Pos 22U
1762 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1764 /* Media and FP Feature Register 0 Definitions */
1765 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1766 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1768 #define FPU_MVFR0_Short_vectors_Pos 24U
1769 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1771 #define FPU_MVFR0_Square_root_Pos 20U
1772 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1774 #define FPU_MVFR0_Divide_Pos 16U
1775 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1777 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1778 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1780 #define FPU_MVFR0_Double_precision_Pos 8U
1781 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1783 #define FPU_MVFR0_Single_precision_Pos 4U
1784 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1786 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1787 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1789 /* Media and FP Feature Register 1 Definitions */
1790 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1791 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1793 #define FPU_MVFR1_FP_HPFP_Pos 24U
1794 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1796 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1797 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1799 #define FPU_MVFR1_FtZ_mode_Pos 0U
1800 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1802 
1815 typedef struct
1816 {
1817  __IOM uint32_t DHCSR;
1818  __OM uint32_t DCRSR;
1819  __IOM uint32_t DCRDR;
1820  __IOM uint32_t DEMCR;
1821  uint32_t RESERVED4[1U];
1822  __IOM uint32_t DAUTHCTRL;
1823  __IOM uint32_t DSCSR;
1824 } CoreDebug_Type;
1825 
1826 /* Debug Halting Control and Status Register Definitions */
1827 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1828 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1830 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1831 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1833 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1834 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1836 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1837 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1839 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1840 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1842 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1843 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1845 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1846 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1848 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1849 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1851 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1852 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1854 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1855 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1857 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1858 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1860 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1861 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1863 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1864 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1866 /* Debug Core Register Selector Register Definitions */
1867 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1868 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1870 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1871 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1873 /* Debug Exception and Monitor Control Register Definitions */
1874 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1875 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1877 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1878 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1880 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1881 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1883 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1884 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1886 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1887 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1889 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1890 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1892 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1893 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1895 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1896 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1898 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1899 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1901 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1902 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1904 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1905 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1907 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1908 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1910 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1911 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1913 /* Debug Authentication Control Register Definitions */
1914 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1915 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1917 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1918 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1920 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1921 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1923 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1924 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1926 /* Debug Security Control and Status Register Definitions */
1927 #define CoreDebug_DSCSR_CDS_Pos 16U
1928 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1930 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1931 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1933 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1934 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1936 
1952 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1953 
1960 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1961 
1972 /* Memory mapping of Core Hardware */
1973  #define SCS_BASE (0xE000E000UL)
1974  #define ITM_BASE (0xE0000000UL)
1975  #define DWT_BASE (0xE0001000UL)
1976  #define TPI_BASE (0xE0040000UL)
1977  #define CoreDebug_BASE (0xE000EDF0UL)
1978  #define SysTick_BASE (SCS_BASE + 0x0010UL)
1979  #define NVIC_BASE (SCS_BASE + 0x0100UL)
1980  #define SCB_BASE (SCS_BASE + 0x0D00UL)
1982  #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1983  #define SCB ((SCB_Type *) SCB_BASE )
1984  #define SysTick ((SysTick_Type *) SysTick_BASE )
1985  #define NVIC ((NVIC_Type *) NVIC_BASE )
1986  #define ITM ((ITM_Type *) ITM_BASE )
1987  #define DWT ((DWT_Type *) DWT_BASE )
1988  #define TPI ((TPI_Type *) TPI_BASE )
1989  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
1991  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1992  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1993  #define MPU ((MPU_Type *) MPU_BASE )
1994  #endif
1995 
1996  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1997  #define SAU_BASE (SCS_BASE + 0x0DD0UL)
1998  #define SAU ((SAU_Type *) SAU_BASE )
1999  #endif
2000 
2001  #define FPU_BASE (SCS_BASE + 0x0F30UL)
2002  #define FPU ((FPU_Type *) FPU_BASE )
2004 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2005  #define SCS_BASE_NS (0xE002E000UL)
2006  #define CoreDebug_BASE_NS (0xE002EDF0UL)
2007  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
2008  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
2009  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
2011  #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
2012  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
2013  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
2014  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
2015  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
2017  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2018  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
2019  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
2020  #endif
2021 
2022  #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
2023  #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
2025 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2026 
2030 /*******************************************************************************
2031  * Hardware Abstraction Layer
2032  Core Function Interface contains:
2033  - Core NVIC Functions
2034  - Core SysTick Functions
2035  - Core Debug Functions
2036  - Core Register Access Functions
2037  ******************************************************************************/
2044 /* ########################## NVIC functions #################################### */
2052 #ifdef CMSIS_NVIC_VIRTUAL
2053  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2054  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2055  #endif
2056  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2057 #else
2058  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2059  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2060  #define NVIC_EnableIRQ __NVIC_EnableIRQ
2061  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2062  #define NVIC_DisableIRQ __NVIC_DisableIRQ
2063  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2064  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2065  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2066  #define NVIC_GetActive __NVIC_GetActive
2067  #define NVIC_SetPriority __NVIC_SetPriority
2068  #define NVIC_GetPriority __NVIC_GetPriority
2069  #define NVIC_SystemReset __NVIC_SystemReset
2070 #endif /* CMSIS_NVIC_VIRTUAL */
2071 
2072 #ifdef CMSIS_VECTAB_VIRTUAL
2073  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2074  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2075  #endif
2076  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2077 #else
2078  #define NVIC_SetVector __NVIC_SetVector
2079  #define NVIC_GetVector __NVIC_GetVector
2080 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2081 
2082 #define NVIC_USER_IRQ_OFFSET 16
2083 
2084 
2085 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2086 
2087 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2088 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2089 
2090 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2091 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2092 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2093 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2094 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2095 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2096 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
2097 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2098 
2099 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2101 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2102 #else
2103 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2104 #endif
2105 
2106 
2116 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2117 {
2118  uint32_t reg_value;
2119  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2120 
2121  reg_value = SCB->AIRCR; /* read old register configuration */
2122  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2123  reg_value = (reg_value |
2124  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2125  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2126  SCB->AIRCR = reg_value;
2127 }
2128 
2129 
2135 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2136 {
2137  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2138 }
2139 
2140 
2147 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2148 {
2149  if ((int32_t)(IRQn) >= 0)
2150  {
2151  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2152  }
2153 }
2154 
2155 
2164 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2165 {
2166  if ((int32_t)(IRQn) >= 0)
2167  {
2168  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2169  }
2170  else
2171  {
2172  return(0U);
2173  }
2174 }
2175 
2176 
2183 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2184 {
2185  if ((int32_t)(IRQn) >= 0)
2186  {
2187  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2188  __DSB();
2189  __ISB();
2190  }
2191 }
2192 
2193 
2202 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2203 {
2204  if ((int32_t)(IRQn) >= 0)
2205  {
2206  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2207  }
2208  else
2209  {
2210  return(0U);
2211  }
2212 }
2213 
2214 
2221 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2222 {
2223  if ((int32_t)(IRQn) >= 0)
2224  {
2225  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2226  }
2227 }
2228 
2229 
2236 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2237 {
2238  if ((int32_t)(IRQn) >= 0)
2239  {
2240  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2241  }
2242 }
2243 
2244 
2253 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2254 {
2255  if ((int32_t)(IRQn) >= 0)
2256  {
2257  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2258  }
2259  else
2260  {
2261  return(0U);
2262  }
2263 }
2264 
2265 
2266 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2267 
2275 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2276 {
2277  if ((int32_t)(IRQn) >= 0)
2278  {
2279  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2280  }
2281  else
2282  {
2283  return(0U);
2284  }
2285 }
2286 
2287 
2296 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2297 {
2298  if ((int32_t)(IRQn) >= 0)
2299  {
2300  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2301  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2302  }
2303  else
2304  {
2305  return(0U);
2306  }
2307 }
2308 
2309 
2318 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2319 {
2320  if ((int32_t)(IRQn) >= 0)
2321  {
2322  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2323  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2324  }
2325  else
2326  {
2327  return(0U);
2328  }
2329 }
2330 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2331 
2332 
2342 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2343 {
2344  if ((int32_t)(IRQn) >= 0)
2345  {
2346  NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2347  }
2348  else
2349  {
2350  SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2351  }
2352 }
2353 
2354 
2364 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2365 {
2366 
2367  if ((int32_t)(IRQn) >= 0)
2368  {
2369  return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2370  }
2371  else
2372  {
2373  return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2374  }
2375 }
2376 
2377 
2389 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2390 {
2391  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2392  uint32_t PreemptPriorityBits;
2393  uint32_t SubPriorityBits;
2394 
2395  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2396  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2397 
2398  return (
2399  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2400  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2401  );
2402 }
2403 
2404 
2416 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2417 {
2418  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2419  uint32_t PreemptPriorityBits;
2420  uint32_t SubPriorityBits;
2421 
2422  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2423  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2424 
2425  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2426  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2427 }
2428 
2429 
2439 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2440 {
2441  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2442  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2443 }
2444 
2445 
2454 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2455 {
2456  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2457  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2458 }
2459 
2460 
2465 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2466 {
2467  __DSB(); /* Ensure all outstanding memory accesses included
2468  buffered write are completed before reset */
2469  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2470  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2471  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2472  __DSB(); /* Ensure completion of memory access */
2473 
2474  for(;;) /* wait until reset */
2475  {
2476  __NOP();
2477  }
2478 }
2479 
2480 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2481 
2490 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2491 {
2492  uint32_t reg_value;
2493  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2494 
2495  reg_value = SCB_NS->AIRCR; /* read old register configuration */
2496  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2497  reg_value = (reg_value |
2498  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2499  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2500  SCB_NS->AIRCR = reg_value;
2501 }
2502 
2503 
2509 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2510 {
2511  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2512 }
2513 
2514 
2521 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2522 {
2523  if ((int32_t)(IRQn) >= 0)
2524  {
2525  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2526  }
2527 }
2528 
2529 
2538 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2539 {
2540  if ((int32_t)(IRQn) >= 0)
2541  {
2542  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2543  }
2544  else
2545  {
2546  return(0U);
2547  }
2548 }
2549 
2550 
2557 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2558 {
2559  if ((int32_t)(IRQn) >= 0)
2560  {
2561  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2562  }
2563 }
2564 
2565 
2574 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2575 {
2576  if ((int32_t)(IRQn) >= 0)
2577  {
2578  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2579  }
2580  else
2581  {
2582  return(0U);
2583  }
2584 }
2585 
2586 
2593 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2594 {
2595  if ((int32_t)(IRQn) >= 0)
2596  {
2597  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2598  }
2599 }
2600 
2601 
2608 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2609 {
2610  if ((int32_t)(IRQn) >= 0)
2611  {
2612  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2613  }
2614 }
2615 
2616 
2625 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2626 {
2627  if ((int32_t)(IRQn) >= 0)
2628  {
2629  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2630  }
2631  else
2632  {
2633  return(0U);
2634  }
2635 }
2636 
2637 
2647 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2648 {
2649  if ((int32_t)(IRQn) >= 0)
2650  {
2651  NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2652  }
2653  else
2654  {
2655  SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2656  }
2657 }
2658 
2659 
2668 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2669 {
2670 
2671  if ((int32_t)(IRQn) >= 0)
2672  {
2673  return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2674  }
2675  else
2676  {
2677  return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2678  }
2679 }
2680 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2681 
2684 /* ########################## MPU functions #################################### */
2685 
2686 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2687 
2688 #include "mpu_armv8.h"
2689 
2690 #endif
2691 
2692 /* ########################## FPU functions #################################### */
2708 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2709 {
2710  uint32_t mvfr0;
2711 
2712  mvfr0 = FPU->MVFR0;
2713  if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2714  {
2715  return 2U; /* Double + Single precision FPU */
2716  }
2717  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2718  {
2719  return 1U; /* Single precision FPU */
2720  }
2721  else
2722  {
2723  return 0U; /* No FPU */
2724  }
2725 }
2726 
2727 
2732 /* ########################## SAU functions #################################### */
2740 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2741 
2746 __STATIC_INLINE void TZ_SAU_Enable(void)
2747 {
2748  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2749 }
2750 
2751 
2752 
2757 __STATIC_INLINE void TZ_SAU_Disable(void)
2758 {
2759  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2760 }
2761 
2762 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2763 
2769 /* ################################## SysTick function ############################################ */
2777 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2778 
2790 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2791 {
2792  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2793  {
2794  return (1UL); /* Reload value impossible */
2795  }
2796 
2797  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2798  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2799  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2800  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2801  SysTick_CTRL_TICKINT_Msk |
2802  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2803  return (0UL); /* Function successful */
2804 }
2805 
2806 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2807 
2819 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2820 {
2821  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2822  {
2823  return (1UL); /* Reload value impossible */
2824  }
2825 
2826  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2827  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2828  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2829  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2830  SysTick_CTRL_TICKINT_Msk |
2831  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2832  return (0UL); /* Function successful */
2833 }
2834 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2835 
2836 #endif
2837 
2842 /* ##################################### Debug In/Output function ########################################### */
2850 extern volatile int32_t ITM_RxBuffer;
2851 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2862 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2863 {
2864  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2865  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2866  {
2867  while (ITM->PORT[0U].u32 == 0UL)
2868  {
2869  __NOP();
2870  }
2871  ITM->PORT[0U].u8 = (uint8_t)ch;
2872  }
2873  return (ch);
2874 }
2875 
2876 
2883 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2884 {
2885  int32_t ch = -1; /* no character available */
2886 
2887  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2888  {
2889  ch = ITM_RxBuffer;
2890  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2891  }
2892 
2893  return (ch);
2894 }
2895 
2896 
2903 __STATIC_INLINE int32_t ITM_CheckChar (void)
2904 {
2905 
2906  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2907  {
2908  return (0); /* no character available */
2909  }
2910  else
2911  {
2912  return (1); /* character available */
2913  }
2914 }
2915 
2921 #ifdef __cplusplus
2922 }
2923 #endif
2924 
2925 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
2926 
2927 #endif /* __CMSIS_GENERIC */
SCB
#define SCB
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1983
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2054
APSR_Type::@376::Q
uint32_t Q
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:321
COMP2
#define COMP2
Definition: stm32h735xx.h:2592
APSR_Type::@376::C
uint32_t C
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:323
COMP1
#define COMP1
Definition: stm32h735xx.h:2591
__IOM
#define __IOM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:281
IPSR_Type::@377::ISR
uint32_t ISR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:357
IRQn
IRQn
Definition: MIMXRT1052.h:78
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2106
SCB_Type::ID_ADR
__IM uint32_t ID_ADR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:515
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1047
cmsis_compiler.h
CMSIS compiler generic header file.
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:331
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:634
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:944
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1781
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:274
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1031
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:933
xPSR_Type::@378::IT
uint32_t IT
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:380
ITM_Type::IMCR
__IOM uint32_t IMCR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1103
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1052.h:91
ITM_Type::IWR
__OM uint32_t IWR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1101
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2079
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2701
__NOP
#define __NOP
No Operation.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:416
ITM_Type::DEVARCH
__IM uint32_t DEVARCH
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1108
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2010
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1978
ITM_Type::@380::u32
__OM uint32_t u32
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1092
xPSR_Type::@378::Z
uint32_t Z
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:384
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:455
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1164
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1050
ITM
#define ITM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1986
CONTROL_Type::@379::FPCA
uint32_t FPCA
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:428
CONTROL_Type::@379::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:430
__IM
#define __IM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:279
APSR_Type::@376::V
uint32_t V
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:322
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1119
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1902
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1993
__STATIC_INLINE
#define __STATIC_INLINE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:63
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
__OM
#define __OM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:280
SCB_Type::NSACR
__IOM uint32_t NSACR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:523
xPSR_Type::@378::T
uint32_t T
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:379
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1057
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f407xx.h:66
APSR_Type::@376::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:320
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:386
APSR_Type::@376::N
uint32_t N
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:325
xPSR_Type::@378::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:376
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2129
CONTROL_Type::@379::SFPA
uint32_t SFPA
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:429
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:612
IPSR_Type::@377::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:358
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1871
SCnSCB_Type::CPPWR
__IOM uint32_t CPPWR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1014
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1940
NVIC
#define NVIC
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1985
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2681
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2145
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:2851
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1639
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:627
NVIC_SetPriority
#define NVIC_SetPriority
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:2067
CONTROL_Type::@379::SPSEL
uint32_t SPSEL
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:427
CONTROL_Type::@379::nPRIV
uint32_t nPRIV
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:426
xPSR_Type::@378::GE
uint32_t GE
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:377
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1527
ITM_Type::IRR
__IM uint32_t IRR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1102
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1269
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1053
xPSR_Type::@378::N
uint32_t N
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:385
__NO_RETURN
#define __NO_RETURN
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:69
ITM_Type::@380::u8
__OM uint8_t u8
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1090
COMP12
#define COMP12
Definition: stm32h735xx.h:2590
DWT_Type::DEVARCH
__IM uint32_t DEVARCH
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1277
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:421
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1890
SysTick
#define SysTick
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1984
APSR_Type::@376::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:318
xPSR_Type::@378::Q
uint32_t Q
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:381
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:2082
xPSR_Type::@378::V
uint32_t V
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:382
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:921
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:628
cmsis_version.h
CMSIS Core(M) Version definitions.
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2156
APSR_Type::@376::GE
uint32_t GE
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:319
ITM_Type::@380::u16
__OM uint16_t u16
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1091
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2032
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2199
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1959
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1052.h:266
FPU
#define FPU
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:2002
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:979
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:313
xPSR_Type::@378::C
uint32_t C
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:383
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1921
APSR_Type::@376::Z
uint32_t Z
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:324
xPSR_Type::@378::ISR
uint32_t ISR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:375
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:1784
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:613
xPSR_Type::@378::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h:378

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:13:48