Type definitions for the Core Debug Registers. More...

Collaboration diagram for Core Debug Registers (CoreDebug):

Modules
	Core register bit field macros
	Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

Classes
struct	CoreDebug_Type
	Structure type to access the Core Debug Register (CoreDebug). More...

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

Detailed Description

Type definitions for the Core Debug Registers.

SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file.

Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M1 header file.

Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file.

Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file.

Macro Definition Documentation

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [1/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1061 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [2/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1061 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [3/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1061 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [4/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1061 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [5/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1136 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [6/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1136 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [7/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1136 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [8/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1136 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [9/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1826 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [10/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1901 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [11/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1901 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [12/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1921 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [13/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1921 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [14/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1921 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [15/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1982 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [16/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1996 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [17/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1996 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [18/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1996 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [1/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1060 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [2/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1060 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [3/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1060 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [4/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1060 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [5/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1135 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [6/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1135 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [7/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1135 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [8/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1135 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [9/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1825 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [10/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1900 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [11/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1900 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [12/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1920 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [13/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1920 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [14/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1920 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [15/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1981 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [16/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1995 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [17/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1995 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [18/18]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1995 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [1/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1055 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [2/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1055 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [3/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1055 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [4/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1055 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [5/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1130 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [6/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1130 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [7/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1130 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [8/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1130 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [9/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1820 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [10/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1895 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [11/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1895 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [12/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1915 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [13/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1915 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [14/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1915 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [15/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1976 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [16/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1990 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [17/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1990 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [18/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1990 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [1/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1054 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [2/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1054 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [3/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1054 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [4/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1054 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [5/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1129 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [6/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1129 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [7/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1129 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [8/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1129 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [9/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1819 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [10/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1894 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [11/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1894 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [12/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1914 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [13/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1914 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [14/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1914 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [15/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1975 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [16/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1989 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [17/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1989 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [18/18]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1989 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [1/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1064 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [2/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1064 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [3/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1064 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [4/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1064 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [5/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1139 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [6/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1139 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [7/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1139 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [8/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1139 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [9/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1829 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [10/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1904 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [11/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1904 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [12/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1924 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [13/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1924 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [14/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1924 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [15/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1985 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [16/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1999 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [17/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1999 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [18/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1999 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [1/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1063 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [2/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1063 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [3/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1063 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [4/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1063 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [5/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1138 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [6/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1138 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [7/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1138 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [8/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1138 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [9/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1828 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [10/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1903 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [11/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1903 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [12/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1923 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [13/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1923 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [14/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1923 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [15/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1984 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [16/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1998 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [17/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1998 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [18/18]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1998 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [1/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1058 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [2/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1058 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [3/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1058 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [4/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1058 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [5/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1133 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [6/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1133 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [7/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1133 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [8/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1133 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [9/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1823 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [10/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1898 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [11/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1898 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [12/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1918 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [13/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1918 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [14/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1918 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [15/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1979 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [16/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1993 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [17/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1993 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [18/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1993 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [1/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1057 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [2/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1057 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [3/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1057 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [4/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1057 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [5/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1132 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [6/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1132 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [7/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1132 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [8/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1132 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [9/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1822 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [10/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1897 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [11/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1897 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [12/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1917 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [13/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1917 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [14/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1917 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [15/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1978 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [16/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1992 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [17/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1992 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [18/18]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1992 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [1/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1041 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [2/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1041 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [3/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1041 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [4/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1041 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [5/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1116 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [6/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1116 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [7/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1116 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [8/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1116 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [9/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1279 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [10/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1284 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [11/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1284 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [12/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1284 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [13/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1296 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [14/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1304 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [15/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1304 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [16/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1304 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [17/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1466 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [18/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1475 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [19/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1475 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [20/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1475 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [21/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1475 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [22/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1475 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [23/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1683 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [24/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1683 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [25/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1683 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [26/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1683 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [27/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1689 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [28/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1689 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [29/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1776 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [30/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1851 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [31/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1851 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [32/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1871 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [33/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1871 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [34/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1871 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [35/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1932 of file core_armv81mml.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [36/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1946 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [37/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1946 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [38/38]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1946 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [1/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1040 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [2/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1040 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [3/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1040 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [4/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1040 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [5/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1115 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [6/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1115 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [7/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1115 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [8/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1115 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [9/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1278 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [10/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1283 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [11/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1283 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [12/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1283 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [13/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1295 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [14/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1303 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [15/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1303 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [16/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1303 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [17/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1465 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [18/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1474 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [19/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1474 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [20/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1474 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [21/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1474 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [22/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1474 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [23/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1682 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [24/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1682 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [25/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1682 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [26/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1682 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [27/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1688 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [28/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1688 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [29/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1775 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [30/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1850 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [31/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1850 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [32/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1870 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [33/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1870 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [34/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1870 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [35/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1931 of file core_armv81mml.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [36/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1945 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [37/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1945 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [38/38]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1945 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [1/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1038 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [2/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1038 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [3/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1038 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [4/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1038 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [5/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1113 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [6/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1113 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [7/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1113 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [8/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1113 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [9/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1276 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [10/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1281 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [11/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1281 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [12/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1281 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [13/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1293 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [14/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1301 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [15/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1301 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [16/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1301 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [17/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1463 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [18/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1472 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [19/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1472 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [20/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1472 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [21/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1472 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [22/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1472 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [23/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1680 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [24/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1680 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [25/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1680 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [26/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1680 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [27/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1686 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [28/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1686 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [29/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1773 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [30/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1848 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [31/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1848 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [32/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1868 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [33/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1868 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [34/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1868 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [35/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1929 of file core_armv81mml.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [36/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1943 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [37/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1943 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [38/38]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1943 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [1/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1037 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [2/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1037 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [3/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1037 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [4/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1037 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [5/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1112 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [6/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1112 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [7/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1112 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [8/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1112 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [9/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1275 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [10/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1280 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [11/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1280 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [12/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1280 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [13/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1292 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [14/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1300 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [15/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1300 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [16/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1300 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [17/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1462 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [18/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1471 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [19/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1471 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [20/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1471 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [21/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1471 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [22/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1471 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [23/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1679 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [24/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1679 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [25/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1679 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [26/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1679 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [27/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1685 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [28/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1685 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [29/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1772 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [30/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1847 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [31/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1847 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [32/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1867 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [33/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1867 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [34/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1867 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [35/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1928 of file core_armv81mml.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [36/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1942 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [37/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1942 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [38/38]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1942 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_DWTENA_Msk [1/8]

#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

CoreDebug DEMCR: DWTENA Mask

Definition at line 1045 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_DWTENA_Msk [2/8]

#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

CoreDebug DEMCR: DWTENA Mask

Definition at line 1045 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_DWTENA_Msk [3/8]

#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

CoreDebug DEMCR: DWTENA Mask

Definition at line 1045 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_DWTENA_Msk [4/8]

#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

CoreDebug DEMCR: DWTENA Mask

Definition at line 1045 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_DWTENA_Msk [5/8]

#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

CoreDebug DEMCR: DWTENA Mask

Definition at line 1120 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_DWTENA_Msk [6/8]

#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

CoreDebug DEMCR: DWTENA Mask

Definition at line 1120 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_DWTENA_Msk [7/8]

#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

CoreDebug DEMCR: DWTENA Mask

Definition at line 1120 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_DWTENA_Msk [8/8]

#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

CoreDebug DEMCR: DWTENA Mask

Definition at line 1120 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_DWTENA_Pos [1/8]

#define CoreDebug_DEMCR_DWTENA_Pos 24U

CoreDebug DEMCR: DWTENA Position

Definition at line 1044 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_DWTENA_Pos [2/8]

#define CoreDebug_DEMCR_DWTENA_Pos 24U

CoreDebug DEMCR: DWTENA Position

Definition at line 1044 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_DWTENA_Pos [3/8]

#define CoreDebug_DEMCR_DWTENA_Pos 24U

CoreDebug DEMCR: DWTENA Position

Definition at line 1044 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_DWTENA_Pos [4/8]

#define CoreDebug_DEMCR_DWTENA_Pos 24U

CoreDebug DEMCR: DWTENA Position

Definition at line 1044 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_DWTENA_Pos [5/8]

#define CoreDebug_DEMCR_DWTENA_Pos 24U

CoreDebug DEMCR: DWTENA Position

Definition at line 1119 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_DWTENA_Pos [6/8]

#define CoreDebug_DEMCR_DWTENA_Pos 24U

CoreDebug DEMCR: DWTENA Position

Definition at line 1119 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_DWTENA_Pos [7/8]

#define CoreDebug_DEMCR_DWTENA_Pos 24U

CoreDebug DEMCR: DWTENA Position

Definition at line 1119 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_DWTENA_Pos [8/8]

#define CoreDebug_DEMCR_DWTENA_Pos 24U

CoreDebug DEMCR: DWTENA Position

Definition at line 1119 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [1/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1295 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [2/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1300 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [3/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1300 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [4/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1300 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [5/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1312 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [6/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1320 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [7/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1320 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [8/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1320 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [9/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1482 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [10/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1491 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [11/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1491 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [12/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1491 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [13/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1491 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [14/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1491 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [15/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1699 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [16/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1699 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [17/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1699 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [18/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1699 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [19/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1705 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [20/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1705 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [21/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1792 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [22/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1867 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [23/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1867 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [24/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1887 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [25/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1887 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [26/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1887 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [27/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1948 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [28/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1962 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [29/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1962 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [30/30]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1962 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [1/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1294 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [2/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1299 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [3/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1299 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [4/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1299 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [5/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1311 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [6/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1319 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [7/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1319 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [8/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1319 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [9/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1481 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [10/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1490 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [11/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1490 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [12/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1490 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [13/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1490 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [14/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1490 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [15/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1698 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [16/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1698 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [17/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1698 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [18/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1698 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [19/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1704 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [20/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1704 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [21/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1791 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [22/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1866 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [23/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1866 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [24/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1886 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [25/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1886 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [26/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1886 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [27/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1947 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [28/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1961 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [29/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1961 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [30/30]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1961 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [1/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1292 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [2/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1297 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [3/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1297 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [4/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1297 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [5/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1309 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [6/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1317 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [7/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1317 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [8/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1317 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [9/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1479 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [10/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1488 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [11/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1488 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [12/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1488 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [13/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1488 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [14/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1488 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [15/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1696 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [16/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1696 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [17/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1696 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [18/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1696 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [19/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1702 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [20/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1702 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [21/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1789 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [22/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1864 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [23/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1864 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [24/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1884 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [25/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1884 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [26/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1884 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [27/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1945 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [28/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1959 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [29/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1959 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [30/30]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1959 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [1/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1291 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [2/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1296 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [3/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1296 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [4/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1296 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [5/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1308 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [6/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1316 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [7/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1316 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [8/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1316 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [9/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1478 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [10/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1487 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [11/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1487 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [12/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1487 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [13/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1487 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [14/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1487 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [15/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1695 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [16/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1695 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [17/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1695 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [18/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1695 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [19/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1701 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [20/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1701 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [21/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1788 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [22/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1863 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [23/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1863 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [24/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1883 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [25/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1883 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [26/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1883 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [27/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1944 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [28/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1958 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [29/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1958 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [30/30]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1958 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [1/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1286 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [2/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1291 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [3/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1291 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [4/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1291 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [5/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1303 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [6/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1311 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [7/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1311 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [8/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1311 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [9/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1473 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [10/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1482 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [11/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1482 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [12/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1482 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [13/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1482 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [14/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1482 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [15/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1690 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [16/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1690 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [17/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1690 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [18/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1690 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [19/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1696 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [20/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1696 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [21/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1783 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [22/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1858 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [23/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1858 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [24/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1878 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [25/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1878 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [26/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1878 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [27/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1939 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [28/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1953 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [29/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1953 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [30/30]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1953 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [1/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1285 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [2/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1290 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [3/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1290 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [4/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1290 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [5/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1302 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [6/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1310 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [7/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1310 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [8/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1310 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [9/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1472 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [10/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1481 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [11/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1481 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [12/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1481 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [13/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1481 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [14/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1481 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [15/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1689 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [16/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1689 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [17/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1689 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [18/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1689 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [19/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1695 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [20/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1695 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [21/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1782 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [22/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1857 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [23/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1857 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [24/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1877 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [25/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1877 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [26/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1877 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [27/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1938 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [28/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1952 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [29/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1952 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [30/30]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1952 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [1/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1289 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [2/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1294 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [3/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1294 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [4/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1294 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [5/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1306 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [6/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1314 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [7/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1314 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [8/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1314 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [9/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1476 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [10/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1485 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [11/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1485 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [12/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1485 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [13/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1485 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [14/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1485 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [15/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1693 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [16/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1693 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [17/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1693 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [18/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1693 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [19/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1699 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [20/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1699 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [21/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1786 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [22/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1861 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [23/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1861 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [24/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1881 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [25/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1881 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [26/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1881 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [27/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1942 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [28/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1956 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [29/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1956 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [30/30]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1956 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [1/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1288 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [2/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1293 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [3/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1293 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [4/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1293 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [5/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1305 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [6/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1313 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [7/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1313 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [8/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1313 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [9/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1475 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [10/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1484 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [11/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1484 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [12/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1484 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [13/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1484 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [14/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1484 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [15/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1692 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [16/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1692 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [17/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1692 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [18/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1692 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [19/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1698 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [20/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1698 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [21/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1785 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [22/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1860 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [23/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1860 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [24/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1880 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [25/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1880 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [26/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1880 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [27/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1941 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [28/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1955 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [29/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1955 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [30/30]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1955 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [1/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1283 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [2/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1288 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [3/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1288 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [4/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1288 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [5/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1300 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [6/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1308 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [7/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1308 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [8/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1308 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [9/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1470 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [10/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1479 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [11/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1479 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [12/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1479 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [13/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1479 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [14/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1479 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [15/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1687 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [16/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1687 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [17/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1687 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [18/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1687 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [19/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1693 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [20/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1693 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [21/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1780 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [22/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1855 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [23/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1855 of file core_cm35p.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [24/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1875 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [25/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1875 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [26/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1875 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [27/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1936 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [28/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1950 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [29/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1950 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [30/30]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1950 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [1/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1282 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [2/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1287 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [3/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1287 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [4/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1287 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [5/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1299 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [6/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1307 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [7/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1307 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [8/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1307 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [9/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1469 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [10/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1478 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [11/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1478 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [12/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1478 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [13/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1478 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [14/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1478 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [15/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1686 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [16/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1686 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [17/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1686 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [18/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1686 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [19/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1692 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [20/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1692 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [21/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1779 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [22/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1854 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [23/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1854 of file core_cm35p.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [24/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1874 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [25/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1874 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [26/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1874 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [27/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1935 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [28/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1949 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [29/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1949 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [30/30]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1949 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [1/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1304 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [2/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1309 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [3/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1309 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [4/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1309 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [5/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1321 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [6/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1329 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [7/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1329 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [8/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1329 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [9/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1491 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [10/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1500 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [11/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1500 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [12/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1500 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [13/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1500 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [14/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1500 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [15/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1708 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [16/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1708 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [17/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1708 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [18/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1708 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [19/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1714 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [20/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1714 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [21/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1801 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [22/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1876 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [23/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1876 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [24/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1896 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [25/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1896 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [26/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1896 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [27/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1957 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [28/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1971 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [29/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1971 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [30/30]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1971 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [1/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1303 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [2/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1308 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [3/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1308 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [4/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1308 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [5/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1320 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [6/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1328 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [7/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1328 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [8/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1328 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [9/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1490 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [10/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1499 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [11/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1499 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [12/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1499 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [13/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1499 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [14/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1499 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [15/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1707 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [16/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1707 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [17/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1707 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [18/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1707 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [19/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1713 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [20/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1713 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [21/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1800 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [22/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1875 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [23/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1875 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [24/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1895 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [25/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1895 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [26/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1895 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [27/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1956 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [28/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1970 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [29/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1970 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [30/30]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1970 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [1/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1310 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [2/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1315 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [3/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1315 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [4/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1315 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [5/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1327 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [6/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1335 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [7/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1335 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [8/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1335 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [9/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1497 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [10/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1506 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [11/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1506 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [12/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1506 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [13/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1506 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [14/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1506 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [15/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1714 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [16/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1714 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [17/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1714 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [18/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1714 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [19/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1720 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [20/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1720 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [21/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1807 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [22/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1882 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [23/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1882 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [24/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1902 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [25/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1902 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [26/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1902 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [27/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1963 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [28/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1977 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [29/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1977 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [30/30]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1977 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [1/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1309 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [2/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1314 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [3/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1314 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [4/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1314 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [5/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1326 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [6/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1334 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [7/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1334 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [8/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1334 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [9/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1496 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [10/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1505 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [11/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1505 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [12/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1505 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [13/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1505 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [14/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1505 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [15/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1713 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [16/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1713 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [17/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1713 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [18/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1713 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [19/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1719 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [20/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1719 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [21/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1806 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [22/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1881 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [23/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1881 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [24/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1901 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [25/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1901 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [26/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1901 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [27/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1962 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [28/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1976 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [29/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1976 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [30/30]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1976 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [1/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1051 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [2/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1051 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [3/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1051 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [4/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1051 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [5/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1126 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [6/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1126 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [7/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1126 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [8/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1126 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [9/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1319 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [10/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1324 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [11/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1324 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [12/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1324 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [13/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1336 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [14/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1344 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [15/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1344 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [16/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1344 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [17/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1506 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [18/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1515 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [19/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1515 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [20/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1515 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [21/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1515 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [22/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1515 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [23/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1723 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [24/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1723 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [25/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1723 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [26/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1723 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [27/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1729 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [28/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1729 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [29/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1816 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [30/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1891 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [31/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1891 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [32/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1911 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [33/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1911 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [34/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1911 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [35/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1972 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [36/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1986 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [37/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1986 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [38/38]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1986 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [1/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1050 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [2/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1050 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [3/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1050 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [4/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1050 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [5/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1125 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [6/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1125 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [7/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1125 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [8/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1125 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [9/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1318 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [10/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1323 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [11/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1323 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [12/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1323 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [13/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1335 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [14/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1343 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [15/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1343 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [16/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1343 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [17/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1505 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [18/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1514 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [19/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1514 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [20/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1514 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [21/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1514 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [22/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1514 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [23/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1722 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [24/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1722 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [25/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1722 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [26/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1722 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [27/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1728 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [28/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1728 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [29/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1815 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [30/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1890 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [31/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1890 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [32/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1910 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [33/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1910 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [34/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1910 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [35/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1971 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [36/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1985 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [37/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1985 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [38/38]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1985 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [1/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1048 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [2/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1048 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [3/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1048 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [4/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1048 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [5/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1123 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [6/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1123 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [7/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1123 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [8/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1123 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [9/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1298 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [10/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1303 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [11/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1303 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [12/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1303 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [13/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1315 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [14/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1323 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [15/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1323 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [16/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1323 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [17/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1485 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [18/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1494 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [19/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1494 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [20/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1494 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [21/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1494 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [22/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1494 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [23/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1702 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [24/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1702 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [25/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1702 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [26/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1702 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [27/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1708 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [28/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1708 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [29/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1795 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [30/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1870 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [31/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1870 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [32/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1890 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [33/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1890 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [34/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1890 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [35/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1951 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [36/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1965 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [37/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1965 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [38/38]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1965 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [1/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1047 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [2/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1047 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [3/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1047 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [4/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1047 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [5/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1122 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [6/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1122 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [7/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1122 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [8/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1122 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [9/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1297 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [10/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1302 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [11/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1302 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [12/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1302 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [13/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1314 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [14/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1322 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [15/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1322 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [16/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1322 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [17/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1484 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [18/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1493 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [19/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1493 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [20/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1493 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [21/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1493 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [22/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1493 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [23/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1701 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [24/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1701 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [25/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1701 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [26/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1701 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [27/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1707 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [28/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1707 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [29/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1794 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [30/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1869 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [31/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1869 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [32/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1889 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [33/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1889 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [34/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1889 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [35/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1950 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [36/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1964 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [37/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1964 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [38/38]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1964 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [1/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1301 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [2/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1306 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [3/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1306 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [4/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1306 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [5/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1318 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [6/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1326 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [7/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1326 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [8/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1326 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [9/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1488 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [10/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1497 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [11/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1497 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [12/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1497 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [13/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1497 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [14/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1497 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [15/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1705 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [16/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1705 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [17/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1705 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [18/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1705 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [19/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1711 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [20/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1711 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [21/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1798 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [22/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1873 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [23/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1873 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [24/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1893 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [25/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1893 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [26/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1893 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [27/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1954 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [28/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1968 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [29/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1968 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [30/30]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1968 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [1/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1300 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [2/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1305 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [3/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1305 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [4/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1305 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [5/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1317 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [6/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1325 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [7/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1325 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [8/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1325 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [9/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1487 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [10/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1496 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [11/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1496 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [12/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1496 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [13/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1496 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [14/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1496 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [15/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1704 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [16/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1704 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [17/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1704 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [18/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1704 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [19/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1710 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [20/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1710 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [21/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1797 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [22/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1872 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [23/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1872 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [24/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1892 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [25/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1892 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [26/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1892 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [27/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1953 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [28/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1967 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [29/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1967 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [30/30]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1967 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [1/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1316 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [2/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1321 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [3/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1321 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [4/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1321 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [5/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1333 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [6/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1341 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [7/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1341 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [8/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1341 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [9/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1503 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [10/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1512 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [11/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1512 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [12/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1512 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [13/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1512 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [14/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1512 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [15/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1720 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [16/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1720 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [17/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1720 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [18/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1720 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [19/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1726 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [20/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1726 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [21/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1813 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [22/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1888 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [23/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1888 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [24/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1908 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [25/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1908 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [26/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1908 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [27/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1969 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [28/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1983 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [29/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1983 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [30/30]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1983 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [1/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1315 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [2/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1320 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [3/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1320 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [4/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1320 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [5/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1332 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [6/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1340 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [7/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1340 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [8/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1340 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [9/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1502 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [10/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1511 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [11/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1511 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [12/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1511 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [13/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1511 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [14/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1511 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [15/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1719 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [16/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1719 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [17/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1719 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [18/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1719 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [19/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1725 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [20/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1725 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [21/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1812 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [22/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1887 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [23/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1887 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [24/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1907 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [25/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1907 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [26/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1907 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [27/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1968 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [28/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1982 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [29/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1982 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [30/30]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1982 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [1/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1313 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [2/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1318 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [3/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1318 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [4/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1318 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [5/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1330 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [6/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1338 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [7/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1338 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [8/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1338 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [9/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1500 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [10/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1509 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [11/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1509 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [12/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1509 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [13/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1509 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [14/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1509 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [15/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1717 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [16/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1717 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [17/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1717 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [18/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1717 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [19/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1723 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [20/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1723 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [21/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1810 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [22/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1885 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [23/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1885 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [24/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1905 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [25/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1905 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [26/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1905 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [27/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1966 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [28/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1980 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [29/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1980 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [30/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1980 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [1/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1312 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [2/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1317 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [3/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1317 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [4/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1317 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [5/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1329 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [6/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1337 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [7/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1337 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [8/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1337 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [9/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1499 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [10/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1508 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [11/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1508 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [12/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1508 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [13/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1508 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [14/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1508 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [15/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1716 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [16/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1716 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [17/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1716 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [18/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1716 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [19/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1722 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [20/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1722 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [21/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1809 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [22/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1884 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [23/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1884 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [24/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1904 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [25/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1904 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [26/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1904 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [27/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1965 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [28/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1979 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [29/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1979 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [30/30]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1979 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [1/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1307 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [2/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1312 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [3/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1312 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [4/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1312 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [5/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1324 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [6/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1332 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [7/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1332 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [8/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1332 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [9/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1494 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [10/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1503 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [11/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1503 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [12/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1503 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [13/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1503 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [14/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1503 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [15/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1711 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [16/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1711 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [17/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1711 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [18/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1711 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [19/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1717 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [20/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1717 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [21/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1804 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [22/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1879 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [23/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1879 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [24/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1899 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [25/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1899 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [26/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1899 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [27/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1960 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [28/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1974 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [29/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1974 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [30/30]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1974 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [1/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1306 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [2/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1311 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [3/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1311 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [4/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1311 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [5/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1323 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [6/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1331 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [7/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1331 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [8/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1331 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [9/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1493 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [10/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1502 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [11/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1502 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [12/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1502 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [13/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1502 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [14/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1502 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [15/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1710 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [16/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1710 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [17/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1710 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [18/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1710 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [19/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1716 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [20/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1716 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [21/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1803 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [22/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1878 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [23/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1878 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [24/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1898 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [25/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1898 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [26/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1898 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [27/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1959 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [28/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1973 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [29/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1973 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [30/30]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1973 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [1/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1034 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [2/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1034 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [3/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1034 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [4/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1034 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [5/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1109 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [6/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1109 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [7/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1109 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [8/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1109 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [9/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1272 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [10/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1277 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [11/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1277 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [12/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1277 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [13/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1289 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [14/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1297 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [15/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1297 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [16/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1297 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [17/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1459 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [18/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1468 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [19/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1468 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [20/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1468 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [21/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1468 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [22/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1468 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [23/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1676 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [24/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1676 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [25/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1676 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [26/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1676 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [27/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1682 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [28/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1682 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [29/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1769 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [30/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1844 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [31/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1844 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [32/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1864 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [33/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1864 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [34/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1864 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [35/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1925 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [36/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1939 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [37/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1939 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [38/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1939 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [1/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1033 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [2/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1033 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [3/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1033 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [4/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1033 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [5/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1108 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [6/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1108 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [7/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1108 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [8/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1108 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [9/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1271 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [10/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1276 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [11/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1276 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [12/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1276 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [13/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1288 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [14/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1296 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [15/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1296 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [16/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1296 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [17/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1458 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [18/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1467 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [19/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1467 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [20/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1467 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [21/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1467 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [22/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1467 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [23/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1675 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [24/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1675 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [25/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1675 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [26/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1675 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [27/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1681 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [28/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1681 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [29/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1768 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [30/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1843 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [31/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1843 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [32/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1863 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [33/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1863 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [34/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1863 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [35/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1924 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [36/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1938 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [37/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1938 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [38/38]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1938 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [1/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1031 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [2/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1031 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [3/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1031 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [4/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1031 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [5/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1106 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [6/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1106 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [7/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1106 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [8/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1106 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [9/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1269 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [10/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1274 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [11/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1274 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [12/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1274 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [13/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1286 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [14/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1294 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [15/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1294 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [16/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1294 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [17/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1456 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [18/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1465 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [19/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1465 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [20/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1465 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [21/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1465 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [22/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1465 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [23/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1673 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [24/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1673 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [25/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1673 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [26/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1673 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [27/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1679 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [28/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1679 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [29/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1766 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [30/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1841 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [31/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1841 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [32/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1861 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [33/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1861 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [34/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1861 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [35/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1922 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [36/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1936 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [37/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1936 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [38/38]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1936 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [1/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1030 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [2/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1030 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [3/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1030 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [4/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1030 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [5/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1105 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [6/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1105 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [7/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1105 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [8/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1105 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [9/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1268 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [10/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1273 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [11/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1273 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [12/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1273 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [13/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1285 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [14/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1293 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [15/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1293 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [16/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1293 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [17/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1455 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [18/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1464 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [19/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1464 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [20/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1464 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [21/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1464 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [22/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1464 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [23/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1672 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [24/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1672 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [25/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1672 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [26/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1672 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [27/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1678 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [28/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1678 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [29/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1765 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [30/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1840 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [31/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1840 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [32/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1860 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [33/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1860 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [34/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1860 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [35/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1921 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [36/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1935 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [37/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1935 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [38/38]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1935 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [1/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1025 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [2/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1025 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [3/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1025 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [4/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1025 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [5/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1100 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [6/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1100 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [7/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1100 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [8/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1100 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [9/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1263 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [10/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1268 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [11/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1268 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [12/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1268 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [13/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1280 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [14/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1288 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [15/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1288 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [16/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1288 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [17/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1450 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [18/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1459 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [19/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1459 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [20/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1459 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [21/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1459 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [22/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1459 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [23/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1667 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [24/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1667 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [25/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1667 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [26/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1667 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [27/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1673 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [28/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1673 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [29/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1760 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [30/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1835 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [31/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1835 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [32/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1855 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [33/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1855 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [34/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1855 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [35/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1916 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [36/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1930 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [37/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1930 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [38/38]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1930 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [1/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1024 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [2/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1024 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [3/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1024 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [4/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1024 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [5/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1099 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [6/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1099 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [7/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1099 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [8/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1099 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [9/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1262 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [10/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1267 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [11/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1267 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [12/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1267 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [13/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1279 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [14/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1287 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [15/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1287 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [16/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1287 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [17/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1449 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [18/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1458 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [19/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1458 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [20/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1458 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [21/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1458 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [22/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1458 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [23/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1666 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [24/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1666 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [25/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1666 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [26/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1666 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [27/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1672 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [28/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1672 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [29/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1759 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [30/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1834 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [31/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1834 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [32/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1854 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [33/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1854 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [34/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1854 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [35/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1915 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [36/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1929 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [37/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1929 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [38/38]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1929 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [1/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1260 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [2/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1265 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [3/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1265 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [4/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1265 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [5/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1277 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [6/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1285 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [7/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1285 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [8/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1285 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [9/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1447 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [10/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1456 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [11/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1456 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [12/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1456 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [13/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1456 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [14/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1456 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [15/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1664 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [16/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1664 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [17/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1664 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [18/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1664 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [19/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1670 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [20/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1670 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [21/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1757 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [22/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1832 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [23/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1832 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [24/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1852 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [25/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1852 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [26/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1852 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [27/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1913 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [28/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1927 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [29/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1927 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [30/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1927 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [1/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1259 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [2/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1264 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [3/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1264 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [4/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1264 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [5/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1276 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [6/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1284 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [7/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1284 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [8/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1284 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [9/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1446 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [10/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1455 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [11/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1455 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [12/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1455 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [13/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1455 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [14/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1455 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [15/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1663 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [16/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1663 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [17/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1663 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [18/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1663 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [19/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1669 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [20/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1669 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [21/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1756 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [22/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1831 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [23/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1831 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [24/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1851 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [25/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1851 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [26/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1851 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [27/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1912 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [28/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1926 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [29/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1926 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [30/30]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1926 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [1/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1028 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [2/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1028 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [3/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1028 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [4/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1028 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [5/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1103 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [6/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1103 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [7/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1103 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [8/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1103 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [9/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1266 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [10/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1271 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [11/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1271 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [12/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1271 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [13/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1283 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [14/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1291 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [15/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1291 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [16/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1291 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [17/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1453 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [18/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1462 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [19/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1462 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [20/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1462 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [21/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1462 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [22/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1462 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [23/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1670 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [24/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1670 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [25/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1670 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [26/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1670 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [27/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1676 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [28/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1676 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [29/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1763 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [30/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1838 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [31/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1838 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [32/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1858 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [33/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1858 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [34/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1858 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [35/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1919 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [36/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1933 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [37/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1933 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [38/38]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1933 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [1/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1027 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [2/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1027 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [3/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1027 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [4/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1027 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [5/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1102 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [6/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1102 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [7/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1102 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [8/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1102 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [9/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1265 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [10/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1270 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [11/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1270 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [12/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1270 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [13/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1282 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [14/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1290 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [15/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1290 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [16/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1290 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [17/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1452 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [18/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1461 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [19/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1461 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [20/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1461 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [21/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1461 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [22/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1461 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [23/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1669 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [24/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1669 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [25/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1669 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [26/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1669 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [27/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1675 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [28/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1675 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [29/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1762 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [30/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1837 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [31/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1837 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [32/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1857 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [33/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1857 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [34/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1857 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [35/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1918 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [36/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1932 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [37/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1932 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [38/38]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1932 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [1/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1001 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [2/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1001 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [3/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1001 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [4/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1001 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [5/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1076 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [6/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1076 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [7/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1076 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [8/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1076 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [9/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1239 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [10/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1244 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [11/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1244 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [12/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1244 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [13/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1256 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [14/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1264 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [15/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1264 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [16/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1264 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [17/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1426 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [18/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1435 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [19/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1435 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [20/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1435 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [21/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1435 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [22/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1435 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [23/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1643 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [24/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1643 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [25/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1643 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [26/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1643 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [27/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1649 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [28/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1649 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [29/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1733 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [30/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1808 of file core_cm35p.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [31/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1808 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [32/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1828 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [33/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1828 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [34/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1828 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [35/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1889 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [36/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1903 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [37/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1903 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [38/38]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1903 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [1/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1000 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [2/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1000 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [3/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1000 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [4/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1000 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [5/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1075 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [6/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1075 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [7/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1075 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [8/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1075 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [9/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1238 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [10/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1243 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [11/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1243 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [12/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1243 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [13/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1255 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [14/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1263 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [15/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1263 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [16/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1263 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [17/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1425 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [18/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1434 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [19/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1434 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [20/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1434 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [21/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1434 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [22/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1434 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [23/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1642 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [24/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1642 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [25/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1642 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [26/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1642 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [27/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1648 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [28/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1648 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [29/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1732 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [30/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1807 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [31/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1807 of file core_cm35p.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [32/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1827 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [33/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1827 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [34/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1827 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [35/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1888 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [36/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1902 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [37/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1902 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [38/38]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1902 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [1/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1019 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [2/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1019 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [3/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1019 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [4/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1019 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [5/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1094 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [6/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1094 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [7/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1094 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [8/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1094 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [9/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1254 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [10/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1259 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [11/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1259 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [12/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1259 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [13/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1271 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [14/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1279 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [15/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1279 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [16/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1279 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [17/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1441 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [18/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1450 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [19/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1450 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [20/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1450 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [21/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1450 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [22/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1450 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [23/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1658 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [24/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1658 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [25/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1658 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [26/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1658 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [27/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1664 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [28/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1664 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [29/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1751 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [30/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1826 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [31/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1826 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [32/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1846 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [33/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1846 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [34/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1846 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [35/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1907 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [36/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1921 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [37/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1921 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [38/38]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1921 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [1/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1018 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [2/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1018 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [3/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1018 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [4/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1018 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [5/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1093 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [6/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1093 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [7/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1093 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [8/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1093 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [9/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1253 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [10/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1258 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [11/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1258 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [12/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1258 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [13/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1270 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [14/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1278 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [15/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1278 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [16/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1278 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [17/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1440 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [18/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1449 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [19/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1449 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [20/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1449 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [21/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1449 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [22/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1449 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [23/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1657 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [24/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1657 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [25/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1657 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [26/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1657 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [27/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1663 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [28/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1663 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [29/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1750 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [30/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1825 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [31/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1825 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [32/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1845 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [33/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1845 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [34/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1845 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [35/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1906 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [36/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1920 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [37/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1920 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [38/38]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1920 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [1/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1013 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [2/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1013 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [3/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1013 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [4/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1013 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [5/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1088 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [6/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1088 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [7/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1088 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [8/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1088 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [9/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1248 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [10/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1253 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [11/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1253 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [12/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1253 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [13/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1265 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [14/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1273 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [15/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1273 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [16/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1273 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [17/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1435 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [18/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1444 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [19/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1444 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [20/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1444 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [21/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1444 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [22/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1444 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [23/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1652 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [24/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1652 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [25/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1652 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [26/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1652 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [27/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1658 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [28/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1658 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [29/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1745 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [30/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1820 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [31/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1820 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [32/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1840 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [33/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1840 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [34/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1840 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [35/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1901 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [36/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1915 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [37/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1915 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [38/38]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1915 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [1/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1012 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [2/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1012 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [3/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1012 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [4/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1012 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [5/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1087 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [6/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1087 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [7/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1087 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [8/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1087 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [9/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1247 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [10/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1252 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [11/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1252 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [12/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1252 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [13/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1264 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [14/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1272 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [15/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1272 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [16/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1272 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [17/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1434 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [18/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1443 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [19/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1443 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [20/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1443 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [21/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1443 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [22/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1443 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [23/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1651 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [24/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1651 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [25/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1651 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [26/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1651 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [27/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1657 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [28/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1657 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [29/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1744 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [30/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1819 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [31/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1819 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [32/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1839 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [33/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1839 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [34/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1839 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [35/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1900 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [36/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1914 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [37/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1914 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [38/38]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1914 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [1/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1022 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [2/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1022 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [3/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1022 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [4/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1022 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [5/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1097 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [6/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1097 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [7/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1097 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [8/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1097 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [9/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1257 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [10/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1262 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [11/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1262 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [12/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1262 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [13/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1274 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [14/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1282 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [15/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1282 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [16/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1282 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [17/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1444 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [18/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1453 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [19/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1453 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [20/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1453 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [21/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1453 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [22/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1453 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [23/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1661 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [24/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1661 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [25/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1661 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [26/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1661 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [27/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1667 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [28/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1667 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [29/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1754 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [30/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1829 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [31/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1829 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [32/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1849 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [33/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1849 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [34/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1849 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [35/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1910 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [36/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1924 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [37/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1924 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [38/38]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1924 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [1/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1021 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [2/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1021 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [3/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1021 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [4/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1021 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [5/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1096 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [6/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1096 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [7/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1096 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [8/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1096 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [9/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1256 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [10/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1261 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [11/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1261 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [12/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1261 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [13/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1273 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [14/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1281 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [15/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1281 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [16/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1281 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [17/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1443 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [18/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1452 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [19/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1452 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [20/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1452 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [21/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1452 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [22/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1452 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [23/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1660 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [24/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1660 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [25/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1660 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [26/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1660 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [27/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1666 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [28/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1666 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [29/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1753 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [30/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1828 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [31/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1828 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [32/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1848 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [33/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1848 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [34/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1848 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [35/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1909 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [36/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1923 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [37/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1923 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [38/38]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1923 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [1/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1007 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [2/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1007 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [3/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1007 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [4/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1007 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [5/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1082 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [6/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1082 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [7/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1082 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [8/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1082 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [9/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1242 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [10/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1247 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [11/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1247 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [12/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1247 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [13/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1259 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [14/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1267 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [15/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1267 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [16/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1267 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [17/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1429 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [18/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1438 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [19/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1438 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [20/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1438 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [21/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1438 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [22/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1438 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [23/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1646 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [24/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1646 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [25/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1646 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [26/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1646 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [27/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1652 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [28/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1652 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [29/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1739 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [30/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1814 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [31/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1814 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [32/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1834 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [33/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1834 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [34/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1834 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [35/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1895 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [36/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1909 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [37/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1909 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [38/38]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1909 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [1/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1006 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [2/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1006 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [3/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1006 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [4/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1006 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [5/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1081 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [6/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1081 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [7/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1081 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [8/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1081 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [9/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1241 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [10/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1246 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [11/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1246 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [12/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1246 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [13/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1258 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [14/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1266 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [15/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1266 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [16/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1266 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [17/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1428 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [18/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1437 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [19/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1437 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [20/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1437 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [21/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1437 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [22/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1437 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [23/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1645 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [24/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1645 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [25/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1645 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [26/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1645 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [27/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1651 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [28/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1651 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [29/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1738 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [30/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1813 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [31/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1813 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [32/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1833 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [33/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1833 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [34/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1833 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [35/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1894 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [36/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1908 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [37/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1908 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [38/38]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1908 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [1/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1004 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [2/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1004 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [3/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1004 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [4/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1004 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [5/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1079 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [6/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1079 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [7/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1079 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [8/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1079 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [9/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1736 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [10/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1811 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [11/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1811 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [12/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1831 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [13/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1831 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [14/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1831 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [15/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1892 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [16/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1906 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [17/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1906 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [18/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1906 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [1/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1003 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [2/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1003 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [3/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1003 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [4/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1003 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [5/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1078 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [6/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1078 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [7/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1078 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [8/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1078 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [9/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1735 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [10/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1810 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [11/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1810 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [12/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1830 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [13/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1830 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [14/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1830 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [15/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1891 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [16/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1905 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [17/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1905 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [18/18]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1905 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [1/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1010 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [2/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1010 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [3/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1010 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [4/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1010 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [5/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1085 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [6/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1085 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [7/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1085 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [8/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1085 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [9/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1245 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [10/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1250 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [11/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1250 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [12/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1250 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [13/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1262 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [14/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1270 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [15/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1270 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [16/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1270 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [17/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1432 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [18/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1441 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [19/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1441 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [20/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1441 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [21/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1441 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [22/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1441 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [23/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1649 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [24/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1649 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [25/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1649 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [26/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1649 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [27/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1655 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [28/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1655 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [29/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1742 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [30/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1817 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [31/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1817 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [32/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1837 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [33/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1837 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [34/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1837 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [35/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1898 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [36/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1912 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [37/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1912 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [38/38]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1912 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.