Type definitions for the Instrumentation Trace Macrocell (ITM) More...

Collaboration diagram for Instrumentation Trace Macrocell (ITM):

Modules
	Data Watchpoint and Trace (DWT)
	Type definitions for the Data Watchpoint and Trace (DWT)

Classes
struct	ITM_Type
	Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

Detailed Description

Type definitions for the Instrumentation Trace Macrocell (ITM)

Macro Definition Documentation

◆ ITM_IMCR_INTEGRATION_Msk [1/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 806 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IMCR_INTEGRATION_Msk [2/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 806 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IMCR_INTEGRATION_Msk [3/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 806 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IMCR_INTEGRATION_Msk [4/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 824 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IMCR_INTEGRATION_Msk [5/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 824 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IMCR_INTEGRATION_Msk [6/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 824 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IMCR_INTEGRATION_Msk [7/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 889 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Msk [8/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 889 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Msk [9/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 889 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Msk [10/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 889 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Msk [11/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 889 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Msk [12/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1091 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IMCR_INTEGRATION_Msk [13/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1091 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IMCR_INTEGRATION_Msk [14/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1091 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IMCR_INTEGRATION_Msk [15/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1091 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IMCR_INTEGRATION_Msk [16/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1176 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IMCR_INTEGRATION_Msk [17/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1176 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IMCR_INTEGRATION_Msk [18/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1176 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IMCR_INTEGRATION_Msk [19/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1176 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IMCR_INTEGRATION_Msk [20/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1176 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IMCR_INTEGRATION_Msk [21/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1176 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IMCR_INTEGRATION_Msk [22/22]

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1177 of file core_armv81mml.h.

◆ ITM_IMCR_INTEGRATION_Pos [1/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 805 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IMCR_INTEGRATION_Pos [2/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 805 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IMCR_INTEGRATION_Pos [3/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 805 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IMCR_INTEGRATION_Pos [4/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 823 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IMCR_INTEGRATION_Pos [5/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 823 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IMCR_INTEGRATION_Pos [6/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 823 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IMCR_INTEGRATION_Pos [7/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 888 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Pos [8/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 888 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Pos [9/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 888 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Pos [10/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 888 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Pos [11/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 888 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IMCR_INTEGRATION_Pos [12/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1090 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IMCR_INTEGRATION_Pos [13/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1090 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IMCR_INTEGRATION_Pos [14/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1090 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IMCR_INTEGRATION_Pos [15/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1090 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IMCR_INTEGRATION_Pos [16/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1175 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IMCR_INTEGRATION_Pos [17/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1175 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IMCR_INTEGRATION_Pos [18/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1175 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IMCR_INTEGRATION_Pos [19/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1175 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IMCR_INTEGRATION_Pos [20/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1175 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IMCR_INTEGRATION_Pos [21/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1175 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IMCR_INTEGRATION_Pos [22/22]

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1176 of file core_armv81mml.h.

◆ ITM_IRR_ATREADYM_Msk [1/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 802 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IRR_ATREADYM_Msk [2/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 802 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IRR_ATREADYM_Msk [3/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 802 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IRR_ATREADYM_Msk [4/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 820 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IRR_ATREADYM_Msk [5/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 820 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IRR_ATREADYM_Msk [6/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 820 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IRR_ATREADYM_Msk [7/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 885 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Msk [8/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 885 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Msk [9/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 885 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Msk [10/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 885 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Msk [11/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 885 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Msk [12/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1087 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IRR_ATREADYM_Msk [13/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1087 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IRR_ATREADYM_Msk [14/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1087 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IRR_ATREADYM_Msk [15/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1087 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IRR_ATREADYM_Msk [16/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1172 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IRR_ATREADYM_Msk [17/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1172 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IRR_ATREADYM_Msk [18/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1172 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IRR_ATREADYM_Msk [19/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1172 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IRR_ATREADYM_Msk [20/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1172 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IRR_ATREADYM_Msk [21/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1172 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IRR_ATREADYM_Msk [22/22]

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1173 of file core_armv81mml.h.

◆ ITM_IRR_ATREADYM_Pos [1/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 801 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IRR_ATREADYM_Pos [2/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 801 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IRR_ATREADYM_Pos [3/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 801 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IRR_ATREADYM_Pos [4/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 819 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IRR_ATREADYM_Pos [5/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 819 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IRR_ATREADYM_Pos [6/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 819 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IRR_ATREADYM_Pos [7/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 884 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Pos [8/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 884 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Pos [9/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 884 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Pos [10/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 884 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Pos [11/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 884 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IRR_ATREADYM_Pos [12/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1086 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IRR_ATREADYM_Pos [13/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1086 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IRR_ATREADYM_Pos [14/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1086 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IRR_ATREADYM_Pos [15/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1086 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IRR_ATREADYM_Pos [16/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1171 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IRR_ATREADYM_Pos [17/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1171 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IRR_ATREADYM_Pos [18/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1171 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IRR_ATREADYM_Pos [19/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1171 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IRR_ATREADYM_Pos [20/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1171 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IRR_ATREADYM_Pos [21/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1171 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IRR_ATREADYM_Pos [22/22]

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1172 of file core_armv81mml.h.

◆ ITM_IWR_ATVALIDM_Msk [1/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 798 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IWR_ATVALIDM_Msk [2/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 798 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IWR_ATVALIDM_Msk [3/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 798 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IWR_ATVALIDM_Msk [4/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 816 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IWR_ATVALIDM_Msk [5/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 816 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IWR_ATVALIDM_Msk [6/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 816 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IWR_ATVALIDM_Msk [7/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 881 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Msk [8/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 881 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Msk [9/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 881 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Msk [10/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 881 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Msk [11/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 881 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Msk [12/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1083 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IWR_ATVALIDM_Msk [13/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1083 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IWR_ATVALIDM_Msk [14/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1083 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IWR_ATVALIDM_Msk [15/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1083 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IWR_ATVALIDM_Msk [16/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1168 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IWR_ATVALIDM_Msk [17/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1168 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IWR_ATVALIDM_Msk [18/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1168 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IWR_ATVALIDM_Msk [19/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1168 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IWR_ATVALIDM_Msk [20/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1168 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IWR_ATVALIDM_Msk [21/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1168 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IWR_ATVALIDM_Msk [22/22]

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1169 of file core_armv81mml.h.

◆ ITM_IWR_ATVALIDM_Pos [1/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 797 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IWR_ATVALIDM_Pos [2/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 797 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IWR_ATVALIDM_Pos [3/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 797 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_IWR_ATVALIDM_Pos [4/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 815 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IWR_ATVALIDM_Pos [5/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 815 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IWR_ATVALIDM_Pos [6/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 815 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_IWR_ATVALIDM_Pos [7/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 880 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Pos [8/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 880 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Pos [9/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 880 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Pos [10/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 880 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Pos [11/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 880 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_IWR_ATVALIDM_Pos [12/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1082 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IWR_ATVALIDM_Pos [13/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1082 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IWR_ATVALIDM_Pos [14/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1082 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IWR_ATVALIDM_Pos [15/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1082 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_IWR_ATVALIDM_Pos [16/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1167 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IWR_ATVALIDM_Pos [17/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1167 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IWR_ATVALIDM_Pos [18/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1167 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IWR_ATVALIDM_Pos [19/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1167 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IWR_ATVALIDM_Pos [20/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1167 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_IWR_ATVALIDM_Pos [21/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1167 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_IWR_ATVALIDM_Pos [22/22]

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1168 of file core_armv81mml.h.

◆ ITM_LSR_Access_Msk [1/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 808 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Access_Msk [2/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 813 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Access_Msk [3/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 813 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Access_Msk [4/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 813 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Access_Msk [5/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 823 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Access_Msk [6/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 831 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Access_Msk [7/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 831 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Access_Msk [8/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 831 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Access_Msk [9/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 881 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Msk [10/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 896 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Msk [11/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 896 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Msk [12/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 896 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Msk [13/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 896 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Msk [14/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 896 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Msk [15/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1088 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Access_Msk [16/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1088 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Access_Msk [17/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1088 of file core_cm35p.h.

◆ ITM_LSR_Access_Msk [18/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1098 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Msk [19/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1098 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Msk [20/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1098 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Msk [21/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1098 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Msk [22/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1101 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_LSR_Access_Msk [23/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1101 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Msk [24/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1183 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Access_Msk [25/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1183 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Access_Msk [26/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1183 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Access_Msk [27/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1183 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Access_Msk [28/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1183 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Access_Msk [29/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1183 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Access_Msk [30/30]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1184 of file core_armv81mml.h.

◆ ITM_LSR_Access_Pos [1/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 807 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Access_Pos [2/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 812 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Access_Pos [3/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 812 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Access_Pos [4/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 812 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Access_Pos [5/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 822 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Access_Pos [6/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 830 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Access_Pos [7/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 830 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Access_Pos [8/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 830 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Access_Pos [9/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 880 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Pos [10/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 895 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Pos [11/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 895 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Pos [12/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 895 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Pos [13/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 895 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Pos [14/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 895 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Access_Pos [15/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1087 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Access_Pos [16/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1087 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Access_Pos [17/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1087 of file core_cm35p.h.

◆ ITM_LSR_Access_Pos [18/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1097 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Pos [19/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1097 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Pos [20/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1097 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Pos [21/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1097 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Pos [22/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1100 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_LSR_Access_Pos [23/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1100 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Access_Pos [24/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1182 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Access_Pos [25/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1182 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Access_Pos [26/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1182 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Access_Pos [27/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1182 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Access_Pos [28/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1182 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Access_Pos [29/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1182 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Access_Pos [30/30]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1183 of file core_armv81mml.h.

◆ ITM_LSR_ByteAcc_Msk [1/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 805 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_ByteAcc_Msk [2/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 810 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_ByteAcc_Msk [3/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 810 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_ByteAcc_Msk [4/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 810 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_ByteAcc_Msk [5/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 820 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_ByteAcc_Msk [6/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 828 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_ByteAcc_Msk [7/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 828 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_ByteAcc_Msk [8/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 828 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_ByteAcc_Msk [9/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 878 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Msk [10/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 893 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Msk [11/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 893 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Msk [12/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 893 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Msk [13/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 893 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Msk [14/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 893 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Msk [15/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1085 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Msk [16/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1085 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_ByteAcc_Msk [17/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1085 of file core_cm35p.h.

◆ ITM_LSR_ByteAcc_Msk [18/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1095 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Msk [19/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1095 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Msk [20/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1095 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Msk [21/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1095 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Msk [22/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1098 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_LSR_ByteAcc_Msk [23/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1098 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Msk [24/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1180 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Msk [25/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1180 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_ByteAcc_Msk [26/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1180 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_ByteAcc_Msk [27/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1180 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_ByteAcc_Msk [28/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1180 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Msk [29/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1180 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Msk [30/30]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1181 of file core_armv81mml.h.

◆ ITM_LSR_ByteAcc_Pos [1/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 804 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_ByteAcc_Pos [2/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 809 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_ByteAcc_Pos [3/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 809 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_ByteAcc_Pos [4/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 809 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_ByteAcc_Pos [5/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 819 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_ByteAcc_Pos [6/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 827 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_ByteAcc_Pos [7/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 827 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_ByteAcc_Pos [8/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 827 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_ByteAcc_Pos [9/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 877 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Pos [10/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 892 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Pos [11/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 892 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Pos [12/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 892 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Pos [13/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 892 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Pos [14/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 892 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_ByteAcc_Pos [15/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1084 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Pos [16/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1084 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_ByteAcc_Pos [17/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1084 of file core_cm35p.h.

◆ ITM_LSR_ByteAcc_Pos [18/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1094 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Pos [19/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1094 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Pos [20/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1094 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Pos [21/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1094 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Pos [22/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1097 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_LSR_ByteAcc_Pos [23/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1097 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_ByteAcc_Pos [24/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1179 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_ByteAcc_Pos [25/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1179 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Pos [26/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1179 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_ByteAcc_Pos [27/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1179 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_ByteAcc_Pos [28/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1179 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Pos [29/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1179 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Pos [30/30]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1180 of file core_armv81mml.h.

◆ ITM_LSR_Present_Msk [1/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 811 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Present_Msk [2/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 816 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Present_Msk [3/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 816 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Present_Msk [4/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 816 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Present_Msk [5/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 826 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Present_Msk [6/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 834 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Present_Msk [7/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 834 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Present_Msk [8/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 834 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Present_Msk [9/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 884 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Msk [10/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 899 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Msk [11/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 899 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Msk [12/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 899 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Msk [13/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 899 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Msk [14/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 899 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Msk [15/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1091 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Present_Msk [16/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1091 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Present_Msk [17/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1091 of file core_cm35p.h.

◆ ITM_LSR_Present_Msk [18/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1101 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Msk [19/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1101 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Msk [20/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1101 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Msk [21/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1101 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Msk [22/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1104 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Msk [23/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1104 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_LSR_Present_Msk [24/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1186 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Present_Msk [25/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1186 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Present_Msk [26/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1186 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Present_Msk [27/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1186 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Present_Msk [28/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1186 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Present_Msk [29/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1186 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Present_Msk [30/30]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1187 of file core_armv81mml.h.

◆ ITM_LSR_Present_Pos [1/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 810 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Present_Pos [2/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 815 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Present_Pos [3/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 815 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Present_Pos [4/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 815 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_LSR_Present_Pos [5/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 825 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Present_Pos [6/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 833 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Present_Pos [7/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 833 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Present_Pos [8/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 833 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_LSR_Present_Pos [9/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 883 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Pos [10/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 898 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Pos [11/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 898 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Pos [12/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 898 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Pos [13/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 898 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Pos [14/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 898 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_LSR_Present_Pos [15/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1090 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Present_Pos [16/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1090 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Present_Pos [17/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1090 of file core_cm35p.h.

◆ ITM_LSR_Present_Pos [18/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1100 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Pos [19/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1100 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Pos [20/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1100 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Pos [21/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1100 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Pos [22/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1103 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_LSR_Present_Pos [23/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1103 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_LSR_Present_Pos [24/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1185 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Present_Pos [25/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1185 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Present_Pos [26/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1185 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Present_Pos [27/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1185 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_LSR_Present_Pos [28/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1185 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Present_Pos [29/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1185 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_LSR_Present_Pos [30/30]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1186 of file core_armv81mml.h.

◆ ITM_STIM_DISABLED_Msk [1/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1043 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_DISABLED_Msk [2/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1043 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_DISABLED_Msk [3/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1043 of file core_cm35p.h.

◆ ITM_STIM_DISABLED_Msk [4/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1126 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_DISABLED_Msk [5/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1126 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_DISABLED_Msk [6/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1126 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_DISABLED_Msk [7/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1126 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_DISABLED_Msk [8/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1126 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_DISABLED_Msk [9/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1126 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_DISABLED_Msk [10/10]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1127 of file core_armv81mml.h.

◆ ITM_STIM_DISABLED_Pos [1/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1042 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_DISABLED_Pos [2/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1042 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_DISABLED_Pos [3/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1042 of file core_cm35p.h.

◆ ITM_STIM_DISABLED_Pos [4/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1125 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_DISABLED_Pos [5/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1125 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_DISABLED_Pos [6/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1125 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_DISABLED_Pos [7/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1125 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_DISABLED_Pos [8/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1125 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_DISABLED_Pos [9/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1125 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_DISABLED_Pos [10/10]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1126 of file core_armv81mml.h.

◆ ITM_STIM_FIFOREADY_Msk [1/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1046 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Msk [2/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1046 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_FIFOREADY_Msk [3/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1046 of file core_cm35p.h.

◆ ITM_STIM_FIFOREADY_Msk [4/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1129 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_FIFOREADY_Msk [5/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1129 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_FIFOREADY_Msk [6/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1129 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_FIFOREADY_Msk [7/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1129 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Msk [8/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1129 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Msk [9/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1129 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Msk [10/10]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1130 of file core_armv81mml.h.

◆ ITM_STIM_FIFOREADY_Pos [1/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1045 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Pos [2/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1045 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_FIFOREADY_Pos [3/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1045 of file core_cm35p.h.

◆ ITM_STIM_FIFOREADY_Pos [4/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1128 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_FIFOREADY_Pos [5/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1128 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_FIFOREADY_Pos [6/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1128 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Pos [7/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1128 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_STIM_FIFOREADY_Pos [8/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1128 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Pos [9/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1128 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Pos [10/10]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1129 of file core_armv81mml.h.

◆ ITM_TCR_BUSY_Msk [1/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 770 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_BUSY_Msk [2/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 770 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_BUSY_Msk [3/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 770 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_BUSY_Msk [4/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 777 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_BUSY_Msk [5/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 788 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_BUSY_Msk [6/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 788 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_BUSY_Msk [7/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 788 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_BUSY_Msk [8/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 792 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_BUSY_Msk [9/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 850 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Msk [10/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 853 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Msk [11/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 853 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Msk [12/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 853 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Msk [13/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 853 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Msk [14/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 853 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Msk [15/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1054 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_BUSY_Msk [16/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1054 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_BUSY_Msk [17/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1054 of file core_cm35p.h.

◆ ITM_TCR_BUSY_Msk [18/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1055 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Msk [19/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1055 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Msk [20/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1055 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Msk [21/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1055 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Msk [22/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1070 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_BUSY_Msk [23/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1070 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Msk [24/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1137 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_BUSY_Msk [25/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1137 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_BUSY_Msk [26/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1137 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_BUSY_Msk [27/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1137 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_BUSY_Msk [28/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1137 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_BUSY_Msk [29/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1137 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_BUSY_Msk [30/30]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1138 of file core_armv81mml.h.

◆ ITM_TCR_BUSY_Pos [1/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 769 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_BUSY_Pos [2/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 769 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_BUSY_Pos [3/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 769 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_BUSY_Pos [4/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 776 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_BUSY_Pos [5/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 787 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_BUSY_Pos [6/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 787 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_BUSY_Pos [7/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 787 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_BUSY_Pos [8/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 791 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_BUSY_Pos [9/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 849 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Pos [10/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 852 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Pos [11/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 852 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Pos [12/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 852 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Pos [13/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 852 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Pos [14/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 852 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_BUSY_Pos [15/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1053 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_BUSY_Pos [16/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1053 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_BUSY_Pos [17/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1053 of file core_cm35p.h.

◆ ITM_TCR_BUSY_Pos [18/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1054 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Pos [19/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1054 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Pos [20/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1054 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Pos [21/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1054 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Pos [22/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1069 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_BUSY_Pos [23/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1069 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_BUSY_Pos [24/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1136 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_BUSY_Pos [25/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1136 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_BUSY_Pos [26/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1136 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_BUSY_Pos [27/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1136 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_BUSY_Pos [28/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1136 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_BUSY_Pos [29/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1136 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_BUSY_Pos [30/30]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1137 of file core_armv81mml.h.

◆ ITM_TCR_DWTENA_Msk [1/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 785 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_DWTENA_Msk [2/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 785 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_DWTENA_Msk [3/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 785 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_DWTENA_Msk [4/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 792 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_DWTENA_Msk [5/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 803 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_DWTENA_Msk [6/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 803 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_DWTENA_Msk [7/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 803 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_DWTENA_Msk [8/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 807 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_DWTENA_Msk [9/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 865 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [10/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 868 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [11/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 868 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [12/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 868 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [13/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 868 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [14/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 868 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [15/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1070 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Msk [16/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1070 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Msk [17/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1070 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Msk [18/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1070 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Msk [19/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1072 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_DWTENA_Msk [20/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1072 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_DWTENA_Msk [21/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1072 of file core_cm35p.h.

◆ ITM_TCR_DWTENA_Msk [22/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1085 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_DWTENA_Msk [23/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1085 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Msk [24/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1155 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_DWTENA_Msk [25/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1155 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_DWTENA_Msk [26/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1155 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_DWTENA_Msk [27/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1155 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_DWTENA_Msk [28/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1155 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_DWTENA_Msk [29/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1155 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_DWTENA_Msk [30/30]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1156 of file core_armv81mml.h.

◆ ITM_TCR_DWTENA_Pos [1/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 784 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_DWTENA_Pos [2/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 784 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_DWTENA_Pos [3/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 784 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_DWTENA_Pos [4/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 791 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_DWTENA_Pos [5/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 802 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_DWTENA_Pos [6/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 802 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_DWTENA_Pos [7/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 802 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_DWTENA_Pos [8/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 806 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_DWTENA_Pos [9/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 864 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [10/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 867 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [11/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 867 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [12/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 867 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [13/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 867 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [14/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 867 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [15/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1069 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Pos [16/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1069 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Pos [17/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1069 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Pos [18/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1069 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Pos [19/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1071 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_DWTENA_Pos [20/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1071 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_DWTENA_Pos [21/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1071 of file core_cm35p.h.

◆ ITM_TCR_DWTENA_Pos [22/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1084 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_DWTENA_Pos [23/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1084 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_DWTENA_Pos [24/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1154 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_DWTENA_Pos [25/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1154 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_DWTENA_Pos [26/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1154 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_DWTENA_Pos [27/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1154 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_DWTENA_Pos [28/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1154 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_DWTENA_Pos [29/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1154 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_DWTENA_Pos [30/30]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1155 of file core_armv81mml.h.

◆ ITM_TCR_GTSFREQ_Msk [1/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 776 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_GTSFREQ_Msk [2/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 776 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_GTSFREQ_Msk [3/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 776 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_GTSFREQ_Msk [4/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 783 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_GTSFREQ_Msk [5/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 794 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_GTSFREQ_Msk [6/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 794 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_GTSFREQ_Msk [7/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 794 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_GTSFREQ_Msk [8/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 798 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_GTSFREQ_Msk [9/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 856 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [10/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 859 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [11/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 859 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [12/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 859 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [13/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 859 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [14/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 859 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [15/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1060 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Msk [16/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1060 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_GTSFREQ_Msk [17/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1060 of file core_cm35p.h.

◆ ITM_TCR_GTSFREQ_Msk [18/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1061 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Msk [19/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1061 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Msk [20/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1061 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Msk [21/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1061 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Msk [22/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1076 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Msk [23/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1076 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Msk [24/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1143 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_GTSFREQ_Msk [25/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1143 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Msk [26/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1143 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_GTSFREQ_Msk [27/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1143 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_GTSFREQ_Msk [28/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1143 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Msk [29/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1143 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Msk [30/30]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1144 of file core_armv81mml.h.

◆ ITM_TCR_GTSFREQ_Pos [1/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 775 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_GTSFREQ_Pos [2/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 775 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_GTSFREQ_Pos [3/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 775 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_GTSFREQ_Pos [4/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 782 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_GTSFREQ_Pos [5/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 793 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_GTSFREQ_Pos [6/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 793 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_GTSFREQ_Pos [7/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 793 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_GTSFREQ_Pos [8/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 797 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_GTSFREQ_Pos [9/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 855 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [10/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 858 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [11/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 858 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [12/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 858 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [13/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 858 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [14/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 858 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [15/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1059 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_GTSFREQ_Pos [16/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1059 of file core_cm35p.h.

◆ ITM_TCR_GTSFREQ_Pos [17/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1059 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Pos [18/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1060 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Pos [19/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1060 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Pos [20/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1060 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Pos [21/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1060 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Pos [22/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1075 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Pos [23/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1075 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_GTSFREQ_Pos [24/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1142 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_GTSFREQ_Pos [25/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1142 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_GTSFREQ_Pos [26/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1142 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Pos [27/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1142 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_GTSFREQ_Pos [28/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1142 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Pos [29/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1142 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Pos [30/30]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1143 of file core_armv81mml.h.

◆ ITM_TCR_ITMENA_Msk [1/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 794 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_ITMENA_Msk [2/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 794 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_ITMENA_Msk [3/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 794 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_ITMENA_Msk [4/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 801 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_ITMENA_Msk [5/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 812 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_ITMENA_Msk [6/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 812 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_ITMENA_Msk [7/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 812 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_ITMENA_Msk [8/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 816 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_ITMENA_Msk [9/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 874 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [10/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 877 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [11/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 877 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [12/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 877 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [13/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 877 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [14/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 877 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [15/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1079 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Msk [16/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1079 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Msk [17/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1079 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Msk [18/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1079 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Msk [19/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1081 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_ITMENA_Msk [20/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1081 of file core_cm35p.h.

◆ ITM_TCR_ITMENA_Msk [21/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1081 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_ITMENA_Msk [22/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1094 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_ITMENA_Msk [23/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1094 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Msk [24/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1164 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_ITMENA_Msk [25/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1164 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_ITMENA_Msk [26/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1164 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_ITMENA_Msk [27/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1164 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_ITMENA_Msk [28/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1164 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_ITMENA_Msk [29/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1164 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_ITMENA_Msk [30/30]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1165 of file core_armv81mml.h.

◆ ITM_TCR_ITMENA_Pos [1/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 793 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_ITMENA_Pos [2/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 793 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_ITMENA_Pos [3/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 793 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_ITMENA_Pos [4/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 800 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_ITMENA_Pos [5/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 811 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_ITMENA_Pos [6/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 811 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_ITMENA_Pos [7/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 811 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_ITMENA_Pos [8/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 815 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_ITMENA_Pos [9/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 873 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [10/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 876 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [11/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 876 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [12/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 876 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [13/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 876 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [14/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 876 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [15/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1078 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Pos [16/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1078 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Pos [17/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1078 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Pos [18/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1078 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Pos [19/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1080 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_ITMENA_Pos [20/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1080 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_ITMENA_Pos [21/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1080 of file core_cm35p.h.

◆ ITM_TCR_ITMENA_Pos [22/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1093 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_ITMENA_Pos [23/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1093 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_ITMENA_Pos [24/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1163 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_ITMENA_Pos [25/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1163 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_ITMENA_Pos [26/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1163 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_ITMENA_Pos [27/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1163 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_ITMENA_Pos [28/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1163 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_ITMENA_Pos [29/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1163 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_ITMENA_Pos [30/30]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1164 of file core_armv81mml.h.

◆ ITM_TCR_STALLENA_Msk [1/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1066 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_STALLENA_Msk [2/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1066 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_STALLENA_Msk [3/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1066 of file core_cm35p.h.

◆ ITM_TCR_STALLENA_Msk [4/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1149 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_STALLENA_Msk [5/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1149 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_STALLENA_Msk [6/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1149 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_STALLENA_Msk [7/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1149 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_STALLENA_Msk [8/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1149 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_STALLENA_Msk [9/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1149 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_STALLENA_Msk [10/10]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1150 of file core_armv81mml.h.

◆ ITM_TCR_STALLENA_Pos [1/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1065 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_STALLENA_Pos [2/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1065 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_STALLENA_Pos [3/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1065 of file core_cm35p.h.

◆ ITM_TCR_STALLENA_Pos [4/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1148 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_STALLENA_Pos [5/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1148 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_STALLENA_Pos [6/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1148 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_STALLENA_Pos [7/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1148 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_STALLENA_Pos [8/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1148 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_STALLENA_Pos [9/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1148 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_STALLENA_Pos [10/10]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1149 of file core_armv81mml.h.

◆ ITM_TCR_SWOENA_Msk [1/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 782 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SWOENA_Msk [2/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 782 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SWOENA_Msk [3/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 782 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SWOENA_Msk [4/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 789 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SWOENA_Msk [5/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 800 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SWOENA_Msk [6/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 800 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SWOENA_Msk [7/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 800 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SWOENA_Msk [8/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 804 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SWOENA_Msk [9/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 862 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Msk [10/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 865 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Msk [11/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 865 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Msk [12/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 865 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Msk [13/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 865 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Msk [14/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 865 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Msk [15/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1067 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Msk [16/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1067 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Msk [17/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1067 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Msk [18/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1067 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Msk [19/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1069 of file core_cm35p.h.

◆ ITM_TCR_SWOENA_Msk [20/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1069 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SWOENA_Msk [21/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1069 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SWOENA_Msk [22/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1082 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Msk [23/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1082 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_SWOENA_Msk [24/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1152 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SWOENA_Msk [25/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1152 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SWOENA_Msk [26/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1152 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SWOENA_Msk [27/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1152 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SWOENA_Msk [28/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1152 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SWOENA_Msk [29/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1152 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SWOENA_Msk [30/30]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1153 of file core_armv81mml.h.

◆ ITM_TCR_SWOENA_Pos [1/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 781 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SWOENA_Pos [2/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 781 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SWOENA_Pos [3/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 781 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SWOENA_Pos [4/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 788 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SWOENA_Pos [5/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 799 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SWOENA_Pos [6/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 799 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SWOENA_Pos [7/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 799 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SWOENA_Pos [8/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 803 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SWOENA_Pos [9/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 861 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [10/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 864 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [11/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 864 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [12/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 864 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [13/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 864 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [14/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 864 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [15/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1066 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Pos [16/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1066 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Pos [17/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1066 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Pos [18/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1066 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Pos [19/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1068 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SWOENA_Pos [20/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1068 of file core_cm35p.h.

◆ ITM_TCR_SWOENA_Pos [21/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1068 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SWOENA_Pos [22/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1081 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_SWOENA_Pos [23/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1081 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SWOENA_Pos [24/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1151 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SWOENA_Pos [25/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1151 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SWOENA_Pos [26/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1151 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SWOENA_Pos [27/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1151 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SWOENA_Pos [28/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1151 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SWOENA_Pos [29/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1151 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SWOENA_Pos [30/30]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1152 of file core_armv81mml.h.

◆ ITM_TCR_SYNCENA_Msk [1/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 788 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SYNCENA_Msk [2/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 788 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SYNCENA_Msk [3/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 788 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SYNCENA_Msk [4/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 795 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SYNCENA_Msk [5/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 806 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SYNCENA_Msk [6/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 806 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SYNCENA_Msk [7/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 806 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SYNCENA_Msk [8/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 810 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SYNCENA_Msk [9/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 868 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [10/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 871 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [11/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 871 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [12/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 871 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [13/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 871 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [14/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 871 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [15/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1073 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Msk [16/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1073 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Msk [17/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1073 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Msk [18/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1073 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Msk [19/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1075 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SYNCENA_Msk [20/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1075 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Msk [21/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1075 of file core_cm35p.h.

◆ ITM_TCR_SYNCENA_Msk [22/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1088 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_SYNCENA_Msk [23/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1088 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Msk [24/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1158 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SYNCENA_Msk [25/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1158 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SYNCENA_Msk [26/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1158 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SYNCENA_Msk [27/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1158 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Msk [28/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1158 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Msk [29/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1158 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Msk [30/30]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1159 of file core_armv81mml.h.

◆ ITM_TCR_SYNCENA_Pos [1/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 787 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SYNCENA_Pos [2/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 787 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SYNCENA_Pos [3/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 787 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SYNCENA_Pos [4/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 794 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_SYNCENA_Pos [5/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 805 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SYNCENA_Pos [6/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 805 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SYNCENA_Pos [7/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 805 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SYNCENA_Pos [8/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 809 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_SYNCENA_Pos [9/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 867 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [10/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 870 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [11/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 870 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [12/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 870 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [13/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 870 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [14/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 870 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [15/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1072 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Pos [16/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1072 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Pos [17/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1072 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Pos [18/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1072 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Pos [19/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1074 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SYNCENA_Pos [20/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1074 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Pos [21/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1074 of file core_cm35p.h.

◆ ITM_TCR_SYNCENA_Pos [22/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1087 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_SYNCENA_Pos [23/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1087 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_SYNCENA_Pos [24/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1157 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SYNCENA_Pos [25/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1157 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SYNCENA_Pos [26/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1157 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_SYNCENA_Pos [27/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1157 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Pos [28/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1157 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Pos [29/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1157 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Pos [30/30]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1158 of file core_armv81mml.h.

◆ ITM_TCR_TraceBusID_Msk [1/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 773 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TraceBusID_Msk [2/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 773 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TraceBusID_Msk [3/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 773 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TraceBusID_Msk [4/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 780 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TraceBusID_Msk [5/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 791 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TraceBusID_Msk [6/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 791 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TraceBusID_Msk [7/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 791 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TraceBusID_Msk [8/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 795 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TraceBusID_Msk [9/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 853 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Msk [10/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 856 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Msk [11/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 856 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Msk [12/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 856 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Msk [13/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 856 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Msk [14/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 856 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TRACEBUSID_Msk [1/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1057 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Msk [2/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1057 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [3/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1057 of file core_cm35p.h.

◆ ITM_TCR_TraceBusID_Msk [15/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 1058 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Msk [16/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 1058 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Msk [17/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 1058 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Msk [18/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 1058 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Msk [19/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 1073 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Msk [20/20]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 1073 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_TRACEBUSID_Msk [4/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1140 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [5/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1140 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Msk [6/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1140 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [7/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1140 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Msk [8/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1140 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Msk [9/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1140 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [10/10]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1141 of file core_armv81mml.h.

◆ ITM_TCR_TraceBusID_Pos [1/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 772 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TraceBusID_Pos [2/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 772 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TraceBusID_Pos [3/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 772 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TraceBusID_Pos [4/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 779 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TraceBusID_Pos [5/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 790 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TraceBusID_Pos [6/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 790 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TraceBusID_Pos [7/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 790 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TraceBusID_Pos [8/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 794 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TraceBusID_Pos [9/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 852 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Pos [10/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 855 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Pos [11/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 855 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Pos [12/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 855 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Pos [13/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 855 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TraceBusID_Pos [14/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 855 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TRACEBUSID_Pos [1/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1056 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [2/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1056 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Pos [3/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1056 of file core_cm35p.h.

◆ ITM_TCR_TraceBusID_Pos [15/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1057 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Pos [16/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1057 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Pos [17/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1057 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Pos [18/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1057 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Pos [19/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1072 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TraceBusID_Pos [20/20]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1072 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_TRACEBUSID_Pos [4/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1139 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Pos [5/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1139 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [6/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1139 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Pos [7/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1139 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [8/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1139 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [9/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1139 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Pos [10/10]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1140 of file core_armv81mml.h.

◆ ITM_TCR_TSENA_Msk [1/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 791 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSENA_Msk [2/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 791 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSENA_Msk [3/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 791 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSENA_Msk [4/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 798 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSENA_Msk [5/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 809 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSENA_Msk [6/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 809 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSENA_Msk [7/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 809 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSENA_Msk [8/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 813 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSENA_Msk [9/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 871 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Msk [10/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 874 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Msk [11/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 874 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Msk [12/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 874 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Msk [13/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 874 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Msk [14/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 874 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Msk [15/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1076 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Msk [16/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1076 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Msk [17/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1076 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Msk [18/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1076 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Msk [19/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1078 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSENA_Msk [20/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1078 of file core_cm35p.h.

◆ ITM_TCR_TSENA_Msk [21/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1078 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSENA_Msk [22/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1091 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_TSENA_Msk [23/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1091 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Msk [24/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1161 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSENA_Msk [25/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1161 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSENA_Msk [26/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1161 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSENA_Msk [27/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1161 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSENA_Msk [28/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1161 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSENA_Msk [29/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1161 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSENA_Msk [30/30]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1162 of file core_armv81mml.h.

◆ ITM_TCR_TSENA_Pos [1/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 790 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSENA_Pos [2/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 790 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSENA_Pos [3/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 790 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSENA_Pos [4/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 797 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSENA_Pos [5/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 808 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSENA_Pos [6/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 808 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSENA_Pos [7/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 808 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSENA_Pos [8/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 812 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSENA_Pos [9/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 870 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Pos [10/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 873 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Pos [11/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 873 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Pos [12/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 873 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Pos [13/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 873 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Pos [14/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 873 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSENA_Pos [15/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1075 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Pos [16/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1075 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Pos [17/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1075 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Pos [18/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1075 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Pos [19/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1077 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSENA_Pos [20/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1077 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSENA_Pos [21/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1077 of file core_cm35p.h.

◆ ITM_TCR_TSENA_Pos [22/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1090 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_TSENA_Pos [23/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1090 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSENA_Pos [24/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1160 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSENA_Pos [25/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1160 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSENA_Pos [26/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1160 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSENA_Pos [27/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1160 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSENA_Pos [28/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1160 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSENA_Pos [29/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1160 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSENA_Pos [30/30]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1161 of file core_armv81mml.h.

◆ ITM_TCR_TSPrescale_Msk [1/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 779 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSPrescale_Msk [2/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 779 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSPrescale_Msk [3/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 779 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSPrescale_Msk [4/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 786 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSPrescale_Msk [5/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 797 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSPrescale_Msk [6/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 797 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSPrescale_Msk [7/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 797 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSPrescale_Msk [8/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 801 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSPrescale_Msk [9/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 859 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Msk [10/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 862 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Msk [11/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 862 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Msk [12/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 862 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Msk [13/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 862 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Msk [14/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 862 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPRESCALE_Msk [1/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1063 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Msk [2/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1063 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [3/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1063 of file core_cm35p.h.

◆ ITM_TCR_TSPrescale_Msk [15/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 1064 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPrescale_Msk [16/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 1064 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPrescale_Msk [17/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 1064 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPrescale_Msk [18/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 1064 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPrescale_Msk [19/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 1079 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_TSPrescale_Msk [20/20]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 1079 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPRESCALE_Msk [4/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1146 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Msk [5/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1146 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Msk [6/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1146 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Msk [7/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1146 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [8/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1146 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [9/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1146 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [10/10]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1147 of file core_armv81mml.h.

◆ ITM_TCR_TSPrescale_Pos [1/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 778 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSPrescale_Pos [2/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 778 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSPrescale_Pos [3/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 778 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSPrescale_Pos [4/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 785 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TCR_TSPrescale_Pos [5/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 796 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSPrescale_Pos [6/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 796 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSPrescale_Pos [7/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 796 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSPrescale_Pos [8/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 800 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TCR_TSPrescale_Pos [9/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 858 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Pos [10/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 861 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Pos [11/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 861 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Pos [12/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 861 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Pos [13/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 861 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPrescale_Pos [14/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 861 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TCR_TSPRESCALE_Pos [1/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1062 of file core_cm35p.h.

◆ ITM_TCR_TSPRESCALE_Pos [2/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1062 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [3/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1062 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSPrescale_Pos [15/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 1063 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPrescale_Pos [16/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 1063 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPrescale_Pos [17/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 1063 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPrescale_Pos [18/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 1063 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPrescale_Pos [19/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 1078 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TCR_TSPrescale_Pos [20/20]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 1078 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TCR_TSPRESCALE_Pos [4/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1145 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [5/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1145 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Pos [6/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1145 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [7/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1145 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Pos [8/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1145 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [9/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1145 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Pos [10/10]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1146 of file core_armv81mml.h.

◆ ITM_TPR_PRIVMASK_Msk [1/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 766 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TPR_PRIVMASK_Msk [2/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 766 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TPR_PRIVMASK_Msk [3/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 766 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TPR_PRIVMASK_Msk [4/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 773 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ ITM_TPR_PRIVMASK_Msk [5/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 784 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TPR_PRIVMASK_Msk [6/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 784 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TPR_PRIVMASK_Msk [7/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 784 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TPR_PRIVMASK_Msk [8/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 788 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ ITM_TPR_PRIVMASK_Msk [9/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 846 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [10/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 849 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [11/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 849 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [12/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 849 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [13/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 849 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [14/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 849 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [15/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1050 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TPR_PRIVMASK_Msk [16/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1050 of file core_cm35p.h.

◆ ITM_TPR_PRIVMASK_Msk [17/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1050 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Msk [18/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1051 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TPR_PRIVMASK_Msk [19/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1051 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TPR_PRIVMASK_Msk [20/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1051 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TPR_PRIVMASK_Msk [21/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1051 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TPR_PRIVMASK_Msk [22/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1066 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ ITM_TPR_PRIVMASK_Msk [23/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1066 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ ITM_TPR_PRIVMASK_Msk [24/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1133 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TPR_PRIVMASK_Msk [25/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1133 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TPR_PRIVMASK_Msk [26/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1133 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Msk [27/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1133 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Msk [28/30]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1133 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ ITM_TPR_PRIVMASK_Msk [29/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1133 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Msk [30/30]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1134 of file core_armv81mml.h.