Type definitions for the Floating Point Unit (FPU) More...

Collaboration diagram for Floating Point Unit (FPU):

Modules
	Core Debug Registers (CoreDebug)
	Type definitions for the Core Debug Registers.

Classes
struct	FPU_Type
	Structure type to access the Floating Point Unit (FPU). More...

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_MVFR2_VFP_Misc_Pos 4U

#define	FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_MVFR2_VFP_Misc_Pos 4U

#define	FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_MVFR2_VFP_Misc_Pos 4U

#define	FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

Detailed Description

Type definitions for the Floating Point Unit (FPU)

Macro Definition Documentation

◆ FPU_FPCAR_ADDRESS_Msk [1/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1345 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Msk [2/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1359 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Msk [3/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1359 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Msk [4/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1359 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Msk [5/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1359 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Msk [6/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1359 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Msk [7/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1565 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Msk [8/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1565 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Msk [9/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1565 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Msk [10/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1565 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Msk [11/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1568 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Msk [12/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1568 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Msk [13/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1654 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [14/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1729 of file core_cm35p.h.

◆ FPU_FPCAR_ADDRESS_Msk [15/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1729 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Msk [16/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1749 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [17/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1749 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [18/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1749 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [19/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1810 of file core_armv81mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [20/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1824 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Msk [21/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1824 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Msk [22/22]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1824 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Pos [1/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1344 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [2/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1358 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [3/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1358 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [4/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1358 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [5/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1358 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [6/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1358 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [7/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1564 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Pos [8/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1564 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Pos [9/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1564 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Pos [10/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1564 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Pos [11/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1567 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Pos [12/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1567 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Pos [13/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1653 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [14/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1728 of file core_cm35p.h.

◆ FPU_FPCAR_ADDRESS_Pos [15/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1728 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Pos [16/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1748 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [17/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1748 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [18/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1748 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [19/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1809 of file core_armv81mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [20/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1823 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Pos [21/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1823 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Pos [22/22]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1823 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_ASPEN_Msk [1/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1317 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [2/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1331 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [3/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1331 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [4/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1331 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [5/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1331 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [6/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1331 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [7/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1537 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Msk [8/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1537 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Msk [9/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1537 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Msk [10/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1537 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Msk [11/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1540 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Msk [12/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1540 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Msk [13/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1602 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Msk [14/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1677 of file core_cm35p.h.

◆ FPU_FPCCR_ASPEN_Msk [15/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1677 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_ASPEN_Msk [16/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1697 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Msk [17/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1697 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Msk [18/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1697 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Msk [19/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1758 of file core_armv81mml.h.

◆ FPU_FPCCR_ASPEN_Msk [20/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1772 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_ASPEN_Msk [21/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1772 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_ASPEN_Msk [22/22]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1772 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_ASPEN_Pos [1/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1316 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [2/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1330 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [3/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1330 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [4/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1330 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [5/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1330 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [6/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1330 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [7/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1536 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Pos [8/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1536 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Pos [9/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1536 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Pos [10/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1536 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Pos [11/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1539 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Pos [12/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1539 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_ASPEN_Pos [13/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1601 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Pos [14/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1676 of file core_cm35p.h.

◆ FPU_FPCCR_ASPEN_Pos [15/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1676 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_ASPEN_Pos [16/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1696 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Pos [17/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1696 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Pos [18/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1696 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Pos [19/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1757 of file core_armv81mml.h.

◆ FPU_FPCCR_ASPEN_Pos [20/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1771 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_ASPEN_Pos [21/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1771 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_ASPEN_Pos [22/22]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1771 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_BFRDY_Msk [1/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1326 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [2/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1340 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [3/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1340 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [4/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1340 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [5/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1340 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [6/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1340 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [7/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1546 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Msk [8/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1546 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Msk [9/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1546 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Msk [10/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1546 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Msk [11/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1549 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Msk [12/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1549 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Msk [13/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1632 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Msk [14/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1707 of file core_cm35p.h.

◆ FPU_FPCCR_BFRDY_Msk [15/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1707 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_BFRDY_Msk [16/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1727 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Msk [17/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1727 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Msk [18/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1727 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Msk [19/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1788 of file core_armv81mml.h.

◆ FPU_FPCCR_BFRDY_Msk [20/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1802 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_BFRDY_Msk [21/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1802 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_BFRDY_Msk [22/22]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1802 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_BFRDY_Pos [1/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1325 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [2/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1339 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [3/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1339 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [4/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1339 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [5/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1339 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [6/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1339 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [7/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1545 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Pos [8/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1545 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Pos [9/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1545 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Pos [10/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1545 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Pos [11/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1548 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Pos [12/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1548 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_BFRDY_Pos [13/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1631 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Pos [14/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1706 of file core_cm35p.h.

◆ FPU_FPCCR_BFRDY_Pos [15/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1706 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_BFRDY_Pos [16/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1726 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Pos [17/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1726 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Pos [18/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1726 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Pos [19/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1787 of file core_armv81mml.h.

◆ FPU_FPCCR_BFRDY_Pos [20/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1801 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_BFRDY_Pos [21/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1801 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_BFRDY_Pos [22/22]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1801 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Msk [1/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1611 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [2/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1686 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRET_Msk [3/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1686 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Msk [4/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1706 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [5/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1706 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [6/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1706 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [7/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1767 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [8/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1781 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Msk [9/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1781 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Msk [10/10]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1781 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Pos [1/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1610 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [2/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1685 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRET_Pos [3/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1685 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Pos [4/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1705 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [5/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1705 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [6/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1705 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [7/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1766 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [8/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1780 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Pos [9/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1780 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Pos [10/10]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1780 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Msk [1/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1614 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [2/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1689 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRETS_Msk [3/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1689 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Msk [4/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1709 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [5/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1709 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [6/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1709 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [7/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1770 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [8/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1784 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Msk [9/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1784 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Msk [10/10]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1784 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Pos [1/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1613 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [2/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1688 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRETS_Pos [3/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1688 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Pos [4/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1708 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [5/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1708 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [6/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1708 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [7/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1769 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [8/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1783 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Pos [9/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1783 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Pos [10/10]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1783 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_HFRDY_Msk [1/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1332 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Msk [2/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1346 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Msk [3/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1346 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Msk [4/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1346 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Msk [5/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1346 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Msk [6/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1346 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Msk [7/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1552 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Msk [8/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1552 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Msk [9/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1552 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Msk [10/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1552 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Msk [11/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1555 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Msk [12/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1555 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Msk [13/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1638 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Msk [14/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1713 of file core_cm35p.h.

◆ FPU_FPCCR_HFRDY_Msk [15/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1713 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_HFRDY_Msk [16/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1733 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Msk [17/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1733 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Msk [18/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1733 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Msk [19/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1794 of file core_armv81mml.h.

◆ FPU_FPCCR_HFRDY_Msk [20/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1808 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_HFRDY_Msk [21/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1808 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_HFRDY_Msk [22/22]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1808 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_HFRDY_Pos [1/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1331 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [2/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1345 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [3/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1345 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [4/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1345 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [5/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1345 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [6/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1345 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [7/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1551 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Pos [8/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1551 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Pos [9/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1551 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Pos [10/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1551 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Pos [11/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1554 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Pos [12/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1554 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_HFRDY_Pos [13/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1637 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Pos [14/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1712 of file core_cm35p.h.

◆ FPU_FPCCR_HFRDY_Pos [15/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1712 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_HFRDY_Pos [16/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1732 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Pos [17/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1732 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Pos [18/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1732 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Pos [19/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1793 of file core_armv81mml.h.

◆ FPU_FPCCR_HFRDY_Pos [20/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1807 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_HFRDY_Pos [21/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1807 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_HFRDY_Pos [22/22]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1807 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPACT_Msk [1/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1341 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [2/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1355 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [3/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1355 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [4/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1355 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [5/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1355 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [6/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1355 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [7/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1561 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Msk [8/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1561 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Msk [9/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1561 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Msk [10/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1561 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Msk [11/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1564 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Msk [12/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1564 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Msk [13/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1650 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Msk [14/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1725 of file core_cm35p.h.

◆ FPU_FPCCR_LSPACT_Msk [15/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1725 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPACT_Msk [16/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1745 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Msk [17/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1745 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Msk [18/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1745 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Msk [19/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1806 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPACT_Msk [20/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1820 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPACT_Msk [21/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1820 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPACT_Msk [22/22]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1820 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPACT_Pos [1/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1340 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [2/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1354 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [3/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1354 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [4/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1354 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [5/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1354 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [6/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1354 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [7/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1560 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Pos [8/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1560 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Pos [9/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1560 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Pos [10/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1560 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Pos [11/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1563 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Pos [12/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1563 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPACT_Pos [13/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1649 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Pos [14/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1724 of file core_cm35p.h.

◆ FPU_FPCCR_LSPACT_Pos [15/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1724 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPACT_Pos [16/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1744 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Pos [17/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1744 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Pos [18/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1744 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Pos [19/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1805 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPACT_Pos [20/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1819 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPACT_Pos [21/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1819 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPACT_Pos [22/22]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1819 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPEN_Msk [1/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1320 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [2/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1334 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [3/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1334 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [4/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1334 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [5/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1334 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [6/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1334 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [7/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1540 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Msk [8/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1540 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Msk [9/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1540 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Msk [10/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1540 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Msk [11/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1543 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Msk [12/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1543 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Msk [13/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1605 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Msk [14/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1680 of file core_cm35p.h.

◆ FPU_FPCCR_LSPEN_Msk [15/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1680 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPEN_Msk [16/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1700 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Msk [17/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1700 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Msk [18/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1700 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Msk [19/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1761 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPEN_Msk [20/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1775 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPEN_Msk [21/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1775 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPEN_Msk [22/22]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1775 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPEN_Pos [1/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1319 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [2/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1333 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [3/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1333 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [4/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1333 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [5/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1333 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [6/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1333 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [7/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1539 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Pos [8/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1539 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Pos [9/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1539 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Pos [10/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1539 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Pos [11/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1542 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Pos [12/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1542 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_LSPEN_Pos [13/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1604 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Pos [14/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1679 of file core_cm35p.h.

◆ FPU_FPCCR_LSPEN_Pos [15/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1679 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPEN_Pos [16/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1699 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Pos [17/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1699 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Pos [18/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1699 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Pos [19/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1760 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPEN_Pos [20/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1774 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPEN_Pos [21/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1774 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPEN_Pos [22/22]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1774 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPENS_Msk [1/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1608 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Msk [2/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1683 of file core_cm35p.h.

◆ FPU_FPCCR_LSPENS_Msk [3/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1683 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPENS_Msk [4/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1703 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Msk [5/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1703 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Msk [6/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1703 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Msk [7/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1764 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPENS_Msk [8/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1778 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPENS_Msk [9/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1778 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPENS_Msk [10/10]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1778 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPENS_Pos [1/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1607 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Pos [2/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1682 of file core_cm35p.h.

◆ FPU_FPCCR_LSPENS_Pos [3/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1682 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPENS_Pos [4/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1702 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Pos [5/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1702 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Pos [6/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1702 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Pos [7/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1763 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPENS_Pos [8/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1777 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPENS_Pos [9/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1777 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_LSPENS_Pos [10/10]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1777 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MMRDY_Msk [1/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1329 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Msk [2/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1343 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Msk [3/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1343 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Msk [4/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1343 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Msk [5/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1343 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Msk [6/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1343 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Msk [7/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1549 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Msk [8/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1549 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Msk [9/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1549 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Msk [10/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1549 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Msk [11/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1552 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Msk [12/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1552 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Msk [13/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1635 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Msk [14/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1710 of file core_cm35p.h.

◆ FPU_FPCCR_MMRDY_Msk [15/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1710 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MMRDY_Msk [16/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1730 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Msk [17/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1730 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Msk [18/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1730 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Msk [19/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1791 of file core_armv81mml.h.

◆ FPU_FPCCR_MMRDY_Msk [20/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1805 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MMRDY_Msk [21/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1805 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MMRDY_Msk [22/22]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1805 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MMRDY_Pos [1/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1328 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [2/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1342 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [3/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1342 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [4/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1342 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [5/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1342 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [6/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1342 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [7/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1548 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Pos [8/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1548 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Pos [9/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1548 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Pos [10/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1548 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Pos [11/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1551 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Pos [12/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1551 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_MMRDY_Pos [13/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1634 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Pos [14/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1709 of file core_cm35p.h.

◆ FPU_FPCCR_MMRDY_Pos [15/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1709 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MMRDY_Pos [16/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1729 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Pos [17/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1729 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Pos [18/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1729 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Pos [19/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1790 of file core_armv81mml.h.

◆ FPU_FPCCR_MMRDY_Pos [20/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1804 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MMRDY_Pos [21/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1804 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MMRDY_Pos [22/22]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1804 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MONRDY_Msk [1/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1323 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [2/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1337 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [3/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1337 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [4/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1337 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [5/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1337 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [6/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1337 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [7/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1543 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Msk [8/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1543 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Msk [9/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1543 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Msk [10/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1543 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Msk [11/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1546 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Msk [12/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1546 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Msk [13/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1626 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Msk [14/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1701 of file core_cm35p.h.

◆ FPU_FPCCR_MONRDY_Msk [15/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1701 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MONRDY_Msk [16/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1721 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Msk [17/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1721 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Msk [18/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1721 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Msk [19/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1782 of file core_armv81mml.h.

◆ FPU_FPCCR_MONRDY_Msk [20/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1796 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MONRDY_Msk [21/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1796 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MONRDY_Msk [22/22]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1796 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MONRDY_Pos [1/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1322 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [2/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1336 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [3/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1336 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [4/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1336 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [5/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1336 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [6/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1336 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [7/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1542 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Pos [8/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1542 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Pos [9/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1542 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Pos [10/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1542 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Pos [11/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1545 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Pos [12/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1545 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_MONRDY_Pos [13/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1625 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Pos [14/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1700 of file core_cm35p.h.

◆ FPU_FPCCR_MONRDY_Pos [15/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1700 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MONRDY_Pos [16/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1720 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Pos [17/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1720 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Pos [18/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1720 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Pos [19/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1781 of file core_armv81mml.h.

◆ FPU_FPCCR_MONRDY_Pos [20/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1795 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MONRDY_Pos [21/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1795 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_MONRDY_Pos [22/22]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1795 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_S_Msk [1/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1644 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_S_Msk [2/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1719 of file core_cm35p.h.

◆ FPU_FPCCR_S_Msk [3/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1719 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_S_Msk [4/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1739 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_S_Msk [5/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1739 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_S_Msk [6/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1739 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_S_Msk [7/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1800 of file core_armv81mml.h.

◆ FPU_FPCCR_S_Msk [8/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1814 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_S_Msk [9/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1814 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_S_Msk [10/10]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1814 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_S_Pos [1/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1643 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_S_Pos [2/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1718 of file core_cm35p.h.

◆ FPU_FPCCR_S_Pos [3/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1718 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_S_Pos [4/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1738 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_S_Pos [5/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1738 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_S_Pos [6/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1738 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_S_Pos [7/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1799 of file core_armv81mml.h.

◆ FPU_FPCCR_S_Pos [8/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1813 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_S_Pos [9/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1813 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_S_Pos [10/10]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1813 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SFRDY_Msk [1/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1629 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Msk [2/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1704 of file core_cm35p.h.

◆ FPU_FPCCR_SFRDY_Msk [3/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1704 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SFRDY_Msk [4/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1724 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Msk [5/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1724 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Msk [6/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1724 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Msk [7/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1785 of file core_armv81mml.h.

◆ FPU_FPCCR_SFRDY_Msk [8/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1799 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SFRDY_Msk [9/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1799 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SFRDY_Msk [10/10]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1799 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SFRDY_Pos [1/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1628 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Pos [2/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1703 of file core_cm35p.h.

◆ FPU_FPCCR_SFRDY_Pos [3/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1703 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SFRDY_Pos [4/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1723 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Pos [5/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1723 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Pos [6/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1723 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Pos [7/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1784 of file core_armv81mml.h.

◆ FPU_FPCCR_SFRDY_Pos [8/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1798 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SFRDY_Pos [9/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1798 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SFRDY_Pos [10/10]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1798 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [1/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1623 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [2/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1698 of file core_cm35p.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [3/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1698 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [4/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1718 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [5/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1718 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [6/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1718 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [7/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1779 of file core_armv81mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [8/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1793 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [9/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1793 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [10/10]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1793 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [1/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1622 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [2/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1697 of file core_cm35p.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [3/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1697 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [4/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1717 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [5/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1717 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [6/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1717 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [7/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1778 of file core_armv81mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [8/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1792 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [9/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1792 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [10/10]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1792 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_THREAD_Msk [1/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1335 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Msk [2/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1349 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Msk [3/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1349 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Msk [4/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1349 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Msk [5/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1349 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Msk [6/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1349 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Msk [7/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1555 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Msk [8/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1555 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Msk [9/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1555 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Msk [10/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1555 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Msk [11/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1558 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Msk [12/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1558 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_THREAD_Msk [13/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1641 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Msk [14/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1716 of file core_cm35p.h.

◆ FPU_FPCCR_THREAD_Msk [15/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1716 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_THREAD_Msk [16/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1736 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Msk [17/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1736 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Msk [18/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1736 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Msk [19/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1797 of file core_armv81mml.h.

◆ FPU_FPCCR_THREAD_Msk [20/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1811 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_THREAD_Msk [21/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1811 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_THREAD_Msk [22/22]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1811 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_THREAD_Pos [1/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1334 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [2/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1348 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [3/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1348 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [4/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1348 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [5/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1348 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [6/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1348 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [7/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1554 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Pos [8/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1554 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Pos [9/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1554 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Pos [10/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1554 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Pos [11/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1557 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_THREAD_Pos [12/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1557 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_THREAD_Pos [13/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1640 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Pos [14/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1715 of file core_cm35p.h.

◆ FPU_FPCCR_THREAD_Pos [15/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1715 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_THREAD_Pos [16/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1735 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Pos [17/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1735 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Pos [18/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1735 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Pos [19/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1796 of file core_armv81mml.h.

◆ FPU_FPCCR_THREAD_Pos [20/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1810 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_THREAD_Pos [21/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1810 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_THREAD_Pos [22/22]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1810 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_TS_Msk [1/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1617 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_TS_Msk [2/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1692 of file core_cm35p.h.

◆ FPU_FPCCR_TS_Msk [3/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1692 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_TS_Msk [4/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1712 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_TS_Msk [5/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1712 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_TS_Msk [6/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1712 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_TS_Msk [7/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1773 of file core_armv81mml.h.

◆ FPU_FPCCR_TS_Msk [8/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1787 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_TS_Msk [9/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1787 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_TS_Msk [10/10]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1787 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_TS_Pos [1/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1616 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_TS_Pos [2/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1691 of file core_cm35p.h.

◆ FPU_FPCCR_TS_Pos [3/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1691 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_TS_Pos [4/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1711 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_TS_Pos [5/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1711 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_TS_Pos [6/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1711 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_TS_Pos [7/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1772 of file core_armv81mml.h.

◆ FPU_FPCCR_TS_Pos [8/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1786 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_TS_Pos [9/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1786 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_TS_Pos [10/10]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1786 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_UFRDY_Msk [1/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1620 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Msk [2/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1695 of file core_cm35p.h.

◆ FPU_FPCCR_UFRDY_Msk [3/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1695 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_UFRDY_Msk [4/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1715 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Msk [5/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1715 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Msk [6/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1715 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Msk [7/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1776 of file core_armv81mml.h.

◆ FPU_FPCCR_UFRDY_Msk [8/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1790 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_UFRDY_Msk [9/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1790 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_UFRDY_Msk [10/10]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1790 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_UFRDY_Pos [1/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1619 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Pos [2/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1694 of file core_cm35p.h.

◆ FPU_FPCCR_UFRDY_Pos [3/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1694 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_UFRDY_Pos [4/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1714 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Pos [5/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1714 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Pos [6/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1714 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Pos [7/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1775 of file core_armv81mml.h.

◆ FPU_FPCCR_UFRDY_Pos [8/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1789 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_UFRDY_Pos [9/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1789 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_UFRDY_Pos [10/10]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1789 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_USER_Msk [1/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1338 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Msk [2/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1352 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Msk [3/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1352 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Msk [4/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1352 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Msk [5/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1352 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Msk [6/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1352 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Msk [7/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1558 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Msk [8/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1558 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Msk [9/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1558 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Msk [10/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1558 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Msk [11/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1561 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_USER_Msk [12/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1561 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Msk [13/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1647 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_USER_Msk [14/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1722 of file core_cm35p.h.

◆ FPU_FPCCR_USER_Msk [15/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1722 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_USER_Msk [16/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1742 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_USER_Msk [17/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1742 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_USER_Msk [18/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1742 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_USER_Msk [19/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1803 of file core_armv81mml.h.

◆ FPU_FPCCR_USER_Msk [20/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1817 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_USER_Msk [21/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1817 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_USER_Msk [22/22]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1817 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_USER_Pos [1/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1337 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Pos [2/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1351 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Pos [3/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1351 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Pos [4/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1351 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Pos [5/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1351 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Pos [6/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1351 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPCCR_USER_Pos [7/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1557 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Pos [8/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1557 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Pos [9/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1557 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Pos [10/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1557 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Pos [11/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1560 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPCCR_USER_Pos [12/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1560 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPCCR_USER_Pos [13/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1646 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_USER_Pos [14/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1721 of file core_cm35p.h.

◆ FPU_FPCCR_USER_Pos [15/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1721 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_USER_Pos [16/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1741 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_USER_Pos [17/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1741 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_USER_Pos [18/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1741 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPCCR_USER_Pos [19/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1802 of file core_armv81mml.h.

◆ FPU_FPCCR_USER_Pos [20/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1816 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_USER_Pos [21/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1816 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPCCR_USER_Pos [22/22]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1816 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_AHP_Msk [1/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1349 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [2/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1363 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [3/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1363 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [4/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1363 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [5/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1363 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [6/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1363 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [7/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1569 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Msk [8/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1569 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Msk [9/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1569 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Msk [10/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1569 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Msk [11/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1572 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Msk [12/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1572 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPDSCR_AHP_Msk [13/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1658 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Msk [14/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1733 of file core_cm35p.h.

◆ FPU_FPDSCR_AHP_Msk [15/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1733 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_AHP_Msk [16/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1753 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Msk [17/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1753 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Msk [18/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1753 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Msk [19/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1814 of file core_armv81mml.h.

◆ FPU_FPDSCR_AHP_Msk [20/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1828 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_AHP_Msk [21/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1828 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_AHP_Msk [22/22]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1828 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_AHP_Pos [1/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1348 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [2/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1362 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [3/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1362 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [4/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1362 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [5/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1362 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [6/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1362 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [7/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1568 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Pos [8/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1568 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Pos [9/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1568 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Pos [10/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1568 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Pos [11/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1571 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_AHP_Pos [12/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1571 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPDSCR_AHP_Pos [13/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1657 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Pos [14/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1732 of file core_cm35p.h.

◆ FPU_FPDSCR_AHP_Pos [15/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1732 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_AHP_Pos [16/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1752 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Pos [17/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1752 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Pos [18/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1752 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Pos [19/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1813 of file core_armv81mml.h.

◆ FPU_FPDSCR_AHP_Pos [20/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1827 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_AHP_Pos [21/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1827 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_AHP_Pos [22/22]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1827 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_DN_Msk [1/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1352 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [2/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1366 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [3/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1366 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [4/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1366 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [5/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1366 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [6/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1366 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [7/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1572 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Msk [8/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1572 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Msk [9/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1572 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Msk [10/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1572 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Msk [11/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1575 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Msk [12/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1575 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPDSCR_DN_Msk [13/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1661 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_DN_Msk [14/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1736 of file core_cm35p.h.

◆ FPU_FPDSCR_DN_Msk [15/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1736 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_DN_Msk [16/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1756 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_DN_Msk [17/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1756 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_DN_Msk [18/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1756 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_DN_Msk [19/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1817 of file core_armv81mml.h.

◆ FPU_FPDSCR_DN_Msk [20/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1831 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_DN_Msk [21/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1831 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_DN_Msk [22/22]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1831 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_DN_Pos [1/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1351 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [2/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1365 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [3/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1365 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [4/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1365 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [5/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1365 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [6/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1365 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [7/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1571 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Pos [8/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1571 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Pos [9/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1571 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Pos [10/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1571 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Pos [11/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1574 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_DN_Pos [12/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1574 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPDSCR_DN_Pos [13/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1660 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_DN_Pos [14/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1735 of file core_cm35p.h.

◆ FPU_FPDSCR_DN_Pos [15/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1735 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_DN_Pos [16/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1755 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_DN_Pos [17/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1755 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_DN_Pos [18/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1755 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_DN_Pos [19/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1816 of file core_armv81mml.h.

◆ FPU_FPDSCR_DN_Pos [20/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1830 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_DN_Pos [21/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1830 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_DN_Pos [22/22]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1830 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_FZ_Msk [1/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1355 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Msk [2/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1369 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Msk [3/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1369 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Msk [4/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1369 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Msk [5/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1369 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Msk [6/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1369 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Msk [7/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1575 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Msk [8/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1575 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Msk [9/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1575 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Msk [10/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1575 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Msk [11/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1578 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Msk [12/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1578 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPDSCR_FZ_Msk [13/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1664 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Msk [14/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1739 of file core_cm35p.h.

◆ FPU_FPDSCR_FZ_Msk [15/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1739 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_FZ_Msk [16/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1759 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Msk [17/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1759 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Msk [18/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1759 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Msk [19/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1820 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Msk [20/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1834 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_FZ_Msk [21/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1834 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_FZ_Msk [22/22]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1834 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_FZ_Pos [1/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1354 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [2/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1368 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [3/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1368 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [4/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1368 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [5/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1368 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [6/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1368 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [7/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1574 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Pos [8/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1574 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Pos [9/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1574 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Pos [10/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1574 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Pos [11/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1577 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPDSCR_FZ_Pos [12/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1577 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_FZ_Pos [13/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1663 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Pos [14/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1738 of file core_cm35p.h.

◆ FPU_FPDSCR_FZ_Pos [15/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1738 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_FZ_Pos [16/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1758 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Pos [17/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1758 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Pos [18/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1758 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Pos [19/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1819 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Pos [20/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1833 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_FZ_Pos [21/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1833 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_FZ_Pos [22/22]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1833 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_RMode_Msk [1/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1358 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Msk [2/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1372 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Msk [3/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1372 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Msk [4/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1372 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Msk [5/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1372 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Msk [6/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1372 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Msk [7/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1578 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Msk [8/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1578 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Msk [9/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1578 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Msk [10/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1578 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Msk [11/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1581 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Msk [12/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1581 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPDSCR_RMode_Msk [13/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1667 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Msk [14/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1742 of file core_cm35p.h.

◆ FPU_FPDSCR_RMode_Msk [15/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1742 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_RMode_Msk [16/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1762 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Msk [17/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1762 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Msk [18/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1762 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Msk [19/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1823 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Msk [20/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1837 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_RMode_Msk [21/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1837 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_RMode_Msk [22/22]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1837 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_RMode_Pos [1/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1357 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [2/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1371 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [3/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1371 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [4/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1371 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [5/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1371 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [6/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1371 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [7/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1577 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Pos [8/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1577 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Pos [9/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1577 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Pos [10/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1577 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Pos [11/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1580 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_FPDSCR_RMode_Pos [12/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1580 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_FPDSCR_RMode_Pos [13/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1666 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Pos [14/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1741 of file core_cm35p.h.

◆ FPU_FPDSCR_RMode_Pos [15/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1741 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_RMode_Pos [16/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1761 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Pos [17/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1761 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Pos [18/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1761 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Pos [19/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1822 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Pos [20/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1836 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_RMode_Pos [21/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1836 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_FPDSCR_RMode_Pos [22/22]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1836 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [1/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1383 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [2/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1397 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [3/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1397 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [4/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1397 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [5/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1397 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [6/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1397 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [7/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1603 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [8/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1603 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [9/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1603 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [10/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1603 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [11/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1606 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [12/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1606 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [13/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1692 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [14/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1767 of file core_cm35p.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [15/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1767 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [16/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1787 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [17/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1787 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [18/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1787 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [19/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1848 of file core_armv81mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [20/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1862 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [21/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1862 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [22/22]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1862 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [1/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1382 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [2/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1396 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [3/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1396 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [4/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1396 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [5/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1396 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [6/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1396 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [7/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1602 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [8/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1602 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [9/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1602 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [10/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1602 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [11/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1605 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [12/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1605 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [13/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1691 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [14/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1766 of file core_cm35p.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [15/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1766 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [16/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1786 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [17/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1786 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [18/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1786 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [19/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1847 of file core_armv81mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [20/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1861 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [21/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1861 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [22/22]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1861 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Divide_Msk [1/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1371 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [2/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1385 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [3/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1385 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [4/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1385 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [5/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1385 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [6/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1385 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [7/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1591 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Msk [8/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1591 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Msk [9/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1591 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Msk [10/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1591 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Msk [11/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1594 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Divide_Msk [12/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1594 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Msk [13/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1680 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Divide_Msk [14/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1755 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Divide_Msk [15/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1755 of file core_cm35p.h.

◆ FPU_MVFR0_Divide_Msk [16/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1775 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Divide_Msk [17/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1775 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Divide_Msk [18/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1775 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Divide_Msk [19/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1836 of file core_armv81mml.h.

◆ FPU_MVFR0_Divide_Msk [20/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1850 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Divide_Msk [21/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1850 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Divide_Msk [22/22]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1850 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Divide_Pos [1/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1370 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [2/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1384 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [3/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1384 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [4/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1384 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [5/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1384 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [6/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1384 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [7/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1590 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Pos [8/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1590 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Pos [9/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1590 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Pos [10/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1590 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Pos [11/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1593 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Divide_Pos [12/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1593 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Divide_Pos [13/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1679 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Divide_Pos [14/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1754 of file core_cm35p.h.

◆ FPU_MVFR0_Divide_Pos [15/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1754 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Divide_Pos [16/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1774 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Divide_Pos [17/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1774 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Divide_Pos [18/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1774 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Divide_Pos [19/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1835 of file core_armv81mml.h.

◆ FPU_MVFR0_Divide_Pos [20/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1849 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Divide_Pos [21/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1849 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Divide_Pos [22/22]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1849 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Double_precision_Msk [1/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1377 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [2/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1391 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [3/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1391 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [4/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1391 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [5/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1391 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [6/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1391 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [7/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1597 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Msk [8/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1597 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Msk [9/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1597 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Msk [10/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1597 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Msk [11/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1600 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Msk [12/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1600 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Msk [13/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1686 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Msk [14/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1761 of file core_cm35p.h.

◆ FPU_MVFR0_Double_precision_Msk [15/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1761 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Double_precision_Msk [16/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1781 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Msk [17/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1781 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Msk [18/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1781 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Msk [19/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1842 of file core_armv81mml.h.

◆ FPU_MVFR0_Double_precision_Msk [20/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1856 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Double_precision_Msk [21/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1856 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Double_precision_Msk [22/22]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1856 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Double_precision_Pos [1/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1376 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [2/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1390 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [3/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1390 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [4/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1390 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [5/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1390 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [6/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1390 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [7/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1596 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Pos [8/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1596 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Pos [9/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1596 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Pos [10/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1596 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Pos [11/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1599 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Pos [12/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1599 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Double_precision_Pos [13/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1685 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Pos [14/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1760 of file core_cm35p.h.

◆ FPU_MVFR0_Double_precision_Pos [15/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1760 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Double_precision_Pos [16/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1780 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Pos [17/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1780 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Pos [18/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1780 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Pos [19/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1841 of file core_armv81mml.h.

◆ FPU_MVFR0_Double_precision_Pos [20/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1855 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Double_precision_Pos [21/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1855 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Double_precision_Pos [22/22]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1855 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [1/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1374 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [2/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1388 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [3/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1388 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [4/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1388 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [5/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1388 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [6/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1388 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [7/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1594 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [8/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1594 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [9/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1594 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [10/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1594 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [11/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1597 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [12/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1597 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [13/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1683 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [14/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1758 of file core_cm35p.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [15/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1758 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [16/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1778 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [17/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1778 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [18/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1778 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [19/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1839 of file core_armv81mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [20/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1853 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [21/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1853 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [22/22]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1853 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [1/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1373 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [2/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1387 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [3/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1387 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [4/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1387 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [5/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1387 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [6/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1387 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [7/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1593 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [8/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1593 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [9/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1593 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [10/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1593 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [11/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1596 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [12/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1596 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [13/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1682 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [14/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1757 of file core_cm35p.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [15/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1757 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [16/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1777 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [17/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1777 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [18/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1777 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [19/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1838 of file core_armv81mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [20/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1852 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [21/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1852 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [22/22]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1852 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [1/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1362 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [2/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1376 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [3/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1376 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [4/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1376 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [5/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1376 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [6/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1376 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [7/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1582 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [8/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1582 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [9/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1582 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [10/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1582 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [11/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1585 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [12/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1585 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [13/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1671 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [14/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1746 of file core_cm35p.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [15/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1746 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [16/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1766 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [17/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1766 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [18/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1766 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [19/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1827 of file core_armv81mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [20/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1841 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [21/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1841 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [22/22]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1841 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [1/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1361 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [2/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1375 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [3/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1375 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [4/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1375 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [5/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1375 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [6/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1375 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [7/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1581 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [8/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1581 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [9/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1581 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [10/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1581 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [11/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1584 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [12/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1584 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [13/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1670 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [14/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1745 of file core_cm35p.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [15/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1745 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [16/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1765 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [17/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1765 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [18/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1765 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [19/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1826 of file core_armv81mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [20/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1840 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [21/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1840 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [22/22]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1840 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Msk [1/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1365 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Msk [2/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1379 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Msk [3/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1379 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Msk [4/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1379 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Msk [5/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1379 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Msk [6/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1379 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Msk [7/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1585 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Msk [8/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1585 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Msk [9/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1585 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Msk [10/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1585 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Msk [11/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1588 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Msk [12/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1588 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Msk [13/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1674 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [14/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1749 of file core_cm35p.h.

◆ FPU_MVFR0_Short_vectors_Msk [15/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1749 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Msk [16/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1769 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [17/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1769 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [18/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1769 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [19/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1830 of file core_armv81mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [20/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1844 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Msk [21/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1844 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Msk [22/22]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1844 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Pos [1/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1364 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [2/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1378 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [3/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1378 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [4/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1378 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [5/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1378 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [6/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1378 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [7/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1584 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Pos [8/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1584 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Pos [9/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1584 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Pos [10/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1584 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Pos [11/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1587 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Pos [12/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1587 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Pos [13/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1673 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [14/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1748 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Pos [15/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1748 of file core_cm35p.h.

◆ FPU_MVFR0_Short_vectors_Pos [16/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1768 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [17/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1768 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [18/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1768 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [19/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1829 of file core_armv81mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [20/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1843 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Pos [21/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1843 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Pos [22/22]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1843 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Single_precision_Msk [1/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1380 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Msk [2/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1394 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Msk [3/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1394 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Msk [4/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1394 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Msk [5/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1394 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Msk [6/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1394 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Msk [7/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1600 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Msk [8/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1600 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Msk [9/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1600 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Msk [10/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1600 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Msk [11/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1603 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Msk [12/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1603 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Msk [13/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1689 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Msk [14/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1764 of file core_cm35p.h.

◆ FPU_MVFR0_Single_precision_Msk [15/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1764 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Single_precision_Msk [16/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1784 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Msk [17/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1784 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Msk [18/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1784 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Msk [19/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1845 of file core_armv81mml.h.

◆ FPU_MVFR0_Single_precision_Msk [20/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1859 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Single_precision_Msk [21/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1859 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Single_precision_Msk [22/22]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1859 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Single_precision_Pos [1/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1379 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [2/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1393 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [3/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1393 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [4/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1393 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [5/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1393 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [6/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1393 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [7/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1599 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Pos [8/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1599 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Pos [9/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1599 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Pos [10/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1599 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Pos [11/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1602 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Pos [12/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1602 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Single_precision_Pos [13/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1688 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Pos [14/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1763 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Single_precision_Pos [15/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1763 of file core_cm35p.h.

◆ FPU_MVFR0_Single_precision_Pos [16/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1783 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Pos [17/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1783 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Pos [18/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1783 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Pos [19/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1844 of file core_armv81mml.h.

◆ FPU_MVFR0_Single_precision_Pos [20/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1858 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Single_precision_Pos [21/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1858 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Single_precision_Pos [22/22]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1858 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Square_root_Msk [1/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1368 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [2/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1382 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [3/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1382 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [4/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1382 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [5/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1382 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [6/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1382 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [7/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1588 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Square_root_Msk [8/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1588 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Square_root_Msk [9/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1588 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Square_root_Msk [10/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1588 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Square_root_Msk [11/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1591 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ FPU_MVFR0_Square_root_Msk [12/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1591 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ FPU_MVFR0_Square_root_Msk [13/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1677 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Msk [14/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1752 of file core_cm35p.h.

◆ FPU_MVFR0_Square_root_Msk [15/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1752 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Square_root_Msk [16/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1772 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Msk [17/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1772 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Msk [18/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1772 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Msk [19/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1833 of file core_armv81mml.h.

◆ FPU_MVFR0_Square_root_Msk [20/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1847 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Square_root_Msk [21/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1847 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ FPU_MVFR0_Square_root_Msk [22/22]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1847 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.