Core Register type definitions. More...

Collaboration diagram for Status and Control Registers:

Modules
	Nested Vectored Interrupt Controller (NVIC)
	Type definitions for the NVIC Registers.

Classes
union	APSR_Type
	Union type to access the Application Program Status Register (APSR). More...

union	CONTROL_Type
	Union type to access the Control Registers (CONTROL). More...

union	IPSR_Type
	Union type to access the Interrupt Program Status Register (IPSR). More...

union	xPSR_Type
	Union type to access the Special-Purpose Program Status Registers (xPSR). More...

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

Detailed Description

Core Register type definitions.

Macro Definition Documentation

◆ APSR_C_Msk [1/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_C_Msk [2/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_C_Msk [3/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_C_Msk [4/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_C_Msk [5/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_C_Msk [6/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_C_Msk [7/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_C_Msk [8/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_C_Msk [9/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 226 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_C_Msk [10/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 226 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_C_Msk [11/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 226 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_C_Msk [12/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 226 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_C_Msk [13/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_C_Msk [14/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_C_Msk [15/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_C_Msk [16/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_C_Msk [17/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_C_Msk [18/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_C_Msk [19/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_C_Msk [20/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_C_Msk [21/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 231 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_C_Msk [22/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 231 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_C_Msk [23/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 231 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_C_Msk [24/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 231 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_C_Msk [25/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_C_Msk [26/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_C_Msk [27/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_C_Msk [28/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_C_Msk [29/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_C_Msk [30/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_C_Msk [31/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_C_Msk [32/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_C_Msk [33/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 283 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Msk [34/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 283 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Msk [35/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 283 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Msk [36/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 283 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Msk [37/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 283 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Msk [38/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 283 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Msk [39/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 298 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_C_Msk [40/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 298 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Msk [41/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 298 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Msk [42/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 298 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Msk [43/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 298 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Msk [44/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 298 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Msk [45/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_C_Msk [46/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_C_Msk [47/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_C_Msk [48/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_C_Msk [49/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_C_Msk [50/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file core_cm35p.h.

◆ APSR_C_Msk [51/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_C_Msk [52/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_C_Msk [53/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_C_Msk [54/54]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 339 of file core_armv81mml.h.

◆ APSR_C_Pos [1/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_C_Pos [2/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_C_Pos [3/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_C_Pos [4/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_C_Pos [5/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_C_Pos [6/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_C_Pos [7/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_C_Pos [8/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_C_Pos [9/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 225 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_C_Pos [10/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 225 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_C_Pos [11/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 225 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_C_Pos [12/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 225 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_C_Pos [13/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_C_Pos [14/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_C_Pos [15/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_C_Pos [16/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_C_Pos [17/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_C_Pos [18/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_C_Pos [19/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_C_Pos [20/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_C_Pos [21/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 230 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_C_Pos [22/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 230 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_C_Pos [23/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 230 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_C_Pos [24/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 230 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_C_Pos [25/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_C_Pos [26/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_C_Pos [27/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_C_Pos [28/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_C_Pos [29/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_C_Pos [30/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_C_Pos [31/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_C_Pos [32/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_C_Pos [33/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 282 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Pos [34/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 282 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Pos [35/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 282 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Pos [36/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 282 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Pos [37/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 282 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Pos [38/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 282 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_C_Pos [39/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 297 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Pos [40/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 297 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Pos [41/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 297 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Pos [42/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 297 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Pos [43/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 297 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_C_Pos [44/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 297 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_C_Pos [45/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_C_Pos [46/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_C_Pos [47/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_C_Pos [48/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_C_Pos [49/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_C_Pos [50/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file core_cm35p.h.

◆ APSR_C_Pos [51/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_C_Pos [52/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_C_Pos [53/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_C_Pos [54/54]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 338 of file core_armv81mml.h.

◆ APSR_GE_Msk [1/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 292 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Msk [2/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 292 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Msk [3/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 292 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Msk [4/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 292 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Msk [5/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 292 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Msk [6/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 292 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Msk [7/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 307 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Msk [8/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 307 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Msk [9/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 307 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Msk [10/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 307 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Msk [11/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 307 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_GE_Msk [12/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 307 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Msk [13/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_GE_Msk [14/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_GE_Msk [15/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_GE_Msk [16/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_GE_Msk [17/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_GE_Msk [18/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file core_cm35p.h.

◆ APSR_GE_Msk [19/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_GE_Msk [20/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_GE_Msk [21/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_GE_Msk [22/22]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 348 of file core_armv81mml.h.

◆ APSR_GE_Pos [1/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 291 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Pos [2/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 291 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Pos [3/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 291 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Pos [4/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 291 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Pos [5/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 291 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Pos [6/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 291 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_GE_Pos [7/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 306 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Pos [8/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 306 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Pos [9/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 306 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Pos [10/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 306 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_GE_Pos [11/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 306 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Pos [12/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 306 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_GE_Pos [13/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_GE_Pos [14/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_GE_Pos [15/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_GE_Pos [16/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_GE_Pos [17/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_GE_Pos [18/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file core_cm35p.h.

◆ APSR_GE_Pos [19/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_GE_Pos [20/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_GE_Pos [21/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_GE_Pos [22/22]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 347 of file core_armv81mml.h.

◆ APSR_N_Msk [1/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_N_Msk [2/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_N_Msk [3/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_N_Msk [4/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_N_Msk [5/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_N_Msk [6/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_N_Msk [7/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_N_Msk [8/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_N_Msk [9/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 220 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_N_Msk [10/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 220 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_N_Msk [11/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 220 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_N_Msk [12/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 220 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_N_Msk [13/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_N_Msk [14/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_N_Msk [15/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_N_Msk [16/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_N_Msk [17/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_N_Msk [18/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_N_Msk [19/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_N_Msk [20/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_N_Msk [21/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 225 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_N_Msk [22/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 225 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_N_Msk [23/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 225 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_N_Msk [24/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 225 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_N_Msk [25/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_N_Msk [26/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_N_Msk [27/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_N_Msk [28/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_N_Msk [29/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_N_Msk [30/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_N_Msk [31/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_N_Msk [32/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_N_Msk [33/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 277 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Msk [34/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 277 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Msk [35/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 277 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Msk [36/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 277 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Msk [37/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 277 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Msk [38/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 277 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Msk [39/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 292 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Msk [40/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 292 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Msk [41/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 292 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_N_Msk [42/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 292 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Msk [43/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 292 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Msk [44/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 292 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Msk [45/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_N_Msk [46/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_N_Msk [47/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_N_Msk [48/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_N_Msk [49/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_N_Msk [50/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file core_cm35p.h.

◆ APSR_N_Msk [51/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_N_Msk [52/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_N_Msk [53/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_N_Msk [54/54]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 333 of file core_armv81mml.h.

◆ APSR_N_Pos [1/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_N_Pos [2/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_N_Pos [3/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_N_Pos [4/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_N_Pos [5/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_N_Pos [6/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_N_Pos [7/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_N_Pos [8/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_N_Pos [9/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 219 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_N_Pos [10/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 219 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_N_Pos [11/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 219 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_N_Pos [12/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 219 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_N_Pos [13/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_N_Pos [14/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_N_Pos [15/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_N_Pos [16/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_N_Pos [17/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_N_Pos [18/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_N_Pos [19/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_N_Pos [20/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_N_Pos [21/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 224 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_N_Pos [22/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 224 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_N_Pos [23/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 224 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_N_Pos [24/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 224 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_N_Pos [25/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_N_Pos [26/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_N_Pos [27/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_N_Pos [28/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_N_Pos [29/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_N_Pos [30/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_N_Pos [31/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_N_Pos [32/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_N_Pos [33/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 276 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Pos [34/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 276 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Pos [35/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 276 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Pos [36/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 276 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Pos [37/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 276 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Pos [38/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 276 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_N_Pos [39/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 291 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Pos [40/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 291 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Pos [41/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 291 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Pos [42/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 291 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_N_Pos [43/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 291 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Pos [44/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 291 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_N_Pos [45/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_N_Pos [46/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_N_Pos [47/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_N_Pos [48/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_N_Pos [49/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_N_Pos [50/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file core_cm35p.h.

◆ APSR_N_Pos [51/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_N_Pos [52/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_N_Pos [53/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_N_Pos [54/54]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 332 of file core_armv81mml.h.

◆ APSR_Q_Msk [1/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_Q_Msk [2/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_Q_Msk [3/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_Q_Msk [4/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_Q_Msk [5/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_Q_Msk [6/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_Q_Msk [7/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_Q_Msk [8/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_Q_Msk [9/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 289 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Msk [10/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 289 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Msk [11/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 289 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Msk [12/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 289 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Msk [13/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 289 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Msk [14/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 289 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Msk [15/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 304 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Msk [16/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 304 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_Q_Msk [17/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 304 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Msk [18/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 304 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Msk [19/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 304 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Msk [20/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 304 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Msk [21/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_Q_Msk [22/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_Q_Msk [23/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_Q_Msk [24/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_Q_Msk [25/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_Q_Msk [26/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file core_cm35p.h.

◆ APSR_Q_Msk [27/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_Q_Msk [28/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_Q_Msk [29/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_Q_Msk [30/30]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 345 of file core_armv81mml.h.

◆ APSR_Q_Pos [1/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_Q_Pos [2/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_Q_Pos [3/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_Q_Pos [4/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_Q_Pos [5/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_Q_Pos [6/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_Q_Pos [7/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_Q_Pos [8/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_Q_Pos [9/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 288 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Pos [10/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 288 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Pos [11/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 288 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Pos [12/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 288 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Pos [13/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 288 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Pos [14/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 288 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_Q_Pos [15/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 303 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Pos [16/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 303 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_Q_Pos [17/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 303 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Pos [18/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 303 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Pos [19/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 303 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Pos [20/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 303 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_Q_Pos [21/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_Q_Pos [22/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_Q_Pos [23/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_Q_Pos [24/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_Q_Pos [25/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_Q_Pos [26/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file core_cm35p.h.

◆ APSR_Q_Pos [27/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_Q_Pos [28/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_Q_Pos [29/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_Q_Pos [30/30]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 344 of file core_armv81mml.h.

◆ APSR_V_Msk [1/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_V_Msk [2/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_V_Msk [3/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_V_Msk [4/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_V_Msk [5/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_V_Msk [6/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_V_Msk [7/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_V_Msk [8/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_V_Msk [9/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 229 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_V_Msk [10/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 229 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_V_Msk [11/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 229 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_V_Msk [12/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 229 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_V_Msk [13/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_V_Msk [14/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_V_Msk [15/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_V_Msk [16/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_V_Msk [17/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_V_Msk [18/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_V_Msk [19/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_V_Msk [20/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_V_Msk [21/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 234 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_V_Msk [22/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 234 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_V_Msk [23/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 234 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_V_Msk [24/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 234 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_V_Msk [25/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_V_Msk [26/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_V_Msk [27/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_V_Msk [28/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_V_Msk [29/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_V_Msk [30/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_V_Msk [31/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_V_Msk [32/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_V_Msk [33/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 286 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Msk [34/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 286 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Msk [35/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 286 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Msk [36/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 286 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Msk [37/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 286 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Msk [38/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 286 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Msk [39/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 301 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Msk [40/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 301 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_V_Msk [41/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 301 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Msk [42/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 301 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Msk [43/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 301 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Msk [44/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 301 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Msk [45/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_V_Msk [46/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_V_Msk [47/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_V_Msk [48/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_V_Msk [49/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_V_Msk [50/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file core_cm35p.h.

◆ APSR_V_Msk [51/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_V_Msk [52/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_V_Msk [53/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_V_Msk [54/54]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 342 of file core_armv81mml.h.

◆ APSR_V_Pos [1/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_V_Pos [2/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_V_Pos [3/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_V_Pos [4/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_V_Pos [5/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_V_Pos [6/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_V_Pos [7/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ APSR_V_Pos [8/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ APSR_V_Pos [9/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 228 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_V_Pos [10/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 228 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_V_Pos [11/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 228 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_V_Pos [12/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 228 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ APSR_V_Pos [13/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_V_Pos [14/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_V_Pos [15/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_V_Pos [16/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_V_Pos [17/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_V_Pos [18/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_V_Pos [19/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ APSR_V_Pos [20/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ APSR_V_Pos [21/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 233 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_V_Pos [22/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 233 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_V_Pos [23/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 233 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_V_Pos [24/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 233 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ APSR_V_Pos [25/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_V_Pos [26/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_V_Pos [27/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_V_Pos [28/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_V_Pos [29/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_V_Pos [30/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_V_Pos [31/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ APSR_V_Pos [32/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ APSR_V_Pos [33/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 285 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Pos [34/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 285 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Pos [35/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 285 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Pos [36/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 285 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Pos [37/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 285 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Pos [38/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 285 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ APSR_V_Pos [39/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 300 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Pos [40/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 300 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Pos [41/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 300 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Pos [42/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 300 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Pos [43/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 300 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ APSR_V_Pos [44/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 300 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ APSR_V_Pos [45/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_V_Pos [46/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_V_Pos [47/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_V_Pos [48/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_V_Pos [49/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_V_Pos [50/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file core_cm35p.h.

◆ APSR_V_Pos [51/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_V_Pos [52/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ APSR_V_Pos [53/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ APSR_V_Pos [54/54]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 341 of file core_armv81mml.h.