stm32f407xx.h
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1 
34 #ifndef __STM32F407xx_H
35 #define __STM32F407xx_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
48 #define __CM4_REV 0x0001U
49 #define __MPU_PRESENT 1U
50 #define __NVIC_PRIO_BITS 4U
51 #define __Vendor_SysTickConfig 0U
52 #define __FPU_PRESENT 1U
66 typedef enum
67 {
68 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69  NonMaskableInt_IRQn = -14,
70  MemoryManagement_IRQn = -12,
71  BusFault_IRQn = -11,
72  UsageFault_IRQn = -10,
73  SVCall_IRQn = -5,
74  DebugMonitor_IRQn = -4,
75  PendSV_IRQn = -2,
76  SysTick_IRQn = -1,
77 /****** STM32 specific Interrupt Numbers **********************************************************************/
78  WWDG_IRQn = 0,
79  PVD_IRQn = 1,
80  TAMP_STAMP_IRQn = 2,
81  RTC_WKUP_IRQn = 3,
82  FLASH_IRQn = 4,
83  RCC_IRQn = 5,
84  EXTI0_IRQn = 6,
85  EXTI1_IRQn = 7,
86  EXTI2_IRQn = 8,
87  EXTI3_IRQn = 9,
88  EXTI4_IRQn = 10,
89  DMA1_Stream0_IRQn = 11,
90  DMA1_Stream1_IRQn = 12,
91  DMA1_Stream2_IRQn = 13,
92  DMA1_Stream3_IRQn = 14,
93  DMA1_Stream4_IRQn = 15,
94  DMA1_Stream5_IRQn = 16,
95  DMA1_Stream6_IRQn = 17,
96  ADC_IRQn = 18,
97  CAN1_TX_IRQn = 19,
98  CAN1_RX0_IRQn = 20,
99  CAN1_RX1_IRQn = 21,
100  CAN1_SCE_IRQn = 22,
101  EXTI9_5_IRQn = 23,
102  TIM1_BRK_TIM9_IRQn = 24,
103  TIM1_UP_TIM10_IRQn = 25,
104  TIM1_TRG_COM_TIM11_IRQn = 26,
105  TIM1_CC_IRQn = 27,
106  TIM2_IRQn = 28,
107  TIM3_IRQn = 29,
108  TIM4_IRQn = 30,
109  I2C1_EV_IRQn = 31,
110  I2C1_ER_IRQn = 32,
111  I2C2_EV_IRQn = 33,
112  I2C2_ER_IRQn = 34,
113  SPI1_IRQn = 35,
114  SPI2_IRQn = 36,
115  USART1_IRQn = 37,
116  USART2_IRQn = 38,
117  USART3_IRQn = 39,
118  EXTI15_10_IRQn = 40,
119  RTC_Alarm_IRQn = 41,
120  OTG_FS_WKUP_IRQn = 42,
121  TIM8_BRK_TIM12_IRQn = 43,
122  TIM8_UP_TIM13_IRQn = 44,
123  TIM8_TRG_COM_TIM14_IRQn = 45,
124  TIM8_CC_IRQn = 46,
125  DMA1_Stream7_IRQn = 47,
126  FSMC_IRQn = 48,
127  SDIO_IRQn = 49,
128  TIM5_IRQn = 50,
129  SPI3_IRQn = 51,
130  UART4_IRQn = 52,
131  UART5_IRQn = 53,
132  TIM6_DAC_IRQn = 54,
133  TIM7_IRQn = 55,
134  DMA2_Stream0_IRQn = 56,
135  DMA2_Stream1_IRQn = 57,
136  DMA2_Stream2_IRQn = 58,
137  DMA2_Stream3_IRQn = 59,
138  DMA2_Stream4_IRQn = 60,
139  ETH_IRQn = 61,
140  ETH_WKUP_IRQn = 62,
141  CAN2_TX_IRQn = 63,
142  CAN2_RX0_IRQn = 64,
143  CAN2_RX1_IRQn = 65,
144  CAN2_SCE_IRQn = 66,
145  OTG_FS_IRQn = 67,
146  DMA2_Stream5_IRQn = 68,
147  DMA2_Stream6_IRQn = 69,
148  DMA2_Stream7_IRQn = 70,
149  USART6_IRQn = 71,
150  I2C3_EV_IRQn = 72,
151  I2C3_ER_IRQn = 73,
152  OTG_HS_EP1_OUT_IRQn = 74,
153  OTG_HS_EP1_IN_IRQn = 75,
154  OTG_HS_WKUP_IRQn = 76,
155  OTG_HS_IRQn = 77,
156  DCMI_IRQn = 78,
157  RNG_IRQn = 80,
158  FPU_IRQn = 81
159 } IRQn_Type;
160 /* Legacy define */
161 #define HASH_RNG_IRQn RNG_IRQn
162 
167 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
168 #include "system_stm32f4xx.h"
169 #include <stdint.h>
170 
179 typedef struct
180 {
181  __IO uint32_t SR;
182  __IO uint32_t CR1;
183  __IO uint32_t CR2;
184  __IO uint32_t SMPR1;
185  __IO uint32_t SMPR2;
186  __IO uint32_t JOFR1;
187  __IO uint32_t JOFR2;
188  __IO uint32_t JOFR3;
189  __IO uint32_t JOFR4;
190  __IO uint32_t HTR;
191  __IO uint32_t LTR;
192  __IO uint32_t SQR1;
193  __IO uint32_t SQR2;
194  __IO uint32_t SQR3;
195  __IO uint32_t JSQR;
196  __IO uint32_t JDR1;
197  __IO uint32_t JDR2;
198  __IO uint32_t JDR3;
199  __IO uint32_t JDR4;
200  __IO uint32_t DR;
201 } ADC_TypeDef;
202 
203 typedef struct
204 {
205  __IO uint32_t CSR;
206  __IO uint32_t CCR;
207  __IO uint32_t CDR;
209 } ADC_Common_TypeDef;
210 
211 
216 typedef struct
217 {
218  __IO uint32_t TIR;
219  __IO uint32_t TDTR;
220  __IO uint32_t TDLR;
221  __IO uint32_t TDHR;
222 } CAN_TxMailBox_TypeDef;
223 
228 typedef struct
229 {
230  __IO uint32_t RIR;
231  __IO uint32_t RDTR;
232  __IO uint32_t RDLR;
233  __IO uint32_t RDHR;
234 } CAN_FIFOMailBox_TypeDef;
235 
240 typedef struct
241 {
242  __IO uint32_t FR1;
243  __IO uint32_t FR2;
244 } CAN_FilterRegister_TypeDef;
245 
250 typedef struct
251 {
252  __IO uint32_t MCR;
253  __IO uint32_t MSR;
254  __IO uint32_t TSR;
255  __IO uint32_t RF0R;
256  __IO uint32_t RF1R;
257  __IO uint32_t IER;
258  __IO uint32_t ESR;
259  __IO uint32_t BTR;
260  uint32_t RESERVED0[88];
261  CAN_TxMailBox_TypeDef sTxMailBox[3];
262  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
263  uint32_t RESERVED1[12];
264  __IO uint32_t FMR;
265  __IO uint32_t FM1R;
266  uint32_t RESERVED2;
267  __IO uint32_t FS1R;
268  uint32_t RESERVED3;
269  __IO uint32_t FFA1R;
270  uint32_t RESERVED4;
271  __IO uint32_t FA1R;
272  uint32_t RESERVED5[8];
273  CAN_FilterRegister_TypeDef sFilterRegister[28];
274 } CAN_TypeDef;
275 
280 typedef struct
281 {
282  __IO uint32_t DR;
283  __IO uint8_t IDR;
284  uint8_t RESERVED0;
285  uint16_t RESERVED1;
286  __IO uint32_t CR;
287 } CRC_TypeDef;
288 
293 typedef struct
294 {
295  __IO uint32_t CR;
296  __IO uint32_t SWTRIGR;
297  __IO uint32_t DHR12R1;
298  __IO uint32_t DHR12L1;
299  __IO uint32_t DHR8R1;
300  __IO uint32_t DHR12R2;
301  __IO uint32_t DHR12L2;
302  __IO uint32_t DHR8R2;
303  __IO uint32_t DHR12RD;
304  __IO uint32_t DHR12LD;
305  __IO uint32_t DHR8RD;
306  __IO uint32_t DOR1;
307  __IO uint32_t DOR2;
308  __IO uint32_t SR;
309 } DAC_TypeDef;
310 
315 typedef struct
316 {
317  __IO uint32_t IDCODE;
318  __IO uint32_t CR;
319  __IO uint32_t APB1FZ;
320  __IO uint32_t APB2FZ;
321 }DBGMCU_TypeDef;
322 
327 typedef struct
328 {
329  __IO uint32_t CR;
330  __IO uint32_t SR;
331  __IO uint32_t RISR;
332  __IO uint32_t IER;
333  __IO uint32_t MISR;
334  __IO uint32_t ICR;
335  __IO uint32_t ESCR;
336  __IO uint32_t ESUR;
337  __IO uint32_t CWSTRTR;
338  __IO uint32_t CWSIZER;
339  __IO uint32_t DR;
340 } DCMI_TypeDef;
341 
346 typedef struct
347 {
348  __IO uint32_t CR;
349  __IO uint32_t NDTR;
350  __IO uint32_t PAR;
351  __IO uint32_t M0AR;
352  __IO uint32_t M1AR;
353  __IO uint32_t FCR;
354 } DMA_Stream_TypeDef;
355 
356 typedef struct
357 {
358  __IO uint32_t LISR;
359  __IO uint32_t HISR;
360  __IO uint32_t LIFCR;
361  __IO uint32_t HIFCR;
362 } DMA_TypeDef;
363 
368 typedef struct
369 {
370  __IO uint32_t MACCR;
371  __IO uint32_t MACFFR;
372  __IO uint32_t MACHTHR;
373  __IO uint32_t MACHTLR;
374  __IO uint32_t MACMIIAR;
375  __IO uint32_t MACMIIDR;
376  __IO uint32_t MACFCR;
377  __IO uint32_t MACVLANTR; /* 8 */
378  uint32_t RESERVED0[2];
379  __IO uint32_t MACRWUFFR; /* 11 */
380  __IO uint32_t MACPMTCSR;
381  uint32_t RESERVED1;
382  __IO uint32_t MACDBGR;
383  __IO uint32_t MACSR; /* 15 */
384  __IO uint32_t MACIMR;
385  __IO uint32_t MACA0HR;
386  __IO uint32_t MACA0LR;
387  __IO uint32_t MACA1HR;
388  __IO uint32_t MACA1LR;
389  __IO uint32_t MACA2HR;
390  __IO uint32_t MACA2LR;
391  __IO uint32_t MACA3HR;
392  __IO uint32_t MACA3LR; /* 24 */
393  uint32_t RESERVED2[40];
394  __IO uint32_t MMCCR; /* 65 */
395  __IO uint32_t MMCRIR;
396  __IO uint32_t MMCTIR;
397  __IO uint32_t MMCRIMR;
398  __IO uint32_t MMCTIMR; /* 69 */
399  uint32_t RESERVED3[14];
400  __IO uint32_t MMCTGFSCCR; /* 84 */
401  __IO uint32_t MMCTGFMSCCR;
402  uint32_t RESERVED4[5];
403  __IO uint32_t MMCTGFCR;
404  uint32_t RESERVED5[10];
405  __IO uint32_t MMCRFCECR;
406  __IO uint32_t MMCRFAECR;
407  uint32_t RESERVED6[10];
408  __IO uint32_t MMCRGUFCR;
409  uint32_t RESERVED7[334];
410  __IO uint32_t PTPTSCR;
411  __IO uint32_t PTPSSIR;
412  __IO uint32_t PTPTSHR;
413  __IO uint32_t PTPTSLR;
414  __IO uint32_t PTPTSHUR;
415  __IO uint32_t PTPTSLUR;
416  __IO uint32_t PTPTSAR;
417  __IO uint32_t PTPTTHR;
418  __IO uint32_t PTPTTLR;
419  __IO uint32_t RESERVED8;
420  __IO uint32_t PTPTSSR;
421  uint32_t RESERVED9[565];
422  __IO uint32_t DMABMR;
423  __IO uint32_t DMATPDR;
424  __IO uint32_t DMARPDR;
425  __IO uint32_t DMARDLAR;
426  __IO uint32_t DMATDLAR;
427  __IO uint32_t DMASR;
428  __IO uint32_t DMAOMR;
429  __IO uint32_t DMAIER;
430  __IO uint32_t DMAMFBOCR;
431  __IO uint32_t DMARSWTR;
432  uint32_t RESERVED10[8];
433  __IO uint32_t DMACHTDR;
434  __IO uint32_t DMACHRDR;
435  __IO uint32_t DMACHTBAR;
436  __IO uint32_t DMACHRBAR;
437 } ETH_TypeDef;
438 
443 typedef struct
444 {
445  __IO uint32_t IMR;
446  __IO uint32_t EMR;
447  __IO uint32_t RTSR;
448  __IO uint32_t FTSR;
449  __IO uint32_t SWIER;
450  __IO uint32_t PR;
451 } EXTI_TypeDef;
452 
457 typedef struct
458 {
459  __IO uint32_t ACR;
460  __IO uint32_t KEYR;
461  __IO uint32_t OPTKEYR;
462  __IO uint32_t SR;
463  __IO uint32_t CR;
464  __IO uint32_t OPTCR;
465  __IO uint32_t OPTCR1;
466 } FLASH_TypeDef;
467 
468 
469 
474 typedef struct
475 {
476  __IO uint32_t BTCR[8];
477 } FSMC_Bank1_TypeDef;
478 
483 typedef struct
484 {
485  __IO uint32_t BWTR[7];
486 } FSMC_Bank1E_TypeDef;
487 
492 typedef struct
493 {
494  __IO uint32_t PCR2;
495  __IO uint32_t SR2;
496  __IO uint32_t PMEM2;
497  __IO uint32_t PATT2;
498  uint32_t RESERVED0;
499  __IO uint32_t ECCR2;
500  uint32_t RESERVED1;
501  uint32_t RESERVED2;
502  __IO uint32_t PCR3;
503  __IO uint32_t SR3;
504  __IO uint32_t PMEM3;
505  __IO uint32_t PATT3;
506  uint32_t RESERVED3;
507  __IO uint32_t ECCR3;
508 } FSMC_Bank2_3_TypeDef;
509 
514 typedef struct
515 {
516  __IO uint32_t PCR4;
517  __IO uint32_t SR4;
518  __IO uint32_t PMEM4;
519  __IO uint32_t PATT4;
520  __IO uint32_t PIO4;
521 } FSMC_Bank4_TypeDef;
522 
527 typedef struct
528 {
529  __IO uint32_t MODER;
530  __IO uint32_t OTYPER;
531  __IO uint32_t OSPEEDR;
532  __IO uint32_t PUPDR;
533  __IO uint32_t IDR;
534  __IO uint32_t ODR;
535  __IO uint32_t BSRR;
536  __IO uint32_t LCKR;
537  __IO uint32_t AFR[2];
538 } GPIO_TypeDef;
539 
544 typedef struct
545 {
546  __IO uint32_t MEMRMP;
547  __IO uint32_t PMC;
548  __IO uint32_t EXTICR[4];
549  uint32_t RESERVED[2];
550  __IO uint32_t CMPCR;
551 } SYSCFG_TypeDef;
552 
557 typedef struct
558 {
559  __IO uint32_t CR1;
560  __IO uint32_t CR2;
561  __IO uint32_t OAR1;
562  __IO uint32_t OAR2;
563  __IO uint32_t DR;
564  __IO uint32_t SR1;
565  __IO uint32_t SR2;
566  __IO uint32_t CCR;
567  __IO uint32_t TRISE;
568 } I2C_TypeDef;
569 
574 typedef struct
575 {
576  __IO uint32_t KR;
577  __IO uint32_t PR;
578  __IO uint32_t RLR;
579  __IO uint32_t SR;
580 } IWDG_TypeDef;
581 
582 
587 typedef struct
588 {
589  __IO uint32_t CR;
590  __IO uint32_t CSR;
591 } PWR_TypeDef;
592 
597 typedef struct
598 {
599  __IO uint32_t CR;
600  __IO uint32_t PLLCFGR;
601  __IO uint32_t CFGR;
602  __IO uint32_t CIR;
603  __IO uint32_t AHB1RSTR;
604  __IO uint32_t AHB2RSTR;
605  __IO uint32_t AHB3RSTR;
606  uint32_t RESERVED0;
607  __IO uint32_t APB1RSTR;
608  __IO uint32_t APB2RSTR;
609  uint32_t RESERVED1[2];
610  __IO uint32_t AHB1ENR;
611  __IO uint32_t AHB2ENR;
612  __IO uint32_t AHB3ENR;
613  uint32_t RESERVED2;
614  __IO uint32_t APB1ENR;
615  __IO uint32_t APB2ENR;
616  uint32_t RESERVED3[2];
617  __IO uint32_t AHB1LPENR;
618  __IO uint32_t AHB2LPENR;
619  __IO uint32_t AHB3LPENR;
620  uint32_t RESERVED4;
621  __IO uint32_t APB1LPENR;
622  __IO uint32_t APB2LPENR;
623  uint32_t RESERVED5[2];
624  __IO uint32_t BDCR;
625  __IO uint32_t CSR;
626  uint32_t RESERVED6[2];
627  __IO uint32_t SSCGR;
628  __IO uint32_t PLLI2SCFGR;
629 } RCC_TypeDef;
630 
635 typedef struct
636 {
637  __IO uint32_t TR;
638  __IO uint32_t DR;
639  __IO uint32_t CR;
640  __IO uint32_t ISR;
641  __IO uint32_t PRER;
642  __IO uint32_t WUTR;
643  __IO uint32_t CALIBR;
644  __IO uint32_t ALRMAR;
645  __IO uint32_t ALRMBR;
646  __IO uint32_t WPR;
647  __IO uint32_t SSR;
648  __IO uint32_t SHIFTR;
649  __IO uint32_t TSTR;
650  __IO uint32_t TSDR;
651  __IO uint32_t TSSSR;
652  __IO uint32_t CALR;
653  __IO uint32_t TAFCR;
654  __IO uint32_t ALRMASSR;
655  __IO uint32_t ALRMBSSR;
656  uint32_t RESERVED7;
657  __IO uint32_t BKP0R;
658  __IO uint32_t BKP1R;
659  __IO uint32_t BKP2R;
660  __IO uint32_t BKP3R;
661  __IO uint32_t BKP4R;
662  __IO uint32_t BKP5R;
663  __IO uint32_t BKP6R;
664  __IO uint32_t BKP7R;
665  __IO uint32_t BKP8R;
666  __IO uint32_t BKP9R;
667  __IO uint32_t BKP10R;
668  __IO uint32_t BKP11R;
669  __IO uint32_t BKP12R;
670  __IO uint32_t BKP13R;
671  __IO uint32_t BKP14R;
672  __IO uint32_t BKP15R;
673  __IO uint32_t BKP16R;
674  __IO uint32_t BKP17R;
675  __IO uint32_t BKP18R;
676  __IO uint32_t BKP19R;
677 } RTC_TypeDef;
678 
683 typedef struct
684 {
685  __IO uint32_t POWER;
686  __IO uint32_t CLKCR;
687  __IO uint32_t ARG;
688  __IO uint32_t CMD;
689  __IO const uint32_t RESPCMD;
690  __IO const uint32_t RESP1;
691  __IO const uint32_t RESP2;
692  __IO const uint32_t RESP3;
693  __IO const uint32_t RESP4;
694  __IO uint32_t DTIMER;
695  __IO uint32_t DLEN;
696  __IO uint32_t DCTRL;
697  __IO const uint32_t DCOUNT;
698  __IO const uint32_t STA;
699  __IO uint32_t ICR;
700  __IO uint32_t MASK;
701  uint32_t RESERVED0[2];
702  __IO const uint32_t FIFOCNT;
703  uint32_t RESERVED1[13];
704  __IO uint32_t FIFO;
705 } SDIO_TypeDef;
706 
711 typedef struct
712 {
713  __IO uint32_t CR1;
714  __IO uint32_t CR2;
715  __IO uint32_t SR;
716  __IO uint32_t DR;
717  __IO uint32_t CRCPR;
718  __IO uint32_t RXCRCR;
719  __IO uint32_t TXCRCR;
720  __IO uint32_t I2SCFGR;
721  __IO uint32_t I2SPR;
722 } SPI_TypeDef;
723 
724 
729 typedef struct
730 {
731  __IO uint32_t CR1;
732  __IO uint32_t CR2;
733  __IO uint32_t SMCR;
734  __IO uint32_t DIER;
735  __IO uint32_t SR;
736  __IO uint32_t EGR;
737  __IO uint32_t CCMR1;
738  __IO uint32_t CCMR2;
739  __IO uint32_t CCER;
740  __IO uint32_t CNT;
741  __IO uint32_t PSC;
742  __IO uint32_t ARR;
743  __IO uint32_t RCR;
744  __IO uint32_t CCR1;
745  __IO uint32_t CCR2;
746  __IO uint32_t CCR3;
747  __IO uint32_t CCR4;
748  __IO uint32_t BDTR;
749  __IO uint32_t DCR;
750  __IO uint32_t DMAR;
751  __IO uint32_t OR;
752 } TIM_TypeDef;
753 
758 typedef struct
759 {
760  __IO uint32_t SR;
761  __IO uint32_t DR;
762  __IO uint32_t BRR;
763  __IO uint32_t CR1;
764  __IO uint32_t CR2;
765  __IO uint32_t CR3;
766  __IO uint32_t GTPR;
767 } USART_TypeDef;
768 
773 typedef struct
774 {
775  __IO uint32_t CR;
776  __IO uint32_t CFR;
777  __IO uint32_t SR;
778 } WWDG_TypeDef;
779 
784 typedef struct
785 {
786  __IO uint32_t CR;
787  __IO uint32_t SR;
788  __IO uint32_t DR;
789 } RNG_TypeDef;
790 
794 typedef struct
795 {
796  __IO uint32_t GOTGCTL;
797  __IO uint32_t GOTGINT;
798  __IO uint32_t GAHBCFG;
799  __IO uint32_t GUSBCFG;
800  __IO uint32_t GRSTCTL;
801  __IO uint32_t GINTSTS;
802  __IO uint32_t GINTMSK;
803  __IO uint32_t GRXSTSR;
804  __IO uint32_t GRXSTSP;
805  __IO uint32_t GRXFSIZ;
806  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
807  __IO uint32_t HNPTXSTS;
808  uint32_t Reserved30[2];
809  __IO uint32_t GCCFG;
810  __IO uint32_t CID;
811  uint32_t Reserved40[48];
812  __IO uint32_t HPTXFSIZ;
813  __IO uint32_t DIEPTXF[0x0F];
814 } USB_OTG_GlobalTypeDef;
815 
819 typedef struct
820 {
821  __IO uint32_t DCFG;
822  __IO uint32_t DCTL;
823  __IO uint32_t DSTS;
824  uint32_t Reserved0C;
825  __IO uint32_t DIEPMSK;
826  __IO uint32_t DOEPMSK;
827  __IO uint32_t DAINT;
828  __IO uint32_t DAINTMSK;
829  uint32_t Reserved20;
830  uint32_t Reserved9;
831  __IO uint32_t DVBUSDIS;
832  __IO uint32_t DVBUSPULSE;
833  __IO uint32_t DTHRCTL;
834  __IO uint32_t DIEPEMPMSK;
835  __IO uint32_t DEACHINT;
836  __IO uint32_t DEACHMSK;
837  uint32_t Reserved40;
838  __IO uint32_t DINEP1MSK;
839  uint32_t Reserved44[15];
840  __IO uint32_t DOUTEP1MSK;
841 } USB_OTG_DeviceTypeDef;
842 
846 typedef struct
847 {
848  __IO uint32_t DIEPCTL;
849  uint32_t Reserved04;
850  __IO uint32_t DIEPINT;
851  uint32_t Reserved0C;
852  __IO uint32_t DIEPTSIZ;
853  __IO uint32_t DIEPDMA;
854  __IO uint32_t DTXFSTS;
855  uint32_t Reserved18;
856 } USB_OTG_INEndpointTypeDef;
857 
861 typedef struct
862 {
863  __IO uint32_t DOEPCTL;
864  uint32_t Reserved04;
865  __IO uint32_t DOEPINT;
866  uint32_t Reserved0C;
867  __IO uint32_t DOEPTSIZ;
868  __IO uint32_t DOEPDMA;
869  uint32_t Reserved18[2];
870 } USB_OTG_OUTEndpointTypeDef;
871 
875 typedef struct
876 {
877  __IO uint32_t HCFG;
878  __IO uint32_t HFIR;
879  __IO uint32_t HFNUM;
880  uint32_t Reserved40C;
881  __IO uint32_t HPTXSTS;
882  __IO uint32_t HAINT;
883  __IO uint32_t HAINTMSK;
884 } USB_OTG_HostTypeDef;
885 
889 typedef struct
890 {
891  __IO uint32_t HCCHAR;
892  __IO uint32_t HCSPLT;
893  __IO uint32_t HCINT;
894  __IO uint32_t HCINTMSK;
895  __IO uint32_t HCTSIZ;
896  __IO uint32_t HCDMA;
897  uint32_t Reserved[2];
898 } USB_OTG_HostChannelTypeDef;
899 
907 #define FLASH_BASE 0x08000000UL
908 #define CCMDATARAM_BASE 0x10000000UL
909 #define SRAM1_BASE 0x20000000UL
910 #define SRAM2_BASE 0x2001C000UL
911 #define PERIPH_BASE 0x40000000UL
912 #define BKPSRAM_BASE 0x40024000UL
913 #define FSMC_R_BASE 0xA0000000UL
914 #define SRAM1_BB_BASE 0x22000000UL
915 #define SRAM2_BB_BASE 0x22380000UL
916 #define PERIPH_BB_BASE 0x42000000UL
917 #define BKPSRAM_BB_BASE 0x42480000UL
918 #define FLASH_END 0x080FFFFFUL
919 #define FLASH_OTP_BASE 0x1FFF7800UL
920 #define FLASH_OTP_END 0x1FFF7A0FUL
921 #define CCMDATARAM_END 0x1000FFFFUL
923 /* Legacy defines */
924 #define SRAM_BASE SRAM1_BASE
925 #define SRAM_BB_BASE SRAM1_BB_BASE
926 
928 #define APB1PERIPH_BASE PERIPH_BASE
929 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
930 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
931 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
932 
934 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
935 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
936 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
937 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
938 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
939 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
940 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
941 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
942 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
943 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
944 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
945 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
946 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
947 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
948 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
949 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
950 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
951 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
952 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
953 #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
954 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
955 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
956 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
957 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
958 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
959 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
960 #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
961 
963 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
964 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
965 #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
966 #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
967 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
968 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
969 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
970 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
971 /* Legacy define */
972 #define ADC_BASE ADC123_COMMON_BASE
973 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
974 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
975 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
976 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
977 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
978 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
979 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
980 
982 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
983 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
984 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
985 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
986 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
987 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
988 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
989 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
990 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
991 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
992 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
993 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
994 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
995 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
996 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
997 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
998 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
999 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1000 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1001 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1002 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1003 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1004 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1005 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1006 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1007 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1008 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1009 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1010 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1011 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1012 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1013 #define ETH_MAC_BASE (ETH_BASE)
1014 #define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1015 #define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1016 #define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1017 
1019 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1020 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1021 
1023 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
1024 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
1025 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL)
1026 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)
1027 
1028 
1030 #define DBGMCU_BASE 0xE0042000UL
1031 
1032 #define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1033 #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1034 
1035 #define USB_OTG_GLOBAL_BASE 0x000UL
1036 #define USB_OTG_DEVICE_BASE 0x800UL
1037 #define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1038 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1039 #define USB_OTG_EP_REG_SIZE 0x20UL
1040 #define USB_OTG_HOST_BASE 0x400UL
1041 #define USB_OTG_HOST_PORT_BASE 0x440UL
1042 #define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1043 #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1044 #define USB_OTG_PCGCCTL_BASE 0xE00UL
1045 #define USB_OTG_FIFO_BASE 0x1000UL
1046 #define USB_OTG_FIFO_SIZE 0x1000UL
1047 
1048 #define UID_BASE 0x1FFF7A10UL
1049 #define FLASHSIZE_BASE 0x1FFF7A22UL
1050 #define PACKAGE_BASE 0x1FFF7BF0UL
1058 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1059 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1060 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1061 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1062 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1063 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1064 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1065 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1066 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1067 #define RTC ((RTC_TypeDef *) RTC_BASE)
1068 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1069 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1070 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1071 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1072 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1073 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1074 #define USART2 ((USART_TypeDef *) USART2_BASE)
1075 #define USART3 ((USART_TypeDef *) USART3_BASE)
1076 #define UART4 ((USART_TypeDef *) UART4_BASE)
1077 #define UART5 ((USART_TypeDef *) UART5_BASE)
1078 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1079 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1080 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1081 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1082 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1083 #define PWR ((PWR_TypeDef *) PWR_BASE)
1084 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1085 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1086 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1087 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1088 #define USART1 ((USART_TypeDef *) USART1_BASE)
1089 #define USART6 ((USART_TypeDef *) USART6_BASE)
1090 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1091 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1092 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1093 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1094 /* Legacy define */
1095 #define ADC ADC123_COMMON
1096 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1097 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1098 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1099 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1100 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1101 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1102 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1103 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1104 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1105 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1106 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1107 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1108 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1109 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1110 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1111 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1112 #define CRC ((CRC_TypeDef *) CRC_BASE)
1113 #define RCC ((RCC_TypeDef *) RCC_BASE)
1114 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1115 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1116 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1117 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1118 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1119 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1120 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1121 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1122 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1123 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1124 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1125 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1126 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1127 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1128 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1129 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1130 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1131 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1132 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1133 #define ETH ((ETH_TypeDef *) ETH_BASE)
1134 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1135 #define RNG ((RNG_TypeDef *) RNG_BASE)
1136 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1137 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1138 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1139 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1140 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1141 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1142 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1143 
1156 /******************************************************************************/
1157 /* Peripheral Registers_Bits_Definition */
1158 /******************************************************************************/
1159 
1160 /******************************************************************************/
1161 /* */
1162 /* Analog to Digital Converter */
1163 /* */
1164 /******************************************************************************/
1165 /*
1166  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1167  */
1168 #define ADC_MULTIMODE_SUPPORT
1170 /******************** Bit definition for ADC_SR register ********************/
1171 #define ADC_SR_AWD_Pos (0U)
1172 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1173 #define ADC_SR_AWD ADC_SR_AWD_Msk
1174 #define ADC_SR_EOC_Pos (1U)
1175 #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1176 #define ADC_SR_EOC ADC_SR_EOC_Msk
1177 #define ADC_SR_JEOC_Pos (2U)
1178 #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1179 #define ADC_SR_JEOC ADC_SR_JEOC_Msk
1180 #define ADC_SR_JSTRT_Pos (3U)
1181 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1182 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1183 #define ADC_SR_STRT_Pos (4U)
1184 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1185 #define ADC_SR_STRT ADC_SR_STRT_Msk
1186 #define ADC_SR_OVR_Pos (5U)
1187 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1188 #define ADC_SR_OVR ADC_SR_OVR_Msk
1190 /******************* Bit definition for ADC_CR1 register ********************/
1191 #define ADC_CR1_AWDCH_Pos (0U)
1192 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1193 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1194 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1195 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1196 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1197 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1198 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1199 #define ADC_CR1_EOCIE_Pos (5U)
1200 #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1201 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1202 #define ADC_CR1_AWDIE_Pos (6U)
1203 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1204 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1205 #define ADC_CR1_JEOCIE_Pos (7U)
1206 #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1207 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1208 #define ADC_CR1_SCAN_Pos (8U)
1209 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1210 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1211 #define ADC_CR1_AWDSGL_Pos (9U)
1212 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1213 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1214 #define ADC_CR1_JAUTO_Pos (10U)
1215 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1216 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1217 #define ADC_CR1_DISCEN_Pos (11U)
1218 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1219 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1220 #define ADC_CR1_JDISCEN_Pos (12U)
1221 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1222 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1223 #define ADC_CR1_DISCNUM_Pos (13U)
1224 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1225 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1226 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1227 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1228 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1229 #define ADC_CR1_JAWDEN_Pos (22U)
1230 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1231 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1232 #define ADC_CR1_AWDEN_Pos (23U)
1233 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1234 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1235 #define ADC_CR1_RES_Pos (24U)
1236 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1237 #define ADC_CR1_RES ADC_CR1_RES_Msk
1238 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1239 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1240 #define ADC_CR1_OVRIE_Pos (26U)
1241 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1242 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1244 /******************* Bit definition for ADC_CR2 register ********************/
1245 #define ADC_CR2_ADON_Pos (0U)
1246 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1247 #define ADC_CR2_ADON ADC_CR2_ADON_Msk
1248 #define ADC_CR2_CONT_Pos (1U)
1249 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1250 #define ADC_CR2_CONT ADC_CR2_CONT_Msk
1251 #define ADC_CR2_DMA_Pos (8U)
1252 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1253 #define ADC_CR2_DMA ADC_CR2_DMA_Msk
1254 #define ADC_CR2_DDS_Pos (9U)
1255 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1256 #define ADC_CR2_DDS ADC_CR2_DDS_Msk
1257 #define ADC_CR2_EOCS_Pos (10U)
1258 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1259 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1260 #define ADC_CR2_ALIGN_Pos (11U)
1261 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1262 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1263 #define ADC_CR2_JEXTSEL_Pos (16U)
1264 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1265 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1266 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1267 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1268 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1269 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1270 #define ADC_CR2_JEXTEN_Pos (20U)
1271 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1272 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1273 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1274 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1275 #define ADC_CR2_JSWSTART_Pos (22U)
1276 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1277 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1278 #define ADC_CR2_EXTSEL_Pos (24U)
1279 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1280 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1281 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1282 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1283 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1284 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1285 #define ADC_CR2_EXTEN_Pos (28U)
1286 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1287 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1288 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1289 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1290 #define ADC_CR2_SWSTART_Pos (30U)
1291 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1292 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1294 /****************** Bit definition for ADC_SMPR1 register *******************/
1295 #define ADC_SMPR1_SMP10_Pos (0U)
1296 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1297 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1298 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1299 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1300 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1301 #define ADC_SMPR1_SMP11_Pos (3U)
1302 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1303 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1304 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1305 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1306 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1307 #define ADC_SMPR1_SMP12_Pos (6U)
1308 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1309 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1310 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1311 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1312 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1313 #define ADC_SMPR1_SMP13_Pos (9U)
1314 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1315 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1316 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1317 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1318 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1319 #define ADC_SMPR1_SMP14_Pos (12U)
1320 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1321 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1322 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1323 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1324 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1325 #define ADC_SMPR1_SMP15_Pos (15U)
1326 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1327 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1328 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1329 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1330 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1331 #define ADC_SMPR1_SMP16_Pos (18U)
1332 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1333 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1334 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1335 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1336 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1337 #define ADC_SMPR1_SMP17_Pos (21U)
1338 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1339 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1340 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1341 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1342 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1343 #define ADC_SMPR1_SMP18_Pos (24U)
1344 #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1345 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1346 #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1347 #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1348 #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1350 /****************** Bit definition for ADC_SMPR2 register *******************/
1351 #define ADC_SMPR2_SMP0_Pos (0U)
1352 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1353 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1354 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1355 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1356 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1357 #define ADC_SMPR2_SMP1_Pos (3U)
1358 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1359 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1360 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1361 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1362 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1363 #define ADC_SMPR2_SMP2_Pos (6U)
1364 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1365 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1366 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1367 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1368 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1369 #define ADC_SMPR2_SMP3_Pos (9U)
1370 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1371 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1372 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1373 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1374 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1375 #define ADC_SMPR2_SMP4_Pos (12U)
1376 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1377 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1378 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1379 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1380 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1381 #define ADC_SMPR2_SMP5_Pos (15U)
1382 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1383 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1384 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1385 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1386 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1387 #define ADC_SMPR2_SMP6_Pos (18U)
1388 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1389 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1390 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1391 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1392 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1393 #define ADC_SMPR2_SMP7_Pos (21U)
1394 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1395 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1396 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1397 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1398 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1399 #define ADC_SMPR2_SMP8_Pos (24U)
1400 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1401 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1402 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1403 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1404 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1405 #define ADC_SMPR2_SMP9_Pos (27U)
1406 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1407 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1408 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1409 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1410 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1412 /****************** Bit definition for ADC_JOFR1 register *******************/
1413 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1414 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1415 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1417 /****************** Bit definition for ADC_JOFR2 register *******************/
1418 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1419 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1420 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1422 /****************** Bit definition for ADC_JOFR3 register *******************/
1423 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1424 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1425 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1427 /****************** Bit definition for ADC_JOFR4 register *******************/
1428 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1429 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1430 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1432 /******************* Bit definition for ADC_HTR register ********************/
1433 #define ADC_HTR_HT_Pos (0U)
1434 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1435 #define ADC_HTR_HT ADC_HTR_HT_Msk
1437 /******************* Bit definition for ADC_LTR register ********************/
1438 #define ADC_LTR_LT_Pos (0U)
1439 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1440 #define ADC_LTR_LT ADC_LTR_LT_Msk
1442 /******************* Bit definition for ADC_SQR1 register *******************/
1443 #define ADC_SQR1_SQ13_Pos (0U)
1444 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1445 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1446 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1447 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1448 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1449 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1450 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1451 #define ADC_SQR1_SQ14_Pos (5U)
1452 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1453 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1454 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1455 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1456 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1457 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1458 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1459 #define ADC_SQR1_SQ15_Pos (10U)
1460 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1461 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1462 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1463 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1464 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1465 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1466 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1467 #define ADC_SQR1_SQ16_Pos (15U)
1468 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1469 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1470 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1471 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1472 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1473 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1474 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1475 #define ADC_SQR1_L_Pos (20U)
1476 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1477 #define ADC_SQR1_L ADC_SQR1_L_Msk
1478 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1479 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1480 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1481 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1483 /******************* Bit definition for ADC_SQR2 register *******************/
1484 #define ADC_SQR2_SQ7_Pos (0U)
1485 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1486 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1487 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1488 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1489 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1490 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1491 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1492 #define ADC_SQR2_SQ8_Pos (5U)
1493 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1494 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1495 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1496 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1497 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1498 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1499 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1500 #define ADC_SQR2_SQ9_Pos (10U)
1501 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1502 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1503 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1504 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1505 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1506 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1507 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1508 #define ADC_SQR2_SQ10_Pos (15U)
1509 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1510 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1511 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1512 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1513 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1514 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1515 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1516 #define ADC_SQR2_SQ11_Pos (20U)
1517 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1518 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1519 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1520 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1521 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1522 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1523 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1524 #define ADC_SQR2_SQ12_Pos (25U)
1525 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1526 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1527 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1528 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1529 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1530 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1531 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1533 /******************* Bit definition for ADC_SQR3 register *******************/
1534 #define ADC_SQR3_SQ1_Pos (0U)
1535 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1536 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1537 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1538 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1539 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1540 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1541 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1542 #define ADC_SQR3_SQ2_Pos (5U)
1543 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1544 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1545 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1546 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1547 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1548 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1549 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1550 #define ADC_SQR3_SQ3_Pos (10U)
1551 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1552 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1553 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1554 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1555 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1556 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1557 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1558 #define ADC_SQR3_SQ4_Pos (15U)
1559 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1560 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1561 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1562 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1563 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1564 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1565 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1566 #define ADC_SQR3_SQ5_Pos (20U)
1567 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1568 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1569 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1570 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1571 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1572 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1573 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1574 #define ADC_SQR3_SQ6_Pos (25U)
1575 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1576 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1577 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1578 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1579 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1580 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1581 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1583 /******************* Bit definition for ADC_JSQR register *******************/
1584 #define ADC_JSQR_JSQ1_Pos (0U)
1585 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1586 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1587 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1588 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1589 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1590 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1591 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1592 #define ADC_JSQR_JSQ2_Pos (5U)
1593 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1594 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1595 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1596 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1597 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1598 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1599 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1600 #define ADC_JSQR_JSQ3_Pos (10U)
1601 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1602 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1603 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1604 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1605 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1606 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1607 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1608 #define ADC_JSQR_JSQ4_Pos (15U)
1609 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1610 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1611 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1612 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1613 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1614 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1615 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1616 #define ADC_JSQR_JL_Pos (20U)
1617 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1618 #define ADC_JSQR_JL ADC_JSQR_JL_Msk
1619 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1620 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1622 /******************* Bit definition for ADC_JDR1 register *******************/
1623 #define ADC_JDR1_JDATA_Pos (0U)
1624 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1625 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1627 /******************* Bit definition for ADC_JDR2 register *******************/
1628 #define ADC_JDR2_JDATA_Pos (0U)
1629 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1630 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1632 /******************* Bit definition for ADC_JDR3 register *******************/
1633 #define ADC_JDR3_JDATA_Pos (0U)
1634 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1635 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1637 /******************* Bit definition for ADC_JDR4 register *******************/
1638 #define ADC_JDR4_JDATA_Pos (0U)
1639 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1640 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1642 /******************** Bit definition for ADC_DR register ********************/
1643 #define ADC_DR_DATA_Pos (0U)
1644 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1645 #define ADC_DR_DATA ADC_DR_DATA_Msk
1646 #define ADC_DR_ADC2DATA_Pos (16U)
1647 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1648 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1650 /******************* Bit definition for ADC_CSR register ********************/
1651 #define ADC_CSR_AWD1_Pos (0U)
1652 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1653 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1654 #define ADC_CSR_EOC1_Pos (1U)
1655 #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1656 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1657 #define ADC_CSR_JEOC1_Pos (2U)
1658 #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1659 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1660 #define ADC_CSR_JSTRT1_Pos (3U)
1661 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1662 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1663 #define ADC_CSR_STRT1_Pos (4U)
1664 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1665 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1666 #define ADC_CSR_OVR1_Pos (5U)
1667 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1668 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1669 #define ADC_CSR_AWD2_Pos (8U)
1670 #define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1671 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1672 #define ADC_CSR_EOC2_Pos (9U)
1673 #define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1674 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1675 #define ADC_CSR_JEOC2_Pos (10U)
1676 #define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1677 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1678 #define ADC_CSR_JSTRT2_Pos (11U)
1679 #define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1680 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1681 #define ADC_CSR_STRT2_Pos (12U)
1682 #define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1683 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1684 #define ADC_CSR_OVR2_Pos (13U)
1685 #define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1686 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1687 #define ADC_CSR_AWD3_Pos (16U)
1688 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1689 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1690 #define ADC_CSR_EOC3_Pos (17U)
1691 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1692 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1693 #define ADC_CSR_JEOC3_Pos (18U)
1694 #define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1695 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1696 #define ADC_CSR_JSTRT3_Pos (19U)
1697 #define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1698 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1699 #define ADC_CSR_STRT3_Pos (20U)
1700 #define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1701 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1702 #define ADC_CSR_OVR3_Pos (21U)
1703 #define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1704 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1706 /* Legacy defines */
1707 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1708 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1709 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1710 
1711 /******************* Bit definition for ADC_CCR register ********************/
1712 #define ADC_CCR_MULTI_Pos (0U)
1713 #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1714 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1715 #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1716 #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1717 #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1718 #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1719 #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1720 #define ADC_CCR_DELAY_Pos (8U)
1721 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1722 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1723 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1724 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1725 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1726 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1727 #define ADC_CCR_DDS_Pos (13U)
1728 #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1729 #define ADC_CCR_DDS ADC_CCR_DDS_Msk
1730 #define ADC_CCR_DMA_Pos (14U)
1731 #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1732 #define ADC_CCR_DMA ADC_CCR_DMA_Msk
1733 #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1734 #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1735 #define ADC_CCR_ADCPRE_Pos (16U)
1736 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1737 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1738 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1739 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1740 #define ADC_CCR_VBATE_Pos (22U)
1741 #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1742 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1743 #define ADC_CCR_TSVREFE_Pos (23U)
1744 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1745 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1747 /******************* Bit definition for ADC_CDR register ********************/
1748 #define ADC_CDR_DATA1_Pos (0U)
1749 #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1750 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1751 #define ADC_CDR_DATA2_Pos (16U)
1752 #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1753 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1755 /* Legacy defines */
1756 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1757 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1758 
1759 /******************************************************************************/
1760 /* */
1761 /* Controller Area Network */
1762 /* */
1763 /******************************************************************************/
1765 /******************* Bit definition for CAN_MCR register ********************/
1766 #define CAN_MCR_INRQ_Pos (0U)
1767 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1768 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1769 #define CAN_MCR_SLEEP_Pos (1U)
1770 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1771 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1772 #define CAN_MCR_TXFP_Pos (2U)
1773 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1774 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1775 #define CAN_MCR_RFLM_Pos (3U)
1776 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1777 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1778 #define CAN_MCR_NART_Pos (4U)
1779 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1780 #define CAN_MCR_NART CAN_MCR_NART_Msk
1781 #define CAN_MCR_AWUM_Pos (5U)
1782 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1783 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1784 #define CAN_MCR_ABOM_Pos (6U)
1785 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1786 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1787 #define CAN_MCR_TTCM_Pos (7U)
1788 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1789 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1790 #define CAN_MCR_RESET_Pos (15U)
1791 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1792 #define CAN_MCR_RESET CAN_MCR_RESET_Msk
1793 #define CAN_MCR_DBF_Pos (16U)
1794 #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1795 #define CAN_MCR_DBF CAN_MCR_DBF_Msk
1796 /******************* Bit definition for CAN_MSR register ********************/
1797 #define CAN_MSR_INAK_Pos (0U)
1798 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1799 #define CAN_MSR_INAK CAN_MSR_INAK_Msk
1800 #define CAN_MSR_SLAK_Pos (1U)
1801 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1802 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1803 #define CAN_MSR_ERRI_Pos (2U)
1804 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1805 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1806 #define CAN_MSR_WKUI_Pos (3U)
1807 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1808 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1809 #define CAN_MSR_SLAKI_Pos (4U)
1810 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1811 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1812 #define CAN_MSR_TXM_Pos (8U)
1813 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1814 #define CAN_MSR_TXM CAN_MSR_TXM_Msk
1815 #define CAN_MSR_RXM_Pos (9U)
1816 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1817 #define CAN_MSR_RXM CAN_MSR_RXM_Msk
1818 #define CAN_MSR_SAMP_Pos (10U)
1819 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1820 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1821 #define CAN_MSR_RX_Pos (11U)
1822 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1823 #define CAN_MSR_RX CAN_MSR_RX_Msk
1825 /******************* Bit definition for CAN_TSR register ********************/
1826 #define CAN_TSR_RQCP0_Pos (0U)
1827 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1828 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1829 #define CAN_TSR_TXOK0_Pos (1U)
1830 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1831 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1832 #define CAN_TSR_ALST0_Pos (2U)
1833 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1834 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1835 #define CAN_TSR_TERR0_Pos (3U)
1836 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1837 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1838 #define CAN_TSR_ABRQ0_Pos (7U)
1839 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1840 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1841 #define CAN_TSR_RQCP1_Pos (8U)
1842 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1843 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1844 #define CAN_TSR_TXOK1_Pos (9U)
1845 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1846 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1847 #define CAN_TSR_ALST1_Pos (10U)
1848 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1849 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1850 #define CAN_TSR_TERR1_Pos (11U)
1851 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1852 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1853 #define CAN_TSR_ABRQ1_Pos (15U)
1854 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1855 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1856 #define CAN_TSR_RQCP2_Pos (16U)
1857 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1858 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1859 #define CAN_TSR_TXOK2_Pos (17U)
1860 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1861 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1862 #define CAN_TSR_ALST2_Pos (18U)
1863 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1864 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1865 #define CAN_TSR_TERR2_Pos (19U)
1866 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1867 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1868 #define CAN_TSR_ABRQ2_Pos (23U)
1869 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1870 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1871 #define CAN_TSR_CODE_Pos (24U)
1872 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1873 #define CAN_TSR_CODE CAN_TSR_CODE_Msk
1875 #define CAN_TSR_TME_Pos (26U)
1876 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1877 #define CAN_TSR_TME CAN_TSR_TME_Msk
1878 #define CAN_TSR_TME0_Pos (26U)
1879 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1880 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1881 #define CAN_TSR_TME1_Pos (27U)
1882 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1883 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1884 #define CAN_TSR_TME2_Pos (28U)
1885 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1886 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1888 #define CAN_TSR_LOW_Pos (29U)
1889 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1890 #define CAN_TSR_LOW CAN_TSR_LOW_Msk
1891 #define CAN_TSR_LOW0_Pos (29U)
1892 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1893 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1894 #define CAN_TSR_LOW1_Pos (30U)
1895 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1896 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1897 #define CAN_TSR_LOW2_Pos (31U)
1898 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1899 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1901 /******************* Bit definition for CAN_RF0R register *******************/
1902 #define CAN_RF0R_FMP0_Pos (0U)
1903 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1904 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1905 #define CAN_RF0R_FULL0_Pos (3U)
1906 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1907 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1908 #define CAN_RF0R_FOVR0_Pos (4U)
1909 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1910 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1911 #define CAN_RF0R_RFOM0_Pos (5U)
1912 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1913 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1915 /******************* Bit definition for CAN_RF1R register *******************/
1916 #define CAN_RF1R_FMP1_Pos (0U)
1917 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1918 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1919 #define CAN_RF1R_FULL1_Pos (3U)
1920 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1921 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1922 #define CAN_RF1R_FOVR1_Pos (4U)
1923 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1924 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1925 #define CAN_RF1R_RFOM1_Pos (5U)
1926 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1927 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1929 /******************** Bit definition for CAN_IER register *******************/
1930 #define CAN_IER_TMEIE_Pos (0U)
1931 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1932 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1933 #define CAN_IER_FMPIE0_Pos (1U)
1934 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1935 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1936 #define CAN_IER_FFIE0_Pos (2U)
1937 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1938 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1939 #define CAN_IER_FOVIE0_Pos (3U)
1940 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1941 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1942 #define CAN_IER_FMPIE1_Pos (4U)
1943 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1944 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1945 #define CAN_IER_FFIE1_Pos (5U)
1946 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1947 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1948 #define CAN_IER_FOVIE1_Pos (6U)
1949 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1950 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
1951 #define CAN_IER_EWGIE_Pos (8U)
1952 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
1953 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
1954 #define CAN_IER_EPVIE_Pos (9U)
1955 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
1956 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
1957 #define CAN_IER_BOFIE_Pos (10U)
1958 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
1959 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
1960 #define CAN_IER_LECIE_Pos (11U)
1961 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
1962 #define CAN_IER_LECIE CAN_IER_LECIE_Msk
1963 #define CAN_IER_ERRIE_Pos (15U)
1964 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
1965 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
1966 #define CAN_IER_WKUIE_Pos (16U)
1967 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
1968 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
1969 #define CAN_IER_SLKIE_Pos (17U)
1970 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
1971 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
1972 #define CAN_IER_EWGIE_Pos (8U)
1973 
1974 /******************** Bit definition for CAN_ESR register *******************/
1975 #define CAN_ESR_EWGF_Pos (0U)
1976 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
1977 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
1978 #define CAN_ESR_EPVF_Pos (1U)
1979 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
1980 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
1981 #define CAN_ESR_BOFF_Pos (2U)
1982 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
1983 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
1985 #define CAN_ESR_LEC_Pos (4U)
1986 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
1987 #define CAN_ESR_LEC CAN_ESR_LEC_Msk
1988 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
1989 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
1990 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
1992 #define CAN_ESR_TEC_Pos (16U)
1993 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
1994 #define CAN_ESR_TEC CAN_ESR_TEC_Msk
1995 #define CAN_ESR_REC_Pos (24U)
1996 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
1997 #define CAN_ESR_REC CAN_ESR_REC_Msk
1999 /******************* Bit definition for CAN_BTR register ********************/
2000 #define CAN_BTR_BRP_Pos (0U)
2001 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2002 #define CAN_BTR_BRP CAN_BTR_BRP_Msk
2003 #define CAN_BTR_TS1_Pos (16U)
2004 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2005 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2006 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2007 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2008 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2009 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2010 #define CAN_BTR_TS2_Pos (20U)
2011 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2012 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2013 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2014 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2015 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2016 #define CAN_BTR_SJW_Pos (24U)
2017 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2018 #define CAN_BTR_SJW CAN_BTR_SJW_Msk
2019 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2020 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2021 #define CAN_BTR_LBKM_Pos (30U)
2022 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2023 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2024 #define CAN_BTR_SILM_Pos (31U)
2025 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2026 #define CAN_BTR_SILM CAN_BTR_SILM_Msk
2030 /****************** Bit definition for CAN_TI0R register ********************/
2031 #define CAN_TI0R_TXRQ_Pos (0U)
2032 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2033 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2034 #define CAN_TI0R_RTR_Pos (1U)
2035 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2036 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2037 #define CAN_TI0R_IDE_Pos (2U)
2038 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2039 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2040 #define CAN_TI0R_EXID_Pos (3U)
2041 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2042 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2043 #define CAN_TI0R_STID_Pos (21U)
2044 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2045 #define CAN_TI0R_STID CAN_TI0R_STID_Msk
2047 /****************** Bit definition for CAN_TDT0R register *******************/
2048 #define CAN_TDT0R_DLC_Pos (0U)
2049 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2050 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2051 #define CAN_TDT0R_TGT_Pos (8U)
2052 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2053 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2054 #define CAN_TDT0R_TIME_Pos (16U)
2055 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2056 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2058 /****************** Bit definition for CAN_TDL0R register *******************/
2059 #define CAN_TDL0R_DATA0_Pos (0U)
2060 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2061 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2062 #define CAN_TDL0R_DATA1_Pos (8U)
2063 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2064 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2065 #define CAN_TDL0R_DATA2_Pos (16U)
2066 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2067 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2068 #define CAN_TDL0R_DATA3_Pos (24U)
2069 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2070 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2072 /****************** Bit definition for CAN_TDH0R register *******************/
2073 #define CAN_TDH0R_DATA4_Pos (0U)
2074 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2075 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2076 #define CAN_TDH0R_DATA5_Pos (8U)
2077 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2078 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2079 #define CAN_TDH0R_DATA6_Pos (16U)
2080 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2081 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2082 #define CAN_TDH0R_DATA7_Pos (24U)
2083 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2084 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2086 /******************* Bit definition for CAN_TI1R register *******************/
2087 #define CAN_TI1R_TXRQ_Pos (0U)
2088 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2089 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2090 #define CAN_TI1R_RTR_Pos (1U)
2091 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2092 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2093 #define CAN_TI1R_IDE_Pos (2U)
2094 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2095 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2096 #define CAN_TI1R_EXID_Pos (3U)
2097 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2098 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2099 #define CAN_TI1R_STID_Pos (21U)
2100 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2101 #define CAN_TI1R_STID CAN_TI1R_STID_Msk
2103 /******************* Bit definition for CAN_TDT1R register ******************/
2104 #define CAN_TDT1R_DLC_Pos (0U)
2105 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2106 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2107 #define CAN_TDT1R_TGT_Pos (8U)
2108 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2109 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2110 #define CAN_TDT1R_TIME_Pos (16U)
2111 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2112 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2114 /******************* Bit definition for CAN_TDL1R register ******************/
2115 #define CAN_TDL1R_DATA0_Pos (0U)
2116 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2117 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2118 #define CAN_TDL1R_DATA1_Pos (8U)
2119 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2120 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2121 #define CAN_TDL1R_DATA2_Pos (16U)
2122 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2123 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2124 #define CAN_TDL1R_DATA3_Pos (24U)
2125 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2126 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2128 /******************* Bit definition for CAN_TDH1R register ******************/
2129 #define CAN_TDH1R_DATA4_Pos (0U)
2130 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2131 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2132 #define CAN_TDH1R_DATA5_Pos (8U)
2133 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2134 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2135 #define CAN_TDH1R_DATA6_Pos (16U)
2136 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2137 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2138 #define CAN_TDH1R_DATA7_Pos (24U)
2139 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2140 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2142 /******************* Bit definition for CAN_TI2R register *******************/
2143 #define CAN_TI2R_TXRQ_Pos (0U)
2144 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2145 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2146 #define CAN_TI2R_RTR_Pos (1U)
2147 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2148 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2149 #define CAN_TI2R_IDE_Pos (2U)
2150 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2151 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2152 #define CAN_TI2R_EXID_Pos (3U)
2153 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2154 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2155 #define CAN_TI2R_STID_Pos (21U)
2156 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2157 #define CAN_TI2R_STID CAN_TI2R_STID_Msk
2159 /******************* Bit definition for CAN_TDT2R register ******************/
2160 #define CAN_TDT2R_DLC_Pos (0U)
2161 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2162 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2163 #define CAN_TDT2R_TGT_Pos (8U)
2164 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2165 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2166 #define CAN_TDT2R_TIME_Pos (16U)
2167 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2168 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2170 /******************* Bit definition for CAN_TDL2R register ******************/
2171 #define CAN_TDL2R_DATA0_Pos (0U)
2172 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2173 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2174 #define CAN_TDL2R_DATA1_Pos (8U)
2175 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2176 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2177 #define CAN_TDL2R_DATA2_Pos (16U)
2178 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2179 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2180 #define CAN_TDL2R_DATA3_Pos (24U)
2181 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2182 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2184 /******************* Bit definition for CAN_TDH2R register ******************/
2185 #define CAN_TDH2R_DATA4_Pos (0U)
2186 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2187 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2188 #define CAN_TDH2R_DATA5_Pos (8U)
2189 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2190 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2191 #define CAN_TDH2R_DATA6_Pos (16U)
2192 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2193 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2194 #define CAN_TDH2R_DATA7_Pos (24U)
2195 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2196 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2198 /******************* Bit definition for CAN_RI0R register *******************/
2199 #define CAN_RI0R_RTR_Pos (1U)
2200 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2201 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2202 #define CAN_RI0R_IDE_Pos (2U)
2203 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2204 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2205 #define CAN_RI0R_EXID_Pos (3U)
2206 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2207 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2208 #define CAN_RI0R_STID_Pos (21U)
2209 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2210 #define CAN_RI0R_STID CAN_RI0R_STID_Msk
2212 /******************* Bit definition for CAN_RDT0R register ******************/
2213 #define CAN_RDT0R_DLC_Pos (0U)
2214 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2215 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2216 #define CAN_RDT0R_FMI_Pos (8U)
2217 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2218 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2219 #define CAN_RDT0R_TIME_Pos (16U)
2220 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2221 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2223 /******************* Bit definition for CAN_RDL0R register ******************/
2224 #define CAN_RDL0R_DATA0_Pos (0U)
2225 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2226 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2227 #define CAN_RDL0R_DATA1_Pos (8U)
2228 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2229 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2230 #define CAN_RDL0R_DATA2_Pos (16U)
2231 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2232 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2233 #define CAN_RDL0R_DATA3_Pos (24U)
2234 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2235 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2237 /******************* Bit definition for CAN_RDH0R register ******************/
2238 #define CAN_RDH0R_DATA4_Pos (0U)
2239 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2240 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2241 #define CAN_RDH0R_DATA5_Pos (8U)
2242 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2243 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2244 #define CAN_RDH0R_DATA6_Pos (16U)
2245 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2246 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2247 #define CAN_RDH0R_DATA7_Pos (24U)
2248 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2249 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2251 /******************* Bit definition for CAN_RI1R register *******************/
2252 #define CAN_RI1R_RTR_Pos (1U)
2253 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2254 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2255 #define CAN_RI1R_IDE_Pos (2U)
2256 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2257 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2258 #define CAN_RI1R_EXID_Pos (3U)
2259 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2260 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2261 #define CAN_RI1R_STID_Pos (21U)
2262 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2263 #define CAN_RI1R_STID CAN_RI1R_STID_Msk
2265 /******************* Bit definition for CAN_RDT1R register ******************/
2266 #define CAN_RDT1R_DLC_Pos (0U)
2267 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2268 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2269 #define CAN_RDT1R_FMI_Pos (8U)
2270 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2271 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2272 #define CAN_RDT1R_TIME_Pos (16U)
2273 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2274 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2276 /******************* Bit definition for CAN_RDL1R register ******************/
2277 #define CAN_RDL1R_DATA0_Pos (0U)
2278 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2279 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2280 #define CAN_RDL1R_DATA1_Pos (8U)
2281 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2282 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2283 #define CAN_RDL1R_DATA2_Pos (16U)
2284 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2285 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2286 #define CAN_RDL1R_DATA3_Pos (24U)
2287 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2288 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2290 /******************* Bit definition for CAN_RDH1R register ******************/
2291 #define CAN_RDH1R_DATA4_Pos (0U)
2292 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2293 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2294 #define CAN_RDH1R_DATA5_Pos (8U)
2295 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2296 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2297 #define CAN_RDH1R_DATA6_Pos (16U)
2298 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2299 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2300 #define CAN_RDH1R_DATA7_Pos (24U)
2301 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2302 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2305 /******************* Bit definition for CAN_FMR register ********************/
2306 #define CAN_FMR_FINIT_Pos (0U)
2307 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2308 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2309 #define CAN_FMR_CAN2SB_Pos (8U)
2310 #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2311 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2313 /******************* Bit definition for CAN_FM1R register *******************/
2314 #define CAN_FM1R_FBM_Pos (0U)
2315 #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2316 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2317 #define CAN_FM1R_FBM0_Pos (0U)
2318 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2319 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2320 #define CAN_FM1R_FBM1_Pos (1U)
2321 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2322 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2323 #define CAN_FM1R_FBM2_Pos (2U)
2324 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2325 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2326 #define CAN_FM1R_FBM3_Pos (3U)
2327 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2328 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2329 #define CAN_FM1R_FBM4_Pos (4U)
2330 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2331 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2332 #define CAN_FM1R_FBM5_Pos (5U)
2333 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2334 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2335 #define CAN_FM1R_FBM6_Pos (6U)
2336 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2337 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2338 #define CAN_FM1R_FBM7_Pos (7U)
2339 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2340 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2341 #define CAN_FM1R_FBM8_Pos (8U)
2342 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2343 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2344 #define CAN_FM1R_FBM9_Pos (9U)
2345 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2346 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2347 #define CAN_FM1R_FBM10_Pos (10U)
2348 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2349 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2350 #define CAN_FM1R_FBM11_Pos (11U)
2351 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2352 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2353 #define CAN_FM1R_FBM12_Pos (12U)
2354 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2355 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2356 #define CAN_FM1R_FBM13_Pos (13U)
2357 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2358 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2359 #define CAN_FM1R_FBM14_Pos (14U)
2360 #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2361 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2362 #define CAN_FM1R_FBM15_Pos (15U)
2363 #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2364 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2365 #define CAN_FM1R_FBM16_Pos (16U)
2366 #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2367 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2368 #define CAN_FM1R_FBM17_Pos (17U)
2369 #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2370 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2371 #define CAN_FM1R_FBM18_Pos (18U)
2372 #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2373 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2374 #define CAN_FM1R_FBM19_Pos (19U)
2375 #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2376 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2377 #define CAN_FM1R_FBM20_Pos (20U)
2378 #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2379 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2380 #define CAN_FM1R_FBM21_Pos (21U)
2381 #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2382 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2383 #define CAN_FM1R_FBM22_Pos (22U)
2384 #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2385 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2386 #define CAN_FM1R_FBM23_Pos (23U)
2387 #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2388 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2389 #define CAN_FM1R_FBM24_Pos (24U)
2390 #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2391 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2392 #define CAN_FM1R_FBM25_Pos (25U)
2393 #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2394 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2395 #define CAN_FM1R_FBM26_Pos (26U)
2396 #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2397 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2398 #define CAN_FM1R_FBM27_Pos (27U)
2399 #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2400 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2402 /******************* Bit definition for CAN_FS1R register *******************/
2403 #define CAN_FS1R_FSC_Pos (0U)
2404 #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2405 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2406 #define CAN_FS1R_FSC0_Pos (0U)
2407 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2408 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2409 #define CAN_FS1R_FSC1_Pos (1U)
2410 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2411 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2412 #define CAN_FS1R_FSC2_Pos (2U)
2413 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2414 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2415 #define CAN_FS1R_FSC3_Pos (3U)
2416 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2417 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2418 #define CAN_FS1R_FSC4_Pos (4U)
2419 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2420 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2421 #define CAN_FS1R_FSC5_Pos (5U)
2422 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2423 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2424 #define CAN_FS1R_FSC6_Pos (6U)
2425 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2426 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2427 #define CAN_FS1R_FSC7_Pos (7U)
2428 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2429 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2430 #define CAN_FS1R_FSC8_Pos (8U)
2431 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2432 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2433 #define CAN_FS1R_FSC9_Pos (9U)
2434 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2435 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2436 #define CAN_FS1R_FSC10_Pos (10U)
2437 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2438 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2439 #define CAN_FS1R_FSC11_Pos (11U)
2440 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2441 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2442 #define CAN_FS1R_FSC12_Pos (12U)
2443 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2444 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2445 #define CAN_FS1R_FSC13_Pos (13U)
2446 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2447 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2448 #define CAN_FS1R_FSC14_Pos (14U)
2449 #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2450 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2451 #define CAN_FS1R_FSC15_Pos (15U)
2452 #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2453 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2454 #define CAN_FS1R_FSC16_Pos (16U)
2455 #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2456 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2457 #define CAN_FS1R_FSC17_Pos (17U)
2458 #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2459 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2460 #define CAN_FS1R_FSC18_Pos (18U)
2461 #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2462 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2463 #define CAN_FS1R_FSC19_Pos (19U)
2464 #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2465 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2466 #define CAN_FS1R_FSC20_Pos (20U)
2467 #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2468 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2469 #define CAN_FS1R_FSC21_Pos (21U)
2470 #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2471 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2472 #define CAN_FS1R_FSC22_Pos (22U)
2473 #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2474 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2475 #define CAN_FS1R_FSC23_Pos (23U)
2476 #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2477 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2478 #define CAN_FS1R_FSC24_Pos (24U)
2479 #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2480 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2481 #define CAN_FS1R_FSC25_Pos (25U)
2482 #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2483 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2484 #define CAN_FS1R_FSC26_Pos (26U)
2485 #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2486 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2487 #define CAN_FS1R_FSC27_Pos (27U)
2488 #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2489 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2491 /****************** Bit definition for CAN_FFA1R register *******************/
2492 #define CAN_FFA1R_FFA_Pos (0U)
2493 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2494 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2495 #define CAN_FFA1R_FFA0_Pos (0U)
2496 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2497 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2498 #define CAN_FFA1R_FFA1_Pos (1U)
2499 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2500 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2501 #define CAN_FFA1R_FFA2_Pos (2U)
2502 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2503 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2504 #define CAN_FFA1R_FFA3_Pos (3U)
2505 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2506 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2507 #define CAN_FFA1R_FFA4_Pos (4U)
2508 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2509 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2510 #define CAN_FFA1R_FFA5_Pos (5U)
2511 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2512 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2513 #define CAN_FFA1R_FFA6_Pos (6U)
2514 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2515 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2516 #define CAN_FFA1R_FFA7_Pos (7U)
2517 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2518 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2519 #define CAN_FFA1R_FFA8_Pos (8U)
2520 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2521 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2522 #define CAN_FFA1R_FFA9_Pos (9U)
2523 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2524 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2525 #define CAN_FFA1R_FFA10_Pos (10U)
2526 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2527 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2528 #define CAN_FFA1R_FFA11_Pos (11U)
2529 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2530 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2531 #define CAN_FFA1R_FFA12_Pos (12U)
2532 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2533 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2534 #define CAN_FFA1R_FFA13_Pos (13U)
2535 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2536 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2537 #define CAN_FFA1R_FFA14_Pos (14U)
2538 #define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2539 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2540 #define CAN_FFA1R_FFA15_Pos (15U)
2541 #define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2542 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2543 #define CAN_FFA1R_FFA16_Pos (16U)
2544 #define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2545 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2546 #define CAN_FFA1R_FFA17_Pos (17U)
2547 #define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2548 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2549 #define CAN_FFA1R_FFA18_Pos (18U)
2550 #define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2551 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2552 #define CAN_FFA1R_FFA19_Pos (19U)
2553 #define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2554 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2555 #define CAN_FFA1R_FFA20_Pos (20U)
2556 #define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2557 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2558 #define CAN_FFA1R_FFA21_Pos (21U)
2559 #define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2560 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2561 #define CAN_FFA1R_FFA22_Pos (22U)
2562 #define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2563 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2564 #define CAN_FFA1R_FFA23_Pos (23U)
2565 #define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2566 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2567 #define CAN_FFA1R_FFA24_Pos (24U)
2568 #define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2569 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2570 #define CAN_FFA1R_FFA25_Pos (25U)
2571 #define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2572 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2573 #define CAN_FFA1R_FFA26_Pos (26U)
2574 #define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2575 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2576 #define CAN_FFA1R_FFA27_Pos (27U)
2577 #define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2578 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2580 /******************* Bit definition for CAN_FA1R register *******************/
2581 #define CAN_FA1R_FACT_Pos (0U)
2582 #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2583 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2584 #define CAN_FA1R_FACT0_Pos (0U)
2585 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2586 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2587 #define CAN_FA1R_FACT1_Pos (1U)
2588 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2589 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2590 #define CAN_FA1R_FACT2_Pos (2U)
2591 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2592 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2593 #define CAN_FA1R_FACT3_Pos (3U)
2594 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2595 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2596 #define CAN_FA1R_FACT4_Pos (4U)
2597 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2598 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2599 #define CAN_FA1R_FACT5_Pos (5U)
2600 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2601 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2602 #define CAN_FA1R_FACT6_Pos (6U)
2603 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2604 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2605 #define CAN_FA1R_FACT7_Pos (7U)
2606 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2607 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2608 #define CAN_FA1R_FACT8_Pos (8U)
2609 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2610 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2611 #define CAN_FA1R_FACT9_Pos (9U)
2612 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2613 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2614 #define CAN_FA1R_FACT10_Pos (10U)
2615 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2616 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2617 #define CAN_FA1R_FACT11_Pos (11U)
2618 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2619 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2620 #define CAN_FA1R_FACT12_Pos (12U)
2621 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2622 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2623 #define CAN_FA1R_FACT13_Pos (13U)
2624 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2625 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2626 #define CAN_FA1R_FACT14_Pos (14U)
2627 #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2628 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2629 #define CAN_FA1R_FACT15_Pos (15U)
2630 #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2631 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2632 #define CAN_FA1R_FACT16_Pos (16U)
2633 #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2634 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2635 #define CAN_FA1R_FACT17_Pos (17U)
2636 #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2637 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2638 #define CAN_FA1R_FACT18_Pos (18U)
2639 #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2640 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2641 #define CAN_FA1R_FACT19_Pos (19U)
2642 #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2643 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2644 #define CAN_FA1R_FACT20_Pos (20U)
2645 #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2646 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2647 #define CAN_FA1R_FACT21_Pos (21U)
2648 #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2649 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2650 #define CAN_FA1R_FACT22_Pos (22U)
2651 #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2652 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2653 #define CAN_FA1R_FACT23_Pos (23U)
2654 #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2655 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2656 #define CAN_FA1R_FACT24_Pos (24U)
2657 #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2658 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2659 #define CAN_FA1R_FACT25_Pos (25U)
2660 #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2661 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2662 #define CAN_FA1R_FACT26_Pos (26U)
2663 #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2664 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2665 #define CAN_FA1R_FACT27_Pos (27U)
2666 #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2667 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2670 /******************* Bit definition for CAN_F0R1 register *******************/
2671 #define CAN_F0R1_FB0_Pos (0U)
2672 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2673 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2674 #define CAN_F0R1_FB1_Pos (1U)
2675 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2676 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2677 #define CAN_F0R1_FB2_Pos (2U)
2678 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2679 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2680 #define CAN_F0R1_FB3_Pos (3U)
2681 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2682 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2683 #define CAN_F0R1_FB4_Pos (4U)
2684 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2685 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2686 #define CAN_F0R1_FB5_Pos (5U)
2687 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2688 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2689 #define CAN_F0R1_FB6_Pos (6U)
2690 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2691 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2692 #define CAN_F0R1_FB7_Pos (7U)
2693 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2694 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2695 #define CAN_F0R1_FB8_Pos (8U)
2696 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2697 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2698 #define CAN_F0R1_FB9_Pos (9U)
2699 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2700 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2701 #define CAN_F0R1_FB10_Pos (10U)
2702 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2703 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2704 #define CAN_F0R1_FB11_Pos (11U)
2705 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2706 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2707 #define CAN_F0R1_FB12_Pos (12U)
2708 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2709 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2710 #define CAN_F0R1_FB13_Pos (13U)
2711 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2712 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2713 #define CAN_F0R1_FB14_Pos (14U)
2714 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2715 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2716 #define CAN_F0R1_FB15_Pos (15U)
2717 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2718 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2719 #define CAN_F0R1_FB16_Pos (16U)
2720 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2721 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2722 #define CAN_F0R1_FB17_Pos (17U)
2723 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2724 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2725 #define CAN_F0R1_FB18_Pos (18U)
2726 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2727 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2728 #define CAN_F0R1_FB19_Pos (19U)
2729 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2730 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2731 #define CAN_F0R1_FB20_Pos (20U)
2732 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2733 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2734 #define CAN_F0R1_FB21_Pos (21U)
2735 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2736 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2737 #define CAN_F0R1_FB22_Pos (22U)
2738 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2739 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2740 #define CAN_F0R1_FB23_Pos (23U)
2741 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2742 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2743 #define CAN_F0R1_FB24_Pos (24U)
2744 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2745 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2746 #define CAN_F0R1_FB25_Pos (25U)
2747 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2748 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2749 #define CAN_F0R1_FB26_Pos (26U)
2750 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2751 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2752 #define CAN_F0R1_FB27_Pos (27U)
2753 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2754 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2755 #define CAN_F0R1_FB28_Pos (28U)
2756 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2757 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2758 #define CAN_F0R1_FB29_Pos (29U)
2759 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2760 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2761 #define CAN_F0R1_FB30_Pos (30U)
2762 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2763 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2764 #define CAN_F0R1_FB31_Pos (31U)
2765 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2766 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2768 /******************* Bit definition for CAN_F1R1 register *******************/
2769 #define CAN_F1R1_FB0_Pos (0U)
2770 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2771 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2772 #define CAN_F1R1_FB1_Pos (1U)
2773 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2774 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2775 #define CAN_F1R1_FB2_Pos (2U)
2776 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2777 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2778 #define CAN_F1R1_FB3_Pos (3U)
2779 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2780 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2781 #define CAN_F1R1_FB4_Pos (4U)
2782 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2783 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2784 #define CAN_F1R1_FB5_Pos (5U)
2785 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2786 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2787 #define CAN_F1R1_FB6_Pos (6U)
2788 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2789 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2790 #define CAN_F1R1_FB7_Pos (7U)
2791 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2792 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2793 #define CAN_F1R1_FB8_Pos (8U)
2794 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2795 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2796 #define CAN_F1R1_FB9_Pos (9U)
2797 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2798 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2799 #define CAN_F1R1_FB10_Pos (10U)
2800 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2801 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2802 #define CAN_F1R1_FB11_Pos (11U)
2803 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2804 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2805 #define CAN_F1R1_FB12_Pos (12U)
2806 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2807 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2808 #define CAN_F1R1_FB13_Pos (13U)
2809 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2810 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2811 #define CAN_F1R1_FB14_Pos (14U)
2812 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2813 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2814 #define CAN_F1R1_FB15_Pos (15U)
2815 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2816 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2817 #define CAN_F1R1_FB16_Pos (16U)
2818 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2819 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2820 #define CAN_F1R1_FB17_Pos (17U)
2821 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2822 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2823 #define CAN_F1R1_FB18_Pos (18U)
2824 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2825 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2826 #define CAN_F1R1_FB19_Pos (19U)
2827 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2828 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2829 #define CAN_F1R1_FB20_Pos (20U)
2830 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2831 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2832 #define CAN_F1R1_FB21_Pos (21U)
2833 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2834 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2835 #define CAN_F1R1_FB22_Pos (22U)
2836 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2837 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2838 #define CAN_F1R1_FB23_Pos (23U)
2839 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2840 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2841 #define CAN_F1R1_FB24_Pos (24U)
2842 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2843 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2844 #define CAN_F1R1_FB25_Pos (25U)
2845 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2846 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2847 #define CAN_F1R1_FB26_Pos (26U)
2848 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2849 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2850 #define CAN_F1R1_FB27_Pos (27U)
2851 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2852 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2853 #define CAN_F1R1_FB28_Pos (28U)
2854 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2855 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2856 #define CAN_F1R1_FB29_Pos (29U)
2857 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2858 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2859 #define CAN_F1R1_FB30_Pos (30U)
2860 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2861 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2862 #define CAN_F1R1_FB31_Pos (31U)
2863 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2864 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2866 /******************* Bit definition for CAN_F2R1 register *******************/
2867 #define CAN_F2R1_FB0_Pos (0U)
2868 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2869 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2870 #define CAN_F2R1_FB1_Pos (1U)
2871 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2872 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2873 #define CAN_F2R1_FB2_Pos (2U)
2874 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2875 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2876 #define CAN_F2R1_FB3_Pos (3U)
2877 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2878 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2879 #define CAN_F2R1_FB4_Pos (4U)
2880 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2881 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2882 #define CAN_F2R1_FB5_Pos (5U)
2883 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2884 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2885 #define CAN_F2R1_FB6_Pos (6U)
2886 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2887 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2888 #define CAN_F2R1_FB7_Pos (7U)
2889 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2890 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2891 #define CAN_F2R1_FB8_Pos (8U)
2892 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2893 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2894 #define CAN_F2R1_FB9_Pos (9U)
2895 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2896 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2897 #define CAN_F2R1_FB10_Pos (10U)
2898 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2899 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2900 #define CAN_F2R1_FB11_Pos (11U)
2901 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2902 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2903 #define CAN_F2R1_FB12_Pos (12U)
2904 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2905 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2906 #define CAN_F2R1_FB13_Pos (13U)
2907 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2908 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2909 #define CAN_F2R1_FB14_Pos (14U)
2910 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2911 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2912 #define CAN_F2R1_FB15_Pos (15U)
2913 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2914 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2915 #define CAN_F2R1_FB16_Pos (16U)
2916 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2917 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2918 #define CAN_F2R1_FB17_Pos (17U)
2919 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2920 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2921 #define CAN_F2R1_FB18_Pos (18U)
2922 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2923 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2924 #define CAN_F2R1_FB19_Pos (19U)
2925 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2926 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2927 #define CAN_F2R1_FB20_Pos (20U)
2928 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2929 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2930 #define CAN_F2R1_FB21_Pos (21U)
2931 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2932 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2933 #define CAN_F2R1_FB22_Pos (22U)
2934 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2935 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2936 #define CAN_F2R1_FB23_Pos (23U)
2937 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2938 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2939 #define CAN_F2R1_FB24_Pos (24U)
2940 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2941 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2942 #define CAN_F2R1_FB25_Pos (25U)
2943 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2944 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2945 #define CAN_F2R1_FB26_Pos (26U)
2946 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2947 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2948 #define CAN_F2R1_FB27_Pos (27U)
2949 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2950 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2951 #define CAN_F2R1_FB28_Pos (28U)
2952 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2953 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2954 #define CAN_F2R1_FB29_Pos (29U)
2955 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2956 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2957 #define CAN_F2R1_FB30_Pos (30U)
2958 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2959 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2960 #define CAN_F2R1_FB31_Pos (31U)
2961 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2962 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2964 /******************* Bit definition for CAN_F3R1 register *******************/
2965 #define CAN_F3R1_FB0_Pos (0U)
2966 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2967 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2968 #define CAN_F3R1_FB1_Pos (1U)
2969 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2970 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2971 #define CAN_F3R1_FB2_Pos (2U)
2972 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2973 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
2974 #define CAN_F3R1_FB3_Pos (3U)
2975 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
2976 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
2977 #define CAN_F3R1_FB4_Pos (4U)
2978 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
2979 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
2980 #define CAN_F3R1_FB5_Pos (5U)
2981 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
2982 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
2983 #define CAN_F3R1_FB6_Pos (6U)
2984 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
2985 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
2986 #define CAN_F3R1_FB7_Pos (7U)
2987 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
2988 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
2989 #define CAN_F3R1_FB8_Pos (8U)
2990 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
2991 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
2992 #define CAN_F3R1_FB9_Pos (9U)
2993 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
2994 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
2995 #define CAN_F3R1_FB10_Pos (10U)
2996 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
2997 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
2998 #define CAN_F3R1_FB11_Pos (11U)
2999 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3000 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3001 #define CAN_F3R1_FB12_Pos (12U)
3002 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3003 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3004 #define CAN_F3R1_FB13_Pos (13U)
3005 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3006 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3007 #define CAN_F3R1_FB14_Pos (14U)
3008 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3009 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3010 #define CAN_F3R1_FB15_Pos (15U)
3011 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3012 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3013 #define CAN_F3R1_FB16_Pos (16U)
3014 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3015 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3016 #define CAN_F3R1_FB17_Pos (17U)
3017 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3018 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3019 #define CAN_F3R1_FB18_Pos (18U)
3020 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3021 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3022 #define CAN_F3R1_FB19_Pos (19U)
3023 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3024 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3025 #define CAN_F3R1_FB20_Pos (20U)
3026 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3027 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3028 #define CAN_F3R1_FB21_Pos (21U)
3029 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3030 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3031 #define CAN_F3R1_FB22_Pos (22U)
3032 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3033 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3034 #define CAN_F3R1_FB23_Pos (23U)
3035 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3036 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3037 #define CAN_F3R1_FB24_Pos (24U)
3038 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3039 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3040 #define CAN_F3R1_FB25_Pos (25U)
3041 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3042 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3043 #define CAN_F3R1_FB26_Pos (26U)
3044 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3045 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3046 #define CAN_F3R1_FB27_Pos (27U)
3047 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3048 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3049 #define CAN_F3R1_FB28_Pos (28U)
3050 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3051 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3052 #define CAN_F3R1_FB29_Pos (29U)
3053 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3054 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3055 #define CAN_F3R1_FB30_Pos (30U)
3056 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3057 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3058 #define CAN_F3R1_FB31_Pos (31U)
3059 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3060 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3062 /******************* Bit definition for CAN_F4R1 register *******************/
3063 #define CAN_F4R1_FB0_Pos (0U)
3064 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3065 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3066 #define CAN_F4R1_FB1_Pos (1U)
3067 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3068 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3069 #define CAN_F4R1_FB2_Pos (2U)
3070 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3071 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3072 #define CAN_F4R1_FB3_Pos (3U)
3073 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3074 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3075 #define CAN_F4R1_FB4_Pos (4U)
3076 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3077 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3078 #define CAN_F4R1_FB5_Pos (5U)
3079 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3080 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3081 #define CAN_F4R1_FB6_Pos (6U)
3082 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3083 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3084 #define CAN_F4R1_FB7_Pos (7U)
3085 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3086 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3087 #define CAN_F4R1_FB8_Pos (8U)
3088 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3089 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3090 #define CAN_F4R1_FB9_Pos (9U)
3091 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3092 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3093 #define CAN_F4R1_FB10_Pos (10U)
3094 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3095 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3096 #define CAN_F4R1_FB11_Pos (11U)
3097 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3098 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3099 #define CAN_F4R1_FB12_Pos (12U)
3100 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3101 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3102 #define CAN_F4R1_FB13_Pos (13U)
3103 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3104 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3105 #define CAN_F4R1_FB14_Pos (14U)
3106 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3107 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3108 #define CAN_F4R1_FB15_Pos (15U)
3109 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3110 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3111 #define CAN_F4R1_FB16_Pos (16U)
3112 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3113 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3114 #define CAN_F4R1_FB17_Pos (17U)
3115 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3116 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3117 #define CAN_F4R1_FB18_Pos (18U)
3118 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3119 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3120 #define CAN_F4R1_FB19_Pos (19U)
3121 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3122 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3123 #define CAN_F4R1_FB20_Pos (20U)
3124 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3125 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3126 #define CAN_F4R1_FB21_Pos (21U)
3127 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3128 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3129 #define CAN_F4R1_FB22_Pos (22U)
3130 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3131 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3132 #define CAN_F4R1_FB23_Pos (23U)
3133 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3134 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3135 #define CAN_F4R1_FB24_Pos (24U)
3136 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3137 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3138 #define CAN_F4R1_FB25_Pos (25U)
3139 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3140 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3141 #define CAN_F4R1_FB26_Pos (26U)
3142 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3143 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3144 #define CAN_F4R1_FB27_Pos (27U)
3145 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3146 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3147 #define CAN_F4R1_FB28_Pos (28U)
3148 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3149 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3150 #define CAN_F4R1_FB29_Pos (29U)
3151 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3152 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3153 #define CAN_F4R1_FB30_Pos (30U)
3154 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3155 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3156 #define CAN_F4R1_FB31_Pos (31U)
3157 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3158 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3160 /******************* Bit definition for CAN_F5R1 register *******************/
3161 #define CAN_F5R1_FB0_Pos (0U)
3162 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3163 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3164 #define CAN_F5R1_FB1_Pos (1U)
3165 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3166 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3167 #define CAN_F5R1_FB2_Pos (2U)
3168 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3169 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3170 #define CAN_F5R1_FB3_Pos (3U)
3171 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3172 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3173 #define CAN_F5R1_FB4_Pos (4U)
3174 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3175 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3176 #define CAN_F5R1_FB5_Pos (5U)
3177 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3178 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3179 #define CAN_F5R1_FB6_Pos (6U)
3180 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3181 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3182 #define CAN_F5R1_FB7_Pos (7U)
3183 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3184 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3185 #define CAN_F5R1_FB8_Pos (8U)
3186 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3187 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3188 #define CAN_F5R1_FB9_Pos (9U)
3189 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3190 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3191 #define CAN_F5R1_FB10_Pos (10U)
3192 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3193 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3194 #define CAN_F5R1_FB11_Pos (11U)
3195 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3196 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3197 #define CAN_F5R1_FB12_Pos (12U)
3198 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3199 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3200 #define CAN_F5R1_FB13_Pos (13U)
3201 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3202 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3203 #define CAN_F5R1_FB14_Pos (14U)
3204 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3205 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3206 #define CAN_F5R1_FB15_Pos (15U)
3207 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3208 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3209 #define CAN_F5R1_FB16_Pos (16U)
3210 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3211 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3212 #define CAN_F5R1_FB17_Pos (17U)
3213 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3214 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3215 #define CAN_F5R1_FB18_Pos (18U)
3216 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3217 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3218 #define CAN_F5R1_FB19_Pos (19U)
3219 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3220 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3221 #define CAN_F5R1_FB20_Pos (20U)
3222 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3223 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3224 #define CAN_F5R1_FB21_Pos (21U)
3225 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3226 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3227 #define CAN_F5R1_FB22_Pos (22U)
3228 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3229 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3230 #define CAN_F5R1_FB23_Pos (23U)
3231 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3232 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3233 #define CAN_F5R1_FB24_Pos (24U)
3234 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3235 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3236 #define CAN_F5R1_FB25_Pos (25U)
3237 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3238 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3239 #define CAN_F5R1_FB26_Pos (26U)
3240 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3241 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3242 #define CAN_F5R1_FB27_Pos (27U)
3243 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3244 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3245 #define CAN_F5R1_FB28_Pos (28U)
3246 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3247 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3248 #define CAN_F5R1_FB29_Pos (29U)
3249 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3250 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3251 #define CAN_F5R1_FB30_Pos (30U)
3252 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3253 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3254 #define CAN_F5R1_FB31_Pos (31U)
3255 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3256 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3258 /******************* Bit definition for CAN_F6R1 register *******************/
3259 #define CAN_F6R1_FB0_Pos (0U)
3260 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3261 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3262 #define CAN_F6R1_FB1_Pos (1U)
3263 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3264 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3265 #define CAN_F6R1_FB2_Pos (2U)
3266 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3267 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3268 #define CAN_F6R1_FB3_Pos (3U)
3269 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3270 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3271 #define CAN_F6R1_FB4_Pos (4U)
3272 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3273 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3274 #define CAN_F6R1_FB5_Pos (5U)
3275 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3276 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3277 #define CAN_F6R1_FB6_Pos (6U)
3278 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3279 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3280 #define CAN_F6R1_FB7_Pos (7U)
3281 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3282 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3283 #define CAN_F6R1_FB8_Pos (8U)
3284 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3285 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3286 #define CAN_F6R1_FB9_Pos (9U)
3287 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3288 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3289 #define CAN_F6R1_FB10_Pos (10U)
3290 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3291 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3292 #define CAN_F6R1_FB11_Pos (11U)
3293 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3294 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3295 #define CAN_F6R1_FB12_Pos (12U)
3296 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3297 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3298 #define CAN_F6R1_FB13_Pos (13U)
3299 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3300 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3301 #define CAN_F6R1_FB14_Pos (14U)
3302 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3303 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3304 #define CAN_F6R1_FB15_Pos (15U)
3305 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3306 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3307 #define CAN_F6R1_FB16_Pos (16U)
3308 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3309 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3310 #define CAN_F6R1_FB17_Pos (17U)
3311 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3312 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3313 #define CAN_F6R1_FB18_Pos (18U)
3314 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3315 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3316 #define CAN_F6R1_FB19_Pos (19U)
3317 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3318 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3319 #define CAN_F6R1_FB20_Pos (20U)
3320 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3321 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3322 #define CAN_F6R1_FB21_Pos (21U)
3323 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3324 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3325 #define CAN_F6R1_FB22_Pos (22U)
3326 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3327 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3328 #define CAN_F6R1_FB23_Pos (23U)
3329 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3330 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3331 #define CAN_F6R1_FB24_Pos (24U)
3332 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3333 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3334 #define CAN_F6R1_FB25_Pos (25U)
3335 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3336 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3337 #define CAN_F6R1_FB26_Pos (26U)
3338 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3339 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3340 #define CAN_F6R1_FB27_Pos (27U)
3341 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3342 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3343 #define CAN_F6R1_FB28_Pos (28U)
3344 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3345 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3346 #define CAN_F6R1_FB29_Pos (29U)
3347 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3348 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3349 #define CAN_F6R1_FB30_Pos (30U)
3350 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3351 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3352 #define CAN_F6R1_FB31_Pos (31U)
3353 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3354 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3356 /******************* Bit definition for CAN_F7R1 register *******************/
3357 #define CAN_F7R1_FB0_Pos (0U)
3358 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3359 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3360 #define CAN_F7R1_FB1_Pos (1U)
3361 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3362 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3363 #define CAN_F7R1_FB2_Pos (2U)
3364 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3365 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3366 #define CAN_F7R1_FB3_Pos (3U)
3367 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3368 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3369 #define CAN_F7R1_FB4_Pos (4U)
3370 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3371 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3372 #define CAN_F7R1_FB5_Pos (5U)
3373 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3374 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3375 #define CAN_F7R1_FB6_Pos (6U)
3376 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3377 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3378 #define CAN_F7R1_FB7_Pos (7U)
3379 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3380 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3381 #define CAN_F7R1_FB8_Pos (8U)
3382 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3383 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3384 #define CAN_F7R1_FB9_Pos (9U)
3385 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3386 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3387 #define CAN_F7R1_FB10_Pos (10U)
3388 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3389 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3390 #define CAN_F7R1_FB11_Pos (11U)
3391 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3392 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3393 #define CAN_F7R1_FB12_Pos (12U)
3394 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3395 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3396 #define CAN_F7R1_FB13_Pos (13U)
3397 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3398 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3399 #define CAN_F7R1_FB14_Pos (14U)
3400 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3401 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3402 #define CAN_F7R1_FB15_Pos (15U)
3403 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3404 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3405 #define CAN_F7R1_FB16_Pos (16U)
3406 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3407 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3408 #define CAN_F7R1_FB17_Pos (17U)
3409 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3410 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3411 #define CAN_F7R1_FB18_Pos (18U)
3412 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3413 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3414 #define CAN_F7R1_FB19_Pos (19U)
3415 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3416 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3417 #define CAN_F7R1_FB20_Pos (20U)
3418 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3419 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3420 #define CAN_F7R1_FB21_Pos (21U)
3421 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3422 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3423 #define CAN_F7R1_FB22_Pos (22U)
3424 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3425 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3426 #define CAN_F7R1_FB23_Pos (23U)
3427 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3428 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3429 #define CAN_F7R1_FB24_Pos (24U)
3430 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3431 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3432 #define CAN_F7R1_FB25_Pos (25U)
3433 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3434 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3435 #define CAN_F7R1_FB26_Pos (26U)
3436 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3437 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3438 #define CAN_F7R1_FB27_Pos (27U)
3439 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3440 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3441 #define CAN_F7R1_FB28_Pos (28U)
3442 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3443 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3444 #define CAN_F7R1_FB29_Pos (29U)
3445 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3446 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3447 #define CAN_F7R1_FB30_Pos (30U)
3448 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3449 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3450 #define CAN_F7R1_FB31_Pos (31U)
3451 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3452 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3454 /******************* Bit definition for CAN_F8R1 register *******************/
3455 #define CAN_F8R1_FB0_Pos (0U)
3456 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3457 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3458 #define CAN_F8R1_FB1_Pos (1U)
3459 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3460 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3461 #define CAN_F8R1_FB2_Pos (2U)
3462 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3463 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3464 #define CAN_F8R1_FB3_Pos (3U)
3465 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3466 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3467 #define CAN_F8R1_FB4_Pos (4U)
3468 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3469 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3470 #define CAN_F8R1_FB5_Pos (5U)
3471 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3472 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3473 #define CAN_F8R1_FB6_Pos (6U)
3474 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3475 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3476 #define CAN_F8R1_FB7_Pos (7U)
3477 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3478 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3479 #define CAN_F8R1_FB8_Pos (8U)
3480 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3481 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3482 #define CAN_F8R1_FB9_Pos (9U)
3483 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3484 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3485 #define CAN_F8R1_FB10_Pos (10U)
3486 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3487 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3488 #define CAN_F8R1_FB11_Pos (11U)
3489 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3490 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3491 #define CAN_F8R1_FB12_Pos (12U)
3492 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3493 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3494 #define CAN_F8R1_FB13_Pos (13U)
3495 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3496 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3497 #define CAN_F8R1_FB14_Pos (14U)
3498 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3499 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3500 #define CAN_F8R1_FB15_Pos (15U)
3501 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3502 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3503 #define CAN_F8R1_FB16_Pos (16U)
3504 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3505 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3506 #define CAN_F8R1_FB17_Pos (17U)
3507 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3508 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3509 #define CAN_F8R1_FB18_Pos (18U)
3510 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3511 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3512 #define CAN_F8R1_FB19_Pos (19U)
3513 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3514 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3515 #define CAN_F8R1_FB20_Pos (20U)
3516 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3517 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3518 #define CAN_F8R1_FB21_Pos (21U)
3519 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3520 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3521 #define CAN_F8R1_FB22_Pos (22U)
3522 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3523 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3524 #define CAN_F8R1_FB23_Pos (23U)
3525 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3526 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3527 #define CAN_F8R1_FB24_Pos (24U)
3528 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3529 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3530 #define CAN_F8R1_FB25_Pos (25U)
3531 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3532 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3533 #define CAN_F8R1_FB26_Pos (26U)
3534 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3535 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3536 #define CAN_F8R1_FB27_Pos (27U)
3537 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3538 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3539 #define CAN_F8R1_FB28_Pos (28U)
3540 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3541 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3542 #define CAN_F8R1_FB29_Pos (29U)
3543 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3544 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3545 #define CAN_F8R1_FB30_Pos (30U)
3546 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3547 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3548 #define CAN_F8R1_FB31_Pos (31U)
3549 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3550 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3552 /******************* Bit definition for CAN_F9R1 register *******************/
3553 #define CAN_F9R1_FB0_Pos (0U)
3554 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3555 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3556 #define CAN_F9R1_FB1_Pos (1U)
3557 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3558 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3559 #define CAN_F9R1_FB2_Pos (2U)
3560 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3561 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3562 #define CAN_F9R1_FB3_Pos (3U)
3563 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3564 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3565 #define CAN_F9R1_FB4_Pos (4U)
3566 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3567 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3568 #define CAN_F9R1_FB5_Pos (5U)
3569 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3570 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3571 #define CAN_F9R1_FB6_Pos (6U)
3572 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3573 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3574 #define CAN_F9R1_FB7_Pos (7U)
3575 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3576 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3577 #define CAN_F9R1_FB8_Pos (8U)
3578 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3579 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3580 #define CAN_F9R1_FB9_Pos (9U)
3581 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3582 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3583 #define CAN_F9R1_FB10_Pos (10U)
3584 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3585 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3586 #define CAN_F9R1_FB11_Pos (11U)
3587 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3588 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3589 #define CAN_F9R1_FB12_Pos (12U)
3590 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3591 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3592 #define CAN_F9R1_FB13_Pos (13U)
3593 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3594 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3595 #define CAN_F9R1_FB14_Pos (14U)
3596 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3597 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3598 #define CAN_F9R1_FB15_Pos (15U)
3599 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3600 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3601 #define CAN_F9R1_FB16_Pos (16U)
3602 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3603 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3604 #define CAN_F9R1_FB17_Pos (17U)
3605 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3606 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3607 #define CAN_F9R1_FB18_Pos (18U)
3608 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3609 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3610 #define CAN_F9R1_FB19_Pos (19U)
3611 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3612 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3613 #define CAN_F9R1_FB20_Pos (20U)
3614 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3615 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3616 #define CAN_F9R1_FB21_Pos (21U)
3617 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3618 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3619 #define CAN_F9R1_FB22_Pos (22U)
3620 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3621 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3622 #define CAN_F9R1_FB23_Pos (23U)
3623 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3624 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3625 #define CAN_F9R1_FB24_Pos (24U)
3626 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3627 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3628 #define CAN_F9R1_FB25_Pos (25U)
3629 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3630 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3631 #define CAN_F9R1_FB26_Pos (26U)
3632 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3633 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3634 #define CAN_F9R1_FB27_Pos (27U)
3635 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3636 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3637 #define CAN_F9R1_FB28_Pos (28U)
3638 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3639 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3640 #define CAN_F9R1_FB29_Pos (29U)
3641 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3642 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3643 #define CAN_F9R1_FB30_Pos (30U)
3644 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3645 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3646 #define CAN_F9R1_FB31_Pos (31U)
3647 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3648 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3650 /******************* Bit definition for CAN_F10R1 register ******************/
3651 #define CAN_F10R1_FB0_Pos (0U)
3652 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3653 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3654 #define CAN_F10R1_FB1_Pos (1U)
3655 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3656 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3657 #define CAN_F10R1_FB2_Pos (2U)
3658 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3659 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3660 #define CAN_F10R1_FB3_Pos (3U)
3661 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3662 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3663 #define CAN_F10R1_FB4_Pos (4U)
3664 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3665 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3666 #define CAN_F10R1_FB5_Pos (5U)
3667 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3668 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3669 #define CAN_F10R1_FB6_Pos (6U)
3670 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3671 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3672 #define CAN_F10R1_FB7_Pos (7U)
3673 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3674 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3675 #define CAN_F10R1_FB8_Pos (8U)
3676 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3677 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3678 #define CAN_F10R1_FB9_Pos (9U)
3679 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3680 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3681 #define CAN_F10R1_FB10_Pos (10U)
3682 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3683 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3684 #define CAN_F10R1_FB11_Pos (11U)
3685 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3686 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3687 #define CAN_F10R1_FB12_Pos (12U)
3688 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3689 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3690 #define CAN_F10R1_FB13_Pos (13U)
3691 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3692 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3693 #define CAN_F10R1_FB14_Pos (14U)
3694 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3695 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3696 #define CAN_F10R1_FB15_Pos (15U)
3697 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3698 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3699 #define CAN_F10R1_FB16_Pos (16U)
3700 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3701 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3702 #define CAN_F10R1_FB17_Pos (17U)
3703 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3704 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3705 #define CAN_F10R1_FB18_Pos (18U)
3706 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3707 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3708 #define CAN_F10R1_FB19_Pos (19U)
3709 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3710 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3711 #define CAN_F10R1_FB20_Pos (20U)
3712 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3713 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3714 #define CAN_F10R1_FB21_Pos (21U)
3715 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3716 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3717 #define CAN_F10R1_FB22_Pos (22U)
3718 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3719 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3720 #define CAN_F10R1_FB23_Pos (23U)
3721 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3722 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3723 #define CAN_F10R1_FB24_Pos (24U)
3724 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3725 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3726 #define CAN_F10R1_FB25_Pos (25U)
3727 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3728 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3729 #define CAN_F10R1_FB26_Pos (26U)
3730 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3731 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3732 #define CAN_F10R1_FB27_Pos (27U)
3733 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3734 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3735 #define CAN_F10R1_FB28_Pos (28U)
3736 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3737 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3738 #define CAN_F10R1_FB29_Pos (29U)
3739 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3740 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3741 #define CAN_F10R1_FB30_Pos (30U)
3742 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3743 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3744 #define CAN_F10R1_FB31_Pos (31U)
3745 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3746 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3748 /******************* Bit definition for CAN_F11R1 register ******************/
3749 #define CAN_F11R1_FB0_Pos (0U)
3750 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3751 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3752 #define CAN_F11R1_FB1_Pos (1U)
3753 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3754 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3755 #define CAN_F11R1_FB2_Pos (2U)
3756 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3757 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3758 #define CAN_F11R1_FB3_Pos (3U)
3759 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3760 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3761 #define CAN_F11R1_FB4_Pos (4U)
3762 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3763 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3764 #define CAN_F11R1_FB5_Pos (5U)
3765 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3766 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3767 #define CAN_F11R1_FB6_Pos (6U)
3768 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3769 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3770 #define CAN_F11R1_FB7_Pos (7U)
3771 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3772 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3773 #define CAN_F11R1_FB8_Pos (8U)
3774 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3775 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3776 #define CAN_F11R1_FB9_Pos (9U)
3777 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3778 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3779 #define CAN_F11R1_FB10_Pos (10U)
3780 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3781 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3782 #define CAN_F11R1_FB11_Pos (11U)
3783 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3784 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3785 #define CAN_F11R1_FB12_Pos (12U)
3786 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3787 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3788 #define CAN_F11R1_FB13_Pos (13U)
3789 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3790 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3791 #define CAN_F11R1_FB14_Pos (14U)
3792 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3793 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3794 #define CAN_F11R1_FB15_Pos (15U)
3795 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3796 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3797 #define CAN_F11R1_FB16_Pos (16U)
3798 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3799 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3800 #define CAN_F11R1_FB17_Pos (17U)
3801 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3802 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3803 #define CAN_F11R1_FB18_Pos (18U)
3804 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3805 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3806 #define CAN_F11R1_FB19_Pos (19U)
3807 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3808 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3809 #define CAN_F11R1_FB20_Pos (20U)
3810 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3811 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3812 #define CAN_F11R1_FB21_Pos (21U)
3813 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3814 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3815 #define CAN_F11R1_FB22_Pos (22U)
3816 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3817 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3818 #define CAN_F11R1_FB23_Pos (23U)
3819 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3820 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3821 #define CAN_F11R1_FB24_Pos (24U)
3822 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3823 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3824 #define CAN_F11R1_FB25_Pos (25U)
3825 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3826 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3827 #define CAN_F11R1_FB26_Pos (26U)
3828 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3829 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3830 #define CAN_F11R1_FB27_Pos (27U)
3831 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3832 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3833 #define CAN_F11R1_FB28_Pos (28U)
3834 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3835 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3836 #define CAN_F11R1_FB29_Pos (29U)
3837 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3838 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3839 #define CAN_F11R1_FB30_Pos (30U)
3840 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3841 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3842 #define CAN_F11R1_FB31_Pos (31U)
3843 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3844 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3846 /******************* Bit definition for CAN_F12R1 register ******************/
3847 #define CAN_F12R1_FB0_Pos (0U)
3848 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3849 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3850 #define CAN_F12R1_FB1_Pos (1U)
3851 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3852 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3853 #define CAN_F12R1_FB2_Pos (2U)
3854 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3855 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3856 #define CAN_F12R1_FB3_Pos (3U)
3857 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3858 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3859 #define CAN_F12R1_FB4_Pos (4U)
3860 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3861 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3862 #define CAN_F12R1_FB5_Pos (5U)
3863 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3864 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3865 #define CAN_F12R1_FB6_Pos (6U)
3866 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3867 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3868 #define CAN_F12R1_FB7_Pos (7U)
3869 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3870 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3871 #define CAN_F12R1_FB8_Pos (8U)
3872 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3873 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3874 #define CAN_F12R1_FB9_Pos (9U)
3875 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3876 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3877 #define CAN_F12R1_FB10_Pos (10U)
3878 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3879 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3880 #define CAN_F12R1_FB11_Pos (11U)
3881 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3882 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3883 #define CAN_F12R1_FB12_Pos (12U)
3884 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3885 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3886 #define CAN_F12R1_FB13_Pos (13U)
3887 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3888 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3889 #define CAN_F12R1_FB14_Pos (14U)
3890 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3891 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3892 #define CAN_F12R1_FB15_Pos (15U)
3893 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3894 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3895 #define CAN_F12R1_FB16_Pos (16U)
3896 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3897 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3898 #define CAN_F12R1_FB17_Pos (17U)
3899 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3900 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3901 #define CAN_F12R1_FB18_Pos (18U)
3902 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3903 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3904 #define CAN_F12R1_FB19_Pos (19U)
3905 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3906 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3907 #define CAN_F12R1_FB20_Pos (20U)
3908 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3909 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3910 #define CAN_F12R1_FB21_Pos (21U)
3911 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3912 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3913 #define CAN_F12R1_FB22_Pos (22U)
3914 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3915 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3916 #define CAN_F12R1_FB23_Pos (23U)
3917 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3918 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3919 #define CAN_F12R1_FB24_Pos (24U)
3920 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3921 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3922 #define CAN_F12R1_FB25_Pos (25U)
3923 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3924 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3925 #define CAN_F12R1_FB26_Pos (26U)
3926 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3927 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3928 #define CAN_F12R1_FB27_Pos (27U)
3929 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3930 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3931 #define CAN_F12R1_FB28_Pos (28U)
3932 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3933 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3934 #define CAN_F12R1_FB29_Pos (29U)
3935 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3936 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3937 #define CAN_F12R1_FB30_Pos (30U)
3938 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3939 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3940 #define CAN_F12R1_FB31_Pos (31U)
3941 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3942 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3944 /******************* Bit definition for CAN_F13R1 register ******************/
3945 #define CAN_F13R1_FB0_Pos (0U)
3946 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3947 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3948 #define CAN_F13R1_FB1_Pos (1U)
3949 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3950 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3951 #define CAN_F13R1_FB2_Pos (2U)
3952 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3953 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3954 #define CAN_F13R1_FB3_Pos (3U)
3955 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3956 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3957 #define CAN_F13R1_FB4_Pos (4U)
3958 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3959 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3960 #define CAN_F13R1_FB5_Pos (5U)
3961 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3962 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3963 #define CAN_F13R1_FB6_Pos (6U)
3964 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3965 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3966 #define CAN_F13R1_FB7_Pos (7U)
3967 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3968 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3969 #define CAN_F13R1_FB8_Pos (8U)
3970 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3971 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3972 #define CAN_F13R1_FB9_Pos (9U)
3973 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
3974 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
3975 #define CAN_F13R1_FB10_Pos (10U)
3976 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
3977 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
3978 #define CAN_F13R1_FB11_Pos (11U)
3979 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
3980 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
3981 #define CAN_F13R1_FB12_Pos (12U)
3982 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
3983 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
3984 #define CAN_F13R1_FB13_Pos (13U)
3985 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
3986 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
3987 #define CAN_F13R1_FB14_Pos (14U)
3988 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
3989 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
3990 #define CAN_F13R1_FB15_Pos (15U)
3991 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
3992 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
3993 #define CAN_F13R1_FB16_Pos (16U)
3994 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
3995 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
3996 #define CAN_F13R1_FB17_Pos (17U)
3997 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
3998 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
3999 #define CAN_F13R1_FB18_Pos (18U)
4000 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4001 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4002 #define CAN_F13R1_FB19_Pos (19U)
4003 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4004 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4005 #define CAN_F13R1_FB20_Pos (20U)
4006 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4007 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4008 #define CAN_F13R1_FB21_Pos (21U)
4009 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4010 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4011 #define CAN_F13R1_FB22_Pos (22U)
4012 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4013 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4014 #define CAN_F13R1_FB23_Pos (23U)
4015 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4016 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4017 #define CAN_F13R1_FB24_Pos (24U)
4018 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4019 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4020 #define CAN_F13R1_FB25_Pos (25U)
4021 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4022 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4023 #define CAN_F13R1_FB26_Pos (26U)
4024 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4025 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4026 #define CAN_F13R1_FB27_Pos (27U)
4027 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4028 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4029 #define CAN_F13R1_FB28_Pos (28U)
4030 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4031 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4032 #define CAN_F13R1_FB29_Pos (29U)
4033 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4034 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4035 #define CAN_F13R1_FB30_Pos (30U)
4036 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4037 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4038 #define CAN_F13R1_FB31_Pos (31U)
4039 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4040 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4042 /******************* Bit definition for CAN_F0R2 register *******************/
4043 #define CAN_F0R2_FB0_Pos (0U)
4044 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4045 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4046 #define CAN_F0R2_FB1_Pos (1U)
4047 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4048 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4049 #define CAN_F0R2_FB2_Pos (2U)
4050 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4051 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4052 #define CAN_F0R2_FB3_Pos (3U)
4053 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4054 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4055 #define CAN_F0R2_FB4_Pos (4U)
4056 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4057 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4058 #define CAN_F0R2_FB5_Pos (5U)
4059 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4060 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4061 #define CAN_F0R2_FB6_Pos (6U)
4062 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4063 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4064 #define CAN_F0R2_FB7_Pos (7U)
4065 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4066 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4067 #define CAN_F0R2_FB8_Pos (8U)
4068 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4069 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4070 #define CAN_F0R2_FB9_Pos (9U)
4071 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4072 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4073 #define CAN_F0R2_FB10_Pos (10U)
4074 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4075 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4076 #define CAN_F0R2_FB11_Pos (11U)
4077 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4078 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4079 #define CAN_F0R2_FB12_Pos (12U)
4080 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4081 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4082 #define CAN_F0R2_FB13_Pos (13U)
4083 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4084 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4085 #define CAN_F0R2_FB14_Pos (14U)
4086 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4087 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4088 #define CAN_F0R2_FB15_Pos (15U)
4089 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4090 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4091 #define CAN_F0R2_FB16_Pos (16U)
4092 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4093 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4094 #define CAN_F0R2_FB17_Pos (17U)
4095 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4096 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4097 #define CAN_F0R2_FB18_Pos (18U)
4098 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4099 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4100 #define CAN_F0R2_FB19_Pos (19U)
4101 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4102 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4103 #define CAN_F0R2_FB20_Pos (20U)
4104 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4105 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4106 #define CAN_F0R2_FB21_Pos (21U)
4107 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4108 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4109 #define CAN_F0R2_FB22_Pos (22U)
4110 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4111 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4112 #define CAN_F0R2_FB23_Pos (23U)
4113 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4114 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4115 #define CAN_F0R2_FB24_Pos (24U)
4116 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4117 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4118 #define CAN_F0R2_FB25_Pos (25U)
4119 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4120 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4121 #define CAN_F0R2_FB26_Pos (26U)
4122 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4123 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4124 #define CAN_F0R2_FB27_Pos (27U)
4125 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4126 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4127 #define CAN_F0R2_FB28_Pos (28U)
4128 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4129 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4130 #define CAN_F0R2_FB29_Pos (29U)
4131 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4132 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4133 #define CAN_F0R2_FB30_Pos (30U)
4134 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4135 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4136 #define CAN_F0R2_FB31_Pos (31U)
4137 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4138 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4140 /******************* Bit definition for CAN_F1R2 register *******************/
4141 #define CAN_F1R2_FB0_Pos (0U)
4142 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4143 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4144 #define CAN_F1R2_FB1_Pos (1U)
4145 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4146 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4147 #define CAN_F1R2_FB2_Pos (2U)
4148 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4149 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4150 #define CAN_F1R2_FB3_Pos (3U)
4151 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4152 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4153 #define CAN_F1R2_FB4_Pos (4U)
4154 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4155 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4156 #define CAN_F1R2_FB5_Pos (5U)
4157 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4158 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4159 #define CAN_F1R2_FB6_Pos (6U)
4160 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4161 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4162 #define CAN_F1R2_FB7_Pos (7U)
4163 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4164 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4165 #define CAN_F1R2_FB8_Pos (8U)
4166 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4167 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4168 #define CAN_F1R2_FB9_Pos (9U)
4169 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4170 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4171 #define CAN_F1R2_FB10_Pos (10U)
4172 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4173 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4174 #define CAN_F1R2_FB11_Pos (11U)
4175 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4176 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4177 #define CAN_F1R2_FB12_Pos (12U)
4178 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4179 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4180 #define CAN_F1R2_FB13_Pos (13U)
4181 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4182 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4183 #define CAN_F1R2_FB14_Pos (14U)
4184 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4185 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4186 #define CAN_F1R2_FB15_Pos (15U)
4187 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4188 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4189 #define CAN_F1R2_FB16_Pos (16U)
4190 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4191 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4192 #define CAN_F1R2_FB17_Pos (17U)
4193 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4194 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4195 #define CAN_F1R2_FB18_Pos (18U)
4196 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4197 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4198 #define CAN_F1R2_FB19_Pos (19U)
4199 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4200 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4201 #define CAN_F1R2_FB20_Pos (20U)
4202 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4203 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4204 #define CAN_F1R2_FB21_Pos (21U)
4205 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4206 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4207 #define CAN_F1R2_FB22_Pos (22U)
4208 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4209 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4210 #define CAN_F1R2_FB23_Pos (23U)
4211 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4212 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4213 #define CAN_F1R2_FB24_Pos (24U)
4214 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4215 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4216 #define CAN_F1R2_FB25_Pos (25U)
4217 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4218 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4219 #define CAN_F1R2_FB26_Pos (26U)
4220 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4221 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4222 #define CAN_F1R2_FB27_Pos (27U)
4223 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4224 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4225 #define CAN_F1R2_FB28_Pos (28U)
4226 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4227 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4228 #define CAN_F1R2_FB29_Pos (29U)
4229 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4230 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4231 #define CAN_F1R2_FB30_Pos (30U)
4232 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4233 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4234 #define CAN_F1R2_FB31_Pos (31U)
4235 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4236 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4238 /******************* Bit definition for CAN_F2R2 register *******************/
4239 #define CAN_F2R2_FB0_Pos (0U)
4240 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4241 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4242 #define CAN_F2R2_FB1_Pos (1U)
4243 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4244 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4245 #define CAN_F2R2_FB2_Pos (2U)
4246 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4247 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4248 #define CAN_F2R2_FB3_Pos (3U)
4249 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4250 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4251 #define CAN_F2R2_FB4_Pos (4U)
4252 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4253 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4254 #define CAN_F2R2_FB5_Pos (5U)
4255 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4256 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4257 #define CAN_F2R2_FB6_Pos (6U)
4258 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4259 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4260 #define CAN_F2R2_FB7_Pos (7U)
4261 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4262 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4263 #define CAN_F2R2_FB8_Pos (8U)
4264 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4265 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4266 #define CAN_F2R2_FB9_Pos (9U)
4267 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4268 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4269 #define CAN_F2R2_FB10_Pos (10U)
4270 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4271 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4272 #define CAN_F2R2_FB11_Pos (11U)
4273 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4274 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4275 #define CAN_F2R2_FB12_Pos (12U)
4276 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4277 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4278 #define CAN_F2R2_FB13_Pos (13U)
4279 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4280 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4281 #define CAN_F2R2_FB14_Pos (14U)
4282 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4283 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4284 #define CAN_F2R2_FB15_Pos (15U)
4285 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4286 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4287 #define CAN_F2R2_FB16_Pos (16U)
4288 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4289 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4290 #define CAN_F2R2_FB17_Pos (17U)
4291 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4292 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4293 #define CAN_F2R2_FB18_Pos (18U)
4294 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4295 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4296 #define CAN_F2R2_FB19_Pos (19U)
4297 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4298 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4299 #define CAN_F2R2_FB20_Pos (20U)
4300 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4301 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4302 #define CAN_F2R2_FB21_Pos (21U)
4303 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4304 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4305 #define CAN_F2R2_FB22_Pos (22U)
4306 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4307 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4308 #define CAN_F2R2_FB23_Pos (23U)
4309 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4310 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4311 #define CAN_F2R2_FB24_Pos (24U)
4312 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4313 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4314 #define CAN_F2R2_FB25_Pos (25U)
4315 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4316 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4317 #define CAN_F2R2_FB26_Pos (26U)
4318 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4319 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4320 #define CAN_F2R2_FB27_Pos (27U)
4321 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4322 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4323 #define CAN_F2R2_FB28_Pos (28U)
4324 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4325 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4326 #define CAN_F2R2_FB29_Pos (29U)
4327 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4328 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4329 #define CAN_F2R2_FB30_Pos (30U)
4330 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4331 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4332 #define CAN_F2R2_FB31_Pos (31U)
4333 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4334 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4336 /******************* Bit definition for CAN_F3R2 register *******************/
4337 #define CAN_F3R2_FB0_Pos (0U)
4338 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4339 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4340 #define CAN_F3R2_FB1_Pos (1U)
4341 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4342 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4343 #define CAN_F3R2_FB2_Pos (2U)
4344 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4345 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4346 #define CAN_F3R2_FB3_Pos (3U)
4347 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4348 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4349 #define CAN_F3R2_FB4_Pos (4U)
4350 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4351 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4352 #define CAN_F3R2_FB5_Pos (5U)
4353 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4354 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4355 #define CAN_F3R2_FB6_Pos (6U)
4356 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4357 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4358 #define CAN_F3R2_FB7_Pos (7U)
4359 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4360 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4361 #define CAN_F3R2_FB8_Pos (8U)
4362 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4363 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4364 #define CAN_F3R2_FB9_Pos (9U)
4365 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4366 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4367 #define CAN_F3R2_FB10_Pos (10U)
4368 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4369 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4370 #define CAN_F3R2_FB11_Pos (11U)
4371 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4372 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4373 #define CAN_F3R2_FB12_Pos (12U)
4374 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4375 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4376 #define CAN_F3R2_FB13_Pos (13U)
4377 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4378 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4379 #define CAN_F3R2_FB14_Pos (14U)
4380 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4381 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4382 #define CAN_F3R2_FB15_Pos (15U)
4383 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4384 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4385 #define CAN_F3R2_FB16_Pos (16U)
4386 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4387 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4388 #define CAN_F3R2_FB17_Pos (17U)
4389 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4390 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4391 #define CAN_F3R2_FB18_Pos (18U)
4392 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4393 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4394 #define CAN_F3R2_FB19_Pos (19U)
4395 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4396 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4397 #define CAN_F3R2_FB20_Pos (20U)
4398 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4399 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4400 #define CAN_F3R2_FB21_Pos (21U)
4401 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4402 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4403 #define CAN_F3R2_FB22_Pos (22U)
4404 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4405 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4406 #define CAN_F3R2_FB23_Pos (23U)
4407 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4408 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4409 #define CAN_F3R2_FB24_Pos (24U)
4410 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4411 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4412 #define CAN_F3R2_FB25_Pos (25U)
4413 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4414 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4415 #define CAN_F3R2_FB26_Pos (26U)
4416 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4417 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4418 #define CAN_F3R2_FB27_Pos (27U)
4419 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4420 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4421 #define CAN_F3R2_FB28_Pos (28U)
4422 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4423 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4424 #define CAN_F3R2_FB29_Pos (29U)
4425 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4426 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4427 #define CAN_F3R2_FB30_Pos (30U)
4428 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4429 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4430 #define CAN_F3R2_FB31_Pos (31U)
4431 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4432 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4434 /******************* Bit definition for CAN_F4R2 register *******************/
4435 #define CAN_F4R2_FB0_Pos (0U)
4436 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4437 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4438 #define CAN_F4R2_FB1_Pos (1U)
4439 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4440 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4441 #define CAN_F4R2_FB2_Pos (2U)
4442 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4443 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4444 #define CAN_F4R2_FB3_Pos (3U)
4445 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4446 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4447 #define CAN_F4R2_FB4_Pos (4U)
4448 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4449 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4450 #define CAN_F4R2_FB5_Pos (5U)
4451 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4452 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4453 #define CAN_F4R2_FB6_Pos (6U)
4454 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4455 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4456 #define CAN_F4R2_FB7_Pos (7U)
4457 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4458 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4459 #define CAN_F4R2_FB8_Pos (8U)
4460 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4461 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4462 #define CAN_F4R2_FB9_Pos (9U)
4463 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4464 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4465 #define CAN_F4R2_FB10_Pos (10U)
4466 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4467 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4468 #define CAN_F4R2_FB11_Pos (11U)
4469 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4470 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4471 #define CAN_F4R2_FB12_Pos (12U)
4472 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4473 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4474 #define CAN_F4R2_FB13_Pos (13U)
4475 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4476 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4477 #define CAN_F4R2_FB14_Pos (14U)
4478 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4479 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4480 #define CAN_F4R2_FB15_Pos (15U)
4481 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4482 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4483 #define CAN_F4R2_FB16_Pos (16U)
4484 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4485 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4486 #define CAN_F4R2_FB17_Pos (17U)
4487 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4488 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4489 #define CAN_F4R2_FB18_Pos (18U)
4490 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4491 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4492 #define CAN_F4R2_FB19_Pos (19U)
4493 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4494 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4495 #define CAN_F4R2_FB20_Pos (20U)
4496 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4497 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4498 #define CAN_F4R2_FB21_Pos (21U)
4499 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4500 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4501 #define CAN_F4R2_FB22_Pos (22U)
4502 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4503 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4504 #define CAN_F4R2_FB23_Pos (23U)
4505 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4506 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4507 #define CAN_F4R2_FB24_Pos (24U)
4508 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4509 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4510 #define CAN_F4R2_FB25_Pos (25U)
4511 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4512 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4513 #define CAN_F4R2_FB26_Pos (26U)
4514 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4515 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4516 #define CAN_F4R2_FB27_Pos (27U)
4517 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4518 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4519 #define CAN_F4R2_FB28_Pos (28U)
4520 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4521 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4522 #define CAN_F4R2_FB29_Pos (29U)
4523 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4524 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4525 #define CAN_F4R2_FB30_Pos (30U)
4526 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4527 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4528 #define CAN_F4R2_FB31_Pos (31U)
4529 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4530 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4532 /******************* Bit definition for CAN_F5R2 register *******************/
4533 #define CAN_F5R2_FB0_Pos (0U)
4534 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4535 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4536 #define CAN_F5R2_FB1_Pos (1U)
4537 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4538 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4539 #define CAN_F5R2_FB2_Pos (2U)
4540 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4541 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4542 #define CAN_F5R2_FB3_Pos (3U)
4543 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4544 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4545 #define CAN_F5R2_FB4_Pos (4U)
4546 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4547 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4548 #define CAN_F5R2_FB5_Pos (5U)
4549 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4550 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4551 #define CAN_F5R2_FB6_Pos (6U)
4552 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4553 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4554 #define CAN_F5R2_FB7_Pos (7U)
4555 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4556 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4557 #define CAN_F5R2_FB8_Pos (8U)
4558 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4559 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4560 #define CAN_F5R2_FB9_Pos (9U)
4561 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4562 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4563 #define CAN_F5R2_FB10_Pos (10U)
4564 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4565 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4566 #define CAN_F5R2_FB11_Pos (11U)
4567 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4568 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4569 #define CAN_F5R2_FB12_Pos (12U)
4570 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4571 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4572 #define CAN_F5R2_FB13_Pos (13U)
4573 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4574 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4575 #define CAN_F5R2_FB14_Pos (14U)
4576 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4577 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4578 #define CAN_F5R2_FB15_Pos (15U)
4579 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4580 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4581 #define CAN_F5R2_FB16_Pos (16U)
4582 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4583 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4584 #define CAN_F5R2_FB17_Pos (17U)
4585 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4586 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4587 #define CAN_F5R2_FB18_Pos (18U)
4588 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4589 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4590 #define CAN_F5R2_FB19_Pos (19U)
4591 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4592 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4593 #define CAN_F5R2_FB20_Pos (20U)
4594 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4595 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4596 #define CAN_F5R2_FB21_Pos (21U)
4597 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4598 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4599 #define CAN_F5R2_FB22_Pos (22U)
4600 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4601 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4602 #define CAN_F5R2_FB23_Pos (23U)
4603 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4604 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4605 #define CAN_F5R2_FB24_Pos (24U)
4606 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4607 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4608 #define CAN_F5R2_FB25_Pos (25U)
4609 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4610 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4611 #define CAN_F5R2_FB26_Pos (26U)
4612 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4613 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4614 #define CAN_F5R2_FB27_Pos (27U)
4615 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4616 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4617 #define CAN_F5R2_FB28_Pos (28U)
4618 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4619 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4620 #define CAN_F5R2_FB29_Pos (29U)
4621 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4622 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4623 #define CAN_F5R2_FB30_Pos (30U)
4624 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4625 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4626 #define CAN_F5R2_FB31_Pos (31U)
4627 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4628 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4630 /******************* Bit definition for CAN_F6R2 register *******************/
4631 #define CAN_F6R2_FB0_Pos (0U)
4632 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4633 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4634 #define CAN_F6R2_FB1_Pos (1U)
4635 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4636 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4637 #define CAN_F6R2_FB2_Pos (2U)
4638 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4639 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4640 #define CAN_F6R2_FB3_Pos (3U)
4641 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4642 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4643 #define CAN_F6R2_FB4_Pos (4U)
4644 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4645 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4646 #define CAN_F6R2_FB5_Pos (5U)
4647 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4648 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4649 #define CAN_F6R2_FB6_Pos (6U)
4650 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4651 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4652 #define CAN_F6R2_FB7_Pos (7U)
4653 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4654 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4655 #define CAN_F6R2_FB8_Pos (8U)
4656 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4657 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4658 #define CAN_F6R2_FB9_Pos (9U)
4659 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4660 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4661 #define CAN_F6R2_FB10_Pos (10U)
4662 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4663 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4664 #define CAN_F6R2_FB11_Pos (11U)
4665 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4666 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4667 #define CAN_F6R2_FB12_Pos (12U)
4668 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4669 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4670 #define CAN_F6R2_FB13_Pos (13U)
4671 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4672 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4673 #define CAN_F6R2_FB14_Pos (14U)
4674 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4675 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4676 #define CAN_F6R2_FB15_Pos (15U)
4677 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4678 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4679 #define CAN_F6R2_FB16_Pos (16U)
4680 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4681 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4682 #define CAN_F6R2_FB17_Pos (17U)
4683 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4684 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4685 #define CAN_F6R2_FB18_Pos (18U)
4686 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4687 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4688 #define CAN_F6R2_FB19_Pos (19U)
4689 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4690 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4691 #define CAN_F6R2_FB20_Pos (20U)
4692 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4693 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4694 #define CAN_F6R2_FB21_Pos (21U)
4695 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4696 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4697 #define CAN_F6R2_FB22_Pos (22U)
4698 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4699 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4700 #define CAN_F6R2_FB23_Pos (23U)
4701 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4702 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4703 #define CAN_F6R2_FB24_Pos (24U)
4704 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4705 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4706 #define CAN_F6R2_FB25_Pos (25U)
4707 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4708 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4709 #define CAN_F6R2_FB26_Pos (26U)
4710 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4711 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4712 #define CAN_F6R2_FB27_Pos (27U)
4713 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4714 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4715 #define CAN_F6R2_FB28_Pos (28U)
4716 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4717 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4718 #define CAN_F6R2_FB29_Pos (29U)
4719 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4720 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4721 #define CAN_F6R2_FB30_Pos (30U)
4722 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4723 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4724 #define CAN_F6R2_FB31_Pos (31U)
4725 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4726 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4728 /******************* Bit definition for CAN_F7R2 register *******************/
4729 #define CAN_F7R2_FB0_Pos (0U)
4730 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4731 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4732 #define CAN_F7R2_FB1_Pos (1U)
4733 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4734 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4735 #define CAN_F7R2_FB2_Pos (2U)
4736 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4737 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4738 #define CAN_F7R2_FB3_Pos (3U)
4739 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4740 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4741 #define CAN_F7R2_FB4_Pos (4U)
4742 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4743 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4744 #define CAN_F7R2_FB5_Pos (5U)
4745 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4746 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4747 #define CAN_F7R2_FB6_Pos (6U)
4748 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4749 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4750 #define CAN_F7R2_FB7_Pos (7U)
4751 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4752 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4753 #define CAN_F7R2_FB8_Pos (8U)
4754 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4755 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4756 #define CAN_F7R2_FB9_Pos (9U)
4757 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4758 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4759 #define CAN_F7R2_FB10_Pos (10U)
4760 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4761 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4762 #define CAN_F7R2_FB11_Pos (11U)
4763 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4764 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4765 #define CAN_F7R2_FB12_Pos (12U)
4766 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4767 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4768 #define CAN_F7R2_FB13_Pos (13U)
4769 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4770 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4771 #define CAN_F7R2_FB14_Pos (14U)
4772 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4773 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4774 #define CAN_F7R2_FB15_Pos (15U)
4775 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4776 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4777 #define CAN_F7R2_FB16_Pos (16U)
4778 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4779 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4780 #define CAN_F7R2_FB17_Pos (17U)
4781 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4782 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4783 #define CAN_F7R2_FB18_Pos (18U)
4784 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4785 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4786 #define CAN_F7R2_FB19_Pos (19U)
4787 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4788 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4789 #define CAN_F7R2_FB20_Pos (20U)
4790 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4791 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4792 #define CAN_F7R2_FB21_Pos (21U)
4793 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4794 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4795 #define CAN_F7R2_FB22_Pos (22U)
4796 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4797 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4798 #define CAN_F7R2_FB23_Pos (23U)
4799 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4800 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4801 #define CAN_F7R2_FB24_Pos (24U)
4802 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4803 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4804 #define CAN_F7R2_FB25_Pos (25U)
4805 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4806 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4807 #define CAN_F7R2_FB26_Pos (26U)
4808 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4809 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4810 #define CAN_F7R2_FB27_Pos (27U)
4811 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4812 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4813 #define CAN_F7R2_FB28_Pos (28U)
4814 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4815 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4816 #define CAN_F7R2_FB29_Pos (29U)
4817 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4818 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4819 #define CAN_F7R2_FB30_Pos (30U)
4820 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4821 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4822 #define CAN_F7R2_FB31_Pos (31U)
4823 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4824 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4826 /******************* Bit definition for CAN_F8R2 register *******************/
4827 #define CAN_F8R2_FB0_Pos (0U)
4828 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4829 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4830 #define CAN_F8R2_FB1_Pos (1U)
4831 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4832 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4833 #define CAN_F8R2_FB2_Pos (2U)
4834 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4835 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4836 #define CAN_F8R2_FB3_Pos (3U)
4837 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4838 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4839 #define CAN_F8R2_FB4_Pos (4U)
4840 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4841 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4842 #define CAN_F8R2_FB5_Pos (5U)
4843 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4844 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4845 #define CAN_F8R2_FB6_Pos (6U)
4846 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4847 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4848 #define CAN_F8R2_FB7_Pos (7U)
4849 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4850 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4851 #define CAN_F8R2_FB8_Pos (8U)
4852 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4853 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4854 #define CAN_F8R2_FB9_Pos (9U)
4855 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4856 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4857 #define CAN_F8R2_FB10_Pos (10U)
4858 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4859 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4860 #define CAN_F8R2_FB11_Pos (11U)
4861 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4862 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4863 #define CAN_F8R2_FB12_Pos (12U)
4864 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4865 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4866 #define CAN_F8R2_FB13_Pos (13U)
4867 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4868 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4869 #define CAN_F8R2_FB14_Pos (14U)
4870 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4871 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4872 #define CAN_F8R2_FB15_Pos (15U)
4873 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4874 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4875 #define CAN_F8R2_FB16_Pos (16U)
4876 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4877 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4878 #define CAN_F8R2_FB17_Pos (17U)
4879 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4880 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4881 #define CAN_F8R2_FB18_Pos (18U)
4882 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4883 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4884 #define CAN_F8R2_FB19_Pos (19U)
4885 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4886 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4887 #define CAN_F8R2_FB20_Pos (20U)
4888 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4889 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4890 #define CAN_F8R2_FB21_Pos (21U)
4891 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4892 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4893 #define CAN_F8R2_FB22_Pos (22U)
4894 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4895 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4896 #define CAN_F8R2_FB23_Pos (23U)
4897 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4898 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4899 #define CAN_F8R2_FB24_Pos (24U)
4900 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4901 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4902 #define CAN_F8R2_FB25_Pos (25U)
4903 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4904 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4905 #define CAN_F8R2_FB26_Pos (26U)
4906 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4907 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4908 #define CAN_F8R2_FB27_Pos (27U)
4909 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4910 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4911 #define CAN_F8R2_FB28_Pos (28U)
4912 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4913 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4914 #define CAN_F8R2_FB29_Pos (29U)
4915 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4916 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4917 #define CAN_F8R2_FB30_Pos (30U)
4918 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4919 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4920 #define CAN_F8R2_FB31_Pos (31U)
4921 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4922 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4924 /******************* Bit definition for CAN_F9R2 register *******************/
4925 #define CAN_F9R2_FB0_Pos (0U)
4926 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4927 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4928 #define CAN_F9R2_FB1_Pos (1U)
4929 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4930 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4931 #define CAN_F9R2_FB2_Pos (2U)
4932 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4933 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4934 #define CAN_F9R2_FB3_Pos (3U)
4935 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4936 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4937 #define CAN_F9R2_FB4_Pos (4U)
4938 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4939 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4940 #define CAN_F9R2_FB5_Pos (5U)
4941 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4942 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4943 #define CAN_F9R2_FB6_Pos (6U)
4944 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4945 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4946 #define CAN_F9R2_FB7_Pos (7U)
4947 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4948 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4949 #define CAN_F9R2_FB8_Pos (8U)
4950 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4951 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4952 #define CAN_F9R2_FB9_Pos (9U)
4953 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4954 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4955 #define CAN_F9R2_FB10_Pos (10U)
4956 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4957 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4958 #define CAN_F9R2_FB11_Pos (11U)
4959 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4960 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4961 #define CAN_F9R2_FB12_Pos (12U)
4962 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4963 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4964 #define CAN_F9R2_FB13_Pos (13U)
4965 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4966 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4967 #define CAN_F9R2_FB14_Pos (14U)
4968 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4969 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4970 #define CAN_F9R2_FB15_Pos (15U)
4971 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4972 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4973 #define CAN_F9R2_FB16_Pos (16U)
4974 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
4975 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
4976 #define CAN_F9R2_FB17_Pos (17U)
4977 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
4978 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
4979 #define CAN_F9R2_FB18_Pos (18U)
4980 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
4981 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
4982 #define CAN_F9R2_FB19_Pos (19U)
4983 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
4984 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
4985 #define CAN_F9R2_FB20_Pos (20U)
4986 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
4987 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
4988 #define CAN_F9R2_FB21_Pos (21U)
4989 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
4990 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
4991 #define CAN_F9R2_FB22_Pos (22U)
4992 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
4993 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
4994 #define CAN_F9R2_FB23_Pos (23U)
4995 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
4996 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
4997 #define CAN_F9R2_FB24_Pos (24U)
4998 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
4999 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5000 #define CAN_F9R2_FB25_Pos (25U)
5001 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5002 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5003 #define CAN_F9R2_FB26_Pos (26U)
5004 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5005 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5006 #define CAN_F9R2_FB27_Pos (27U)
5007 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5008 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5009 #define CAN_F9R2_FB28_Pos (28U)
5010 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5011 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5012 #define CAN_F9R2_FB29_Pos (29U)
5013 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5014 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5015 #define CAN_F9R2_FB30_Pos (30U)
5016 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5017 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5018 #define CAN_F9R2_FB31_Pos (31U)
5019 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5020 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5022 /******************* Bit definition for CAN_F10R2 register ******************/
5023 #define CAN_F10R2_FB0_Pos (0U)
5024 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5025 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5026 #define CAN_F10R2_FB1_Pos (1U)
5027 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5028 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5029 #define CAN_F10R2_FB2_Pos (2U)
5030 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5031 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5032 #define CAN_F10R2_FB3_Pos (3U)
5033 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5034 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5035 #define CAN_F10R2_FB4_Pos (4U)
5036 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5037 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5038 #define CAN_F10R2_FB5_Pos (5U)
5039 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5040 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5041 #define CAN_F10R2_FB6_Pos (6U)
5042 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5043 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5044 #define CAN_F10R2_FB7_Pos (7U)
5045 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5046 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5047 #define CAN_F10R2_FB8_Pos (8U)
5048 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5049 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5050 #define CAN_F10R2_FB9_Pos (9U)
5051 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5052 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5053 #define CAN_F10R2_FB10_Pos (10U)
5054 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5055 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5056 #define CAN_F10R2_FB11_Pos (11U)
5057 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5058 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5059 #define CAN_F10R2_FB12_Pos (12U)
5060 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5061 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5062 #define CAN_F10R2_FB13_Pos (13U)
5063 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5064 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5065 #define CAN_F10R2_FB14_Pos (14U)
5066 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5067 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5068 #define CAN_F10R2_FB15_Pos (15U)
5069 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5070 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5071 #define CAN_F10R2_FB16_Pos (16U)
5072 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5073 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5074 #define CAN_F10R2_FB17_Pos (17U)
5075 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5076 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5077 #define CAN_F10R2_FB18_Pos (18U)
5078 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5079 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5080 #define CAN_F10R2_FB19_Pos (19U)
5081 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5082 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5083 #define CAN_F10R2_FB20_Pos (20U)
5084 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5085 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5086 #define CAN_F10R2_FB21_Pos (21U)
5087 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5088 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5089 #define CAN_F10R2_FB22_Pos (22U)
5090 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5091 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5092 #define CAN_F10R2_FB23_Pos (23U)
5093 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5094 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5095 #define CAN_F10R2_FB24_Pos (24U)
5096 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5097 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5098 #define CAN_F10R2_FB25_Pos (25U)
5099 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5100 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5101 #define CAN_F10R2_FB26_Pos (26U)
5102 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5103 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5104 #define CAN_F10R2_FB27_Pos (27U)
5105 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5106 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5107 #define CAN_F10R2_FB28_Pos (28U)
5108 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5109 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5110 #define CAN_F10R2_FB29_Pos (29U)
5111 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5112 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5113 #define CAN_F10R2_FB30_Pos (30U)
5114 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5115 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5116 #define CAN_F10R2_FB31_Pos (31U)
5117 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5118 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5120 /******************* Bit definition for CAN_F11R2 register ******************/
5121 #define CAN_F11R2_FB0_Pos (0U)
5122 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5123 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5124 #define CAN_F11R2_FB1_Pos (1U)
5125 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5126 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5127 #define CAN_F11R2_FB2_Pos (2U)
5128 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5129 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5130 #define CAN_F11R2_FB3_Pos (3U)
5131 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5132 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5133 #define CAN_F11R2_FB4_Pos (4U)
5134 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5135 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5136 #define CAN_F11R2_FB5_Pos (5U)
5137 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5138 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5139 #define CAN_F11R2_FB6_Pos (6U)
5140 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5141 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5142 #define CAN_F11R2_FB7_Pos (7U)
5143 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5144 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5145 #define CAN_F11R2_FB8_Pos (8U)
5146 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5147 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5148 #define CAN_F11R2_FB9_Pos (9U)
5149 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5150 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5151 #define CAN_F11R2_FB10_Pos (10U)
5152 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5153 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5154 #define CAN_F11R2_FB11_Pos (11U)
5155 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5156 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5157 #define CAN_F11R2_FB12_Pos (12U)
5158 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5159 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5160 #define CAN_F11R2_FB13_Pos (13U)
5161 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5162 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5163 #define CAN_F11R2_FB14_Pos (14U)
5164 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5165 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5166 #define CAN_F11R2_FB15_Pos (15U)
5167 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5168 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5169 #define CAN_F11R2_FB16_Pos (16U)
5170 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5171 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5172 #define CAN_F11R2_FB17_Pos (17U)
5173 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5174 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5175 #define CAN_F11R2_FB18_Pos (18U)
5176 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5177 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5178 #define CAN_F11R2_FB19_Pos (19U)
5179 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5180 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5181 #define CAN_F11R2_FB20_Pos (20U)
5182 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5183 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5184 #define CAN_F11R2_FB21_Pos (21U)
5185 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5186 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5187 #define CAN_F11R2_FB22_Pos (22U)
5188 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5189 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5190 #define CAN_F11R2_FB23_Pos (23U)
5191 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5192 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5193 #define CAN_F11R2_FB24_Pos (24U)
5194 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5195 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5196 #define CAN_F11R2_FB25_Pos (25U)
5197 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5198 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5199 #define CAN_F11R2_FB26_Pos (26U)
5200 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5201 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5202 #define CAN_F11R2_FB27_Pos (27U)
5203 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5204 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5205 #define CAN_F11R2_FB28_Pos (28U)
5206 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5207 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5208 #define CAN_F11R2_FB29_Pos (29U)
5209 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5210 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5211 #define CAN_F11R2_FB30_Pos (30U)
5212 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5213 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5214 #define CAN_F11R2_FB31_Pos (31U)
5215 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5216 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5218 /******************* Bit definition for CAN_F12R2 register ******************/
5219 #define CAN_F12R2_FB0_Pos (0U)
5220 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5221 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5222 #define CAN_F12R2_FB1_Pos (1U)
5223 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5224 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5225 #define CAN_F12R2_FB2_Pos (2U)
5226 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5227 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5228 #define CAN_F12R2_FB3_Pos (3U)
5229 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5230 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5231 #define CAN_F12R2_FB4_Pos (4U)
5232 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5233 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5234 #define CAN_F12R2_FB5_Pos (5U)
5235 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5236 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5237 #define CAN_F12R2_FB6_Pos (6U)
5238 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5239 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5240 #define CAN_F12R2_FB7_Pos (7U)
5241 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5242 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5243 #define CAN_F12R2_FB8_Pos (8U)
5244 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5245 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5246 #define CAN_F12R2_FB9_Pos (9U)
5247 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5248 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5249 #define CAN_F12R2_FB10_Pos (10U)
5250 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5251 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5252 #define CAN_F12R2_FB11_Pos (11U)
5253 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5254 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5255 #define CAN_F12R2_FB12_Pos (12U)
5256 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5257 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5258 #define CAN_F12R2_FB13_Pos (13U)
5259 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5260 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5261 #define CAN_F12R2_FB14_Pos (14U)
5262 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5263 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5264 #define CAN_F12R2_FB15_Pos (15U)
5265 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5266 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5267 #define CAN_F12R2_FB16_Pos (16U)
5268 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5269 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5270 #define CAN_F12R2_FB17_Pos (17U)
5271 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5272 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5273 #define CAN_F12R2_FB18_Pos (18U)
5274 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5275 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5276 #define CAN_F12R2_FB19_Pos (19U)
5277 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5278 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5279 #define CAN_F12R2_FB20_Pos (20U)
5280 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5281 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5282 #define CAN_F12R2_FB21_Pos (21U)
5283 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5284 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5285 #define CAN_F12R2_FB22_Pos (22U)
5286 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5287 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5288 #define CAN_F12R2_FB23_Pos (23U)
5289 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5290 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5291 #define CAN_F12R2_FB24_Pos (24U)
5292 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5293 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5294 #define CAN_F12R2_FB25_Pos (25U)
5295 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5296 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5297 #define CAN_F12R2_FB26_Pos (26U)
5298 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5299 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5300 #define CAN_F12R2_FB27_Pos (27U)
5301 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5302 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5303 #define CAN_F12R2_FB28_Pos (28U)
5304 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5305 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5306 #define CAN_F12R2_FB29_Pos (29U)
5307 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5308 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5309 #define CAN_F12R2_FB30_Pos (30U)
5310 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5311 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5312 #define CAN_F12R2_FB31_Pos (31U)
5313 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5314 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5316 /******************* Bit definition for CAN_F13R2 register ******************/
5317 #define CAN_F13R2_FB0_Pos (0U)
5318 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5319 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5320 #define CAN_F13R2_FB1_Pos (1U)
5321 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5322 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5323 #define CAN_F13R2_FB2_Pos (2U)
5324 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5325 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5326 #define CAN_F13R2_FB3_Pos (3U)
5327 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5328 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5329 #define CAN_F13R2_FB4_Pos (4U)
5330 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5331 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5332 #define CAN_F13R2_FB5_Pos (5U)
5333 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5334 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5335 #define CAN_F13R2_FB6_Pos (6U)
5336 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5337 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5338 #define CAN_F13R2_FB7_Pos (7U)
5339 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5340 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5341 #define CAN_F13R2_FB8_Pos (8U)
5342 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5343 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5344 #define CAN_F13R2_FB9_Pos (9U)
5345 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5346 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5347 #define CAN_F13R2_FB10_Pos (10U)
5348 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5349 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5350 #define CAN_F13R2_FB11_Pos (11U)
5351 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5352 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5353 #define CAN_F13R2_FB12_Pos (12U)
5354 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5355 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5356 #define CAN_F13R2_FB13_Pos (13U)
5357 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5358 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5359 #define CAN_F13R2_FB14_Pos (14U)
5360 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5361 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5362 #define CAN_F13R2_FB15_Pos (15U)
5363 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5364 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5365 #define CAN_F13R2_FB16_Pos (16U)
5366 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5367 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5368 #define CAN_F13R2_FB17_Pos (17U)
5369 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5370 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5371 #define CAN_F13R2_FB18_Pos (18U)
5372 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5373 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5374 #define CAN_F13R2_FB19_Pos (19U)
5375 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5376 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5377 #define CAN_F13R2_FB20_Pos (20U)
5378 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5379 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5380 #define CAN_F13R2_FB21_Pos (21U)
5381 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5382 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5383 #define CAN_F13R2_FB22_Pos (22U)
5384 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5385 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5386 #define CAN_F13R2_FB23_Pos (23U)
5387 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5388 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5389 #define CAN_F13R2_FB24_Pos (24U)
5390 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5391 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5392 #define CAN_F13R2_FB25_Pos (25U)
5393 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5394 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5395 #define CAN_F13R2_FB26_Pos (26U)
5396 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5397 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5398 #define CAN_F13R2_FB27_Pos (27U)
5399 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5400 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5401 #define CAN_F13R2_FB28_Pos (28U)
5402 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5403 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5404 #define CAN_F13R2_FB29_Pos (29U)
5405 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5406 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5407 #define CAN_F13R2_FB30_Pos (30U)
5408 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5409 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5410 #define CAN_F13R2_FB31_Pos (31U)
5411 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5412 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5414 /******************************************************************************/
5415 /* */
5416 /* CRC calculation unit */
5417 /* */
5418 /******************************************************************************/
5419 /******************* Bit definition for CRC_DR register *********************/
5420 #define CRC_DR_DR_Pos (0U)
5421 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5422 #define CRC_DR_DR CRC_DR_DR_Msk
5425 /******************* Bit definition for CRC_IDR register ********************/
5426 #define CRC_IDR_IDR_Pos (0U)
5427 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5428 #define CRC_IDR_IDR CRC_IDR_IDR_Msk
5431 /******************** Bit definition for CRC_CR register ********************/
5432 #define CRC_CR_RESET_Pos (0U)
5433 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5434 #define CRC_CR_RESET CRC_CR_RESET_Msk
5436 /******************************************************************************/
5437 /* */
5438 /* Digital to Analog Converter */
5439 /* */
5440 /******************************************************************************/
5441 /*
5442  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5443  */
5444 #define DAC_CHANNEL2_SUPPORT
5445 /******************** Bit definition for DAC_CR register ********************/
5446 #define DAC_CR_EN1_Pos (0U)
5447 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5448 #define DAC_CR_EN1 DAC_CR_EN1_Msk
5449 #define DAC_CR_BOFF1_Pos (1U)
5450 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5451 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5452 #define DAC_CR_TEN1_Pos (2U)
5453 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5454 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5456 #define DAC_CR_TSEL1_Pos (3U)
5457 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5458 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5459 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5460 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5461 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5463 #define DAC_CR_WAVE1_Pos (6U)
5464 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5465 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5466 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5467 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5469 #define DAC_CR_MAMP1_Pos (8U)
5470 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5471 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5472 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5473 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5474 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5475 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5477 #define DAC_CR_DMAEN1_Pos (12U)
5478 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5479 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5480 #define DAC_CR_DMAUDRIE1_Pos (13U)
5481 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5482 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5483 #define DAC_CR_EN2_Pos (16U)
5484 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5485 #define DAC_CR_EN2 DAC_CR_EN2_Msk
5486 #define DAC_CR_BOFF2_Pos (17U)
5487 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5488 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5489 #define DAC_CR_TEN2_Pos (18U)
5490 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5491 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5493 #define DAC_CR_TSEL2_Pos (19U)
5494 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5495 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5496 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5497 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5498 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5500 #define DAC_CR_WAVE2_Pos (22U)
5501 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5502 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5503 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5504 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5506 #define DAC_CR_MAMP2_Pos (24U)
5507 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5508 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5509 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5510 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5511 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5512 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5514 #define DAC_CR_DMAEN2_Pos (28U)
5515 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5516 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5517 #define DAC_CR_DMAUDRIE2_Pos (29U)
5518 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5519 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5521 /***************** Bit definition for DAC_SWTRIGR register ******************/
5522 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5523 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5524 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5525 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5526 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5527 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5529 /***************** Bit definition for DAC_DHR12R1 register ******************/
5530 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5531 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5532 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5534 /***************** Bit definition for DAC_DHR12L1 register ******************/
5535 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5536 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5537 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5539 /****************** Bit definition for DAC_DHR8R1 register ******************/
5540 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5541 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5542 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5544 /***************** Bit definition for DAC_DHR12R2 register ******************/
5545 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5546 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5547 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5549 /***************** Bit definition for DAC_DHR12L2 register ******************/
5550 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5551 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5552 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5554 /****************** Bit definition for DAC_DHR8R2 register ******************/
5555 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5556 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5557 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5559 /***************** Bit definition for DAC_DHR12RD register ******************/
5560 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5561 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5562 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5563 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5564 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5565 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5567 /***************** Bit definition for DAC_DHR12LD register ******************/
5568 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5569 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5570 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5571 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5572 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5573 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5575 /****************** Bit definition for DAC_DHR8RD register ******************/
5576 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5577 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5578 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5579 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5580 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5581 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5583 /******************* Bit definition for DAC_DOR1 register *******************/
5584 #define DAC_DOR1_DACC1DOR_Pos (0U)
5585 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5586 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5588 /******************* Bit definition for DAC_DOR2 register *******************/
5589 #define DAC_DOR2_DACC2DOR_Pos (0U)
5590 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5591 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5593 /******************** Bit definition for DAC_SR register ********************/
5594 #define DAC_SR_DMAUDR1_Pos (13U)
5595 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5596 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5597 #define DAC_SR_DMAUDR2_Pos (29U)
5598 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5599 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5601 /******************************************************************************/
5602 /* */
5603 /* DCMI */
5604 /* */
5605 /******************************************************************************/
5606 /******************** Bits definition for DCMI_CR register ******************/
5607 #define DCMI_CR_CAPTURE_Pos (0U)
5608 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5609 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5610 #define DCMI_CR_CM_Pos (1U)
5611 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5612 #define DCMI_CR_CM DCMI_CR_CM_Msk
5613 #define DCMI_CR_CROP_Pos (2U)
5614 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5615 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5616 #define DCMI_CR_JPEG_Pos (3U)
5617 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5618 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5619 #define DCMI_CR_ESS_Pos (4U)
5620 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5621 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5622 #define DCMI_CR_PCKPOL_Pos (5U)
5623 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5624 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5625 #define DCMI_CR_HSPOL_Pos (6U)
5626 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5627 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5628 #define DCMI_CR_VSPOL_Pos (7U)
5629 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5630 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5631 #define DCMI_CR_FCRC_0 0x00000100U
5632 #define DCMI_CR_FCRC_1 0x00000200U
5633 #define DCMI_CR_EDM_0 0x00000400U
5634 #define DCMI_CR_EDM_1 0x00000800U
5635 #define DCMI_CR_CRE_Pos (12U)
5636 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
5637 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
5638 #define DCMI_CR_ENABLE_Pos (14U)
5639 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5640 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5641 
5642 /******************** Bits definition for DCMI_SR register ******************/
5643 #define DCMI_SR_HSYNC_Pos (0U)
5644 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5645 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5646 #define DCMI_SR_VSYNC_Pos (1U)
5647 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5648 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5649 #define DCMI_SR_FNE_Pos (2U)
5650 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5651 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
5652 
5653 /******************** Bits definition for DCMI_RIS register *****************/
5654 #define DCMI_RIS_FRAME_RIS_Pos (0U)
5655 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
5656 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5657 #define DCMI_RIS_OVR_RIS_Pos (1U)
5658 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
5659 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5660 #define DCMI_RIS_ERR_RIS_Pos (2U)
5661 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
5662 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5663 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
5664 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
5665 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5666 #define DCMI_RIS_LINE_RIS_Pos (4U)
5667 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
5668 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5669 /* Legacy defines */
5670 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5671 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5672 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5673 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5674 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5675 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5676 
5677 /******************** Bits definition for DCMI_IER register *****************/
5678 #define DCMI_IER_FRAME_IE_Pos (0U)
5679 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
5680 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5681 #define DCMI_IER_OVR_IE_Pos (1U)
5682 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
5683 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5684 #define DCMI_IER_ERR_IE_Pos (2U)
5685 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
5686 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5687 #define DCMI_IER_VSYNC_IE_Pos (3U)
5688 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
5689 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5690 #define DCMI_IER_LINE_IE_Pos (4U)
5691 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
5692 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5693 /* Legacy defines */
5694 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5695 
5696 /******************** Bits definition for DCMI_MIS register *****************/
5697 #define DCMI_MIS_FRAME_MIS_Pos (0U)
5698 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
5699 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5700 #define DCMI_MIS_OVR_MIS_Pos (1U)
5701 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
5702 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5703 #define DCMI_MIS_ERR_MIS_Pos (2U)
5704 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
5705 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5706 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
5707 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
5708 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5709 #define DCMI_MIS_LINE_MIS_Pos (4U)
5710 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
5711 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5712 
5713 /* Legacy defines */
5714 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5715 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5716 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5717 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5718 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5719 
5720 /******************** Bits definition for DCMI_ICR register *****************/
5721 #define DCMI_ICR_FRAME_ISC_Pos (0U)
5722 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
5723 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5724 #define DCMI_ICR_OVR_ISC_Pos (1U)
5725 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
5726 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5727 #define DCMI_ICR_ERR_ISC_Pos (2U)
5728 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
5729 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5730 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
5731 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
5732 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5733 #define DCMI_ICR_LINE_ISC_Pos (4U)
5734 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
5735 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5736 
5737 /* Legacy defines */
5738 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5739 
5740 /******************** Bits definition for DCMI_ESCR register ******************/
5741 #define DCMI_ESCR_FSC_Pos (0U)
5742 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
5743 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5744 #define DCMI_ESCR_LSC_Pos (8U)
5745 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
5746 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5747 #define DCMI_ESCR_LEC_Pos (16U)
5748 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
5749 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5750 #define DCMI_ESCR_FEC_Pos (24U)
5751 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
5752 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5753 
5754 /******************** Bits definition for DCMI_ESUR register ******************/
5755 #define DCMI_ESUR_FSU_Pos (0U)
5756 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
5757 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5758 #define DCMI_ESUR_LSU_Pos (8U)
5759 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
5760 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5761 #define DCMI_ESUR_LEU_Pos (16U)
5762 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
5763 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5764 #define DCMI_ESUR_FEU_Pos (24U)
5765 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
5766 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5767 
5768 /******************** Bits definition for DCMI_CWSTRT register ******************/
5769 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5770 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
5771 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5772 #define DCMI_CWSTRT_VST_Pos (16U)
5773 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
5774 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5775 
5776 /******************** Bits definition for DCMI_CWSIZE register ******************/
5777 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
5778 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
5779 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5780 #define DCMI_CWSIZE_VLINE_Pos (16U)
5781 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
5782 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5783 
5784 /******************** Bits definition for DCMI_DR register *********************/
5785 #define DCMI_DR_BYTE0_Pos (0U)
5786 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
5787 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5788 #define DCMI_DR_BYTE1_Pos (8U)
5789 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
5790 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5791 #define DCMI_DR_BYTE2_Pos (16U)
5792 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
5793 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5794 #define DCMI_DR_BYTE3_Pos (24U)
5795 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
5796 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5797 
5798 /******************************************************************************/
5799 /* */
5800 /* DMA Controller */
5801 /* */
5802 /******************************************************************************/
5803 /******************** Bits definition for DMA_SxCR register *****************/
5804 #define DMA_SxCR_CHSEL_Pos (25U)
5805 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
5806 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5807 #define DMA_SxCR_CHSEL_0 0x02000000U
5808 #define DMA_SxCR_CHSEL_1 0x04000000U
5809 #define DMA_SxCR_CHSEL_2 0x08000000U
5810 #define DMA_SxCR_MBURST_Pos (23U)
5811 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5812 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5813 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5814 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5815 #define DMA_SxCR_PBURST_Pos (21U)
5816 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5817 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5818 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5819 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5820 #define DMA_SxCR_CT_Pos (19U)
5821 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5822 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
5823 #define DMA_SxCR_DBM_Pos (18U)
5824 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5825 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5826 #define DMA_SxCR_PL_Pos (16U)
5827 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5828 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
5829 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5830 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5831 #define DMA_SxCR_PINCOS_Pos (15U)
5832 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5833 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5834 #define DMA_SxCR_MSIZE_Pos (13U)
5835 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5836 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5837 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5838 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
5839 #define DMA_SxCR_PSIZE_Pos (11U)
5840 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
5841 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5842 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
5843 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
5844 #define DMA_SxCR_MINC_Pos (10U)
5845 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
5846 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5847 #define DMA_SxCR_PINC_Pos (9U)
5848 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
5849 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5850 #define DMA_SxCR_CIRC_Pos (8U)
5851 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
5852 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5853 #define DMA_SxCR_DIR_Pos (6U)
5854 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
5855 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5856 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
5857 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
5858 #define DMA_SxCR_PFCTRL_Pos (5U)
5859 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
5860 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5861 #define DMA_SxCR_TCIE_Pos (4U)
5862 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
5863 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5864 #define DMA_SxCR_HTIE_Pos (3U)
5865 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
5866 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5867 #define DMA_SxCR_TEIE_Pos (2U)
5868 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
5869 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5870 #define DMA_SxCR_DMEIE_Pos (1U)
5871 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
5872 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5873 #define DMA_SxCR_EN_Pos (0U)
5874 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
5875 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
5876 
5877 /* Legacy defines */
5878 #define DMA_SxCR_ACK_Pos (20U)
5879 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
5880 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
5881 
5882 /******************** Bits definition for DMA_SxCNDTR register **************/
5883 #define DMA_SxNDT_Pos (0U)
5884 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
5885 #define DMA_SxNDT DMA_SxNDT_Msk
5886 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
5887 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
5888 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
5889 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
5890 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
5891 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
5892 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
5893 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
5894 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
5895 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
5896 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
5897 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
5898 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
5899 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
5900 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
5901 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
5903 /******************** Bits definition for DMA_SxFCR register ****************/
5904 #define DMA_SxFCR_FEIE_Pos (7U)
5905 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
5906 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5907 #define DMA_SxFCR_FS_Pos (3U)
5908 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
5909 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5910 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
5911 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
5912 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
5913 #define DMA_SxFCR_DMDIS_Pos (2U)
5914 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
5915 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5916 #define DMA_SxFCR_FTH_Pos (0U)
5917 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
5918 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5919 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
5920 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
5922 /******************** Bits definition for DMA_LISR register *****************/
5923 #define DMA_LISR_TCIF3_Pos (27U)
5924 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
5925 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5926 #define DMA_LISR_HTIF3_Pos (26U)
5927 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
5928 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5929 #define DMA_LISR_TEIF3_Pos (25U)
5930 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
5931 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5932 #define DMA_LISR_DMEIF3_Pos (24U)
5933 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
5934 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5935 #define DMA_LISR_FEIF3_Pos (22U)
5936 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
5937 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5938 #define DMA_LISR_TCIF2_Pos (21U)
5939 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
5940 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5941 #define DMA_LISR_HTIF2_Pos (20U)
5942 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
5943 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5944 #define DMA_LISR_TEIF2_Pos (19U)
5945 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
5946 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5947 #define DMA_LISR_DMEIF2_Pos (18U)
5948 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
5949 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5950 #define DMA_LISR_FEIF2_Pos (16U)
5951 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
5952 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5953 #define DMA_LISR_TCIF1_Pos (11U)
5954 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
5955 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5956 #define DMA_LISR_HTIF1_Pos (10U)
5957 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
5958 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5959 #define DMA_LISR_TEIF1_Pos (9U)
5960 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
5961 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5962 #define DMA_LISR_DMEIF1_Pos (8U)
5963 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
5964 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5965 #define DMA_LISR_FEIF1_Pos (6U)
5966 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
5967 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5968 #define DMA_LISR_TCIF0_Pos (5U)
5969 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
5970 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5971 #define DMA_LISR_HTIF0_Pos (4U)
5972 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
5973 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5974 #define DMA_LISR_TEIF0_Pos (3U)
5975 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
5976 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5977 #define DMA_LISR_DMEIF0_Pos (2U)
5978 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
5979 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5980 #define DMA_LISR_FEIF0_Pos (0U)
5981 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
5982 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
5983 
5984 /******************** Bits definition for DMA_HISR register *****************/
5985 #define DMA_HISR_TCIF7_Pos (27U)
5986 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
5987 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
5988 #define DMA_HISR_HTIF7_Pos (26U)
5989 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
5990 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
5991 #define DMA_HISR_TEIF7_Pos (25U)
5992 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
5993 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
5994 #define DMA_HISR_DMEIF7_Pos (24U)
5995 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
5996 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
5997 #define DMA_HISR_FEIF7_Pos (22U)
5998 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
5999 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6000 #define DMA_HISR_TCIF6_Pos (21U)
6001 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6002 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6003 #define DMA_HISR_HTIF6_Pos (20U)
6004 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6005 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6006 #define DMA_HISR_TEIF6_Pos (19U)
6007 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6008 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6009 #define DMA_HISR_DMEIF6_Pos (18U)
6010 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6011 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6012 #define DMA_HISR_FEIF6_Pos (16U)
6013 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6014 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6015 #define DMA_HISR_TCIF5_Pos (11U)
6016 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6017 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6018 #define DMA_HISR_HTIF5_Pos (10U)
6019 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6020 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6021 #define DMA_HISR_TEIF5_Pos (9U)
6022 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6023 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6024 #define DMA_HISR_DMEIF5_Pos (8U)
6025 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6026 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6027 #define DMA_HISR_FEIF5_Pos (6U)
6028 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6029 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6030 #define DMA_HISR_TCIF4_Pos (5U)
6031 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6032 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6033 #define DMA_HISR_HTIF4_Pos (4U)
6034 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6035 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6036 #define DMA_HISR_TEIF4_Pos (3U)
6037 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6038 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6039 #define DMA_HISR_DMEIF4_Pos (2U)
6040 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6041 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6042 #define DMA_HISR_FEIF4_Pos (0U)
6043 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6044 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6045 
6046 /******************** Bits definition for DMA_LIFCR register ****************/
6047 #define DMA_LIFCR_CTCIF3_Pos (27U)
6048 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6049 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6050 #define DMA_LIFCR_CHTIF3_Pos (26U)
6051 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6052 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6053 #define DMA_LIFCR_CTEIF3_Pos (25U)
6054 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6055 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6056 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6057 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6058 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6059 #define DMA_LIFCR_CFEIF3_Pos (22U)
6060 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6061 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6062 #define DMA_LIFCR_CTCIF2_Pos (21U)
6063 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6064 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6065 #define DMA_LIFCR_CHTIF2_Pos (20U)
6066 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6067 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6068 #define DMA_LIFCR_CTEIF2_Pos (19U)
6069 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6070 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6071 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6072 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6073 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6074 #define DMA_LIFCR_CFEIF2_Pos (16U)
6075 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6076 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6077 #define DMA_LIFCR_CTCIF1_Pos (11U)
6078 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6079 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6080 #define DMA_LIFCR_CHTIF1_Pos (10U)
6081 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6082 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6083 #define DMA_LIFCR_CTEIF1_Pos (9U)
6084 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6085 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6086 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6087 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6088 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6089 #define DMA_LIFCR_CFEIF1_Pos (6U)
6090 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6091 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6092 #define DMA_LIFCR_CTCIF0_Pos (5U)
6093 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6094 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6095 #define DMA_LIFCR_CHTIF0_Pos (4U)
6096 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6097 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6098 #define DMA_LIFCR_CTEIF0_Pos (3U)
6099 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6100 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6101 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6102 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6103 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6104 #define DMA_LIFCR_CFEIF0_Pos (0U)
6105 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6106 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6107 
6108 /******************** Bits definition for DMA_HIFCR register ****************/
6109 #define DMA_HIFCR_CTCIF7_Pos (27U)
6110 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6111 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6112 #define DMA_HIFCR_CHTIF7_Pos (26U)
6113 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6114 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6115 #define DMA_HIFCR_CTEIF7_Pos (25U)
6116 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6117 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6118 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6119 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6120 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6121 #define DMA_HIFCR_CFEIF7_Pos (22U)
6122 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6123 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6124 #define DMA_HIFCR_CTCIF6_Pos (21U)
6125 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6126 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6127 #define DMA_HIFCR_CHTIF6_Pos (20U)
6128 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6129 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6130 #define DMA_HIFCR_CTEIF6_Pos (19U)
6131 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6132 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6133 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6134 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6135 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6136 #define DMA_HIFCR_CFEIF6_Pos (16U)
6137 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6138 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6139 #define DMA_HIFCR_CTCIF5_Pos (11U)
6140 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6141 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6142 #define DMA_HIFCR_CHTIF5_Pos (10U)
6143 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6144 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6145 #define DMA_HIFCR_CTEIF5_Pos (9U)
6146 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6147 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6148 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6149 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6150 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6151 #define DMA_HIFCR_CFEIF5_Pos (6U)
6152 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6153 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6154 #define DMA_HIFCR_CTCIF4_Pos (5U)
6155 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6156 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6157 #define DMA_HIFCR_CHTIF4_Pos (4U)
6158 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6159 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6160 #define DMA_HIFCR_CTEIF4_Pos (3U)
6161 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6162 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6163 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6164 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6165 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6166 #define DMA_HIFCR_CFEIF4_Pos (0U)
6167 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6168 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6169 
6170 /****************** Bit definition for DMA_SxPAR register ********************/
6171 #define DMA_SxPAR_PA_Pos (0U)
6172 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6173 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6175 /****************** Bit definition for DMA_SxM0AR register ********************/
6176 #define DMA_SxM0AR_M0A_Pos (0U)
6177 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6178 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6180 /****************** Bit definition for DMA_SxM1AR register ********************/
6181 #define DMA_SxM1AR_M1A_Pos (0U)
6182 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6183 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6186 /******************************************************************************/
6187 /* */
6188 /* External Interrupt/Event Controller */
6189 /* */
6190 /******************************************************************************/
6191 /******************* Bit definition for EXTI_IMR register *******************/
6192 #define EXTI_IMR_MR0_Pos (0U)
6193 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6194 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6195 #define EXTI_IMR_MR1_Pos (1U)
6196 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6197 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6198 #define EXTI_IMR_MR2_Pos (2U)
6199 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6200 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6201 #define EXTI_IMR_MR3_Pos (3U)
6202 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6203 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6204 #define EXTI_IMR_MR4_Pos (4U)
6205 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6206 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6207 #define EXTI_IMR_MR5_Pos (5U)
6208 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6209 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6210 #define EXTI_IMR_MR6_Pos (6U)
6211 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6212 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6213 #define EXTI_IMR_MR7_Pos (7U)
6214 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6215 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6216 #define EXTI_IMR_MR8_Pos (8U)
6217 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6218 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6219 #define EXTI_IMR_MR9_Pos (9U)
6220 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6221 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6222 #define EXTI_IMR_MR10_Pos (10U)
6223 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6224 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6225 #define EXTI_IMR_MR11_Pos (11U)
6226 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6227 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6228 #define EXTI_IMR_MR12_Pos (12U)
6229 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6230 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6231 #define EXTI_IMR_MR13_Pos (13U)
6232 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6233 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6234 #define EXTI_IMR_MR14_Pos (14U)
6235 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6236 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6237 #define EXTI_IMR_MR15_Pos (15U)
6238 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6239 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6240 #define EXTI_IMR_MR16_Pos (16U)
6241 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6242 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6243 #define EXTI_IMR_MR17_Pos (17U)
6244 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6245 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6246 #define EXTI_IMR_MR18_Pos (18U)
6247 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6248 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6249 #define EXTI_IMR_MR19_Pos (19U)
6250 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6251 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6252 #define EXTI_IMR_MR20_Pos (20U)
6253 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6254 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6255 #define EXTI_IMR_MR21_Pos (21U)
6256 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6257 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6258 #define EXTI_IMR_MR22_Pos (22U)
6259 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6260 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6262 /* Reference Defines */
6263 #define EXTI_IMR_IM0 EXTI_IMR_MR0
6264 #define EXTI_IMR_IM1 EXTI_IMR_MR1
6265 #define EXTI_IMR_IM2 EXTI_IMR_MR2
6266 #define EXTI_IMR_IM3 EXTI_IMR_MR3
6267 #define EXTI_IMR_IM4 EXTI_IMR_MR4
6268 #define EXTI_IMR_IM5 EXTI_IMR_MR5
6269 #define EXTI_IMR_IM6 EXTI_IMR_MR6
6270 #define EXTI_IMR_IM7 EXTI_IMR_MR7
6271 #define EXTI_IMR_IM8 EXTI_IMR_MR8
6272 #define EXTI_IMR_IM9 EXTI_IMR_MR9
6273 #define EXTI_IMR_IM10 EXTI_IMR_MR10
6274 #define EXTI_IMR_IM11 EXTI_IMR_MR11
6275 #define EXTI_IMR_IM12 EXTI_IMR_MR12
6276 #define EXTI_IMR_IM13 EXTI_IMR_MR13
6277 #define EXTI_IMR_IM14 EXTI_IMR_MR14
6278 #define EXTI_IMR_IM15 EXTI_IMR_MR15
6279 #define EXTI_IMR_IM16 EXTI_IMR_MR16
6280 #define EXTI_IMR_IM17 EXTI_IMR_MR17
6281 #define EXTI_IMR_IM18 EXTI_IMR_MR18
6282 #define EXTI_IMR_IM19 EXTI_IMR_MR19
6283 #define EXTI_IMR_IM20 EXTI_IMR_MR20
6284 #define EXTI_IMR_IM21 EXTI_IMR_MR21
6285 #define EXTI_IMR_IM22 EXTI_IMR_MR22
6286 #define EXTI_IMR_IM_Pos (0U)
6287 #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
6288 #define EXTI_IMR_IM EXTI_IMR_IM_Msk
6290 /******************* Bit definition for EXTI_EMR register *******************/
6291 #define EXTI_EMR_MR0_Pos (0U)
6292 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6293 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6294 #define EXTI_EMR_MR1_Pos (1U)
6295 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6296 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6297 #define EXTI_EMR_MR2_Pos (2U)
6298 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6299 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6300 #define EXTI_EMR_MR3_Pos (3U)
6301 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6302 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6303 #define EXTI_EMR_MR4_Pos (4U)
6304 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6305 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6306 #define EXTI_EMR_MR5_Pos (5U)
6307 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6308 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6309 #define EXTI_EMR_MR6_Pos (6U)
6310 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6311 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6312 #define EXTI_EMR_MR7_Pos (7U)
6313 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6314 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6315 #define EXTI_EMR_MR8_Pos (8U)
6316 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6317 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6318 #define EXTI_EMR_MR9_Pos (9U)
6319 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6320 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6321 #define EXTI_EMR_MR10_Pos (10U)
6322 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6323 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6324 #define EXTI_EMR_MR11_Pos (11U)
6325 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6326 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6327 #define EXTI_EMR_MR12_Pos (12U)
6328 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6329 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6330 #define EXTI_EMR_MR13_Pos (13U)
6331 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6332 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6333 #define EXTI_EMR_MR14_Pos (14U)
6334 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6335 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6336 #define EXTI_EMR_MR15_Pos (15U)
6337 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6338 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6339 #define EXTI_EMR_MR16_Pos (16U)
6340 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6341 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6342 #define EXTI_EMR_MR17_Pos (17U)
6343 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6344 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6345 #define EXTI_EMR_MR18_Pos (18U)
6346 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6347 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6348 #define EXTI_EMR_MR19_Pos (19U)
6349 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6350 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6351 #define EXTI_EMR_MR20_Pos (20U)
6352 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6353 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6354 #define EXTI_EMR_MR21_Pos (21U)
6355 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6356 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6357 #define EXTI_EMR_MR22_Pos (22U)
6358 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6359 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6361 /* Reference Defines */
6362 #define EXTI_EMR_EM0 EXTI_EMR_MR0
6363 #define EXTI_EMR_EM1 EXTI_EMR_MR1
6364 #define EXTI_EMR_EM2 EXTI_EMR_MR2
6365 #define EXTI_EMR_EM3 EXTI_EMR_MR3
6366 #define EXTI_EMR_EM4 EXTI_EMR_MR4
6367 #define EXTI_EMR_EM5 EXTI_EMR_MR5
6368 #define EXTI_EMR_EM6 EXTI_EMR_MR6
6369 #define EXTI_EMR_EM7 EXTI_EMR_MR7
6370 #define EXTI_EMR_EM8 EXTI_EMR_MR8
6371 #define EXTI_EMR_EM9 EXTI_EMR_MR9
6372 #define EXTI_EMR_EM10 EXTI_EMR_MR10
6373 #define EXTI_EMR_EM11 EXTI_EMR_MR11
6374 #define EXTI_EMR_EM12 EXTI_EMR_MR12
6375 #define EXTI_EMR_EM13 EXTI_EMR_MR13
6376 #define EXTI_EMR_EM14 EXTI_EMR_MR14
6377 #define EXTI_EMR_EM15 EXTI_EMR_MR15
6378 #define EXTI_EMR_EM16 EXTI_EMR_MR16
6379 #define EXTI_EMR_EM17 EXTI_EMR_MR17
6380 #define EXTI_EMR_EM18 EXTI_EMR_MR18
6381 #define EXTI_EMR_EM19 EXTI_EMR_MR19
6382 #define EXTI_EMR_EM20 EXTI_EMR_MR20
6383 #define EXTI_EMR_EM21 EXTI_EMR_MR21
6384 #define EXTI_EMR_EM22 EXTI_EMR_MR22
6385 
6386 /****************** Bit definition for EXTI_RTSR register *******************/
6387 #define EXTI_RTSR_TR0_Pos (0U)
6388 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6389 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6390 #define EXTI_RTSR_TR1_Pos (1U)
6391 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6392 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6393 #define EXTI_RTSR_TR2_Pos (2U)
6394 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6395 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6396 #define EXTI_RTSR_TR3_Pos (3U)
6397 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6398 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6399 #define EXTI_RTSR_TR4_Pos (4U)
6400 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6401 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6402 #define EXTI_RTSR_TR5_Pos (5U)
6403 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6404 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6405 #define EXTI_RTSR_TR6_Pos (6U)
6406 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6407 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6408 #define EXTI_RTSR_TR7_Pos (7U)
6409 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6410 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6411 #define EXTI_RTSR_TR8_Pos (8U)
6412 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6413 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6414 #define EXTI_RTSR_TR9_Pos (9U)
6415 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6416 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6417 #define EXTI_RTSR_TR10_Pos (10U)
6418 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6419 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6420 #define EXTI_RTSR_TR11_Pos (11U)
6421 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6422 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6423 #define EXTI_RTSR_TR12_Pos (12U)
6424 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6425 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6426 #define EXTI_RTSR_TR13_Pos (13U)
6427 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6428 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6429 #define EXTI_RTSR_TR14_Pos (14U)
6430 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6431 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6432 #define EXTI_RTSR_TR15_Pos (15U)
6433 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6434 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6435 #define EXTI_RTSR_TR16_Pos (16U)
6436 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6437 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6438 #define EXTI_RTSR_TR17_Pos (17U)
6439 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6440 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6441 #define EXTI_RTSR_TR18_Pos (18U)
6442 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6443 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6444 #define EXTI_RTSR_TR19_Pos (19U)
6445 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6446 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6447 #define EXTI_RTSR_TR20_Pos (20U)
6448 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6449 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6450 #define EXTI_RTSR_TR21_Pos (21U)
6451 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6452 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6453 #define EXTI_RTSR_TR22_Pos (22U)
6454 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6455 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6457 /****************** Bit definition for EXTI_FTSR register *******************/
6458 #define EXTI_FTSR_TR0_Pos (0U)
6459 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6460 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6461 #define EXTI_FTSR_TR1_Pos (1U)
6462 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6463 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6464 #define EXTI_FTSR_TR2_Pos (2U)
6465 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6466 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6467 #define EXTI_FTSR_TR3_Pos (3U)
6468 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6469 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6470 #define EXTI_FTSR_TR4_Pos (4U)
6471 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6472 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6473 #define EXTI_FTSR_TR5_Pos (5U)
6474 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6475 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6476 #define EXTI_FTSR_TR6_Pos (6U)
6477 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6478 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6479 #define EXTI_FTSR_TR7_Pos (7U)
6480 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6481 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6482 #define EXTI_FTSR_TR8_Pos (8U)
6483 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6484 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6485 #define EXTI_FTSR_TR9_Pos (9U)
6486 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6487 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6488 #define EXTI_FTSR_TR10_Pos (10U)
6489 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6490 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6491 #define EXTI_FTSR_TR11_Pos (11U)
6492 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6493 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6494 #define EXTI_FTSR_TR12_Pos (12U)
6495 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6496 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6497 #define EXTI_FTSR_TR13_Pos (13U)
6498 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6499 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6500 #define EXTI_FTSR_TR14_Pos (14U)
6501 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6502 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6503 #define EXTI_FTSR_TR15_Pos (15U)
6504 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6505 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6506 #define EXTI_FTSR_TR16_Pos (16U)
6507 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6508 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6509 #define EXTI_FTSR_TR17_Pos (17U)
6510 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6511 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6512 #define EXTI_FTSR_TR18_Pos (18U)
6513 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6514 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6515 #define EXTI_FTSR_TR19_Pos (19U)
6516 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6517 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6518 #define EXTI_FTSR_TR20_Pos (20U)
6519 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6520 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6521 #define EXTI_FTSR_TR21_Pos (21U)
6522 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6523 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6524 #define EXTI_FTSR_TR22_Pos (22U)
6525 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6526 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6528 /****************** Bit definition for EXTI_SWIER register ******************/
6529 #define EXTI_SWIER_SWIER0_Pos (0U)
6530 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6531 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6532 #define EXTI_SWIER_SWIER1_Pos (1U)
6533 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6534 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6535 #define EXTI_SWIER_SWIER2_Pos (2U)
6536 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6537 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6538 #define EXTI_SWIER_SWIER3_Pos (3U)
6539 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6540 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6541 #define EXTI_SWIER_SWIER4_Pos (4U)
6542 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6543 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6544 #define EXTI_SWIER_SWIER5_Pos (5U)
6545 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6546 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6547 #define EXTI_SWIER_SWIER6_Pos (6U)
6548 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6549 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6550 #define EXTI_SWIER_SWIER7_Pos (7U)
6551 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6552 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6553 #define EXTI_SWIER_SWIER8_Pos (8U)
6554 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6555 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6556 #define EXTI_SWIER_SWIER9_Pos (9U)
6557 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6558 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6559 #define EXTI_SWIER_SWIER10_Pos (10U)
6560 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6561 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6562 #define EXTI_SWIER_SWIER11_Pos (11U)
6563 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6564 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6565 #define EXTI_SWIER_SWIER12_Pos (12U)
6566 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6567 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6568 #define EXTI_SWIER_SWIER13_Pos (13U)
6569 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6570 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6571 #define EXTI_SWIER_SWIER14_Pos (14U)
6572 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6573 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6574 #define EXTI_SWIER_SWIER15_Pos (15U)
6575 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6576 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6577 #define EXTI_SWIER_SWIER16_Pos (16U)
6578 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6579 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6580 #define EXTI_SWIER_SWIER17_Pos (17U)
6581 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6582 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6583 #define EXTI_SWIER_SWIER18_Pos (18U)
6584 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6585 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6586 #define EXTI_SWIER_SWIER19_Pos (19U)
6587 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6588 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6589 #define EXTI_SWIER_SWIER20_Pos (20U)
6590 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6591 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6592 #define EXTI_SWIER_SWIER21_Pos (21U)
6593 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6594 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6595 #define EXTI_SWIER_SWIER22_Pos (22U)
6596 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6597 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6599 /******************* Bit definition for EXTI_PR register ********************/
6600 #define EXTI_PR_PR0_Pos (0U)
6601 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6602 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6603 #define EXTI_PR_PR1_Pos (1U)
6604 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6605 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6606 #define EXTI_PR_PR2_Pos (2U)
6607 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6608 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6609 #define EXTI_PR_PR3_Pos (3U)
6610 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6611 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6612 #define EXTI_PR_PR4_Pos (4U)
6613 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6614 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6615 #define EXTI_PR_PR5_Pos (5U)
6616 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6617 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6618 #define EXTI_PR_PR6_Pos (6U)
6619 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6620 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6621 #define EXTI_PR_PR7_Pos (7U)
6622 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6623 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6624 #define EXTI_PR_PR8_Pos (8U)
6625 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6626 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6627 #define EXTI_PR_PR9_Pos (9U)
6628 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6629 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6630 #define EXTI_PR_PR10_Pos (10U)
6631 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6632 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6633 #define EXTI_PR_PR11_Pos (11U)
6634 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6635 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6636 #define EXTI_PR_PR12_Pos (12U)
6637 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6638 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6639 #define EXTI_PR_PR13_Pos (13U)
6640 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6641 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6642 #define EXTI_PR_PR14_Pos (14U)
6643 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6644 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6645 #define EXTI_PR_PR15_Pos (15U)
6646 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6647 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6648 #define EXTI_PR_PR16_Pos (16U)
6649 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6650 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6651 #define EXTI_PR_PR17_Pos (17U)
6652 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6653 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6654 #define EXTI_PR_PR18_Pos (18U)
6655 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6656 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6657 #define EXTI_PR_PR19_Pos (19U)
6658 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6659 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6660 #define EXTI_PR_PR20_Pos (20U)
6661 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6662 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6663 #define EXTI_PR_PR21_Pos (21U)
6664 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6665 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6666 #define EXTI_PR_PR22_Pos (22U)
6667 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6668 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6670 /******************************************************************************/
6671 /* */
6672 /* FLASH */
6673 /* */
6674 /******************************************************************************/
6675 /******************* Bits definition for FLASH_ACR register *****************/
6676 #define FLASH_ACR_LATENCY_Pos (0U)
6677 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
6678 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6679 #define FLASH_ACR_LATENCY_0WS 0x00000000U
6680 #define FLASH_ACR_LATENCY_1WS 0x00000001U
6681 #define FLASH_ACR_LATENCY_2WS 0x00000002U
6682 #define FLASH_ACR_LATENCY_3WS 0x00000003U
6683 #define FLASH_ACR_LATENCY_4WS 0x00000004U
6684 #define FLASH_ACR_LATENCY_5WS 0x00000005U
6685 #define FLASH_ACR_LATENCY_6WS 0x00000006U
6686 #define FLASH_ACR_LATENCY_7WS 0x00000007U
6687 
6688 #define FLASH_ACR_PRFTEN_Pos (8U)
6689 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6690 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6691 #define FLASH_ACR_ICEN_Pos (9U)
6692 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6693 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6694 #define FLASH_ACR_DCEN_Pos (10U)
6695 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6696 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6697 #define FLASH_ACR_ICRST_Pos (11U)
6698 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6699 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6700 #define FLASH_ACR_DCRST_Pos (12U)
6701 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6702 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6703 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6704 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
6705 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6706 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6707 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
6708 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6709 
6710 /******************* Bits definition for FLASH_SR register ******************/
6711 #define FLASH_SR_EOP_Pos (0U)
6712 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6713 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
6714 #define FLASH_SR_SOP_Pos (1U)
6715 #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)
6716 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
6717 #define FLASH_SR_WRPERR_Pos (4U)
6718 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6719 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6720 #define FLASH_SR_PGAERR_Pos (5U)
6721 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6722 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6723 #define FLASH_SR_PGPERR_Pos (6U)
6724 #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6725 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6726 #define FLASH_SR_PGSERR_Pos (7U)
6727 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6728 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6729 #define FLASH_SR_BSY_Pos (16U)
6730 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6731 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
6732 
6733 /******************* Bits definition for FLASH_CR register ******************/
6734 #define FLASH_CR_PG_Pos (0U)
6735 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6736 #define FLASH_CR_PG FLASH_CR_PG_Msk
6737 #define FLASH_CR_SER_Pos (1U)
6738 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6739 #define FLASH_CR_SER FLASH_CR_SER_Msk
6740 #define FLASH_CR_MER_Pos (2U)
6741 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6742 #define FLASH_CR_MER FLASH_CR_MER_Msk
6743 #define FLASH_CR_SNB_Pos (3U)
6744 #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
6745 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
6746 #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
6747 #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
6748 #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
6749 #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
6750 #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
6751 #define FLASH_CR_PSIZE_Pos (8U)
6752 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6753 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6754 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6755 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6756 #define FLASH_CR_STRT_Pos (16U)
6757 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6758 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
6759 #define FLASH_CR_EOPIE_Pos (24U)
6760 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6761 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6762 #define FLASH_CR_LOCK_Pos (31U)
6763 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6764 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6765 
6766 /******************* Bits definition for FLASH_OPTCR register ***************/
6767 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
6768 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6769 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6770 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
6771 #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6772 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6773 
6774 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6775 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6776 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
6777 #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6778 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6779 #define FLASH_OPTCR_WDG_SW_Pos (5U)
6780 #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
6781 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6782 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
6783 #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6784 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6785 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6786 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6787 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6788 #define FLASH_OPTCR_RDP_Pos (8U)
6789 #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6790 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6791 #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6792 #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6793 #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6794 #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6795 #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6796 #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6797 #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6798 #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6799 #define FLASH_OPTCR_nWRP_Pos (16U)
6800 #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
6801 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6802 #define FLASH_OPTCR_nWRP_0 0x00010000U
6803 #define FLASH_OPTCR_nWRP_1 0x00020000U
6804 #define FLASH_OPTCR_nWRP_2 0x00040000U
6805 #define FLASH_OPTCR_nWRP_3 0x00080000U
6806 #define FLASH_OPTCR_nWRP_4 0x00100000U
6807 #define FLASH_OPTCR_nWRP_5 0x00200000U
6808 #define FLASH_OPTCR_nWRP_6 0x00400000U
6809 #define FLASH_OPTCR_nWRP_7 0x00800000U
6810 #define FLASH_OPTCR_nWRP_8 0x01000000U
6811 #define FLASH_OPTCR_nWRP_9 0x02000000U
6812 #define FLASH_OPTCR_nWRP_10 0x04000000U
6813 #define FLASH_OPTCR_nWRP_11 0x08000000U
6814 
6815 /****************** Bits definition for FLASH_OPTCR1 register ***************/
6816 #define FLASH_OPTCR1_nWRP_Pos (16U)
6817 #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
6818 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
6819 #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
6820 #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
6821 #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
6822 #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
6823 #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
6824 #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
6825 #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
6826 #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
6827 #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
6828 #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
6829 #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
6830 #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
6832 /******************************************************************************/
6833 /* */
6834 /* Flexible Static Memory Controller */
6835 /* */
6836 /******************************************************************************/
6837 /****************** Bit definition for FSMC_BCR1 register *******************/
6838 #define FSMC_BCR1_MBKEN_Pos (0U)
6839 #define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
6840 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
6841 #define FSMC_BCR1_MUXEN_Pos (1U)
6842 #define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
6843 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
6845 #define FSMC_BCR1_MTYP_Pos (2U)
6846 #define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
6847 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
6848 #define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
6849 #define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
6851 #define FSMC_BCR1_MWID_Pos (4U)
6852 #define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
6853 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
6854 #define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
6855 #define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
6857 #define FSMC_BCR1_FACCEN_Pos (6U)
6858 #define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
6859 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
6860 #define FSMC_BCR1_BURSTEN_Pos (8U)
6861 #define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
6862 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
6863 #define FSMC_BCR1_WAITPOL_Pos (9U)
6864 #define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
6865 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
6866 #define FSMC_BCR1_WRAPMOD_Pos (10U)
6867 #define FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
6868 #define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk
6869 #define FSMC_BCR1_WAITCFG_Pos (11U)
6870 #define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
6871 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
6872 #define FSMC_BCR1_WREN_Pos (12U)
6873 #define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
6874 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
6875 #define FSMC_BCR1_WAITEN_Pos (13U)
6876 #define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
6877 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
6878 #define FSMC_BCR1_EXTMOD_Pos (14U)
6879 #define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
6880 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
6881 #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
6882 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
6883 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
6884 #define FSMC_BCR1_CPSIZE_Pos (16U)
6885 #define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)
6886 #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk
6887 #define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)
6888 #define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)
6889 #define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)
6890 #define FSMC_BCR1_CBURSTRW_Pos (19U)
6891 #define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
6892 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
6894 /****************** Bit definition for FSMC_BCR2 register *******************/
6895 #define FSMC_BCR2_MBKEN_Pos (0U)
6896 #define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
6897 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
6898 #define FSMC_BCR2_MUXEN_Pos (1U)
6899 #define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
6900 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
6902 #define FSMC_BCR2_MTYP_Pos (2U)
6903 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
6904 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
6905 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
6906 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
6908 #define FSMC_BCR2_MWID_Pos (4U)
6909 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
6910 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
6911 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
6912 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
6914 #define FSMC_BCR2_FACCEN_Pos (6U)
6915 #define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
6916 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
6917 #define FSMC_BCR2_BURSTEN_Pos (8U)
6918 #define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
6919 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
6920 #define FSMC_BCR2_WAITPOL_Pos (9U)
6921 #define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
6922 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
6923 #define FSMC_BCR2_WRAPMOD_Pos (10U)
6924 #define FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
6925 #define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk
6926 #define FSMC_BCR2_WAITCFG_Pos (11U)
6927 #define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
6928 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
6929 #define FSMC_BCR2_WREN_Pos (12U)
6930 #define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
6931 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
6932 #define FSMC_BCR2_WAITEN_Pos (13U)
6933 #define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
6934 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
6935 #define FSMC_BCR2_EXTMOD_Pos (14U)
6936 #define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
6937 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
6938 #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
6939 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
6940 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
6941 #define FSMC_BCR2_CPSIZE_Pos (16U)
6942 #define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)
6943 #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk
6944 #define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)
6945 #define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)
6946 #define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)
6947 #define FSMC_BCR2_CBURSTRW_Pos (19U)
6948 #define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
6949 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
6951 /****************** Bit definition for FSMC_BCR3 register *******************/
6952 #define FSMC_BCR3_MBKEN_Pos (0U)
6953 #define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
6954 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
6955 #define FSMC_BCR3_MUXEN_Pos (1U)
6956 #define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
6957 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
6959 #define FSMC_BCR3_MTYP_Pos (2U)
6960 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
6961 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
6962 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
6963 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
6965 #define FSMC_BCR3_MWID_Pos (4U)
6966 #define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
6967 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
6968 #define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
6969 #define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
6971 #define FSMC_BCR3_FACCEN_Pos (6U)
6972 #define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
6973 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
6974 #define FSMC_BCR3_BURSTEN_Pos (8U)
6975 #define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
6976 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
6977 #define FSMC_BCR3_WAITPOL_Pos (9U)
6978 #define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
6979 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
6980 #define FSMC_BCR3_WRAPMOD_Pos (10U)
6981 #define FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
6982 #define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk
6983 #define FSMC_BCR3_WAITCFG_Pos (11U)
6984 #define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
6985 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
6986 #define FSMC_BCR3_WREN_Pos (12U)
6987 #define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
6988 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
6989 #define FSMC_BCR3_WAITEN_Pos (13U)
6990 #define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
6991 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
6992 #define FSMC_BCR3_EXTMOD_Pos (14U)
6993 #define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
6994 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
6995 #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
6996 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
6997 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
6998 #define FSMC_BCR3_CPSIZE_Pos (16U)
6999 #define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)
7000 #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk
7001 #define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)
7002 #define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)
7003 #define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)
7004 #define FSMC_BCR3_CBURSTRW_Pos (19U)
7005 #define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
7006 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
7008 /****************** Bit definition for FSMC_BCR4 register *******************/
7009 #define FSMC_BCR4_MBKEN_Pos (0U)
7010 #define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
7011 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
7012 #define FSMC_BCR4_MUXEN_Pos (1U)
7013 #define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
7014 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
7016 #define FSMC_BCR4_MTYP_Pos (2U)
7017 #define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
7018 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
7019 #define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
7020 #define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
7022 #define FSMC_BCR4_MWID_Pos (4U)
7023 #define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
7024 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
7025 #define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
7026 #define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
7028 #define FSMC_BCR4_FACCEN_Pos (6U)
7029 #define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
7030 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
7031 #define FSMC_BCR4_BURSTEN_Pos (8U)
7032 #define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
7033 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
7034 #define FSMC_BCR4_WAITPOL_Pos (9U)
7035 #define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
7036 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
7037 #define FSMC_BCR4_WRAPMOD_Pos (10U)
7038 #define FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
7039 #define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk
7040 #define FSMC_BCR4_WAITCFG_Pos (11U)
7041 #define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
7042 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
7043 #define FSMC_BCR4_WREN_Pos (12U)
7044 #define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
7045 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
7046 #define FSMC_BCR4_WAITEN_Pos (13U)
7047 #define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
7048 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
7049 #define FSMC_BCR4_EXTMOD_Pos (14U)
7050 #define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
7051 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
7052 #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
7053 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
7054 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
7055 #define FSMC_BCR4_CPSIZE_Pos (16U)
7056 #define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)
7057 #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk
7058 #define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)
7059 #define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)
7060 #define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)
7061 #define FSMC_BCR4_CBURSTRW_Pos (19U)
7062 #define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
7063 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
7065 /****************** Bit definition for FSMC_BTR1 register ******************/
7066 #define FSMC_BTR1_ADDSET_Pos (0U)
7067 #define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
7068 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
7069 #define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
7070 #define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
7071 #define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
7072 #define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
7074 #define FSMC_BTR1_ADDHLD_Pos (4U)
7075 #define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
7076 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
7077 #define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
7078 #define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
7079 #define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
7080 #define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
7082 #define FSMC_BTR1_DATAST_Pos (8U)
7083 #define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
7084 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
7085 #define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
7086 #define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
7087 #define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
7088 #define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
7089 #define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
7090 #define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
7091 #define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
7092 #define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
7094 #define FSMC_BTR1_BUSTURN_Pos (16U)
7095 #define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
7096 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
7097 #define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
7098 #define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
7099 #define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
7100 #define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
7102 #define FSMC_BTR1_CLKDIV_Pos (20U)
7103 #define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
7104 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
7105 #define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
7106 #define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
7107 #define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
7108 #define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
7110 #define FSMC_BTR1_DATLAT_Pos (24U)
7111 #define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
7112 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
7113 #define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
7114 #define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
7115 #define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
7116 #define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
7118 #define FSMC_BTR1_ACCMOD_Pos (28U)
7119 #define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
7120 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
7121 #define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
7122 #define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
7124 /****************** Bit definition for FSMC_BTR2 register *******************/
7125 #define FSMC_BTR2_ADDSET_Pos (0U)
7126 #define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
7127 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
7128 #define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
7129 #define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
7130 #define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
7131 #define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
7133 #define FSMC_BTR2_ADDHLD_Pos (4U)
7134 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
7135 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
7136 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
7137 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
7138 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
7139 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
7141 #define FSMC_BTR2_DATAST_Pos (8U)
7142 #define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
7143 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
7144 #define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
7145 #define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
7146 #define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
7147 #define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
7148 #define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
7149 #define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
7150 #define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
7151 #define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
7153 #define FSMC_BTR2_BUSTURN_Pos (16U)
7154 #define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
7155 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
7156 #define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
7157 #define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
7158 #define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
7159 #define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
7161 #define FSMC_BTR2_CLKDIV_Pos (20U)
7162 #define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
7163 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
7164 #define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
7165 #define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
7166 #define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
7167 #define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
7169 #define FSMC_BTR2_DATLAT_Pos (24U)
7170 #define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
7171 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
7172 #define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
7173 #define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
7174 #define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
7175 #define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
7177 #define FSMC_BTR2_ACCMOD_Pos (28U)
7178 #define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
7179 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
7180 #define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
7181 #define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
7183 /******************* Bit definition for FSMC_BTR3 register *******************/
7184 #define FSMC_BTR3_ADDSET_Pos (0U)
7185 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
7186 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
7187 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
7188 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
7189 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
7190 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
7192 #define FSMC_BTR3_ADDHLD_Pos (4U)
7193 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
7194 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
7195 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
7196 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
7197 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
7198 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
7200 #define FSMC_BTR3_DATAST_Pos (8U)
7201 #define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
7202 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
7203 #define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
7204 #define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
7205 #define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
7206 #define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
7207 #define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
7208 #define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
7209 #define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
7210 #define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
7212 #define FSMC_BTR3_BUSTURN_Pos (16U)
7213 #define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
7214 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
7215 #define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
7216 #define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
7217 #define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
7218 #define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
7220 #define FSMC_BTR3_CLKDIV_Pos (20U)
7221 #define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
7222 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
7223 #define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
7224 #define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
7225 #define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
7226 #define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
7228 #define FSMC_BTR3_DATLAT_Pos (24U)
7229 #define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
7230 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
7231 #define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
7232 #define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
7233 #define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
7234 #define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
7236 #define FSMC_BTR3_ACCMOD_Pos (28U)
7237 #define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
7238 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
7239 #define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
7240 #define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
7242 /****************** Bit definition for FSMC_BTR4 register *******************/
7243 #define FSMC_BTR4_ADDSET_Pos (0U)
7244 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
7245 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
7246 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
7247 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
7248 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
7249 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
7251 #define FSMC_BTR4_ADDHLD_Pos (4U)
7252 #define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
7253 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
7254 #define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
7255 #define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
7256 #define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
7257 #define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
7259 #define FSMC_BTR4_DATAST_Pos (8U)
7260 #define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
7261 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
7262 #define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
7263 #define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
7264 #define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
7265 #define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
7266 #define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
7267 #define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
7268 #define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
7269 #define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
7271 #define FSMC_BTR4_BUSTURN_Pos (16U)
7272 #define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
7273 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
7274 #define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
7275 #define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
7276 #define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
7277 #define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
7279 #define FSMC_BTR4_CLKDIV_Pos (20U)
7280 #define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
7281 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
7282 #define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
7283 #define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
7284 #define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
7285 #define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
7287 #define FSMC_BTR4_DATLAT_Pos (24U)
7288 #define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
7289 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
7290 #define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
7291 #define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
7292 #define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
7293 #define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
7295 #define FSMC_BTR4_ACCMOD_Pos (28U)
7296 #define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
7297 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
7298 #define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
7299 #define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
7301 /****************** Bit definition for FSMC_BWTR1 register ******************/
7302 #define FSMC_BWTR1_ADDSET_Pos (0U)
7303 #define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
7304 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
7305 #define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
7306 #define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
7307 #define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
7308 #define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
7310 #define FSMC_BWTR1_ADDHLD_Pos (4U)
7311 #define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
7312 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
7313 #define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
7314 #define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
7315 #define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
7316 #define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
7318 #define FSMC_BWTR1_DATAST_Pos (8U)
7319 #define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
7320 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
7321 #define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
7322 #define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
7323 #define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
7324 #define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
7325 #define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
7326 #define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
7327 #define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
7328 #define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
7330 #define FSMC_BWTR1_BUSTURN_Pos (16U)
7331 #define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
7332 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
7333 #define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
7334 #define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
7335 #define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
7336 #define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
7338 #define FSMC_BWTR1_ACCMOD_Pos (28U)
7339 #define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
7340 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
7341 #define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
7342 #define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
7344 /****************** Bit definition for FSMC_BWTR2 register ******************/
7345 #define FSMC_BWTR2_ADDSET_Pos (0U)
7346 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
7347 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
7348 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
7349 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
7350 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
7351 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
7353 #define FSMC_BWTR2_ADDHLD_Pos (4U)
7354 #define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
7355 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
7356 #define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
7357 #define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
7358 #define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
7359 #define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
7361 #define FSMC_BWTR2_DATAST_Pos (8U)
7362 #define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
7363 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
7364 #define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
7365 #define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
7366 #define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
7367 #define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
7368 #define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
7369 #define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
7370 #define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
7371 #define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
7373 #define FSMC_BWTR2_BUSTURN_Pos (16U)
7374 #define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
7375 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
7376 #define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
7377 #define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
7378 #define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
7379 #define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
7381 #define FSMC_BWTR2_ACCMOD_Pos (28U)
7382 #define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
7383 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
7384 #define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
7385 #define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
7387 /****************** Bit definition for FSMC_BWTR3 register ******************/
7388 #define FSMC_BWTR3_ADDSET_Pos (0U)
7389 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
7390 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
7391 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
7392 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
7393 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
7394 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
7396 #define FSMC_BWTR3_ADDHLD_Pos (4U)
7397 #define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
7398 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
7399 #define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
7400 #define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
7401 #define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
7402 #define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
7404 #define FSMC_BWTR3_DATAST_Pos (8U)
7405 #define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
7406 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
7407 #define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
7408 #define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
7409 #define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
7410 #define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
7411 #define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
7412 #define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
7413 #define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
7414 #define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
7416 #define FSMC_BWTR3_BUSTURN_Pos (16U)
7417 #define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
7418 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
7419 #define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
7420 #define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
7421 #define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
7422 #define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
7424 #define FSMC_BWTR3_ACCMOD_Pos (28U)
7425 #define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
7426 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
7427 #define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
7428 #define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
7430 /****************** Bit definition for FSMC_BWTR4 register ******************/
7431 #define FSMC_BWTR4_ADDSET_Pos (0U)
7432 #define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
7433 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
7434 #define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
7435 #define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
7436 #define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
7437 #define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
7439 #define FSMC_BWTR4_ADDHLD_Pos (4U)
7440 #define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
7441 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
7442 #define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
7443 #define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
7444 #define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
7445 #define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
7447 #define FSMC_BWTR4_DATAST_Pos (8U)
7448 #define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
7449 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
7450 #define FSMC_BWTR4_DATAST_0 0x00000100U
7451 #define FSMC_BWTR4_DATAST_1 0x00000200U
7452 #define FSMC_BWTR4_DATAST_2 0x00000400U
7453 #define FSMC_BWTR4_DATAST_3 0x00000800U
7454 #define FSMC_BWTR4_DATAST_4 0x00001000U
7455 #define FSMC_BWTR4_DATAST_5 0x00002000U
7456 #define FSMC_BWTR4_DATAST_6 0x00004000U
7457 #define FSMC_BWTR4_DATAST_7 0x00008000U
7459 #define FSMC_BWTR4_BUSTURN_Pos (16U)
7460 #define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
7461 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
7462 #define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
7463 #define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
7464 #define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
7465 #define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
7467 #define FSMC_BWTR4_ACCMOD_Pos (28U)
7468 #define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
7469 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
7470 #define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
7471 #define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
7473 /****************** Bit definition for FSMC_PCR2 register *******************/
7474 #define FSMC_PCR2_PWAITEN_Pos (1U)
7475 #define FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos)
7476 #define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk
7477 #define FSMC_PCR2_PBKEN_Pos (2U)
7478 #define FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos)
7479 #define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk
7480 #define FSMC_PCR2_PTYP_Pos (3U)
7481 #define FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos)
7482 #define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk
7484 #define FSMC_PCR2_PWID_Pos (4U)
7485 #define FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos)
7486 #define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk
7487 #define FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos)
7488 #define FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos)
7490 #define FSMC_PCR2_ECCEN_Pos (6U)
7491 #define FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos)
7492 #define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk
7494 #define FSMC_PCR2_TCLR_Pos (9U)
7495 #define FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos)
7496 #define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk
7497 #define FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos)
7498 #define FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos)
7499 #define FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos)
7500 #define FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos)
7502 #define FSMC_PCR2_TAR_Pos (13U)
7503 #define FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos)
7504 #define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk
7505 #define FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos)
7506 #define FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos)
7507 #define FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos)
7508 #define FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos)
7510 #define FSMC_PCR2_ECCPS_Pos (17U)
7511 #define FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos)
7512 #define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk
7513 #define FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos)
7514 #define FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos)
7515 #define FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos)
7517 /****************** Bit definition for FSMC_PCR3 register *******************/
7518 #define FSMC_PCR3_PWAITEN_Pos (1U)
7519 #define FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos)
7520 #define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk
7521 #define FSMC_PCR3_PBKEN_Pos (2U)
7522 #define FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos)
7523 #define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk
7524 #define FSMC_PCR3_PTYP_Pos (3U)
7525 #define FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos)
7526 #define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk
7528 #define FSMC_PCR3_PWID_Pos (4U)
7529 #define FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos)
7530 #define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk
7531 #define FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos)
7532 #define FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos)
7534 #define FSMC_PCR3_ECCEN_Pos (6U)
7535 #define FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos)
7536 #define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk
7538 #define FSMC_PCR3_TCLR_Pos (9U)
7539 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos)
7540 #define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk
7541 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos)
7542 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos)
7543 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos)
7544 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos)
7546 #define FSMC_PCR3_TAR_Pos (13U)
7547 #define FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos)
7548 #define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk
7549 #define FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos)
7550 #define FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos)
7551 #define FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos)
7552 #define FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos)
7554 #define FSMC_PCR3_ECCPS_Pos (17U)
7555 #define FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos)
7556 #define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk
7557 #define FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos)
7558 #define FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos)
7559 #define FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos)
7561 /****************** Bit definition for FSMC_PCR4 register *******************/
7562 #define FSMC_PCR4_PWAITEN_Pos (1U)
7563 #define FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos)
7564 #define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk
7565 #define FSMC_PCR4_PBKEN_Pos (2U)
7566 #define FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos)
7567 #define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk
7568 #define FSMC_PCR4_PTYP_Pos (3U)
7569 #define FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos)
7570 #define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk
7572 #define FSMC_PCR4_PWID_Pos (4U)
7573 #define FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos)
7574 #define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk
7575 #define FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos)
7576 #define FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos)
7578 #define FSMC_PCR4_ECCEN_Pos (6U)
7579 #define FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos)
7580 #define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk
7582 #define FSMC_PCR4_TCLR_Pos (9U)
7583 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos)
7584 #define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk
7585 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos)
7586 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos)
7587 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos)
7588 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos)
7590 #define FSMC_PCR4_TAR_Pos (13U)
7591 #define FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos)
7592 #define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk
7593 #define FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos)
7594 #define FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos)
7595 #define FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos)
7596 #define FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos)
7598 #define FSMC_PCR4_ECCPS_Pos (17U)
7599 #define FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos)
7600 #define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk
7601 #define FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos)
7602 #define FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos)
7603 #define FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos)
7605 /******************* Bit definition for FSMC_SR2 register *******************/
7606 #define FSMC_SR2_IRS_Pos (0U)
7607 #define FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos)
7608 #define FSMC_SR2_IRS FSMC_SR2_IRS_Msk
7609 #define FSMC_SR2_ILS_Pos (1U)
7610 #define FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos)
7611 #define FSMC_SR2_ILS FSMC_SR2_ILS_Msk
7612 #define FSMC_SR2_IFS_Pos (2U)
7613 #define FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos)
7614 #define FSMC_SR2_IFS FSMC_SR2_IFS_Msk
7615 #define FSMC_SR2_IREN_Pos (3U)
7616 #define FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos)
7617 #define FSMC_SR2_IREN FSMC_SR2_IREN_Msk
7618 #define FSMC_SR2_ILEN_Pos (4U)
7619 #define FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos)
7620 #define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk
7621 #define FSMC_SR2_IFEN_Pos (5U)
7622 #define FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos)
7623 #define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk
7624 #define FSMC_SR2_FEMPT_Pos (6U)
7625 #define FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos)
7626 #define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk
7628 /******************* Bit definition for FSMC_SR3 register *******************/
7629 #define FSMC_SR3_IRS_Pos (0U)
7630 #define FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos)
7631 #define FSMC_SR3_IRS FSMC_SR3_IRS_Msk
7632 #define FSMC_SR3_ILS_Pos (1U)
7633 #define FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos)
7634 #define FSMC_SR3_ILS FSMC_SR3_ILS_Msk
7635 #define FSMC_SR3_IFS_Pos (2U)
7636 #define FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos)
7637 #define FSMC_SR3_IFS FSMC_SR3_IFS_Msk
7638 #define FSMC_SR3_IREN_Pos (3U)
7639 #define FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos)
7640 #define FSMC_SR3_IREN FSMC_SR3_IREN_Msk
7641 #define FSMC_SR3_ILEN_Pos (4U)
7642 #define FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos)
7643 #define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk
7644 #define FSMC_SR3_IFEN_Pos (5U)
7645 #define FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos)
7646 #define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk
7647 #define FSMC_SR3_FEMPT_Pos (6U)
7648 #define FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos)
7649 #define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk
7651 /******************* Bit definition for FSMC_SR4 register *******************/
7652 #define FSMC_SR4_IRS_Pos (0U)
7653 #define FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos)
7654 #define FSMC_SR4_IRS FSMC_SR4_IRS_Msk
7655 #define FSMC_SR4_ILS_Pos (1U)
7656 #define FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos)
7657 #define FSMC_SR4_ILS FSMC_SR4_ILS_Msk
7658 #define FSMC_SR4_IFS_Pos (2U)
7659 #define FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos)
7660 #define FSMC_SR4_IFS FSMC_SR4_IFS_Msk
7661 #define FSMC_SR4_IREN_Pos (3U)
7662 #define FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos)
7663 #define FSMC_SR4_IREN FSMC_SR4_IREN_Msk
7664 #define FSMC_SR4_ILEN_Pos (4U)
7665 #define FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos)
7666 #define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk
7667 #define FSMC_SR4_IFEN_Pos (5U)
7668 #define FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos)
7669 #define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk
7670 #define FSMC_SR4_FEMPT_Pos (6U)
7671 #define FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos)
7672 #define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk
7674 /****************** Bit definition for FSMC_PMEM2 register ******************/
7675 #define FSMC_PMEM2_MEMSET2_Pos (0U)
7676 #define FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
7677 #define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk
7678 #define FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
7679 #define FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
7680 #define FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
7681 #define FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
7682 #define FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
7683 #define FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
7684 #define FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
7685 #define FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
7687 #define FSMC_PMEM2_MEMWAIT2_Pos (8U)
7688 #define FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
7689 #define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk
7690 #define FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
7691 #define FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
7692 #define FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
7693 #define FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
7694 #define FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
7695 #define FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
7696 #define FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
7697 #define FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
7699 #define FSMC_PMEM2_MEMHOLD2_Pos (16U)
7700 #define FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
7701 #define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk
7702 #define FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
7703 #define FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
7704 #define FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
7705 #define FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
7706 #define FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
7707 #define FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
7708 #define FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
7709 #define FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
7711 #define FSMC_PMEM2_MEMHIZ2_Pos (24U)
7712 #define FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
7713 #define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk
7714 #define FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
7715 #define FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
7716 #define FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
7717 #define FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
7718 #define FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
7719 #define FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
7720 #define FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
7721 #define FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
7723 /****************** Bit definition for FSMC_PMEM3 register ******************/
7724 #define FSMC_PMEM3_MEMSET3_Pos (0U)
7725 #define FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
7726 #define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk
7727 #define FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
7728 #define FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
7729 #define FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
7730 #define FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
7731 #define FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
7732 #define FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
7733 #define FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
7734 #define FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
7736 #define FSMC_PMEM3_MEMWAIT3_Pos (8U)
7737 #define FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
7738 #define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk
7739 #define FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
7740 #define FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
7741 #define FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
7742 #define FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
7743 #define FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
7744 #define FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
7745 #define FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
7746 #define FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
7748 #define FSMC_PMEM3_MEMHOLD3_Pos (16U)
7749 #define FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
7750 #define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk
7751 #define FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
7752 #define FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
7753 #define FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
7754 #define FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
7755 #define FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
7756 #define FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
7757 #define FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
7758 #define FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
7760 #define FSMC_PMEM3_MEMHIZ3_Pos (24U)
7761 #define FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
7762 #define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk
7763 #define FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
7764 #define FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
7765 #define FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
7766 #define FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
7767 #define FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
7768 #define FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
7769 #define FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
7770 #define FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
7772 /****************** Bit definition for FSMC_PMEM4 register ******************/
7773 #define FSMC_PMEM4_MEMSET4_Pos (0U)
7774 #define FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
7775 #define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk
7776 #define FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
7777 #define FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
7778 #define FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
7779 #define FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
7780 #define FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
7781 #define FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
7782 #define FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
7783 #define FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
7785 #define FSMC_PMEM4_MEMWAIT4_Pos (8U)
7786 #define FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
7787 #define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk
7788 #define FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
7789 #define FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
7790 #define FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
7791 #define FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
7792 #define FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
7793 #define FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
7794 #define FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
7795 #define FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
7797 #define FSMC_PMEM4_MEMHOLD4_Pos (16U)
7798 #define FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
7799 #define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk
7800 #define FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
7801 #define FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
7802 #define FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
7803 #define FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
7804 #define FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
7805 #define FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
7806 #define FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
7807 #define FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
7809 #define FSMC_PMEM4_MEMHIZ4_Pos (24U)
7810 #define FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
7811 #define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk
7812 #define FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
7813 #define FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
7814 #define FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
7815 #define FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
7816 #define FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
7817 #define FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
7818 #define FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
7819 #define FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
7821 /****************** Bit definition for FSMC_PATT2 register ******************/
7822 #define FSMC_PATT2_ATTSET2_Pos (0U)
7823 #define FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
7824 #define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk
7825 #define FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos)
7826 #define FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos)
7827 #define FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos)
7828 #define FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos)
7829 #define FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos)
7830 #define FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos)
7831 #define FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos)
7832 #define FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos)
7834 #define FSMC_PATT2_ATTWAIT2_Pos (8U)
7835 #define FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
7836 #define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk
7837 #define FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
7838 #define FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
7839 #define FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
7840 #define FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
7841 #define FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
7842 #define FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
7843 #define FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
7844 #define FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
7846 #define FSMC_PATT2_ATTHOLD2_Pos (16U)
7847 #define FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
7848 #define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk
7849 #define FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
7850 #define FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
7851 #define FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
7852 #define FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
7853 #define FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
7854 #define FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
7855 #define FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
7856 #define FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
7858 #define FSMC_PATT2_ATTHIZ2_Pos (24U)
7859 #define FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
7860 #define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk
7861 #define FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
7862 #define FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
7863 #define FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
7864 #define FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
7865 #define FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
7866 #define FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
7867 #define FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
7868 #define FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
7870 /****************** Bit definition for FSMC_PATT3 register ******************/
7871 #define FSMC_PATT3_ATTSET3_Pos (0U)
7872 #define FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
7873 #define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk
7874 #define FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos)
7875 #define FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos)
7876 #define FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos)
7877 #define FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos)
7878 #define FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos)
7879 #define FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos)
7880 #define FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos)
7881 #define FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos)
7883 #define FSMC_PATT3_ATTWAIT3_Pos (8U)
7884 #define FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
7885 #define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk
7886 #define FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
7887 #define FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
7888 #define FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
7889 #define FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
7890 #define FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
7891 #define FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
7892 #define FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
7893 #define FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
7895 #define FSMC_PATT3_ATTHOLD3_Pos (16U)
7896 #define FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
7897 #define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk
7898 #define FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
7899 #define FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
7900 #define FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
7901 #define FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
7902 #define FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
7903 #define FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
7904 #define FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
7905 #define FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
7907 #define FSMC_PATT3_ATTHIZ3_Pos (24U)
7908 #define FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
7909 #define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk
7910 #define FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
7911 #define FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
7912 #define FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
7913 #define FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
7914 #define FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
7915 #define FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
7916 #define FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
7917 #define FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
7919 /****************** Bit definition for FSMC_PATT4 register ******************/
7920 #define FSMC_PATT4_ATTSET4_Pos (0U)
7921 #define FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
7922 #define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk
7923 #define FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos)
7924 #define FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos)
7925 #define FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos)
7926 #define FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos)
7927 #define FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos)
7928 #define FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos)
7929 #define FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos)
7930 #define FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos)
7932 #define FSMC_PATT4_ATTWAIT4_Pos (8U)
7933 #define FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
7934 #define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk
7935 #define FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
7936 #define FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
7937 #define FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
7938 #define FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
7939 #define FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
7940 #define FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
7941 #define FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
7942 #define FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
7944 #define FSMC_PATT4_ATTHOLD4_Pos (16U)
7945 #define FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
7946 #define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk
7947 #define FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
7948 #define FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
7949 #define FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
7950 #define FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
7951 #define FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
7952 #define FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
7953 #define FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
7954 #define FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
7956 #define FSMC_PATT4_ATTHIZ4_Pos (24U)
7957 #define FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
7958 #define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk
7959 #define FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
7960 #define FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
7961 #define FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
7962 #define FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
7963 #define FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
7964 #define FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
7965 #define FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
7966 #define FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
7968 /****************** Bit definition for FSMC_PIO4 register *******************/
7969 #define FSMC_PIO4_IOSET4_Pos (0U)
7970 #define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos)
7971 #define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk
7972 #define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos)
7973 #define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos)
7974 #define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos)
7975 #define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos)
7976 #define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos)
7977 #define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos)
7978 #define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos)
7979 #define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos)
7981 #define FSMC_PIO4_IOWAIT4_Pos (8U)
7982 #define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
7983 #define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk
7984 #define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
7985 #define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
7986 #define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
7987 #define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
7988 #define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
7989 #define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
7990 #define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
7991 #define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
7993 #define FSMC_PIO4_IOHOLD4_Pos (16U)
7994 #define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
7995 #define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk
7996 #define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
7997 #define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
7998 #define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
7999 #define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
8000 #define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
8001 #define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
8002 #define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
8003 #define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
8005 #define FSMC_PIO4_IOHIZ4_Pos (24U)
8006 #define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
8007 #define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk
8008 #define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
8009 #define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
8010 #define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
8011 #define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
8012 #define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
8013 #define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
8014 #define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
8015 #define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
8017 /****************** Bit definition for FSMC_ECCR2 register ******************/
8018 #define FSMC_ECCR2_ECC2_Pos (0U)
8019 #define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
8020 #define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk
8022 /****************** Bit definition for FSMC_ECCR3 register ******************/
8023 #define FSMC_ECCR3_ECC3_Pos (0U)
8024 #define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
8025 #define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk
8027 /******************************************************************************/
8028 /* */
8029 /* General Purpose I/O */
8030 /* */
8031 /******************************************************************************/
8032 /****************** Bits definition for GPIO_MODER register *****************/
8033 #define GPIO_MODER_MODER0_Pos (0U)
8034 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
8035 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8036 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
8037 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
8038 #define GPIO_MODER_MODER1_Pos (2U)
8039 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
8040 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8041 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
8042 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
8043 #define GPIO_MODER_MODER2_Pos (4U)
8044 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
8045 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8046 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
8047 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
8048 #define GPIO_MODER_MODER3_Pos (6U)
8049 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
8050 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8051 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
8052 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
8053 #define GPIO_MODER_MODER4_Pos (8U)
8054 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
8055 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8056 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
8057 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
8058 #define GPIO_MODER_MODER5_Pos (10U)
8059 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
8060 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8061 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
8062 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
8063 #define GPIO_MODER_MODER6_Pos (12U)
8064 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
8065 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8066 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
8067 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
8068 #define GPIO_MODER_MODER7_Pos (14U)
8069 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
8070 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8071 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
8072 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
8073 #define GPIO_MODER_MODER8_Pos (16U)
8074 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
8075 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8076 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
8077 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
8078 #define GPIO_MODER_MODER9_Pos (18U)
8079 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
8080 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8081 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
8082 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
8083 #define GPIO_MODER_MODER10_Pos (20U)
8084 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
8085 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8086 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
8087 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
8088 #define GPIO_MODER_MODER11_Pos (22U)
8089 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
8090 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8091 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
8092 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
8093 #define GPIO_MODER_MODER12_Pos (24U)
8094 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
8095 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8096 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
8097 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
8098 #define GPIO_MODER_MODER13_Pos (26U)
8099 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
8100 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8101 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
8102 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
8103 #define GPIO_MODER_MODER14_Pos (28U)
8104 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
8105 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8106 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
8107 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
8108 #define GPIO_MODER_MODER15_Pos (30U)
8109 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
8110 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8111 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
8112 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
8114 /* Legacy defines */
8115 #define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
8116 #define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
8117 #define GPIO_MODER_MODE0 GPIO_MODER_MODER0
8118 #define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
8119 #define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
8120 #define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
8121 #define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
8122 #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
8123 #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
8124 #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
8125 #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
8126 #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
8127 #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
8128 #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
8129 #define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
8130 #define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
8131 #define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
8132 #define GPIO_MODER_MODE3 GPIO_MODER_MODER3
8133 #define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
8134 #define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
8135 #define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
8136 #define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
8137 #define GPIO_MODER_MODE4 GPIO_MODER_MODER4
8138 #define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
8139 #define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
8140 #define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
8141 #define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
8142 #define GPIO_MODER_MODE5 GPIO_MODER_MODER5
8143 #define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
8144 #define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
8145 #define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
8146 #define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
8147 #define GPIO_MODER_MODE6 GPIO_MODER_MODER6
8148 #define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
8149 #define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
8150 #define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
8151 #define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
8152 #define GPIO_MODER_MODE7 GPIO_MODER_MODER7
8153 #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
8154 #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
8155 #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
8156 #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
8157 #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
8158 #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
8159 #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
8160 #define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
8161 #define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
8162 #define GPIO_MODER_MODE9 GPIO_MODER_MODER9
8163 #define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
8164 #define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
8165 #define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
8166 #define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
8167 #define GPIO_MODER_MODE10 GPIO_MODER_MODER10
8168 #define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
8169 #define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
8170 #define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
8171 #define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
8172 #define GPIO_MODER_MODE11 GPIO_MODER_MODER11
8173 #define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
8174 #define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
8175 #define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
8176 #define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
8177 #define GPIO_MODER_MODE12 GPIO_MODER_MODER12
8178 #define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
8179 #define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
8180 #define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
8181 #define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
8182 #define GPIO_MODER_MODE13 GPIO_MODER_MODER13
8183 #define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
8184 #define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
8185 #define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
8186 #define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
8187 #define GPIO_MODER_MODE14 GPIO_MODER_MODER14
8188 #define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
8189 #define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
8190 #define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
8191 #define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
8192 #define GPIO_MODER_MODE15 GPIO_MODER_MODER15
8193 #define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
8194 #define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
8195 
8196 /****************** Bits definition for GPIO_OTYPER register ****************/
8197 #define GPIO_OTYPER_OT0_Pos (0U)
8198 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
8199 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8200 #define GPIO_OTYPER_OT1_Pos (1U)
8201 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
8202 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8203 #define GPIO_OTYPER_OT2_Pos (2U)
8204 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
8205 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8206 #define GPIO_OTYPER_OT3_Pos (3U)
8207 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
8208 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8209 #define GPIO_OTYPER_OT4_Pos (4U)
8210 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
8211 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8212 #define GPIO_OTYPER_OT5_Pos (5U)
8213 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
8214 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8215 #define GPIO_OTYPER_OT6_Pos (6U)
8216 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
8217 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8218 #define GPIO_OTYPER_OT7_Pos (7U)
8219 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
8220 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8221 #define GPIO_OTYPER_OT8_Pos (8U)
8222 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
8223 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8224 #define GPIO_OTYPER_OT9_Pos (9U)
8225 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
8226 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8227 #define GPIO_OTYPER_OT10_Pos (10U)
8228 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
8229 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8230 #define GPIO_OTYPER_OT11_Pos (11U)
8231 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
8232 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8233 #define GPIO_OTYPER_OT12_Pos (12U)
8234 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
8235 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8236 #define GPIO_OTYPER_OT13_Pos (13U)
8237 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
8238 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8239 #define GPIO_OTYPER_OT14_Pos (14U)
8240 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
8241 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8242 #define GPIO_OTYPER_OT15_Pos (15U)
8243 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
8244 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8245 
8246 /* Legacy defines */
8247 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8248 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8249 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8250 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8251 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8252 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8253 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8254 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8255 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8256 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8257 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8258 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8259 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8260 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8261 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8262 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8263 
8264 /****************** Bits definition for GPIO_OSPEEDR register ***************/
8265 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8266 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
8267 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8268 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
8269 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
8270 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8271 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
8272 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8273 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
8274 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
8275 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8276 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
8277 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8278 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
8279 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
8280 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8281 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
8282 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8283 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
8284 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
8285 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8286 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
8287 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8288 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
8289 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
8290 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8291 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
8292 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8293 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
8294 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
8295 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8296 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
8297 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8298 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
8299 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
8300 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8301 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
8302 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8303 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
8304 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
8305 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8306 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
8307 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8308 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
8309 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
8310 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8311 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
8312 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8313 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
8314 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
8315 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8316 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
8317 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8318 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
8319 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
8320 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8321 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
8322 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8323 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
8324 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
8325 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8326 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
8327 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8328 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
8329 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
8330 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8331 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
8332 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8333 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
8334 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
8335 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8336 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
8337 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8338 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
8339 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
8340 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8341 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
8342 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8343 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
8344 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
8346 /* Legacy defines */
8347 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8348 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8349 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8350 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8351 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8352 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8353 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8354 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8355 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8356 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8357 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8358 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8359 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8360 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8361 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8362 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8363 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8364 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8365 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8366 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8367 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8368 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8369 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8370 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8371 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8372 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8373 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8374 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8375 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8376 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8377 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8378 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8379 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8380 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8381 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8382 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8383 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8384 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8385 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8386 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8387 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8388 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8389 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8390 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8391 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8392 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8393 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8394 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8395 
8396 /****************** Bits definition for GPIO_PUPDR register *****************/
8397 #define GPIO_PUPDR_PUPD0_Pos (0U)
8398 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
8399 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8400 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
8401 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
8402 #define GPIO_PUPDR_PUPD1_Pos (2U)
8403 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
8404 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8405 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
8406 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
8407 #define GPIO_PUPDR_PUPD2_Pos (4U)
8408 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
8409 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8410 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
8411 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
8412 #define GPIO_PUPDR_PUPD3_Pos (6U)
8413 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
8414 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8415 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
8416 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
8417 #define GPIO_PUPDR_PUPD4_Pos (8U)
8418 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
8419 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8420 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
8421 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
8422 #define GPIO_PUPDR_PUPD5_Pos (10U)
8423 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
8424 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8425 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
8426 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
8427 #define GPIO_PUPDR_PUPD6_Pos (12U)
8428 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
8429 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8430 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
8431 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
8432 #define GPIO_PUPDR_PUPD7_Pos (14U)
8433 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
8434 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8435 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
8436 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
8437 #define GPIO_PUPDR_PUPD8_Pos (16U)
8438 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
8439 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8440 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
8441 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
8442 #define GPIO_PUPDR_PUPD9_Pos (18U)
8443 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
8444 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8445 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
8446 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
8447 #define GPIO_PUPDR_PUPD10_Pos (20U)
8448 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
8449 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8450 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
8451 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
8452 #define GPIO_PUPDR_PUPD11_Pos (22U)
8453 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
8454 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8455 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
8456 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
8457 #define GPIO_PUPDR_PUPD12_Pos (24U)
8458 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
8459 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8460 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
8461 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
8462 #define GPIO_PUPDR_PUPD13_Pos (26U)
8463 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
8464 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8465 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
8466 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
8467 #define GPIO_PUPDR_PUPD14_Pos (28U)
8468 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
8469 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8470 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
8471 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
8472 #define GPIO_PUPDR_PUPD15_Pos (30U)
8473 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
8474 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8475 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
8476 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
8478 /* Legacy defines */
8479 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8480 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8481 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8482 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8483 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8484 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8485 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8486 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8487 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8488 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8489 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8490 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8491 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8492 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8493 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8494 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8495 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8496 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8497 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8498 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8499 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8500 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8501 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8502 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8503 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8504 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8505 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8506 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8507 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8508 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8509 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8510 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8511 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8512 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8513 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8514 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8515 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8516 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8517 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8518 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8519 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8520 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8521 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8522 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8523 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8524 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8525 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8526 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8527 
8528 /****************** Bits definition for GPIO_IDR register *******************/
8529 #define GPIO_IDR_ID0_Pos (0U)
8530 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8531 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8532 #define GPIO_IDR_ID1_Pos (1U)
8533 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8534 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8535 #define GPIO_IDR_ID2_Pos (2U)
8536 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8537 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8538 #define GPIO_IDR_ID3_Pos (3U)
8539 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8540 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8541 #define GPIO_IDR_ID4_Pos (4U)
8542 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8543 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8544 #define GPIO_IDR_ID5_Pos (5U)
8545 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8546 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8547 #define GPIO_IDR_ID6_Pos (6U)
8548 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8549 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8550 #define GPIO_IDR_ID7_Pos (7U)
8551 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8552 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8553 #define GPIO_IDR_ID8_Pos (8U)
8554 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8555 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8556 #define GPIO_IDR_ID9_Pos (9U)
8557 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8558 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8559 #define GPIO_IDR_ID10_Pos (10U)
8560 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8561 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8562 #define GPIO_IDR_ID11_Pos (11U)
8563 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8564 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8565 #define GPIO_IDR_ID12_Pos (12U)
8566 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8567 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8568 #define GPIO_IDR_ID13_Pos (13U)
8569 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8570 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8571 #define GPIO_IDR_ID14_Pos (14U)
8572 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8573 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8574 #define GPIO_IDR_ID15_Pos (15U)
8575 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8576 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8577 
8578 /* Legacy defines */
8579 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8580 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8581 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8582 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8583 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8584 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8585 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8586 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8587 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8588 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8589 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8590 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8591 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8592 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8593 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8594 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8595 
8596 /****************** Bits definition for GPIO_ODR register *******************/
8597 #define GPIO_ODR_OD0_Pos (0U)
8598 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8599 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8600 #define GPIO_ODR_OD1_Pos (1U)
8601 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8602 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8603 #define GPIO_ODR_OD2_Pos (2U)
8604 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8605 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8606 #define GPIO_ODR_OD3_Pos (3U)
8607 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8608 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8609 #define GPIO_ODR_OD4_Pos (4U)
8610 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8611 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8612 #define GPIO_ODR_OD5_Pos (5U)
8613 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8614 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8615 #define GPIO_ODR_OD6_Pos (6U)
8616 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8617 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8618 #define GPIO_ODR_OD7_Pos (7U)
8619 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8620 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8621 #define GPIO_ODR_OD8_Pos (8U)
8622 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8623 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8624 #define GPIO_ODR_OD9_Pos (9U)
8625 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8626 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8627 #define GPIO_ODR_OD10_Pos (10U)
8628 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8629 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8630 #define GPIO_ODR_OD11_Pos (11U)
8631 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8632 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8633 #define GPIO_ODR_OD12_Pos (12U)
8634 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8635 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8636 #define GPIO_ODR_OD13_Pos (13U)
8637 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8638 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8639 #define GPIO_ODR_OD14_Pos (14U)
8640 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8641 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8642 #define GPIO_ODR_OD15_Pos (15U)
8643 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8644 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8645 /* Legacy defines */
8646 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8647 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8648 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8649 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8650 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8651 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8652 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8653 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8654 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8655 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8656 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8657 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8658 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8659 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8660 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8661 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8662 
8663 /****************** Bits definition for GPIO_BSRR register ******************/
8664 #define GPIO_BSRR_BS0_Pos (0U)
8665 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8666 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8667 #define GPIO_BSRR_BS1_Pos (1U)
8668 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8669 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8670 #define GPIO_BSRR_BS2_Pos (2U)
8671 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8672 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8673 #define GPIO_BSRR_BS3_Pos (3U)
8674 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8675 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8676 #define GPIO_BSRR_BS4_Pos (4U)
8677 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8678 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8679 #define GPIO_BSRR_BS5_Pos (5U)
8680 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8681 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8682 #define GPIO_BSRR_BS6_Pos (6U)
8683 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8684 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8685 #define GPIO_BSRR_BS7_Pos (7U)
8686 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8687 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8688 #define GPIO_BSRR_BS8_Pos (8U)
8689 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8690 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8691 #define GPIO_BSRR_BS9_Pos (9U)
8692 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8693 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8694 #define GPIO_BSRR_BS10_Pos (10U)
8695 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8696 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8697 #define GPIO_BSRR_BS11_Pos (11U)
8698 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8699 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8700 #define GPIO_BSRR_BS12_Pos (12U)
8701 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8702 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8703 #define GPIO_BSRR_BS13_Pos (13U)
8704 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8705 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8706 #define GPIO_BSRR_BS14_Pos (14U)
8707 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8708 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8709 #define GPIO_BSRR_BS15_Pos (15U)
8710 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8711 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8712 #define GPIO_BSRR_BR0_Pos (16U)
8713 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8714 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8715 #define GPIO_BSRR_BR1_Pos (17U)
8716 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8717 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8718 #define GPIO_BSRR_BR2_Pos (18U)
8719 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8720 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8721 #define GPIO_BSRR_BR3_Pos (19U)
8722 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8723 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8724 #define GPIO_BSRR_BR4_Pos (20U)
8725 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8726 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8727 #define GPIO_BSRR_BR5_Pos (21U)
8728 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8729 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8730 #define GPIO_BSRR_BR6_Pos (22U)
8731 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8732 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8733 #define GPIO_BSRR_BR7_Pos (23U)
8734 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8735 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8736 #define GPIO_BSRR_BR8_Pos (24U)
8737 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8738 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8739 #define GPIO_BSRR_BR9_Pos (25U)
8740 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8741 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8742 #define GPIO_BSRR_BR10_Pos (26U)
8743 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8744 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8745 #define GPIO_BSRR_BR11_Pos (27U)
8746 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8747 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8748 #define GPIO_BSRR_BR12_Pos (28U)
8749 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8750 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8751 #define GPIO_BSRR_BR13_Pos (29U)
8752 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8753 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8754 #define GPIO_BSRR_BR14_Pos (30U)
8755 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8756 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8757 #define GPIO_BSRR_BR15_Pos (31U)
8758 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8759 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8760 
8761 /* Legacy defines */
8762 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8763 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8764 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8765 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8766 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8767 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8768 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8769 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8770 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8771 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8772 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8773 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8774 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8775 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8776 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8777 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8778 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8779 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8780 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8781 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8782 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8783 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8784 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8785 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8786 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8787 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8788 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8789 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8790 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8791 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8792 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8793 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8794 #define GPIO_BRR_BR0 GPIO_BSRR_BR0
8795 #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
8796 #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
8797 #define GPIO_BRR_BR1 GPIO_BSRR_BR1
8798 #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
8799 #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
8800 #define GPIO_BRR_BR2 GPIO_BSRR_BR2
8801 #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
8802 #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
8803 #define GPIO_BRR_BR3 GPIO_BSRR_BR3
8804 #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
8805 #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
8806 #define GPIO_BRR_BR4 GPIO_BSRR_BR4
8807 #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
8808 #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
8809 #define GPIO_BRR_BR5 GPIO_BSRR_BR5
8810 #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
8811 #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
8812 #define GPIO_BRR_BR6 GPIO_BSRR_BR6
8813 #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
8814 #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
8815 #define GPIO_BRR_BR7 GPIO_BSRR_BR7
8816 #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
8817 #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
8818 #define GPIO_BRR_BR8 GPIO_BSRR_BR8
8819 #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
8820 #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
8821 #define GPIO_BRR_BR9 GPIO_BSRR_BR9
8822 #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
8823 #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
8824 #define GPIO_BRR_BR10 GPIO_BSRR_BR10
8825 #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
8826 #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
8827 #define GPIO_BRR_BR11 GPIO_BSRR_BR11
8828 #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
8829 #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
8830 #define GPIO_BRR_BR12 GPIO_BSRR_BR12
8831 #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
8832 #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
8833 #define GPIO_BRR_BR13 GPIO_BSRR_BR13
8834 #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
8835 #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
8836 #define GPIO_BRR_BR14 GPIO_BSRR_BR14
8837 #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
8838 #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
8839 #define GPIO_BRR_BR15 GPIO_BSRR_BR15
8840 #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
8841 #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
8842 /****************** Bit definition for GPIO_LCKR register *********************/
8843 #define GPIO_LCKR_LCK0_Pos (0U)
8844 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8845 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8846 #define GPIO_LCKR_LCK1_Pos (1U)
8847 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8848 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8849 #define GPIO_LCKR_LCK2_Pos (2U)
8850 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8851 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8852 #define GPIO_LCKR_LCK3_Pos (3U)
8853 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8854 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8855 #define GPIO_LCKR_LCK4_Pos (4U)
8856 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8857 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8858 #define GPIO_LCKR_LCK5_Pos (5U)
8859 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8860 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8861 #define GPIO_LCKR_LCK6_Pos (6U)
8862 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8863 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8864 #define GPIO_LCKR_LCK7_Pos (7U)
8865 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8866 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8867 #define GPIO_LCKR_LCK8_Pos (8U)
8868 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8869 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8870 #define GPIO_LCKR_LCK9_Pos (9U)
8871 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8872 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8873 #define GPIO_LCKR_LCK10_Pos (10U)
8874 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8875 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8876 #define GPIO_LCKR_LCK11_Pos (11U)
8877 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8878 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8879 #define GPIO_LCKR_LCK12_Pos (12U)
8880 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8881 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8882 #define GPIO_LCKR_LCK13_Pos (13U)
8883 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8884 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8885 #define GPIO_LCKR_LCK14_Pos (14U)
8886 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8887 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8888 #define GPIO_LCKR_LCK15_Pos (15U)
8889 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8890 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8891 #define GPIO_LCKR_LCKK_Pos (16U)
8892 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8893 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8894 /****************** Bit definition for GPIO_AFRL register *********************/
8895 #define GPIO_AFRL_AFSEL0_Pos (0U)
8896 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8897 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8898 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8899 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8900 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8901 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8902 #define GPIO_AFRL_AFSEL1_Pos (4U)
8903 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8904 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8905 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8906 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8907 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8908 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8909 #define GPIO_AFRL_AFSEL2_Pos (8U)
8910 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8911 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8912 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8913 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8914 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8915 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8916 #define GPIO_AFRL_AFSEL3_Pos (12U)
8917 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8918 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8919 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8920 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8921 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8922 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8923 #define GPIO_AFRL_AFSEL4_Pos (16U)
8924 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8925 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8926 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8927 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8928 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8929 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8930 #define GPIO_AFRL_AFSEL5_Pos (20U)
8931 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8932 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8933 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8934 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8935 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8936 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8937 #define GPIO_AFRL_AFSEL6_Pos (24U)
8938 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8939 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8940 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
8941 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
8942 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
8943 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
8944 #define GPIO_AFRL_AFSEL7_Pos (28U)
8945 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
8946 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8947 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
8948 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
8949 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
8950 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
8952 /* Legacy defines */
8953 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8954 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8955 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8956 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8957 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8958 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8959 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8960 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8961 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8962 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8963 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8964 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8965 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8966 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8967 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8968 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8969 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8970 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8971 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8972 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8973 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8974 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8975 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8976 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8977 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8978 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8979 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8980 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8981 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8982 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8983 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8984 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8985 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8986 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8987 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8988 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8989 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8990 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8991 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8992 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8993 
8994 /****************** Bit definition for GPIO_AFRH register *********************/
8995 #define GPIO_AFRH_AFSEL8_Pos (0U)
8996 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
8997 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8998 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
8999 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
9000 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
9001 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
9002 #define GPIO_AFRH_AFSEL9_Pos (4U)
9003 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
9004 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9005 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
9006 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
9007 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
9008 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
9009 #define GPIO_AFRH_AFSEL10_Pos (8U)
9010 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
9011 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9012 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
9013 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
9014 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
9015 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
9016 #define GPIO_AFRH_AFSEL11_Pos (12U)
9017 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
9018 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9019 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
9020 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
9021 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
9022 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
9023 #define GPIO_AFRH_AFSEL12_Pos (16U)
9024 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
9025 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9026 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
9027 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
9028 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
9029 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
9030 #define GPIO_AFRH_AFSEL13_Pos (20U)
9031 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
9032 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9033 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
9034 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
9035 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
9036 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
9037 #define GPIO_AFRH_AFSEL14_Pos (24U)
9038 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
9039 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9040 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
9041 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
9042 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
9043 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
9044 #define GPIO_AFRH_AFSEL15_Pos (28U)
9045 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
9046 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9047 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
9048 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
9049 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
9050 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
9052 /* Legacy defines */
9053 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9054 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9055 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9056 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9057 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9058 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9059 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9060 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9061 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9062 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9063 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9064 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9065 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9066 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9067 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9068 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9069 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9070 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9071 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9072 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
9073 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9074 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
9075 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
9076 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
9077 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
9078 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9079 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
9080 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
9081 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
9082 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
9083 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9084 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
9085 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
9086 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
9087 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
9088 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9089 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
9090 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
9091 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
9092 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
9093 
9094 
9095 /******************************************************************************/
9096 /* */
9097 /* Inter-integrated Circuit Interface */
9098 /* */
9099 /******************************************************************************/
9100 /******************* Bit definition for I2C_CR1 register ********************/
9101 #define I2C_CR1_PE_Pos (0U)
9102 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9103 #define I2C_CR1_PE I2C_CR1_PE_Msk
9104 #define I2C_CR1_SMBUS_Pos (1U)
9105 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
9106 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
9107 #define I2C_CR1_SMBTYPE_Pos (3U)
9108 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
9109 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
9110 #define I2C_CR1_ENARP_Pos (4U)
9111 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
9112 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
9113 #define I2C_CR1_ENPEC_Pos (5U)
9114 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
9115 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
9116 #define I2C_CR1_ENGC_Pos (6U)
9117 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
9118 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
9119 #define I2C_CR1_NOSTRETCH_Pos (7U)
9120 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9121 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9122 #define I2C_CR1_START_Pos (8U)
9123 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
9124 #define I2C_CR1_START I2C_CR1_START_Msk
9125 #define I2C_CR1_STOP_Pos (9U)
9126 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
9127 #define I2C_CR1_STOP I2C_CR1_STOP_Msk
9128 #define I2C_CR1_ACK_Pos (10U)
9129 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
9130 #define I2C_CR1_ACK I2C_CR1_ACK_Msk
9131 #define I2C_CR1_POS_Pos (11U)
9132 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
9133 #define I2C_CR1_POS I2C_CR1_POS_Msk
9134 #define I2C_CR1_PEC_Pos (12U)
9135 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
9136 #define I2C_CR1_PEC I2C_CR1_PEC_Msk
9137 #define I2C_CR1_ALERT_Pos (13U)
9138 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
9139 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
9140 #define I2C_CR1_SWRST_Pos (15U)
9141 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
9142 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
9144 /******************* Bit definition for I2C_CR2 register ********************/
9145 #define I2C_CR2_FREQ_Pos (0U)
9146 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
9147 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
9148 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
9149 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
9150 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
9151 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
9152 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
9153 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
9155 #define I2C_CR2_ITERREN_Pos (8U)
9156 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
9157 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
9158 #define I2C_CR2_ITEVTEN_Pos (9U)
9159 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
9160 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
9161 #define I2C_CR2_ITBUFEN_Pos (10U)
9162 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
9163 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
9164 #define I2C_CR2_DMAEN_Pos (11U)
9165 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
9166 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
9167 #define I2C_CR2_LAST_Pos (12U)
9168 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
9169 #define I2C_CR2_LAST I2C_CR2_LAST_Msk
9171 /******************* Bit definition for I2C_OAR1 register *******************/
9172 #define I2C_OAR1_ADD1_7 0x000000FEU
9173 #define I2C_OAR1_ADD8_9 0x00000300U
9175 #define I2C_OAR1_ADD0_Pos (0U)
9176 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
9177 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
9178 #define I2C_OAR1_ADD1_Pos (1U)
9179 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
9180 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
9181 #define I2C_OAR1_ADD2_Pos (2U)
9182 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
9183 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
9184 #define I2C_OAR1_ADD3_Pos (3U)
9185 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
9186 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
9187 #define I2C_OAR1_ADD4_Pos (4U)
9188 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
9189 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
9190 #define I2C_OAR1_ADD5_Pos (5U)
9191 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
9192 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
9193 #define I2C_OAR1_ADD6_Pos (6U)
9194 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
9195 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
9196 #define I2C_OAR1_ADD7_Pos (7U)
9197 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
9198 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
9199 #define I2C_OAR1_ADD8_Pos (8U)
9200 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
9201 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
9202 #define I2C_OAR1_ADD9_Pos (9U)
9203 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
9204 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
9206 #define I2C_OAR1_ADDMODE_Pos (15U)
9207 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
9208 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
9210 /******************* Bit definition for I2C_OAR2 register *******************/
9211 #define I2C_OAR2_ENDUAL_Pos (0U)
9212 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
9213 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
9214 #define I2C_OAR2_ADD2_Pos (1U)
9215 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
9216 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
9218 /******************** Bit definition for I2C_DR register ********************/
9219 #define I2C_DR_DR_Pos (0U)
9220 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
9221 #define I2C_DR_DR I2C_DR_DR_Msk
9223 /******************* Bit definition for I2C_SR1 register ********************/
9224 #define I2C_SR1_SB_Pos (0U)
9225 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
9226 #define I2C_SR1_SB I2C_SR1_SB_Msk
9227 #define I2C_SR1_ADDR_Pos (1U)
9228 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
9229 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
9230 #define I2C_SR1_BTF_Pos (2U)
9231 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
9232 #define I2C_SR1_BTF I2C_SR1_BTF_Msk
9233 #define I2C_SR1_ADD10_Pos (3U)
9234 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
9235 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
9236 #define I2C_SR1_STOPF_Pos (4U)
9237 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
9238 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
9239 #define I2C_SR1_RXNE_Pos (6U)
9240 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
9241 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
9242 #define I2C_SR1_TXE_Pos (7U)
9243 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
9244 #define I2C_SR1_TXE I2C_SR1_TXE_Msk
9245 #define I2C_SR1_BERR_Pos (8U)
9246 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
9247 #define I2C_SR1_BERR I2C_SR1_BERR_Msk
9248 #define I2C_SR1_ARLO_Pos (9U)
9249 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
9250 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
9251 #define I2C_SR1_AF_Pos (10U)
9252 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
9253 #define I2C_SR1_AF I2C_SR1_AF_Msk
9254 #define I2C_SR1_OVR_Pos (11U)
9255 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
9256 #define I2C_SR1_OVR I2C_SR1_OVR_Msk
9257 #define I2C_SR1_PECERR_Pos (12U)
9258 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
9259 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
9260 #define I2C_SR1_TIMEOUT_Pos (14U)
9261 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
9262 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
9263 #define I2C_SR1_SMBALERT_Pos (15U)
9264 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
9265 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
9267 /******************* Bit definition for I2C_SR2 register ********************/
9268 #define I2C_SR2_MSL_Pos (0U)
9269 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
9270 #define I2C_SR2_MSL I2C_SR2_MSL_Msk
9271 #define I2C_SR2_BUSY_Pos (1U)
9272 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
9273 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
9274 #define I2C_SR2_TRA_Pos (2U)
9275 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
9276 #define I2C_SR2_TRA I2C_SR2_TRA_Msk
9277 #define I2C_SR2_GENCALL_Pos (4U)
9278 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
9279 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
9280 #define I2C_SR2_SMBDEFAULT_Pos (5U)
9281 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
9282 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
9283 #define I2C_SR2_SMBHOST_Pos (6U)
9284 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
9285 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
9286 #define I2C_SR2_DUALF_Pos (7U)
9287 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
9288 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
9289 #define I2C_SR2_PEC_Pos (8U)
9290 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
9291 #define I2C_SR2_PEC I2C_SR2_PEC_Msk
9293 /******************* Bit definition for I2C_CCR register ********************/
9294 #define I2C_CCR_CCR_Pos (0U)
9295 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
9296 #define I2C_CCR_CCR I2C_CCR_CCR_Msk
9297 #define I2C_CCR_DUTY_Pos (14U)
9298 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
9299 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
9300 #define I2C_CCR_FS_Pos (15U)
9301 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
9302 #define I2C_CCR_FS I2C_CCR_FS_Msk
9304 /****************** Bit definition for I2C_TRISE register *******************/
9305 #define I2C_TRISE_TRISE_Pos (0U)
9306 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
9307 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
9310 /******************************************************************************/
9311 /* */
9312 /* Independent WATCHDOG */
9313 /* */
9314 /******************************************************************************/
9315 /******************* Bit definition for IWDG_KR register ********************/
9316 #define IWDG_KR_KEY_Pos (0U)
9317 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9318 #define IWDG_KR_KEY IWDG_KR_KEY_Msk
9320 /******************* Bit definition for IWDG_PR register ********************/
9321 #define IWDG_PR_PR_Pos (0U)
9322 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9323 #define IWDG_PR_PR IWDG_PR_PR_Msk
9324 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9325 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9326 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9328 /******************* Bit definition for IWDG_RLR register *******************/
9329 #define IWDG_RLR_RL_Pos (0U)
9330 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9331 #define IWDG_RLR_RL IWDG_RLR_RL_Msk
9333 /******************* Bit definition for IWDG_SR register ********************/
9334 #define IWDG_SR_PVU_Pos (0U)
9335 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9336 #define IWDG_SR_PVU IWDG_SR_PVU_Msk
9337 #define IWDG_SR_RVU_Pos (1U)
9338 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9339 #define IWDG_SR_RVU IWDG_SR_RVU_Msk
9343 /******************************************************************************/
9344 /* */
9345 /* Power Control */
9346 /* */
9347 /******************************************************************************/
9348 /******************** Bit definition for PWR_CR register ********************/
9349 #define PWR_CR_LPDS_Pos (0U)
9350 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
9351 #define PWR_CR_LPDS PWR_CR_LPDS_Msk
9352 #define PWR_CR_PDDS_Pos (1U)
9353 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
9354 #define PWR_CR_PDDS PWR_CR_PDDS_Msk
9355 #define PWR_CR_CWUF_Pos (2U)
9356 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
9357 #define PWR_CR_CWUF PWR_CR_CWUF_Msk
9358 #define PWR_CR_CSBF_Pos (3U)
9359 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
9360 #define PWR_CR_CSBF PWR_CR_CSBF_Msk
9361 #define PWR_CR_PVDE_Pos (4U)
9362 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
9363 #define PWR_CR_PVDE PWR_CR_PVDE_Msk
9365 #define PWR_CR_PLS_Pos (5U)
9366 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
9367 #define PWR_CR_PLS PWR_CR_PLS_Msk
9368 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
9369 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
9370 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
9373 #define PWR_CR_PLS_LEV0 0x00000000U
9374 #define PWR_CR_PLS_LEV1 0x00000020U
9375 #define PWR_CR_PLS_LEV2 0x00000040U
9376 #define PWR_CR_PLS_LEV3 0x00000060U
9377 #define PWR_CR_PLS_LEV4 0x00000080U
9378 #define PWR_CR_PLS_LEV5 0x000000A0U
9379 #define PWR_CR_PLS_LEV6 0x000000C0U
9380 #define PWR_CR_PLS_LEV7 0x000000E0U
9381 #define PWR_CR_DBP_Pos (8U)
9382 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
9383 #define PWR_CR_DBP PWR_CR_DBP_Msk
9384 #define PWR_CR_FPDS_Pos (9U)
9385 #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
9386 #define PWR_CR_FPDS PWR_CR_FPDS_Msk
9387 #define PWR_CR_VOS_Pos (14U)
9388 #define PWR_CR_VOS_Msk (0x1UL << PWR_CR_VOS_Pos)
9389 #define PWR_CR_VOS PWR_CR_VOS_Msk
9391 /* Legacy define */
9392 #define PWR_CR_PMODE PWR_CR_VOS
9393 
9394 /******************* Bit definition for PWR_CSR register ********************/
9395 #define PWR_CSR_WUF_Pos (0U)
9396 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
9397 #define PWR_CSR_WUF PWR_CSR_WUF_Msk
9398 #define PWR_CSR_SBF_Pos (1U)
9399 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
9400 #define PWR_CSR_SBF PWR_CSR_SBF_Msk
9401 #define PWR_CSR_PVDO_Pos (2U)
9402 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
9403 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
9404 #define PWR_CSR_BRR_Pos (3U)
9405 #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
9406 #define PWR_CSR_BRR PWR_CSR_BRR_Msk
9407 #define PWR_CSR_EWUP_Pos (8U)
9408 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
9409 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
9410 #define PWR_CSR_BRE_Pos (9U)
9411 #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
9412 #define PWR_CSR_BRE PWR_CSR_BRE_Msk
9413 #define PWR_CSR_VOSRDY_Pos (14U)
9414 #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
9415 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
9417 /* Legacy define */
9418 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
9419 
9420 /******************************************************************************/
9421 /* */
9422 /* Reset and Clock Control */
9423 /* */
9424 /******************************************************************************/
9425 /******************** Bit definition for RCC_CR register ********************/
9426 #define RCC_CR_HSION_Pos (0U)
9427 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9428 #define RCC_CR_HSION RCC_CR_HSION_Msk
9429 #define RCC_CR_HSIRDY_Pos (1U)
9430 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9431 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9432 
9433 #define RCC_CR_HSITRIM_Pos (3U)
9434 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9435 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9436 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9437 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9438 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9439 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9440 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9442 #define RCC_CR_HSICAL_Pos (8U)
9443 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9444 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9445 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9446 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9447 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9448 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9449 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9450 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9451 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9452 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9454 #define RCC_CR_HSEON_Pos (16U)
9455 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9456 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
9457 #define RCC_CR_HSERDY_Pos (17U)
9458 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9459 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9460 #define RCC_CR_HSEBYP_Pos (18U)
9461 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9462 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9463 #define RCC_CR_CSSON_Pos (19U)
9464 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9465 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
9466 #define RCC_CR_PLLON_Pos (24U)
9467 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9468 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
9469 #define RCC_CR_PLLRDY_Pos (25U)
9470 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9471 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9472 /*
9473  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9474  */
9475 #define RCC_PLLI2S_SUPPORT
9477 #define RCC_CR_PLLI2SON_Pos (26U)
9478 #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9479 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9480 #define RCC_CR_PLLI2SRDY_Pos (27U)
9481 #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9482 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9483 
9484 /******************** Bit definition for RCC_PLLCFGR register ***************/
9485 #define RCC_PLLCFGR_PLLM_Pos (0U)
9486 #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9487 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9488 #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9489 #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9490 #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9491 #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9492 #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9493 #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9495 #define RCC_PLLCFGR_PLLN_Pos (6U)
9496 #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9497 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9498 #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9499 #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9500 #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9501 #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9502 #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9503 #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9504 #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9505 #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9506 #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9508 #define RCC_PLLCFGR_PLLP_Pos (16U)
9509 #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9510 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9511 #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9512 #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9514 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
9515 #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9516 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9517 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9518 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9519 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9520 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9521 
9522 #define RCC_PLLCFGR_PLLQ_Pos (24U)
9523 #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9524 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9525 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9526 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9527 #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9528 #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9531 /******************** Bit definition for RCC_CFGR register ******************/
9532 
9533 #define RCC_CFGR_SW_Pos (0U)
9534 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9535 #define RCC_CFGR_SW RCC_CFGR_SW_Msk
9536 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9537 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9539 #define RCC_CFGR_SW_HSI 0x00000000U
9540 #define RCC_CFGR_SW_HSE 0x00000001U
9541 #define RCC_CFGR_SW_PLL 0x00000002U
9544 #define RCC_CFGR_SWS_Pos (2U)
9545 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9546 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9547 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9548 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9550 #define RCC_CFGR_SWS_HSI 0x00000000U
9551 #define RCC_CFGR_SWS_HSE 0x00000004U
9552 #define RCC_CFGR_SWS_PLL 0x00000008U
9555 #define RCC_CFGR_HPRE_Pos (4U)
9556 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9557 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9558 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9559 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9560 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9561 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9563 #define RCC_CFGR_HPRE_DIV1 0x00000000U
9564 #define RCC_CFGR_HPRE_DIV2 0x00000080U
9565 #define RCC_CFGR_HPRE_DIV4 0x00000090U
9566 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
9567 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
9568 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
9569 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
9570 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
9571 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
9574 #define RCC_CFGR_PPRE1_Pos (10U)
9575 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9576 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9577 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9578 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9579 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9581 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
9582 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
9583 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
9584 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
9585 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
9588 #define RCC_CFGR_PPRE2_Pos (13U)
9589 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9590 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9591 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9592 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9593 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9595 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
9596 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
9597 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
9598 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
9599 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
9602 #define RCC_CFGR_RTCPRE_Pos (16U)
9603 #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
9604 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9605 #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
9606 #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
9607 #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
9608 #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
9609 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
9612 #define RCC_CFGR_MCO1_Pos (21U)
9613 #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
9614 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9615 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
9616 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
9618 #define RCC_CFGR_I2SSRC_Pos (23U)
9619 #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
9620 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
9621 
9622 #define RCC_CFGR_MCO1PRE_Pos (24U)
9623 #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
9624 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9625 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
9626 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
9627 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
9629 #define RCC_CFGR_MCO2PRE_Pos (27U)
9630 #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
9631 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9632 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
9633 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
9634 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
9636 #define RCC_CFGR_MCO2_Pos (30U)
9637 #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
9638 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9639 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
9640 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
9642 /******************** Bit definition for RCC_CIR register *******************/
9643 #define RCC_CIR_LSIRDYF_Pos (0U)
9644 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
9645 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9646 #define RCC_CIR_LSERDYF_Pos (1U)
9647 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
9648 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9649 #define RCC_CIR_HSIRDYF_Pos (2U)
9650 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
9651 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9652 #define RCC_CIR_HSERDYF_Pos (3U)
9653 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
9654 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9655 #define RCC_CIR_PLLRDYF_Pos (4U)
9656 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
9657 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9658 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
9659 #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
9660 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9661 
9662 #define RCC_CIR_CSSF_Pos (7U)
9663 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
9664 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9665 #define RCC_CIR_LSIRDYIE_Pos (8U)
9666 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
9667 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9668 #define RCC_CIR_LSERDYIE_Pos (9U)
9669 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
9670 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9671 #define RCC_CIR_HSIRDYIE_Pos (10U)
9672 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
9673 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9674 #define RCC_CIR_HSERDYIE_Pos (11U)
9675 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
9676 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9677 #define RCC_CIR_PLLRDYIE_Pos (12U)
9678 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
9679 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9680 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9681 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
9682 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9683 
9684 #define RCC_CIR_LSIRDYC_Pos (16U)
9685 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
9686 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9687 #define RCC_CIR_LSERDYC_Pos (17U)
9688 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
9689 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9690 #define RCC_CIR_HSIRDYC_Pos (18U)
9691 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
9692 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9693 #define RCC_CIR_HSERDYC_Pos (19U)
9694 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
9695 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9696 #define RCC_CIR_PLLRDYC_Pos (20U)
9697 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
9698 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9699 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
9700 #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
9701 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9702 
9703 #define RCC_CIR_CSSC_Pos (23U)
9704 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
9705 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9706 
9707 /******************** Bit definition for RCC_AHB1RSTR register **************/
9708 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9709 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
9710 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9711 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9712 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
9713 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9714 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9715 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
9716 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9717 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9718 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
9719 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9720 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9721 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
9722 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9723 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9724 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
9725 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9726 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9727 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
9728 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9729 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9730 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
9731 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9732 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
9733 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
9734 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
9735 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
9736 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9737 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9738 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9739 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9740 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9741 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9742 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9743 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9744 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
9745 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
9746 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
9747 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
9748 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
9749 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
9750 
9751 /******************** Bit definition for RCC_AHB2RSTR register **************/
9752 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
9753 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
9754 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
9755 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
9756 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9757 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9758 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9759 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
9760 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9761 /******************** Bit definition for RCC_AHB3RSTR register **************/
9762 #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9763 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
9764 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9765 
9766 
9767 /******************** Bit definition for RCC_APB1RSTR register **************/
9768 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
9769 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
9770 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9771 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
9772 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
9773 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9774 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
9775 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
9776 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9777 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
9778 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
9779 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9780 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
9781 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
9782 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9783 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
9784 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
9785 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9786 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
9787 #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
9788 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9789 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
9790 #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
9791 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9792 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
9793 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
9794 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9795 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
9796 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
9797 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9798 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
9799 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
9800 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9801 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
9802 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
9803 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9804 #define RCC_APB1RSTR_USART2RST_Pos (17U)
9805 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
9806 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9807 #define RCC_APB1RSTR_USART3RST_Pos (18U)
9808 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
9809 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9810 #define RCC_APB1RSTR_UART4RST_Pos (19U)
9811 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
9812 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9813 #define RCC_APB1RSTR_UART5RST_Pos (20U)
9814 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
9815 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9816 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
9817 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
9818 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9819 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
9820 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
9821 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9822 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
9823 #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
9824 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9825 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
9826 #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
9827 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9828 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
9829 #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
9830 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9831 #define RCC_APB1RSTR_PWRRST_Pos (28U)
9832 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
9833 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9834 #define RCC_APB1RSTR_DACRST_Pos (29U)
9835 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
9836 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9837 
9838 /******************** Bit definition for RCC_APB2RSTR register **************/
9839 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
9840 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9841 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9842 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
9843 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
9844 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9845 #define RCC_APB2RSTR_USART1RST_Pos (4U)
9846 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9847 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9848 #define RCC_APB2RSTR_USART6RST_Pos (5U)
9849 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
9850 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9851 #define RCC_APB2RSTR_ADCRST_Pos (8U)
9852 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
9853 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9854 #define RCC_APB2RSTR_SDIORST_Pos (11U)
9855 #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
9856 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9857 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
9858 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9859 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9860 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9861 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9862 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9863 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
9864 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
9865 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9866 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
9867 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
9868 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9869 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
9870 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
9871 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9872 
9873 /* Old SPI1RST bit definition, maintained for legacy purpose */
9874 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
9875 
9876 /******************** Bit definition for RCC_AHB1ENR register ***************/
9877 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9878 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
9879 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9880 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9881 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
9882 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9883 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9884 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
9885 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9886 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
9887 #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
9888 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9889 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9890 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
9891 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9892 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9893 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
9894 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9895 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9896 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
9897 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9898 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9899 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
9900 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9901 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
9902 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
9903 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
9904 #define RCC_AHB1ENR_CRCEN_Pos (12U)
9905 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
9906 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9907 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
9908 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
9909 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
9910 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
9911 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
9912 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
9913 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
9914 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
9915 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9916 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
9917 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
9918 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9919 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
9920 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
9921 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
9922 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
9923 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
9924 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
9925 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
9926 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
9927 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
9928 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
9929 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
9930 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
9931 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
9932 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
9933 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
9934 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
9935 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
9936 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
9937 /******************** Bit definition for RCC_AHB2ENR register ***************/
9938 /*
9939  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9940  */
9941 #define RCC_AHB2_SUPPORT
9943 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
9944 #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
9945 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
9946 #define RCC_AHB2ENR_RNGEN_Pos (6U)
9947 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
9948 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9949 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9950 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
9951 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9952 
9953 /******************** Bit definition for RCC_AHB3ENR register ***************/
9954 /*
9955  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9956  */
9957 #define RCC_AHB3_SUPPORT
9959 #define RCC_AHB3ENR_FSMCEN_Pos (0U)
9960 #define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
9961 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9962 
9963 /******************** Bit definition for RCC_APB1ENR register ***************/
9964 #define RCC_APB1ENR_TIM2EN_Pos (0U)
9965 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
9966 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9967 #define RCC_APB1ENR_TIM3EN_Pos (1U)
9968 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
9969 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9970 #define RCC_APB1ENR_TIM4EN_Pos (2U)
9971 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
9972 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9973 #define RCC_APB1ENR_TIM5EN_Pos (3U)
9974 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
9975 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9976 #define RCC_APB1ENR_TIM6EN_Pos (4U)
9977 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
9978 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9979 #define RCC_APB1ENR_TIM7EN_Pos (5U)
9980 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
9981 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
9982 #define RCC_APB1ENR_TIM12EN_Pos (6U)
9983 #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
9984 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
9985 #define RCC_APB1ENR_TIM13EN_Pos (7U)
9986 #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
9987 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
9988 #define RCC_APB1ENR_TIM14EN_Pos (8U)
9989 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
9990 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
9991 #define RCC_APB1ENR_WWDGEN_Pos (11U)
9992 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
9993 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
9994 #define RCC_APB1ENR_SPI2EN_Pos (14U)
9995 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
9996 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
9997 #define RCC_APB1ENR_SPI3EN_Pos (15U)
9998 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
9999 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
10000 #define RCC_APB1ENR_USART2EN_Pos (17U)
10001 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
10002 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
10003 #define RCC_APB1ENR_USART3EN_Pos (18U)
10004 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
10005 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
10006 #define RCC_APB1ENR_UART4EN_Pos (19U)
10007 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
10008 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
10009 #define RCC_APB1ENR_UART5EN_Pos (20U)
10010 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
10011 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
10012 #define RCC_APB1ENR_I2C1EN_Pos (21U)
10013 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
10014 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
10015 #define RCC_APB1ENR_I2C2EN_Pos (22U)
10016 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
10017 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
10018 #define RCC_APB1ENR_I2C3EN_Pos (23U)
10019 #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
10020 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10021 #define RCC_APB1ENR_CAN1EN_Pos (25U)
10022 #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
10023 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10024 #define RCC_APB1ENR_CAN2EN_Pos (26U)
10025 #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
10026 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10027 #define RCC_APB1ENR_PWREN_Pos (28U)
10028 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
10029 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10030 #define RCC_APB1ENR_DACEN_Pos (29U)
10031 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
10032 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10033 
10034 /******************** Bit definition for RCC_APB2ENR register ***************/
10035 #define RCC_APB2ENR_TIM1EN_Pos (0U)
10036 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
10037 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10038 #define RCC_APB2ENR_TIM8EN_Pos (1U)
10039 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
10040 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10041 #define RCC_APB2ENR_USART1EN_Pos (4U)
10042 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
10043 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10044 #define RCC_APB2ENR_USART6EN_Pos (5U)
10045 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
10046 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10047 #define RCC_APB2ENR_ADC1EN_Pos (8U)
10048 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
10049 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10050 #define RCC_APB2ENR_ADC2EN_Pos (9U)
10051 #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
10052 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
10053 #define RCC_APB2ENR_ADC3EN_Pos (10U)
10054 #define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
10055 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
10056 #define RCC_APB2ENR_SDIOEN_Pos (11U)
10057 #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
10058 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
10059 #define RCC_APB2ENR_SPI1EN_Pos (12U)
10060 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
10061 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10062 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10063 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
10064 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10065 #define RCC_APB2ENR_TIM9EN_Pos (16U)
10066 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
10067 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10068 #define RCC_APB2ENR_TIM10EN_Pos (17U)
10069 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
10070 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10071 #define RCC_APB2ENR_TIM11EN_Pos (18U)
10072 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
10073 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10074 
10075 /******************** Bit definition for RCC_AHB1LPENR register *************/
10076 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10077 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
10078 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10079 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10080 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
10081 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10082 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10083 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
10084 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10085 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10086 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
10087 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10088 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10089 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
10090 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10091 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10092 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
10093 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10094 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10095 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
10096 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10097 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10098 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
10099 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10100 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
10101 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
10102 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
10103 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10104 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
10105 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10106 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10107 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
10108 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10109 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10110 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
10111 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10112 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10113 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
10114 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10115 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
10116 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
10117 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10118 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10119 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
10120 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10121 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10122 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
10123 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10124 
10125 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
10126 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
10127 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
10128 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
10129 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
10130 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
10131 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
10132 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
10133 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
10134 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
10135 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
10136 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
10137 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
10138 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
10139 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
10140 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
10141 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
10142 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10143 
10144 /******************** Bit definition for RCC_AHB2LPENR register *************/
10145 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
10146 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
10147 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
10148 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
10149 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
10150 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
10151 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10152 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
10153 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10154 
10155 /******************** Bit definition for RCC_AHB3LPENR register *************/
10156 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
10157 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
10158 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
10159 
10160 /******************** Bit definition for RCC_APB1LPENR register *************/
10161 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10162 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
10163 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10164 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10165 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
10166 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10167 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10168 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
10169 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10170 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10171 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
10172 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10173 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10174 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
10175 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10176 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10177 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
10178 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10179 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10180 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
10181 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10182 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10183 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
10184 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10185 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10186 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
10187 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10188 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10189 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
10190 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10191 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10192 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
10193 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10194 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10195 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
10196 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10197 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10198 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
10199 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10200 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10201 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
10202 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10203 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10204 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
10205 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10206 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10207 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
10208 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10209 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10210 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
10211 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10212 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10213 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
10214 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10215 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10216 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
10217 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10218 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10219 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
10220 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10221 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10222 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
10223 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10224 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10225 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
10226 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10227 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
10228 #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
10229 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10230 
10231 /******************** Bit definition for RCC_APB2LPENR register *************/
10232 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10233 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
10234 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10235 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10236 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
10237 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10238 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10239 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
10240 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10241 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10242 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
10243 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10244 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10245 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
10246 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10247 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
10248 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
10249 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
10250 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
10251 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
10252 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
10253 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10254 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
10255 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10256 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10257 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
10258 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10259 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10260 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
10261 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10262 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10263 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
10264 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10265 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10266 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
10267 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10268 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10269 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
10270 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10271 
10272 /******************** Bit definition for RCC_BDCR register ******************/
10273 #define RCC_BDCR_LSEON_Pos (0U)
10274 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
10275 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10276 #define RCC_BDCR_LSERDY_Pos (1U)
10277 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
10278 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10279 #define RCC_BDCR_LSEBYP_Pos (2U)
10280 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
10281 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10282 
10283 #define RCC_BDCR_RTCSEL_Pos (8U)
10284 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
10285 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10286 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
10287 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
10289 #define RCC_BDCR_RTCEN_Pos (15U)
10290 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
10291 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10292 #define RCC_BDCR_BDRST_Pos (16U)
10293 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
10294 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10295 
10296 /******************** Bit definition for RCC_CSR register *******************/
10297 #define RCC_CSR_LSION_Pos (0U)
10298 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
10299 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
10300 #define RCC_CSR_LSIRDY_Pos (1U)
10301 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10302 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10303 #define RCC_CSR_RMVF_Pos (24U)
10304 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10305 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10306 #define RCC_CSR_BORRSTF_Pos (25U)
10307 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10308 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10309 #define RCC_CSR_PINRSTF_Pos (26U)
10310 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10311 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10312 #define RCC_CSR_PORRSTF_Pos (27U)
10313 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
10314 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10315 #define RCC_CSR_SFTRSTF_Pos (28U)
10316 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10317 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10318 #define RCC_CSR_IWDGRSTF_Pos (29U)
10319 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10320 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10321 #define RCC_CSR_WWDGRSTF_Pos (30U)
10322 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10323 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10324 #define RCC_CSR_LPWRRSTF_Pos (31U)
10325 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10326 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10327 /* Legacy defines */
10328 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10329 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10330 
10331 /******************** Bit definition for RCC_SSCGR register *****************/
10332 #define RCC_SSCGR_MODPER_Pos (0U)
10333 #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10334 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10335 #define RCC_SSCGR_INCSTEP_Pos (13U)
10336 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10337 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10338 #define RCC_SSCGR_SPREADSEL_Pos (30U)
10339 #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10340 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10341 #define RCC_SSCGR_SSCGEN_Pos (31U)
10342 #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10343 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10344 
10345 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
10346 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10347 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10348 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10349 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10350 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10351 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10352 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10353 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10354 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10355 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10356 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10357 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10359 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10360 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10361 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10362 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10363 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10364 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10367 /******************************************************************************/
10368 /* */
10369 /* RNG */
10370 /* */
10371 /******************************************************************************/
10372 /******************** Bits definition for RNG_CR register *******************/
10373 #define RNG_CR_RNGEN_Pos (2U)
10374 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
10375 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10376 #define RNG_CR_IE_Pos (3U)
10377 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
10378 #define RNG_CR_IE RNG_CR_IE_Msk
10379 
10380 /******************** Bits definition for RNG_SR register *******************/
10381 #define RNG_SR_DRDY_Pos (0U)
10382 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
10383 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
10384 #define RNG_SR_CECS_Pos (1U)
10385 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
10386 #define RNG_SR_CECS RNG_SR_CECS_Msk
10387 #define RNG_SR_SECS_Pos (2U)
10388 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
10389 #define RNG_SR_SECS RNG_SR_SECS_Msk
10390 #define RNG_SR_CEIS_Pos (5U)
10391 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
10392 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
10393 #define RNG_SR_SEIS_Pos (6U)
10394 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
10395 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
10396 
10397 /******************************************************************************/
10398 /* */
10399 /* Real-Time Clock (RTC) */
10400 /* */
10401 /******************************************************************************/
10402 /*
10403  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10404  */
10405 #define RTC_TAMPER2_SUPPORT
10406 #define RTC_AF2_SUPPORT
10407 /******************** Bits definition for RTC_TR register *******************/
10408 #define RTC_TR_PM_Pos (22U)
10409 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10410 #define RTC_TR_PM RTC_TR_PM_Msk
10411 #define RTC_TR_HT_Pos (20U)
10412 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10413 #define RTC_TR_HT RTC_TR_HT_Msk
10414 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10415 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10416 #define RTC_TR_HU_Pos (16U)
10417 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10418 #define RTC_TR_HU RTC_TR_HU_Msk
10419 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10420 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10421 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10422 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10423 #define RTC_TR_MNT_Pos (12U)
10424 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10425 #define RTC_TR_MNT RTC_TR_MNT_Msk
10426 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10427 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10428 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10429 #define RTC_TR_MNU_Pos (8U)
10430 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10431 #define RTC_TR_MNU RTC_TR_MNU_Msk
10432 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10433 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10434 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10435 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10436 #define RTC_TR_ST_Pos (4U)
10437 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10438 #define RTC_TR_ST RTC_TR_ST_Msk
10439 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10440 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10441 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10442 #define RTC_TR_SU_Pos (0U)
10443 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10444 #define RTC_TR_SU RTC_TR_SU_Msk
10445 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10446 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10447 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10448 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10450 /******************** Bits definition for RTC_DR register *******************/
10451 #define RTC_DR_YT_Pos (20U)
10452 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10453 #define RTC_DR_YT RTC_DR_YT_Msk
10454 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10455 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10456 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10457 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10458 #define RTC_DR_YU_Pos (16U)
10459 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10460 #define RTC_DR_YU RTC_DR_YU_Msk
10461 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10462 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10463 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10464 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10465 #define RTC_DR_WDU_Pos (13U)
10466 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10467 #define RTC_DR_WDU RTC_DR_WDU_Msk
10468 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10469 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10470 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10471 #define RTC_DR_MT_Pos (12U)
10472 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10473 #define RTC_DR_MT RTC_DR_MT_Msk
10474 #define RTC_DR_MU_Pos (8U)
10475 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10476 #define RTC_DR_MU RTC_DR_MU_Msk
10477 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10478 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10479 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10480 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10481 #define RTC_DR_DT_Pos (4U)
10482 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10483 #define RTC_DR_DT RTC_DR_DT_Msk
10484 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10485 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10486 #define RTC_DR_DU_Pos (0U)
10487 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10488 #define RTC_DR_DU RTC_DR_DU_Msk
10489 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10490 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10491 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10492 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10494 /******************** Bits definition for RTC_CR register *******************/
10495 #define RTC_CR_COE_Pos (23U)
10496 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10497 #define RTC_CR_COE RTC_CR_COE_Msk
10498 #define RTC_CR_OSEL_Pos (21U)
10499 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10500 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
10501 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10502 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10503 #define RTC_CR_POL_Pos (20U)
10504 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10505 #define RTC_CR_POL RTC_CR_POL_Msk
10506 #define RTC_CR_COSEL_Pos (19U)
10507 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
10508 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
10509 #define RTC_CR_BKP_Pos (18U)
10510 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10511 #define RTC_CR_BKP RTC_CR_BKP_Msk
10512 #define RTC_CR_SUB1H_Pos (17U)
10513 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10514 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10515 #define RTC_CR_ADD1H_Pos (16U)
10516 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10517 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10518 #define RTC_CR_TSIE_Pos (15U)
10519 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10520 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
10521 #define RTC_CR_WUTIE_Pos (14U)
10522 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10523 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10524 #define RTC_CR_ALRBIE_Pos (13U)
10525 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10526 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10527 #define RTC_CR_ALRAIE_Pos (12U)
10528 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10529 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10530 #define RTC_CR_TSE_Pos (11U)
10531 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10532 #define RTC_CR_TSE RTC_CR_TSE_Msk
10533 #define RTC_CR_WUTE_Pos (10U)
10534 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10535 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
10536 #define RTC_CR_ALRBE_Pos (9U)
10537 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10538 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10539 #define RTC_CR_ALRAE_Pos (8U)
10540 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10541 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10542 #define RTC_CR_DCE_Pos (7U)
10543 #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
10544 #define RTC_CR_DCE RTC_CR_DCE_Msk
10545 #define RTC_CR_FMT_Pos (6U)
10546 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10547 #define RTC_CR_FMT RTC_CR_FMT_Msk
10548 #define RTC_CR_BYPSHAD_Pos (5U)
10549 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
10550 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10551 #define RTC_CR_REFCKON_Pos (4U)
10552 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10553 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10554 #define RTC_CR_TSEDGE_Pos (3U)
10555 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10556 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10557 #define RTC_CR_WUCKSEL_Pos (0U)
10558 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10559 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10560 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10561 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10562 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10564 /* Legacy defines */
10565 #define RTC_CR_BCK RTC_CR_BKP
10566 
10567 /******************** Bits definition for RTC_ISR register ******************/
10568 #define RTC_ISR_RECALPF_Pos (16U)
10569 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
10570 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10571 #define RTC_ISR_TAMP1F_Pos (13U)
10572 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10573 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10574 #define RTC_ISR_TAMP2F_Pos (14U)
10575 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
10576 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10577 #define RTC_ISR_TSOVF_Pos (12U)
10578 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10579 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10580 #define RTC_ISR_TSF_Pos (11U)
10581 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10582 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
10583 #define RTC_ISR_WUTF_Pos (10U)
10584 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10585 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10586 #define RTC_ISR_ALRBF_Pos (9U)
10587 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10588 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10589 #define RTC_ISR_ALRAF_Pos (8U)
10590 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10591 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10592 #define RTC_ISR_INIT_Pos (7U)
10593 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10594 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
10595 #define RTC_ISR_INITF_Pos (6U)
10596 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10597 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
10598 #define RTC_ISR_RSF_Pos (5U)
10599 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10600 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
10601 #define RTC_ISR_INITS_Pos (4U)
10602 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10603 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
10604 #define RTC_ISR_SHPF_Pos (3U)
10605 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
10606 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10607 #define RTC_ISR_WUTWF_Pos (2U)
10608 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10609 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10610 #define RTC_ISR_ALRBWF_Pos (1U)
10611 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10612 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10613 #define RTC_ISR_ALRAWF_Pos (0U)
10614 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10615 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10616 
10617 /******************** Bits definition for RTC_PRER register *****************/
10618 #define RTC_PRER_PREDIV_A_Pos (16U)
10619 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10620 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10621 #define RTC_PRER_PREDIV_S_Pos (0U)
10622 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
10623 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10624 
10625 /******************** Bits definition for RTC_WUTR register *****************/
10626 #define RTC_WUTR_WUT_Pos (0U)
10627 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10628 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10629 
10630 /******************** Bits definition for RTC_CALIBR register ***************/
10631 #define RTC_CALIBR_DCS_Pos (7U)
10632 #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
10633 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10634 #define RTC_CALIBR_DC_Pos (0U)
10635 #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
10636 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10637 
10638 /******************** Bits definition for RTC_ALRMAR register ***************/
10639 #define RTC_ALRMAR_MSK4_Pos (31U)
10640 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
10641 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10642 #define RTC_ALRMAR_WDSEL_Pos (30U)
10643 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
10644 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10645 #define RTC_ALRMAR_DT_Pos (28U)
10646 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
10647 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10648 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
10649 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
10650 #define RTC_ALRMAR_DU_Pos (24U)
10651 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
10652 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10653 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
10654 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
10655 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
10656 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
10657 #define RTC_ALRMAR_MSK3_Pos (23U)
10658 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
10659 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10660 #define RTC_ALRMAR_PM_Pos (22U)
10661 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
10662 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10663 #define RTC_ALRMAR_HT_Pos (20U)
10664 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
10665 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10666 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
10667 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
10668 #define RTC_ALRMAR_HU_Pos (16U)
10669 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
10670 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10671 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
10672 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
10673 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
10674 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
10675 #define RTC_ALRMAR_MSK2_Pos (15U)
10676 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
10677 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10678 #define RTC_ALRMAR_MNT_Pos (12U)
10679 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
10680 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10681 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
10682 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
10683 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
10684 #define RTC_ALRMAR_MNU_Pos (8U)
10685 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
10686 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10687 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
10688 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
10689 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
10690 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
10691 #define RTC_ALRMAR_MSK1_Pos (7U)
10692 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
10693 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10694 #define RTC_ALRMAR_ST_Pos (4U)
10695 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
10696 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10697 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
10698 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
10699 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
10700 #define RTC_ALRMAR_SU_Pos (0U)
10701 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
10702 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10703 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
10704 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
10705 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
10706 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
10708 /******************** Bits definition for RTC_ALRMBR register ***************/
10709 #define RTC_ALRMBR_MSK4_Pos (31U)
10710 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
10711 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10712 #define RTC_ALRMBR_WDSEL_Pos (30U)
10713 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
10714 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10715 #define RTC_ALRMBR_DT_Pos (28U)
10716 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
10717 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10718 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
10719 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
10720 #define RTC_ALRMBR_DU_Pos (24U)
10721 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
10722 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10723 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
10724 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
10725 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
10726 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
10727 #define RTC_ALRMBR_MSK3_Pos (23U)
10728 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
10729 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10730 #define RTC_ALRMBR_PM_Pos (22U)
10731 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
10732 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10733 #define RTC_ALRMBR_HT_Pos (20U)
10734 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
10735 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10736 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
10737 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
10738 #define RTC_ALRMBR_HU_Pos (16U)
10739 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
10740 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10741 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
10742 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
10743 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
10744 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
10745 #define RTC_ALRMBR_MSK2_Pos (15U)
10746 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
10747 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10748 #define RTC_ALRMBR_MNT_Pos (12U)
10749 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
10750 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10751 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
10752 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
10753 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
10754 #define RTC_ALRMBR_MNU_Pos (8U)
10755 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
10756 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10757 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
10758 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
10759 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
10760 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
10761 #define RTC_ALRMBR_MSK1_Pos (7U)
10762 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
10763 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10764 #define RTC_ALRMBR_ST_Pos (4U)
10765 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
10766 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10767 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
10768 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
10769 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
10770 #define RTC_ALRMBR_SU_Pos (0U)
10771 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
10772 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10773 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
10774 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
10775 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
10776 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
10778 /******************** Bits definition for RTC_WPR register ******************/
10779 #define RTC_WPR_KEY_Pos (0U)
10780 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
10781 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
10782 
10783 /******************** Bits definition for RTC_SSR register ******************/
10784 #define RTC_SSR_SS_Pos (0U)
10785 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
10786 #define RTC_SSR_SS RTC_SSR_SS_Msk
10787 
10788 /******************** Bits definition for RTC_SHIFTR register ***************/
10789 #define RTC_SHIFTR_SUBFS_Pos (0U)
10790 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
10791 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10792 #define RTC_SHIFTR_ADD1S_Pos (31U)
10793 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
10794 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10795 
10796 /******************** Bits definition for RTC_TSTR register *****************/
10797 #define RTC_TSTR_PM_Pos (22U)
10798 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
10799 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
10800 #define RTC_TSTR_HT_Pos (20U)
10801 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
10802 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
10803 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
10804 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
10805 #define RTC_TSTR_HU_Pos (16U)
10806 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
10807 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
10808 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
10809 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
10810 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
10811 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
10812 #define RTC_TSTR_MNT_Pos (12U)
10813 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
10814 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10815 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
10816 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
10817 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
10818 #define RTC_TSTR_MNU_Pos (8U)
10819 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
10820 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10821 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
10822 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
10823 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
10824 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
10825 #define RTC_TSTR_ST_Pos (4U)
10826 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
10827 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
10828 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
10829 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
10830 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
10831 #define RTC_TSTR_SU_Pos (0U)
10832 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
10833 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
10834 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
10835 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
10836 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
10837 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
10839 /******************** Bits definition for RTC_TSDR register *****************/
10840 #define RTC_TSDR_WDU_Pos (13U)
10841 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
10842 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10843 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
10844 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
10845 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
10846 #define RTC_TSDR_MT_Pos (12U)
10847 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
10848 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
10849 #define RTC_TSDR_MU_Pos (8U)
10850 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
10851 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
10852 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
10853 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
10854 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
10855 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
10856 #define RTC_TSDR_DT_Pos (4U)
10857 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
10858 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
10859 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
10860 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
10861 #define RTC_TSDR_DU_Pos (0U)
10862 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
10863 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
10864 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
10865 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
10866 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
10867 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
10869 /******************** Bits definition for RTC_TSSSR register ****************/
10870 #define RTC_TSSSR_SS_Pos (0U)
10871 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
10872 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10873 
10874 /******************** Bits definition for RTC_CAL register *****************/
10875 #define RTC_CALR_CALP_Pos (15U)
10876 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
10877 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
10878 #define RTC_CALR_CALW8_Pos (14U)
10879 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
10880 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10881 #define RTC_CALR_CALW16_Pos (13U)
10882 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
10883 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10884 #define RTC_CALR_CALM_Pos (0U)
10885 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
10886 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
10887 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
10888 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
10889 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
10890 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
10891 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
10892 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
10893 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
10894 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
10895 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
10897 /******************** Bits definition for RTC_TAFCR register ****************/
10898 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
10899 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
10900 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
10901 #define RTC_TAFCR_TSINSEL_Pos (17U)
10902 #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
10903 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
10904 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
10905 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
10906 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
10907 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
10908 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
10909 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
10910 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
10911 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
10912 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
10913 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
10914 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
10915 #define RTC_TAFCR_TAMPFLT_Pos (11U)
10916 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
10917 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
10918 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
10919 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
10920 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
10921 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
10922 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
10923 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
10924 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
10925 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
10926 #define RTC_TAFCR_TAMPTS_Pos (7U)
10927 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
10928 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
10929 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
10930 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
10931 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
10932 #define RTC_TAFCR_TAMP2E_Pos (3U)
10933 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
10934 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
10935 #define RTC_TAFCR_TAMPIE_Pos (2U)
10936 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
10937 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
10938 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
10939 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
10940 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
10941 #define RTC_TAFCR_TAMP1E_Pos (0U)
10942 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
10943 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
10944 
10945 /* Legacy defines */
10946 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
10947 
10948 /******************** Bits definition for RTC_ALRMASSR register *************/
10949 #define RTC_ALRMASSR_MASKSS_Pos (24U)
10950 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
10951 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10952 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
10953 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
10954 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
10955 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
10956 #define RTC_ALRMASSR_SS_Pos (0U)
10957 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
10958 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10959 
10960 /******************** Bits definition for RTC_ALRMBSSR register *************/
10961 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
10962 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
10963 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10964 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
10965 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
10966 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
10967 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
10968 #define RTC_ALRMBSSR_SS_Pos (0U)
10969 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
10970 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10971 
10972 /******************** Bits definition for RTC_BKP0R register ****************/
10973 #define RTC_BKP0R_Pos (0U)
10974 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
10975 #define RTC_BKP0R RTC_BKP0R_Msk
10976 
10977 /******************** Bits definition for RTC_BKP1R register ****************/
10978 #define RTC_BKP1R_Pos (0U)
10979 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
10980 #define RTC_BKP1R RTC_BKP1R_Msk
10981 
10982 /******************** Bits definition for RTC_BKP2R register ****************/
10983 #define RTC_BKP2R_Pos (0U)
10984 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
10985 #define RTC_BKP2R RTC_BKP2R_Msk
10986 
10987 /******************** Bits definition for RTC_BKP3R register ****************/
10988 #define RTC_BKP3R_Pos (0U)
10989 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
10990 #define RTC_BKP3R RTC_BKP3R_Msk
10991 
10992 /******************** Bits definition for RTC_BKP4R register ****************/
10993 #define RTC_BKP4R_Pos (0U)
10994 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
10995 #define RTC_BKP4R RTC_BKP4R_Msk
10996 
10997 /******************** Bits definition for RTC_BKP5R register ****************/
10998 #define RTC_BKP5R_Pos (0U)
10999 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
11000 #define RTC_BKP5R RTC_BKP5R_Msk
11001 
11002 /******************** Bits definition for RTC_BKP6R register ****************/
11003 #define RTC_BKP6R_Pos (0U)
11004 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
11005 #define RTC_BKP6R RTC_BKP6R_Msk
11006 
11007 /******************** Bits definition for RTC_BKP7R register ****************/
11008 #define RTC_BKP7R_Pos (0U)
11009 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
11010 #define RTC_BKP7R RTC_BKP7R_Msk
11011 
11012 /******************** Bits definition for RTC_BKP8R register ****************/
11013 #define RTC_BKP8R_Pos (0U)
11014 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
11015 #define RTC_BKP8R RTC_BKP8R_Msk
11016 
11017 /******************** Bits definition for RTC_BKP9R register ****************/
11018 #define RTC_BKP9R_Pos (0U)
11019 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
11020 #define RTC_BKP9R RTC_BKP9R_Msk
11021 
11022 /******************** Bits definition for RTC_BKP10R register ***************/
11023 #define RTC_BKP10R_Pos (0U)
11024 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
11025 #define RTC_BKP10R RTC_BKP10R_Msk
11026 
11027 /******************** Bits definition for RTC_BKP11R register ***************/
11028 #define RTC_BKP11R_Pos (0U)
11029 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
11030 #define RTC_BKP11R RTC_BKP11R_Msk
11031 
11032 /******************** Bits definition for RTC_BKP12R register ***************/
11033 #define RTC_BKP12R_Pos (0U)
11034 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
11035 #define RTC_BKP12R RTC_BKP12R_Msk
11036 
11037 /******************** Bits definition for RTC_BKP13R register ***************/
11038 #define RTC_BKP13R_Pos (0U)
11039 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
11040 #define RTC_BKP13R RTC_BKP13R_Msk
11041 
11042 /******************** Bits definition for RTC_BKP14R register ***************/
11043 #define RTC_BKP14R_Pos (0U)
11044 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
11045 #define RTC_BKP14R RTC_BKP14R_Msk
11046 
11047 /******************** Bits definition for RTC_BKP15R register ***************/
11048 #define RTC_BKP15R_Pos (0U)
11049 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
11050 #define RTC_BKP15R RTC_BKP15R_Msk
11051 
11052 /******************** Bits definition for RTC_BKP16R register ***************/
11053 #define RTC_BKP16R_Pos (0U)
11054 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
11055 #define RTC_BKP16R RTC_BKP16R_Msk
11056 
11057 /******************** Bits definition for RTC_BKP17R register ***************/
11058 #define RTC_BKP17R_Pos (0U)
11059 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
11060 #define RTC_BKP17R RTC_BKP17R_Msk
11061 
11062 /******************** Bits definition for RTC_BKP18R register ***************/
11063 #define RTC_BKP18R_Pos (0U)
11064 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
11065 #define RTC_BKP18R RTC_BKP18R_Msk
11066 
11067 /******************** Bits definition for RTC_BKP19R register ***************/
11068 #define RTC_BKP19R_Pos (0U)
11069 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
11070 #define RTC_BKP19R RTC_BKP19R_Msk
11071 
11072 /******************** Number of backup registers ******************************/
11073 #define RTC_BKP_NUMBER 0x000000014U
11074 
11075 
11076 /******************************************************************************/
11077 /* */
11078 /* SD host Interface */
11079 /* */
11080 /******************************************************************************/
11081 /****************** Bit definition for SDIO_POWER register ******************/
11082 #define SDIO_POWER_PWRCTRL_Pos (0U)
11083 #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
11084 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
11085 #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
11086 #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
11088 /****************** Bit definition for SDIO_CLKCR register ******************/
11089 #define SDIO_CLKCR_CLKDIV_Pos (0U)
11090 #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
11091 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
11092 #define SDIO_CLKCR_CLKEN_Pos (8U)
11093 #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
11094 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
11095 #define SDIO_CLKCR_PWRSAV_Pos (9U)
11096 #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
11097 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
11098 #define SDIO_CLKCR_BYPASS_Pos (10U)
11099 #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
11100 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
11102 #define SDIO_CLKCR_WIDBUS_Pos (11U)
11103 #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
11104 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
11105 #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
11106 #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
11108 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
11109 #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
11110 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
11111 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
11112 #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
11113 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
11115 /******************* Bit definition for SDIO_ARG register *******************/
11116 #define SDIO_ARG_CMDARG_Pos (0U)
11117 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
11118 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
11120 /******************* Bit definition for SDIO_CMD register *******************/
11121 #define SDIO_CMD_CMDINDEX_Pos (0U)
11122 #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
11123 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
11125 #define SDIO_CMD_WAITRESP_Pos (6U)
11126 #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
11127 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
11128 #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
11129 #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
11131 #define SDIO_CMD_WAITINT_Pos (8U)
11132 #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
11133 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
11134 #define SDIO_CMD_WAITPEND_Pos (9U)
11135 #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
11136 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
11137 #define SDIO_CMD_CPSMEN_Pos (10U)
11138 #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
11139 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
11140 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
11141 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
11142 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
11143 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
11144 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
11145 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
11146 #define SDIO_CMD_NIEN_Pos (13U)
11147 #define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
11148 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
11149 #define SDIO_CMD_CEATACMD_Pos (14U)
11150 #define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
11151 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
11153 /***************** Bit definition for SDIO_RESPCMD register *****************/
11154 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
11155 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
11156 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
11158 /****************** Bit definition for SDIO_RESP0 register ******************/
11159 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
11160 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
11161 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
11163 /****************** Bit definition for SDIO_RESP1 register ******************/
11164 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
11165 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
11166 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
11168 /****************** Bit definition for SDIO_RESP2 register ******************/
11169 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
11170 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
11171 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
11173 /****************** Bit definition for SDIO_RESP3 register ******************/
11174 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
11175 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
11176 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
11178 /****************** Bit definition for SDIO_RESP4 register ******************/
11179 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
11180 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
11181 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
11183 /****************** Bit definition for SDIO_DTIMER register *****************/
11184 #define SDIO_DTIMER_DATATIME_Pos (0U)
11185 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
11186 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
11188 /****************** Bit definition for SDIO_DLEN register *******************/
11189 #define SDIO_DLEN_DATALENGTH_Pos (0U)
11190 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
11191 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
11193 /****************** Bit definition for SDIO_DCTRL register ******************/
11194 #define SDIO_DCTRL_DTEN_Pos (0U)
11195 #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
11196 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
11197 #define SDIO_DCTRL_DTDIR_Pos (1U)
11198 #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
11199 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
11200 #define SDIO_DCTRL_DTMODE_Pos (2U)
11201 #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
11202 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
11203 #define SDIO_DCTRL_DMAEN_Pos (3U)
11204 #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
11205 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
11207 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
11208 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11209 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
11210 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11211 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11212 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11213 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11215 #define SDIO_DCTRL_RWSTART_Pos (8U)
11216 #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
11217 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
11218 #define SDIO_DCTRL_RWSTOP_Pos (9U)
11219 #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
11220 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
11221 #define SDIO_DCTRL_RWMOD_Pos (10U)
11222 #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
11223 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
11224 #define SDIO_DCTRL_SDIOEN_Pos (11U)
11225 #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
11226 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
11228 /****************** Bit definition for SDIO_DCOUNT register *****************/
11229 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
11230 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
11231 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
11233 /****************** Bit definition for SDIO_STA register ********************/
11234 #define SDIO_STA_CCRCFAIL_Pos (0U)
11235 #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
11236 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
11237 #define SDIO_STA_DCRCFAIL_Pos (1U)
11238 #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
11239 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
11240 #define SDIO_STA_CTIMEOUT_Pos (2U)
11241 #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
11242 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
11243 #define SDIO_STA_DTIMEOUT_Pos (3U)
11244 #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
11245 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
11246 #define SDIO_STA_TXUNDERR_Pos (4U)
11247 #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
11248 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
11249 #define SDIO_STA_RXOVERR_Pos (5U)
11250 #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
11251 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
11252 #define SDIO_STA_CMDREND_Pos (6U)
11253 #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
11254 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
11255 #define SDIO_STA_CMDSENT_Pos (7U)
11256 #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
11257 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
11258 #define SDIO_STA_DATAEND_Pos (8U)
11259 #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
11260 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
11261 #define SDIO_STA_STBITERR_Pos (9U)
11262 #define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
11263 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
11264 #define SDIO_STA_DBCKEND_Pos (10U)
11265 #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
11266 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
11267 #define SDIO_STA_CMDACT_Pos (11U)
11268 #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
11269 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
11270 #define SDIO_STA_TXACT_Pos (12U)
11271 #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
11272 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
11273 #define SDIO_STA_RXACT_Pos (13U)
11274 #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
11275 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
11276 #define SDIO_STA_TXFIFOHE_Pos (14U)
11277 #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
11278 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
11279 #define SDIO_STA_RXFIFOHF_Pos (15U)
11280 #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
11281 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
11282 #define SDIO_STA_TXFIFOF_Pos (16U)
11283 #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
11284 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
11285 #define SDIO_STA_RXFIFOF_Pos (17U)
11286 #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
11287 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
11288 #define SDIO_STA_TXFIFOE_Pos (18U)
11289 #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
11290 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
11291 #define SDIO_STA_RXFIFOE_Pos (19U)
11292 #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
11293 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
11294 #define SDIO_STA_TXDAVL_Pos (20U)
11295 #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
11296 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
11297 #define SDIO_STA_RXDAVL_Pos (21U)
11298 #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
11299 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
11300 #define SDIO_STA_SDIOIT_Pos (22U)
11301 #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
11302 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
11303 #define SDIO_STA_CEATAEND_Pos (23U)
11304 #define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
11305 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
11307 /******************* Bit definition for SDIO_ICR register *******************/
11308 #define SDIO_ICR_CCRCFAILC_Pos (0U)
11309 #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
11310 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
11311 #define SDIO_ICR_DCRCFAILC_Pos (1U)
11312 #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
11313 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
11314 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
11315 #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
11316 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
11317 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
11318 #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
11319 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
11320 #define SDIO_ICR_TXUNDERRC_Pos (4U)
11321 #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
11322 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
11323 #define SDIO_ICR_RXOVERRC_Pos (5U)
11324 #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
11325 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
11326 #define SDIO_ICR_CMDRENDC_Pos (6U)
11327 #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
11328 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
11329 #define SDIO_ICR_CMDSENTC_Pos (7U)
11330 #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
11331 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
11332 #define SDIO_ICR_DATAENDC_Pos (8U)
11333 #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
11334 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
11335 #define SDIO_ICR_STBITERRC_Pos (9U)
11336 #define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
11337 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
11338 #define SDIO_ICR_DBCKENDC_Pos (10U)
11339 #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
11340 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
11341 #define SDIO_ICR_SDIOITC_Pos (22U)
11342 #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
11343 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
11344 #define SDIO_ICR_CEATAENDC_Pos (23U)
11345 #define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
11346 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
11348 /****************** Bit definition for SDIO_MASK register *******************/
11349 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
11350 #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
11351 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
11352 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
11353 #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
11354 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
11355 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11356 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
11357 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
11358 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11359 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
11360 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
11361 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
11362 #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
11363 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
11364 #define SDIO_MASK_RXOVERRIE_Pos (5U)
11365 #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
11366 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
11367 #define SDIO_MASK_CMDRENDIE_Pos (6U)
11368 #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
11369 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
11370 #define SDIO_MASK_CMDSENTIE_Pos (7U)
11371 #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
11372 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
11373 #define SDIO_MASK_DATAENDIE_Pos (8U)
11374 #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
11375 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
11376 #define SDIO_MASK_STBITERRIE_Pos (9U)
11377 #define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
11378 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
11379 #define SDIO_MASK_DBCKENDIE_Pos (10U)
11380 #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
11381 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
11382 #define SDIO_MASK_CMDACTIE_Pos (11U)
11383 #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
11384 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
11385 #define SDIO_MASK_TXACTIE_Pos (12U)
11386 #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
11387 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
11388 #define SDIO_MASK_RXACTIE_Pos (13U)
11389 #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
11390 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
11391 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11392 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
11393 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
11394 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11395 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
11396 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
11397 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
11398 #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
11399 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
11400 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
11401 #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
11402 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
11403 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
11404 #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
11405 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
11406 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
11407 #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
11408 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
11409 #define SDIO_MASK_TXDAVLIE_Pos (20U)
11410 #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
11411 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
11412 #define SDIO_MASK_RXDAVLIE_Pos (21U)
11413 #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
11414 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
11415 #define SDIO_MASK_SDIOITIE_Pos (22U)
11416 #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
11417 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
11418 #define SDIO_MASK_CEATAENDIE_Pos (23U)
11419 #define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
11420 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
11422 /***************** Bit definition for SDIO_FIFOCNT register *****************/
11423 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
11424 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
11425 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
11427 /****************** Bit definition for SDIO_FIFO register *******************/
11428 #define SDIO_FIFO_FIFODATA_Pos (0U)
11429 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
11430 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
11432 /******************************************************************************/
11433 /* */
11434 /* Serial Peripheral Interface */
11435 /* */
11436 /******************************************************************************/
11437 #define SPI_I2S_FULLDUPLEX_SUPPORT
11439 /******************* Bit definition for SPI_CR1 register ********************/
11440 #define SPI_CR1_CPHA_Pos (0U)
11441 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
11442 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
11443 #define SPI_CR1_CPOL_Pos (1U)
11444 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
11445 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
11446 #define SPI_CR1_MSTR_Pos (2U)
11447 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
11448 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
11450 #define SPI_CR1_BR_Pos (3U)
11451 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
11452 #define SPI_CR1_BR SPI_CR1_BR_Msk
11453 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
11454 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
11455 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
11457 #define SPI_CR1_SPE_Pos (6U)
11458 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
11459 #define SPI_CR1_SPE SPI_CR1_SPE_Msk
11460 #define SPI_CR1_LSBFIRST_Pos (7U)
11461 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
11462 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
11463 #define SPI_CR1_SSI_Pos (8U)
11464 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
11465 #define SPI_CR1_SSI SPI_CR1_SSI_Msk
11466 #define SPI_CR1_SSM_Pos (9U)
11467 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
11468 #define SPI_CR1_SSM SPI_CR1_SSM_Msk
11469 #define SPI_CR1_RXONLY_Pos (10U)
11470 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
11471 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
11472 #define SPI_CR1_DFF_Pos (11U)
11473 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
11474 #define SPI_CR1_DFF SPI_CR1_DFF_Msk
11475 #define SPI_CR1_CRCNEXT_Pos (12U)
11476 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
11477 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
11478 #define SPI_CR1_CRCEN_Pos (13U)
11479 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
11480 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
11481 #define SPI_CR1_BIDIOE_Pos (14U)
11482 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
11483 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
11484 #define SPI_CR1_BIDIMODE_Pos (15U)
11485 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
11486 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
11488 /******************* Bit definition for SPI_CR2 register ********************/
11489 #define SPI_CR2_RXDMAEN_Pos (0U)
11490 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
11491 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
11492 #define SPI_CR2_TXDMAEN_Pos (1U)
11493 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
11494 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
11495 #define SPI_CR2_SSOE_Pos (2U)
11496 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
11497 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
11498 #define SPI_CR2_FRF_Pos (4U)
11499 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
11500 #define SPI_CR2_FRF SPI_CR2_FRF_Msk
11501 #define SPI_CR2_ERRIE_Pos (5U)
11502 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
11503 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
11504 #define SPI_CR2_RXNEIE_Pos (6U)
11505 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
11506 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
11507 #define SPI_CR2_TXEIE_Pos (7U)
11508 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
11509 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11511 /******************** Bit definition for SPI_SR register ********************/
11512 #define SPI_SR_RXNE_Pos (0U)
11513 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11514 #define SPI_SR_RXNE SPI_SR_RXNE_Msk
11515 #define SPI_SR_TXE_Pos (1U)
11516 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11517 #define SPI_SR_TXE SPI_SR_TXE_Msk
11518 #define SPI_SR_CHSIDE_Pos (2U)
11519 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11520 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11521 #define SPI_SR_UDR_Pos (3U)
11522 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11523 #define SPI_SR_UDR SPI_SR_UDR_Msk
11524 #define SPI_SR_CRCERR_Pos (4U)
11525 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11526 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11527 #define SPI_SR_MODF_Pos (5U)
11528 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11529 #define SPI_SR_MODF SPI_SR_MODF_Msk
11530 #define SPI_SR_OVR_Pos (6U)
11531 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11532 #define SPI_SR_OVR SPI_SR_OVR_Msk
11533 #define SPI_SR_BSY_Pos (7U)
11534 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11535 #define SPI_SR_BSY SPI_SR_BSY_Msk
11536 #define SPI_SR_FRE_Pos (8U)
11537 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
11538 #define SPI_SR_FRE SPI_SR_FRE_Msk
11540 /******************** Bit definition for SPI_DR register ********************/
11541 #define SPI_DR_DR_Pos (0U)
11542 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11543 #define SPI_DR_DR SPI_DR_DR_Msk
11545 /******************* Bit definition for SPI_CRCPR register ******************/
11546 #define SPI_CRCPR_CRCPOLY_Pos (0U)
11547 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11548 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11550 /****************** Bit definition for SPI_RXCRCR register ******************/
11551 #define SPI_RXCRCR_RXCRC_Pos (0U)
11552 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
11553 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
11555 /****************** Bit definition for SPI_TXCRCR register ******************/
11556 #define SPI_TXCRCR_TXCRC_Pos (0U)
11557 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
11558 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
11560 /****************** Bit definition for SPI_I2SCFGR register *****************/
11561 #define SPI_I2SCFGR_CHLEN_Pos (0U)
11562 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
11563 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
11565 #define SPI_I2SCFGR_DATLEN_Pos (1U)
11566 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
11567 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
11568 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
11569 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
11571 #define SPI_I2SCFGR_CKPOL_Pos (3U)
11572 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
11573 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
11575 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
11576 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
11577 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
11578 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
11579 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
11581 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11582 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
11583 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
11585 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
11586 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
11587 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
11588 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
11589 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
11591 #define SPI_I2SCFGR_I2SE_Pos (10U)
11592 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
11593 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
11594 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
11595 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
11596 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
11598 /****************** Bit definition for SPI_I2SPR register *******************/
11599 #define SPI_I2SPR_I2SDIV_Pos (0U)
11600 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
11601 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
11602 #define SPI_I2SPR_ODD_Pos (8U)
11603 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
11604 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
11605 #define SPI_I2SPR_MCKOE_Pos (9U)
11606 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
11607 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
11609 /******************************************************************************/
11610 /* */
11611 /* SYSCFG */
11612 /* */
11613 /******************************************************************************/
11614 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
11615 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11616 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11617 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
11618 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11619 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11620 /****************** Bit definition for SYSCFG_PMC register ******************/
11621 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
11622 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
11623 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
11624 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
11625 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
11626 
11627 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11628 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11629 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
11630 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
11631 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11632 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
11633 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
11634 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11635 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
11636 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
11637 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11638 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
11639 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
11643 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
11644 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
11645 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
11646 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
11647 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
11648 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
11649 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
11650 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
11651 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
11656 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
11657 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
11658 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
11659 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
11660 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
11661 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
11662 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
11663 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
11664 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
11669 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
11670 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
11671 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
11672 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
11673 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
11674 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
11675 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
11676 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
11677 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
11682 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
11683 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
11684 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
11685 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
11686 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
11687 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
11688 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
11689 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
11690 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
11692 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11693 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11694 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
11695 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
11696 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11697 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
11698 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
11699 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11700 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
11701 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
11702 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11703 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
11704 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
11709 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
11710 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
11711 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
11712 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
11713 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
11714 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
11715 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
11716 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
11717 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
11722 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
11723 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
11724 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
11725 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
11726 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
11727 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
11728 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
11729 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
11730 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
11735 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
11736 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
11737 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
11738 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
11739 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
11740 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
11741 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
11742 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
11743 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
11748 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
11749 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
11750 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
11751 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
11752 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
11753 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
11754 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
11755 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
11756 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
11758 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
11759 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11760 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
11761 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
11762 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11763 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
11764 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
11765 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11766 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
11767 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
11768 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
11769 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
11770 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
11775 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
11776 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
11777 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
11778 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
11779 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
11780 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
11781 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
11782 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
11783 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
11788 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
11789 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
11790 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
11791 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
11792 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
11793 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
11794 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
11795 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
11796 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
11801 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
11802 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
11803 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
11804 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
11805 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
11806 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
11807 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
11808 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
11809 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
11814 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
11815 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
11816 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
11817 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
11818 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
11819 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
11820 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
11821 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
11822 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
11824 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
11825 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
11826 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
11827 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
11828 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
11829 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
11830 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
11831 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
11832 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
11833 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
11834 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
11835 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
11836 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
11841 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
11842 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
11843 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
11844 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
11845 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
11846 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
11847 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
11848 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
11853 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
11854 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
11855 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
11856 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
11857 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
11858 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
11859 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
11860 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
11865 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
11866 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
11867 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
11868 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
11869 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
11870 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
11871 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
11872 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
11877 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
11878 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
11879 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
11880 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
11881 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
11882 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
11883 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
11884 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
11886 /****************** Bit definition for SYSCFG_CMPCR register ****************/
11887 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
11888 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
11889 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
11890 #define SYSCFG_CMPCR_READY_Pos (8U)
11891 #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
11892 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
11894 /******************************************************************************/
11895 /* */
11896 /* TIM */
11897 /* */
11898 /******************************************************************************/
11899 /******************* Bit definition for TIM_CR1 register ********************/
11900 #define TIM_CR1_CEN_Pos (0U)
11901 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
11902 #define TIM_CR1_CEN TIM_CR1_CEN_Msk
11903 #define TIM_CR1_UDIS_Pos (1U)
11904 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
11905 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
11906 #define TIM_CR1_URS_Pos (2U)
11907 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
11908 #define TIM_CR1_URS TIM_CR1_URS_Msk
11909 #define TIM_CR1_OPM_Pos (3U)
11910 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
11911 #define TIM_CR1_OPM TIM_CR1_OPM_Msk
11912 #define TIM_CR1_DIR_Pos (4U)
11913 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
11914 #define TIM_CR1_DIR TIM_CR1_DIR_Msk
11916 #define TIM_CR1_CMS_Pos (5U)
11917 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
11918 #define TIM_CR1_CMS TIM_CR1_CMS_Msk
11919 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
11920 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
11922 #define TIM_CR1_ARPE_Pos (7U)
11923 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
11924 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
11926 #define TIM_CR1_CKD_Pos (8U)
11927 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
11928 #define TIM_CR1_CKD TIM_CR1_CKD_Msk
11929 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
11930 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
11932 /******************* Bit definition for TIM_CR2 register ********************/
11933 #define TIM_CR2_CCPC_Pos (0U)
11934 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
11935 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
11936 #define TIM_CR2_CCUS_Pos (2U)
11937 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
11938 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
11939 #define TIM_CR2_CCDS_Pos (3U)
11940 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
11941 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
11943 #define TIM_CR2_MMS_Pos (4U)
11944 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
11945 #define TIM_CR2_MMS TIM_CR2_MMS_Msk
11946 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
11947 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
11948 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
11950 #define TIM_CR2_TI1S_Pos (7U)
11951 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
11952 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
11953 #define TIM_CR2_OIS1_Pos (8U)
11954 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
11955 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
11956 #define TIM_CR2_OIS1N_Pos (9U)
11957 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
11958 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
11959 #define TIM_CR2_OIS2_Pos (10U)
11960 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
11961 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
11962 #define TIM_CR2_OIS2N_Pos (11U)
11963 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
11964 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
11965 #define TIM_CR2_OIS3_Pos (12U)
11966 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
11967 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
11968 #define TIM_CR2_OIS3N_Pos (13U)
11969 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
11970 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
11971 #define TIM_CR2_OIS4_Pos (14U)
11972 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
11973 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
11975 /******************* Bit definition for TIM_SMCR register *******************/
11976 #define TIM_SMCR_SMS_Pos (0U)
11977 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
11978 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
11979 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
11980 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
11981 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
11983 #define TIM_SMCR_TS_Pos (4U)
11984 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
11985 #define TIM_SMCR_TS TIM_SMCR_TS_Msk
11986 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
11987 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
11988 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
11990 #define TIM_SMCR_MSM_Pos (7U)
11991 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
11992 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
11994 #define TIM_SMCR_ETF_Pos (8U)
11995 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
11996 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
11997 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
11998 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
11999 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
12000 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
12002 #define TIM_SMCR_ETPS_Pos (12U)
12003 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
12004 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
12005 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
12006 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
12008 #define TIM_SMCR_ECE_Pos (14U)
12009 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
12010 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
12011 #define TIM_SMCR_ETP_Pos (15U)
12012 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
12013 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
12015 /******************* Bit definition for TIM_DIER register *******************/
12016 #define TIM_DIER_UIE_Pos (0U)
12017 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
12018 #define TIM_DIER_UIE TIM_DIER_UIE_Msk
12019 #define TIM_DIER_CC1IE_Pos (1U)
12020 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
12021 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
12022 #define TIM_DIER_CC2IE_Pos (2U)
12023 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
12024 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
12025 #define TIM_DIER_CC3IE_Pos (3U)
12026 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
12027 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
12028 #define TIM_DIER_CC4IE_Pos (4U)
12029 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
12030 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
12031 #define TIM_DIER_COMIE_Pos (5U)
12032 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
12033 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
12034 #define TIM_DIER_TIE_Pos (6U)
12035 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
12036 #define TIM_DIER_TIE TIM_DIER_TIE_Msk
12037 #define TIM_DIER_BIE_Pos (7U)
12038 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
12039 #define TIM_DIER_BIE TIM_DIER_BIE_Msk
12040 #define TIM_DIER_UDE_Pos (8U)
12041 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
12042 #define TIM_DIER_UDE TIM_DIER_UDE_Msk
12043 #define TIM_DIER_CC1DE_Pos (9U)
12044 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
12045 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
12046 #define TIM_DIER_CC2DE_Pos (10U)
12047 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
12048 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
12049 #define TIM_DIER_CC3DE_Pos (11U)
12050 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
12051 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
12052 #define TIM_DIER_CC4DE_Pos (12U)
12053 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
12054 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
12055 #define TIM_DIER_COMDE_Pos (13U)
12056 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
12057 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
12058 #define TIM_DIER_TDE_Pos (14U)
12059 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
12060 #define TIM_DIER_TDE TIM_DIER_TDE_Msk
12062 /******************** Bit definition for TIM_SR register ********************/
12063 #define TIM_SR_UIF_Pos (0U)
12064 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
12065 #define TIM_SR_UIF TIM_SR_UIF_Msk
12066 #define TIM_SR_CC1IF_Pos (1U)
12067 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
12068 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
12069 #define TIM_SR_CC2IF_Pos (2U)
12070 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
12071 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
12072 #define TIM_SR_CC3IF_Pos (3U)
12073 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
12074 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
12075 #define TIM_SR_CC4IF_Pos (4U)
12076 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
12077 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
12078 #define TIM_SR_COMIF_Pos (5U)
12079 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
12080 #define TIM_SR_COMIF TIM_SR_COMIF_Msk
12081 #define TIM_SR_TIF_Pos (6U)
12082 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
12083 #define TIM_SR_TIF TIM_SR_TIF_Msk
12084 #define TIM_SR_BIF_Pos (7U)
12085 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
12086 #define TIM_SR_BIF TIM_SR_BIF_Msk
12087 #define TIM_SR_CC1OF_Pos (9U)
12088 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
12089 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
12090 #define TIM_SR_CC2OF_Pos (10U)
12091 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
12092 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
12093 #define TIM_SR_CC3OF_Pos (11U)
12094 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
12095 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
12096 #define TIM_SR_CC4OF_Pos (12U)
12097 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
12098 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
12100 /******************* Bit definition for TIM_EGR register ********************/
12101 #define TIM_EGR_UG_Pos (0U)
12102 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
12103 #define TIM_EGR_UG TIM_EGR_UG_Msk
12104 #define TIM_EGR_CC1G_Pos (1U)
12105 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
12106 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
12107 #define TIM_EGR_CC2G_Pos (2U)
12108 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
12109 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
12110 #define TIM_EGR_CC3G_Pos (3U)
12111 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
12112 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
12113 #define TIM_EGR_CC4G_Pos (4U)
12114 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
12115 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
12116 #define TIM_EGR_COMG_Pos (5U)
12117 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
12118 #define TIM_EGR_COMG TIM_EGR_COMG_Msk
12119 #define TIM_EGR_TG_Pos (6U)
12120 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
12121 #define TIM_EGR_TG TIM_EGR_TG_Msk
12122 #define TIM_EGR_BG_Pos (7U)
12123 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
12124 #define TIM_EGR_BG TIM_EGR_BG_Msk
12126 /****************** Bit definition for TIM_CCMR1 register *******************/
12127 #define TIM_CCMR1_CC1S_Pos (0U)
12128 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
12129 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
12130 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
12131 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
12133 #define TIM_CCMR1_OC1FE_Pos (2U)
12134 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
12135 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
12136 #define TIM_CCMR1_OC1PE_Pos (3U)
12137 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
12138 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
12140 #define TIM_CCMR1_OC1M_Pos (4U)
12141 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
12142 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
12143 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
12144 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
12145 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
12147 #define TIM_CCMR1_OC1CE_Pos (7U)
12148 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
12149 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
12151 #define TIM_CCMR1_CC2S_Pos (8U)
12152 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
12153 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
12154 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
12155 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
12157 #define TIM_CCMR1_OC2FE_Pos (10U)
12158 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
12159 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
12160 #define TIM_CCMR1_OC2PE_Pos (11U)
12161 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
12162 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
12164 #define TIM_CCMR1_OC2M_Pos (12U)
12165 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
12166 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
12167 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
12168 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
12169 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
12171 #define TIM_CCMR1_OC2CE_Pos (15U)
12172 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
12173 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
12175 /*----------------------------------------------------------------------------*/
12176 
12177 #define TIM_CCMR1_IC1PSC_Pos (2U)
12178 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
12179 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
12180 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
12181 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
12183 #define TIM_CCMR1_IC1F_Pos (4U)
12184 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
12185 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
12186 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
12187 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
12188 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
12189 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
12191 #define TIM_CCMR1_IC2PSC_Pos (10U)
12192 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
12193 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
12194 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
12195 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
12197 #define TIM_CCMR1_IC2F_Pos (12U)
12198 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
12199 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
12200 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
12201 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
12202 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
12203 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
12205 /****************** Bit definition for TIM_CCMR2 register *******************/
12206 #define TIM_CCMR2_CC3S_Pos (0U)
12207 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
12208 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
12209 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
12210 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
12212 #define TIM_CCMR2_OC3FE_Pos (2U)
12213 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
12214 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
12215 #define TIM_CCMR2_OC3PE_Pos (3U)
12216 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
12217 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
12219 #define TIM_CCMR2_OC3M_Pos (4U)
12220 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
12221 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
12222 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
12223 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
12224 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
12226 #define TIM_CCMR2_OC3CE_Pos (7U)
12227 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
12228 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
12230 #define TIM_CCMR2_CC4S_Pos (8U)
12231 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
12232 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
12233 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
12234 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
12236 #define TIM_CCMR2_OC4FE_Pos (10U)
12237 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
12238 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
12239 #define TIM_CCMR2_OC4PE_Pos (11U)
12240 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
12241 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
12243 #define TIM_CCMR2_OC4M_Pos (12U)
12244 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
12245 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
12246 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
12247 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
12248 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
12250 #define TIM_CCMR2_OC4CE_Pos (15U)
12251 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
12252 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
12254 /*----------------------------------------------------------------------------*/
12255 
12256 #define TIM_CCMR2_IC3PSC_Pos (2U)
12257 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
12258 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
12259 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
12260 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
12262 #define TIM_CCMR2_IC3F_Pos (4U)
12263 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
12264 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
12265 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
12266 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
12267 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
12268 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
12270 #define TIM_CCMR2_IC4PSC_Pos (10U)
12271 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
12272 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
12273 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
12274 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
12276 #define TIM_CCMR2_IC4F_Pos (12U)
12277 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
12278 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
12279 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
12280 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
12281 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
12282 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
12284 /******************* Bit definition for TIM_CCER register *******************/
12285 #define TIM_CCER_CC1E_Pos (0U)
12286 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
12287 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
12288 #define TIM_CCER_CC1P_Pos (1U)
12289 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
12290 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
12291 #define TIM_CCER_CC1NE_Pos (2U)
12292 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
12293 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
12294 #define TIM_CCER_CC1NP_Pos (3U)
12295 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
12296 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
12297 #define TIM_CCER_CC2E_Pos (4U)
12298 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
12299 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
12300 #define TIM_CCER_CC2P_Pos (5U)
12301 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
12302 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
12303 #define TIM_CCER_CC2NE_Pos (6U)
12304 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
12305 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
12306 #define TIM_CCER_CC2NP_Pos (7U)
12307 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
12308 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
12309 #define TIM_CCER_CC3E_Pos (8U)
12310 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
12311 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
12312 #define TIM_CCER_CC3P_Pos (9U)
12313 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
12314 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
12315 #define TIM_CCER_CC3NE_Pos (10U)
12316 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
12317 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
12318 #define TIM_CCER_CC3NP_Pos (11U)
12319 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
12320 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
12321 #define TIM_CCER_CC4E_Pos (12U)
12322 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
12323 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
12324 #define TIM_CCER_CC4P_Pos (13U)
12325 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
12326 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
12327 #define TIM_CCER_CC4NP_Pos (15U)
12328 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
12329 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
12331 /******************* Bit definition for TIM_CNT register ********************/
12332 #define TIM_CNT_CNT_Pos (0U)
12333 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
12334 #define TIM_CNT_CNT TIM_CNT_CNT_Msk
12336 /******************* Bit definition for TIM_PSC register ********************/
12337 #define TIM_PSC_PSC_Pos (0U)
12338 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
12339 #define TIM_PSC_PSC TIM_PSC_PSC_Msk
12341 /******************* Bit definition for TIM_ARR register ********************/
12342 #define TIM_ARR_ARR_Pos (0U)
12343 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
12344 #define TIM_ARR_ARR TIM_ARR_ARR_Msk
12346 /******************* Bit definition for TIM_RCR register ********************/
12347 #define TIM_RCR_REP_Pos (0U)
12348 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
12349 #define TIM_RCR_REP TIM_RCR_REP_Msk
12351 /******************* Bit definition for TIM_CCR1 register *******************/
12352 #define TIM_CCR1_CCR1_Pos (0U)
12353 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
12354 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
12356 /******************* Bit definition for TIM_CCR2 register *******************/
12357 #define TIM_CCR2_CCR2_Pos (0U)
12358 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
12359 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
12361 /******************* Bit definition for TIM_CCR3 register *******************/
12362 #define TIM_CCR3_CCR3_Pos (0U)
12363 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
12364 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
12366 /******************* Bit definition for TIM_CCR4 register *******************/
12367 #define TIM_CCR4_CCR4_Pos (0U)
12368 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
12369 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
12371 /******************* Bit definition for TIM_BDTR register *******************/
12372 #define TIM_BDTR_DTG_Pos (0U)
12373 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
12374 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
12375 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
12376 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
12377 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
12378 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
12379 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
12380 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
12381 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
12382 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
12384 #define TIM_BDTR_LOCK_Pos (8U)
12385 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
12386 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
12387 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
12388 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
12390 #define TIM_BDTR_OSSI_Pos (10U)
12391 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
12392 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
12393 #define TIM_BDTR_OSSR_Pos (11U)
12394 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
12395 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
12396 #define TIM_BDTR_BKE_Pos (12U)
12397 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
12398 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
12399 #define TIM_BDTR_BKP_Pos (13U)
12400 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
12401 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
12402 #define TIM_BDTR_AOE_Pos (14U)
12403 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
12404 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
12405 #define TIM_BDTR_MOE_Pos (15U)
12406 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
12407 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
12409 /******************* Bit definition for TIM_DCR register ********************/
12410 #define TIM_DCR_DBA_Pos (0U)
12411 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
12412 #define TIM_DCR_DBA TIM_DCR_DBA_Msk
12413 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
12414 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
12415 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
12416 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
12417 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
12419 #define TIM_DCR_DBL_Pos (8U)
12420 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
12421 #define TIM_DCR_DBL TIM_DCR_DBL_Msk
12422 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
12423 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
12424 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
12425 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
12426 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
12428 /******************* Bit definition for TIM_DMAR register *******************/
12429 #define TIM_DMAR_DMAB_Pos (0U)
12430 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
12431 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
12433 /******************* Bit definition for TIM_OR register *********************/
12434 #define TIM_OR_TI1_RMP_Pos (0U)
12435 #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
12436 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
12437 #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
12438 #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
12440 #define TIM_OR_TI4_RMP_Pos (6U)
12441 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
12442 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
12443 #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
12444 #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
12445 #define TIM_OR_ITR1_RMP_Pos (10U)
12446 #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
12447 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
12448 #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
12449 #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
12452 /******************************************************************************/
12453 /* */
12454 /* Universal Synchronous Asynchronous Receiver Transmitter */
12455 /* */
12456 /******************************************************************************/
12457 /******************* Bit definition for USART_SR register *******************/
12458 #define USART_SR_PE_Pos (0U)
12459 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
12460 #define USART_SR_PE USART_SR_PE_Msk
12461 #define USART_SR_FE_Pos (1U)
12462 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
12463 #define USART_SR_FE USART_SR_FE_Msk
12464 #define USART_SR_NE_Pos (2U)
12465 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
12466 #define USART_SR_NE USART_SR_NE_Msk
12467 #define USART_SR_ORE_Pos (3U)
12468 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
12469 #define USART_SR_ORE USART_SR_ORE_Msk
12470 #define USART_SR_IDLE_Pos (4U)
12471 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
12472 #define USART_SR_IDLE USART_SR_IDLE_Msk
12473 #define USART_SR_RXNE_Pos (5U)
12474 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
12475 #define USART_SR_RXNE USART_SR_RXNE_Msk
12476 #define USART_SR_TC_Pos (6U)
12477 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
12478 #define USART_SR_TC USART_SR_TC_Msk
12479 #define USART_SR_TXE_Pos (7U)
12480 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
12481 #define USART_SR_TXE USART_SR_TXE_Msk
12482 #define USART_SR_LBD_Pos (8U)
12483 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
12484 #define USART_SR_LBD USART_SR_LBD_Msk
12485 #define USART_SR_CTS_Pos (9U)
12486 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
12487 #define USART_SR_CTS USART_SR_CTS_Msk
12489 /******************* Bit definition for USART_DR register *******************/
12490 #define USART_DR_DR_Pos (0U)
12491 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
12492 #define USART_DR_DR USART_DR_DR_Msk
12494 /****************** Bit definition for USART_BRR register *******************/
12495 #define USART_BRR_DIV_Fraction_Pos (0U)
12496 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
12497 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
12498 #define USART_BRR_DIV_Mantissa_Pos (4U)
12499 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
12500 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
12502 /****************** Bit definition for USART_CR1 register *******************/
12503 #define USART_CR1_SBK_Pos (0U)
12504 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
12505 #define USART_CR1_SBK USART_CR1_SBK_Msk
12506 #define USART_CR1_RWU_Pos (1U)
12507 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
12508 #define USART_CR1_RWU USART_CR1_RWU_Msk
12509 #define USART_CR1_RE_Pos (2U)
12510 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
12511 #define USART_CR1_RE USART_CR1_RE_Msk
12512 #define USART_CR1_TE_Pos (3U)
12513 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
12514 #define USART_CR1_TE USART_CR1_TE_Msk
12515 #define USART_CR1_IDLEIE_Pos (4U)
12516 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
12517 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
12518 #define USART_CR1_RXNEIE_Pos (5U)
12519 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
12520 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
12521 #define USART_CR1_TCIE_Pos (6U)
12522 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
12523 #define USART_CR1_TCIE USART_CR1_TCIE_Msk
12524 #define USART_CR1_TXEIE_Pos (7U)
12525 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
12526 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
12527 #define USART_CR1_PEIE_Pos (8U)
12528 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
12529 #define USART_CR1_PEIE USART_CR1_PEIE_Msk
12530 #define USART_CR1_PS_Pos (9U)
12531 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
12532 #define USART_CR1_PS USART_CR1_PS_Msk
12533 #define USART_CR1_PCE_Pos (10U)
12534 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
12535 #define USART_CR1_PCE USART_CR1_PCE_Msk
12536 #define USART_CR1_WAKE_Pos (11U)
12537 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
12538 #define USART_CR1_WAKE USART_CR1_WAKE_Msk
12539 #define USART_CR1_M_Pos (12U)
12540 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
12541 #define USART_CR1_M USART_CR1_M_Msk
12542 #define USART_CR1_UE_Pos (13U)
12543 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
12544 #define USART_CR1_UE USART_CR1_UE_Msk
12545 #define USART_CR1_OVER8_Pos (15U)
12546 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
12547 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk
12549 /****************** Bit definition for USART_CR2 register *******************/
12550 #define USART_CR2_ADD_Pos (0U)
12551 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
12552 #define USART_CR2_ADD USART_CR2_ADD_Msk
12553 #define USART_CR2_LBDL_Pos (5U)
12554 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
12555 #define USART_CR2_LBDL USART_CR2_LBDL_Msk
12556 #define USART_CR2_LBDIE_Pos (6U)
12557 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
12558 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
12559 #define USART_CR2_LBCL_Pos (8U)
12560 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
12561 #define USART_CR2_LBCL USART_CR2_LBCL_Msk
12562 #define USART_CR2_CPHA_Pos (9U)
12563 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
12564 #define USART_CR2_CPHA USART_CR2_CPHA_Msk
12565 #define USART_CR2_CPOL_Pos (10U)
12566 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
12567 #define USART_CR2_CPOL USART_CR2_CPOL_Msk
12568 #define USART_CR2_CLKEN_Pos (11U)
12569 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
12570 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
12572 #define USART_CR2_STOP_Pos (12U)
12573 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
12574 #define USART_CR2_STOP USART_CR2_STOP_Msk
12575 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
12576 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
12578 #define USART_CR2_LINEN_Pos (14U)
12579 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
12580 #define USART_CR2_LINEN USART_CR2_LINEN_Msk
12582 /****************** Bit definition for USART_CR3 register *******************/
12583 #define USART_CR3_EIE_Pos (0U)
12584 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
12585 #define USART_CR3_EIE USART_CR3_EIE_Msk
12586 #define USART_CR3_IREN_Pos (1U)
12587 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
12588 #define USART_CR3_IREN USART_CR3_IREN_Msk
12589 #define USART_CR3_IRLP_Pos (2U)
12590 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
12591 #define USART_CR3_IRLP USART_CR3_IRLP_Msk
12592 #define USART_CR3_HDSEL_Pos (3U)
12593 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
12594 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
12595 #define USART_CR3_NACK_Pos (4U)
12596 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
12597 #define USART_CR3_NACK USART_CR3_NACK_Msk
12598 #define USART_CR3_SCEN_Pos (5U)
12599 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
12600 #define USART_CR3_SCEN USART_CR3_SCEN_Msk
12601 #define USART_CR3_DMAR_Pos (6U)
12602 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
12603 #define USART_CR3_DMAR USART_CR3_DMAR_Msk
12604 #define USART_CR3_DMAT_Pos (7U)
12605 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
12606 #define USART_CR3_DMAT USART_CR3_DMAT_Msk
12607 #define USART_CR3_RTSE_Pos (8U)
12608 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
12609 #define USART_CR3_RTSE USART_CR3_RTSE_Msk
12610 #define USART_CR3_CTSE_Pos (9U)
12611 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
12612 #define USART_CR3_CTSE USART_CR3_CTSE_Msk
12613 #define USART_CR3_CTSIE_Pos (10U)
12614 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
12615 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
12616 #define USART_CR3_ONEBIT_Pos (11U)
12617 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
12618 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
12620 /****************** Bit definition for USART_GTPR register ******************/
12621 #define USART_GTPR_PSC_Pos (0U)
12622 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
12623 #define USART_GTPR_PSC USART_GTPR_PSC_Msk
12624 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
12625 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
12626 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
12627 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
12628 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
12629 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
12630 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
12631 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
12633 #define USART_GTPR_GT_Pos (8U)
12634 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
12635 #define USART_GTPR_GT USART_GTPR_GT_Msk
12637 /******************************************************************************/
12638 /* */
12639 /* Window WATCHDOG */
12640 /* */
12641 /******************************************************************************/
12642 /******************* Bit definition for WWDG_CR register ********************/
12643 #define WWDG_CR_T_Pos (0U)
12644 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
12645 #define WWDG_CR_T WWDG_CR_T_Msk
12646 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
12647 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
12648 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
12649 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
12650 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
12651 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
12652 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
12653 /* Legacy defines */
12654 #define WWDG_CR_T0 WWDG_CR_T_0
12655 #define WWDG_CR_T1 WWDG_CR_T_1
12656 #define WWDG_CR_T2 WWDG_CR_T_2
12657 #define WWDG_CR_T3 WWDG_CR_T_3
12658 #define WWDG_CR_T4 WWDG_CR_T_4
12659 #define WWDG_CR_T5 WWDG_CR_T_5
12660 #define WWDG_CR_T6 WWDG_CR_T_6
12661 
12662 #define WWDG_CR_WDGA_Pos (7U)
12663 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
12664 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
12666 /******************* Bit definition for WWDG_CFR register *******************/
12667 #define WWDG_CFR_W_Pos (0U)
12668 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
12669 #define WWDG_CFR_W WWDG_CFR_W_Msk
12670 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
12671 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
12672 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
12673 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
12674 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
12675 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
12676 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
12677 /* Legacy defines */
12678 #define WWDG_CFR_W0 WWDG_CFR_W_0
12679 #define WWDG_CFR_W1 WWDG_CFR_W_1
12680 #define WWDG_CFR_W2 WWDG_CFR_W_2
12681 #define WWDG_CFR_W3 WWDG_CFR_W_3
12682 #define WWDG_CFR_W4 WWDG_CFR_W_4
12683 #define WWDG_CFR_W5 WWDG_CFR_W_5
12684 #define WWDG_CFR_W6 WWDG_CFR_W_6
12685 
12686 #define WWDG_CFR_WDGTB_Pos (7U)
12687 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
12688 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
12689 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
12690 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
12691 /* Legacy defines */
12692 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
12693 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
12694 
12695 #define WWDG_CFR_EWI_Pos (9U)
12696 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
12697 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
12699 /******************* Bit definition for WWDG_SR register ********************/
12700 #define WWDG_SR_EWIF_Pos (0U)
12701 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
12702 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
12705 /******************************************************************************/
12706 /* */
12707 /* DBG */
12708 /* */
12709 /******************************************************************************/
12710 /******************** Bit definition for DBGMCU_IDCODE register *************/
12711 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
12712 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
12713 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
12714 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
12715 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
12716 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
12717 
12718 /******************** Bit definition for DBGMCU_CR register *****************/
12719 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
12720 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
12721 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
12722 #define DBGMCU_CR_DBG_STOP_Pos (1U)
12723 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
12724 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
12725 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
12726 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
12727 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
12728 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
12729 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
12730 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
12731 
12732 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
12733 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
12734 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
12735 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
12736 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
12738 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
12739 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
12740 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
12741 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
12742 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
12743 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
12744 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
12745 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
12746 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
12747 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
12748 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
12749 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
12750 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
12751 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
12752 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
12753 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
12754 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
12755 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
12756 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
12757 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
12758 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
12759 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
12760 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
12761 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
12762 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
12763 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
12764 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
12765 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
12766 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
12767 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
12768 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
12769 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
12770 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
12771 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
12772 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
12773 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
12774 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
12775 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
12776 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
12777 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
12778 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
12779 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
12780 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
12781 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
12782 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
12783 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
12784 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
12785 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
12786 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
12787 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
12788 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
12789 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
12790 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
12791 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
12792 
12793 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
12794 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
12795 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
12796 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
12797 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
12798 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
12799 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
12800 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
12801 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
12802 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
12803 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
12804 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
12805 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
12806 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
12807 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
12808 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
12809 
12810 /******************************************************************************/
12811 /* */
12812 /* Ethernet MAC Registers bits definitions */
12813 /* */
12814 /******************************************************************************/
12815 /* Bit definition for Ethernet MAC Control Register register */
12816 #define ETH_MACCR_WD_Pos (23U)
12817 #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
12818 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
12819 #define ETH_MACCR_JD_Pos (22U)
12820 #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
12821 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
12822 #define ETH_MACCR_IFG_Pos (17U)
12823 #define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
12824 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
12825 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
12826 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
12827 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
12828 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
12829 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
12830 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
12831 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
12832 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
12833 #define ETH_MACCR_CSD_Pos (16U)
12834 #define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
12835 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
12836 #define ETH_MACCR_FES_Pos (14U)
12837 #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
12838 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
12839 #define ETH_MACCR_ROD_Pos (13U)
12840 #define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
12841 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
12842 #define ETH_MACCR_LM_Pos (12U)
12843 #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
12844 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
12845 #define ETH_MACCR_DM_Pos (11U)
12846 #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
12847 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
12848 #define ETH_MACCR_IPCO_Pos (10U)
12849 #define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
12850 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
12851 #define ETH_MACCR_RD_Pos (9U)
12852 #define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
12853 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
12854 #define ETH_MACCR_APCS_Pos (7U)
12855 #define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
12856 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
12857 #define ETH_MACCR_BL_Pos (5U)
12858 #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
12859 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
12860  a transmission attempt during retries after a collision: 0 =< r <2^k */
12861 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
12862 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
12863 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
12864 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
12865 #define ETH_MACCR_DC_Pos (4U)
12866 #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
12867 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
12868 #define ETH_MACCR_TE_Pos (3U)
12869 #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
12870 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
12871 #define ETH_MACCR_RE_Pos (2U)
12872 #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
12873 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
12874 
12875 /* Bit definition for Ethernet MAC Frame Filter Register */
12876 #define ETH_MACFFR_RA_Pos (31U)
12877 #define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
12878 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
12879 #define ETH_MACFFR_HPF_Pos (10U)
12880 #define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
12881 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
12882 #define ETH_MACFFR_SAF_Pos (9U)
12883 #define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
12884 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
12885 #define ETH_MACFFR_SAIF_Pos (8U)
12886 #define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
12887 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
12888 #define ETH_MACFFR_PCF_Pos (6U)
12889 #define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
12890 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
12891 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
12892 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
12893 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
12894 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
12895 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
12896 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
12897 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
12898 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
12899 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
12900 #define ETH_MACFFR_BFD_Pos (5U)
12901 #define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
12902 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
12903 #define ETH_MACFFR_PAM_Pos (4U)
12904 #define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
12905 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
12906 #define ETH_MACFFR_DAIF_Pos (3U)
12907 #define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
12908 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
12909 #define ETH_MACFFR_HM_Pos (2U)
12910 #define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
12911 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
12912 #define ETH_MACFFR_HU_Pos (1U)
12913 #define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
12914 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
12915 #define ETH_MACFFR_PM_Pos (0U)
12916 #define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
12917 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
12918 
12919 /* Bit definition for Ethernet MAC Hash Table High Register */
12920 #define ETH_MACHTHR_HTH_Pos (0U)
12921 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
12922 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
12923 
12924 /* Bit definition for Ethernet MAC Hash Table Low Register */
12925 #define ETH_MACHTLR_HTL_Pos (0U)
12926 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
12927 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
12928 
12929 /* Bit definition for Ethernet MAC MII Address Register */
12930 #define ETH_MACMIIAR_PA_Pos (11U)
12931 #define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
12932 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
12933 #define ETH_MACMIIAR_MR_Pos (6U)
12934 #define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
12935 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
12936 #define ETH_MACMIIAR_CR_Pos (2U)
12937 #define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
12938 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
12939 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
12940 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
12941 #define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
12942 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
12943 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
12944 #define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
12945 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
12946 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
12947 #define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
12948 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
12949 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
12950 #define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
12951 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
12952 #define ETH_MACMIIAR_MW_Pos (1U)
12953 #define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
12954 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
12955 #define ETH_MACMIIAR_MB_Pos (0U)
12956 #define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
12957 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
12958 
12959 /* Bit definition for Ethernet MAC MII Data Register */
12960 #define ETH_MACMIIDR_MD_Pos (0U)
12961 #define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
12962 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
12963 
12964 /* Bit definition for Ethernet MAC Flow Control Register */
12965 #define ETH_MACFCR_PT_Pos (16U)
12966 #define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
12967 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
12968 #define ETH_MACFCR_ZQPD_Pos (7U)
12969 #define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
12970 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
12971 #define ETH_MACFCR_PLT_Pos (4U)
12972 #define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
12973 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
12974 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
12975 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
12976 #define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
12977 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
12978 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
12979 #define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
12980 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
12981 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
12982 #define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
12983 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
12984 #define ETH_MACFCR_UPFD_Pos (3U)
12985 #define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
12986 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
12987 #define ETH_MACFCR_RFCE_Pos (2U)
12988 #define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
12989 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
12990 #define ETH_MACFCR_TFCE_Pos (1U)
12991 #define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
12992 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
12993 #define ETH_MACFCR_FCBBPA_Pos (0U)
12994 #define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
12995 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
12996 
12997 /* Bit definition for Ethernet MAC VLAN Tag Register */
12998 #define ETH_MACVLANTR_VLANTC_Pos (16U)
12999 #define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
13000 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
13001 #define ETH_MACVLANTR_VLANTI_Pos (0U)
13002 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
13003 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
13004 
13005 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
13006 #define ETH_MACRWUFFR_D_Pos (0U)
13007 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
13008 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
13009 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
13010  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
13011 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
13012  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
13013  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
13014  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
13015  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
13016  RSVD - Filter1 Command - RSVD - Filter0 Command
13017  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
13018  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
13019  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
13020 
13021 /* Bit definition for Ethernet MAC PMT Control and Status Register */
13022 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
13023 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
13024 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
13025 #define ETH_MACPMTCSR_GU_Pos (9U)
13026 #define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
13027 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
13028 #define ETH_MACPMTCSR_WFR_Pos (6U)
13029 #define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
13030 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
13031 #define ETH_MACPMTCSR_MPR_Pos (5U)
13032 #define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
13033 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
13034 #define ETH_MACPMTCSR_WFE_Pos (2U)
13035 #define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
13036 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
13037 #define ETH_MACPMTCSR_MPE_Pos (1U)
13038 #define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
13039 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
13040 #define ETH_MACPMTCSR_PD_Pos (0U)
13041 #define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
13042 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
13043 
13044 /* Bit definition for Ethernet MAC debug Register */
13045 #define ETH_MACDBGR_TFF_Pos (25U)
13046 #define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
13047 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
13048 #define ETH_MACDBGR_TFNE_Pos (24U)
13049 #define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
13050 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
13051 #define ETH_MACDBGR_TFWA_Pos (22U)
13052 #define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
13053 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
13054 #define ETH_MACDBGR_TFRS_Pos (20U)
13055 #define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
13056 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
13057 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
13058 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
13059 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
13060 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
13061 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
13062 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
13063 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
13064 #define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
13065 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
13066 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
13067 #define ETH_MACDBGR_MTP_Pos (19U)
13068 #define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
13069 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
13070 #define ETH_MACDBGR_MTFCS_Pos (17U)
13071 #define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
13072 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
13073 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
13074 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
13075 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
13076 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
13077 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
13078 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
13079 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
13080 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
13081 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
13082 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
13083 #define ETH_MACDBGR_MMTEA_Pos (16U)
13084 #define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
13085 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
13086 #define ETH_MACDBGR_RFFL_Pos (8U)
13087 #define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
13088 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
13089 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
13090 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
13091 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
13092 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
13093 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
13094 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
13095 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
13096 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
13097 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
13098 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
13099 #define ETH_MACDBGR_RFRCS_Pos (5U)
13100 #define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
13101 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
13102 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
13103 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
13104 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
13105 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
13106 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
13107 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
13108 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
13109 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
13110 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
13111 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
13112 #define ETH_MACDBGR_RFWRA_Pos (4U)
13113 #define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
13114 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
13115 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
13116 #define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
13117 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
13118 #define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
13119 #define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
13120 #define ETH_MACDBGR_MMRPEA_Pos (0U)
13121 #define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
13122 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
13123 
13124 /* Bit definition for Ethernet MAC Status Register */
13125 #define ETH_MACSR_TSTS_Pos (9U)
13126 #define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
13127 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
13128 #define ETH_MACSR_MMCTS_Pos (6U)
13129 #define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
13130 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
13131 #define ETH_MACSR_MMMCRS_Pos (5U)
13132 #define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
13133 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
13134 #define ETH_MACSR_MMCS_Pos (4U)
13135 #define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
13136 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
13137 #define ETH_MACSR_PMTS_Pos (3U)
13138 #define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
13139 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
13140 
13141 /* Bit definition for Ethernet MAC Interrupt Mask Register */
13142 #define ETH_MACIMR_TSTIM_Pos (9U)
13143 #define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
13144 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
13145 #define ETH_MACIMR_PMTIM_Pos (3U)
13146 #define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
13147 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
13148 
13149 /* Bit definition for Ethernet MAC Address0 High Register */
13150 #define ETH_MACA0HR_MACA0H_Pos (0U)
13151 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
13152 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
13153 
13154 /* Bit definition for Ethernet MAC Address0 Low Register */
13155 #define ETH_MACA0LR_MACA0L_Pos (0U)
13156 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
13157 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
13158 
13159 /* Bit definition for Ethernet MAC Address1 High Register */
13160 #define ETH_MACA1HR_AE_Pos (31U)
13161 #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
13162 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
13163 #define ETH_MACA1HR_SA_Pos (30U)
13164 #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
13165 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
13166 #define ETH_MACA1HR_MBC_Pos (24U)
13167 #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
13168 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
13169 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13170 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13171 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13172 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13173 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13174 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
13175 #define ETH_MACA1HR_MACA1H_Pos (0U)
13176 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
13177 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
13178 
13179 /* Bit definition for Ethernet MAC Address1 Low Register */
13180 #define ETH_MACA1LR_MACA1L_Pos (0U)
13181 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
13182 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
13183 
13184 /* Bit definition for Ethernet MAC Address2 High Register */
13185 #define ETH_MACA2HR_AE_Pos (31U)
13186 #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
13187 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
13188 #define ETH_MACA2HR_SA_Pos (30U)
13189 #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
13190 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
13191 #define ETH_MACA2HR_MBC_Pos (24U)
13192 #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
13193 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
13194 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13195 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13196 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13197 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13198 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13199 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
13200 #define ETH_MACA2HR_MACA2H_Pos (0U)
13201 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
13202 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
13203 
13204 /* Bit definition for Ethernet MAC Address2 Low Register */
13205 #define ETH_MACA2LR_MACA2L_Pos (0U)
13206 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
13207 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
13208 
13209 /* Bit definition for Ethernet MAC Address3 High Register */
13210 #define ETH_MACA3HR_AE_Pos (31U)
13211 #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
13212 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
13213 #define ETH_MACA3HR_SA_Pos (30U)
13214 #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
13215 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
13216 #define ETH_MACA3HR_MBC_Pos (24U)
13217 #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
13218 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
13219 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13220 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13221 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13222 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13223 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13224 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
13225 #define ETH_MACA3HR_MACA3H_Pos (0U)
13226 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
13227 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
13228 
13229 /* Bit definition for Ethernet MAC Address3 Low Register */
13230 #define ETH_MACA3LR_MACA3L_Pos (0U)
13231 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
13232 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
13233 
13234 /******************************************************************************/
13235 /* Ethernet MMC Registers bits definition */
13236 /******************************************************************************/
13237 
13238 /* Bit definition for Ethernet MMC Contol Register */
13239 #define ETH_MMCCR_MCFHP_Pos (5U)
13240 #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
13241 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
13242 #define ETH_MMCCR_MCP_Pos (4U)
13243 #define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
13244 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
13245 #define ETH_MMCCR_MCF_Pos (3U)
13246 #define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
13247 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
13248 #define ETH_MMCCR_ROR_Pos (2U)
13249 #define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
13250 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
13251 #define ETH_MMCCR_CSR_Pos (1U)
13252 #define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
13253 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
13254 #define ETH_MMCCR_CR_Pos (0U)
13255 #define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
13256 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
13257 
13258 /* Bit definition for Ethernet MMC Receive Interrupt Register */
13259 #define ETH_MMCRIR_RGUFS_Pos (17U)
13260 #define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
13261 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
13262 #define ETH_MMCRIR_RFAES_Pos (6U)
13263 #define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
13264 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
13265 #define ETH_MMCRIR_RFCES_Pos (5U)
13266 #define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
13267 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
13268 
13269 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
13270 #define ETH_MMCTIR_TGFS_Pos (21U)
13271 #define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
13272 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
13273 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
13274 #define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
13275 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
13276 #define ETH_MMCTIR_TGFSCS_Pos (14U)
13277 #define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
13278 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
13279 
13280 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
13281 #define ETH_MMCRIMR_RGUFM_Pos (17U)
13282 #define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
13283 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
13284 #define ETH_MMCRIMR_RFAEM_Pos (6U)
13285 #define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
13286 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
13287 #define ETH_MMCRIMR_RFCEM_Pos (5U)
13288 #define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
13289 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
13290 
13291 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
13292 #define ETH_MMCTIMR_TGFM_Pos (21U)
13293 #define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
13294 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
13295 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
13296 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
13297 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
13298 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
13299 #define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
13300 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
13301 
13302 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
13303 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
13304 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
13305 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
13306 
13307 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
13308 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
13309 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
13310 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
13311 
13312 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
13313 #define ETH_MMCTGFCR_TGFC_Pos (0U)
13314 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
13315 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
13316 
13317 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
13318 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
13319 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
13320 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
13321 
13322 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
13323 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
13324 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
13325 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
13326 
13327 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
13328 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
13329 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
13330 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
13331 
13332 /******************************************************************************/
13333 /* Ethernet PTP Registers bits definition */
13334 /******************************************************************************/
13335 
13336 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
13337 #define ETH_PTPTSCR_TSCNT_Pos (16U)
13338 #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
13339 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
13340 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
13341 #define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos)
13342 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
13343 #define ETH_PTPTSSR_TSSEME_Pos (14U)
13344 #define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos)
13345 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
13346 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
13347 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos)
13348 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
13349 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
13350 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos)
13351 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
13352 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
13353 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos)
13354 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
13355 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
13356 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos)
13357 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
13358 #define ETH_PTPTSSR_TSSSR_Pos (9U)
13359 #define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos)
13360 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
13361 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
13362 #define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos)
13363 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
13364 
13365 #define ETH_PTPTSCR_TSARU_Pos (5U)
13366 #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
13367 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
13368 #define ETH_PTPTSCR_TSITE_Pos (4U)
13369 #define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
13370 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
13371 #define ETH_PTPTSCR_TSSTU_Pos (3U)
13372 #define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
13373 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
13374 #define ETH_PTPTSCR_TSSTI_Pos (2U)
13375 #define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
13376 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
13377 #define ETH_PTPTSCR_TSFCU_Pos (1U)
13378 #define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
13379 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
13380 #define ETH_PTPTSCR_TSE_Pos (0U)
13381 #define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
13382 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
13383 
13384 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
13385 #define ETH_PTPSSIR_STSSI_Pos (0U)
13386 #define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
13387 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
13388 
13389 /* Bit definition for Ethernet PTP Time Stamp High Register */
13390 #define ETH_PTPTSHR_STS_Pos (0U)
13391 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
13392 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
13393 
13394 /* Bit definition for Ethernet PTP Time Stamp Low Register */
13395 #define ETH_PTPTSLR_STPNS_Pos (31U)
13396 #define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
13397 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
13398 #define ETH_PTPTSLR_STSS_Pos (0U)
13399 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
13400 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
13401 
13402 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
13403 #define ETH_PTPTSHUR_TSUS_Pos (0U)
13404 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
13405 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
13406 
13407 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
13408 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
13409 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
13410 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
13411 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
13412 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
13413 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
13414 
13415 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
13416 #define ETH_PTPTSAR_TSA_Pos (0U)
13417 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
13418 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
13419 
13420 /* Bit definition for Ethernet PTP Target Time High Register */
13421 #define ETH_PTPTTHR_TTSH_Pos (0U)
13422 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
13423 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
13424 
13425 /* Bit definition for Ethernet PTP Target Time Low Register */
13426 #define ETH_PTPTTLR_TTSL_Pos (0U)
13427 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
13428 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
13429 
13430 /* Bit definition for Ethernet PTP Time Stamp Status Register */
13431 #define ETH_PTPTSSR_TSTTR_Pos (5U)
13432 #define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
13433 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
13434 #define ETH_PTPTSSR_TSSO_Pos (4U)
13435 #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
13436 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
13437 
13438 /******************************************************************************/
13439 /* Ethernet DMA Registers bits definition */
13440 /******************************************************************************/
13441 
13442 /* Bit definition for Ethernet DMA Bus Mode Register */
13443 #define ETH_DMABMR_AAB_Pos (25U)
13444 #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
13445 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
13446 #define ETH_DMABMR_FPM_Pos (24U)
13447 #define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
13448 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
13449 #define ETH_DMABMR_USP_Pos (23U)
13450 #define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
13451 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
13452 #define ETH_DMABMR_RDP_Pos (17U)
13453 #define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
13454 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
13455 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
13456 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
13457 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13458 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13459 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13460 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13461 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13462 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13463 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13464 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13465 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
13466 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
13467 #define ETH_DMABMR_FB_Pos (16U)
13468 #define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
13469 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
13470 #define ETH_DMABMR_RTPR_Pos (14U)
13471 #define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
13472 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
13473 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
13474 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
13475 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
13476 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
13477 #define ETH_DMABMR_PBL_Pos (8U)
13478 #define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
13479 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
13480 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
13481 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
13482 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13483 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13484 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13485 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13486 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13487 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13488 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13489 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13490 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
13491 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
13492 #define ETH_DMABMR_EDE_Pos (7U)
13493 #define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
13494 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
13495 #define ETH_DMABMR_DSL_Pos (2U)
13496 #define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
13497 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
13498 #define ETH_DMABMR_DA_Pos (1U)
13499 #define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
13500 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
13501 #define ETH_DMABMR_SR_Pos (0U)
13502 #define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
13503 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
13504 
13505 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
13506 #define ETH_DMATPDR_TPD_Pos (0U)
13507 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
13508 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
13509 
13510 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
13511 #define ETH_DMARPDR_RPD_Pos (0U)
13512 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
13513 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
13514 
13515 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
13516 #define ETH_DMARDLAR_SRL_Pos (0U)
13517 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
13518 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
13519 
13520 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
13521 #define ETH_DMATDLAR_STL_Pos (0U)
13522 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
13523 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
13524 
13525 /* Bit definition for Ethernet DMA Status Register */
13526 #define ETH_DMASR_TSTS_Pos (29U)
13527 #define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
13528 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
13529 #define ETH_DMASR_PMTS_Pos (28U)
13530 #define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
13531 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
13532 #define ETH_DMASR_MMCS_Pos (27U)
13533 #define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
13534 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
13535 #define ETH_DMASR_EBS_Pos (23U)
13536 #define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
13537 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
13538  /* combination with EBS[2:0] for GetFlagStatus function */
13539 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
13540 #define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
13541 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
13542 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
13543 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
13544 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
13545 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
13546 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
13547 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
13548 #define ETH_DMASR_TPS_Pos (20U)
13549 #define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
13550 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
13551 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
13552 #define ETH_DMASR_TPS_Fetching_Pos (20U)
13553 #define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
13554 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
13555 #define ETH_DMASR_TPS_Waiting_Pos (21U)
13556 #define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
13557 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
13558 #define ETH_DMASR_TPS_Reading_Pos (20U)
13559 #define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
13560 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
13561 #define ETH_DMASR_TPS_Suspended_Pos (21U)
13562 #define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
13563 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
13564 #define ETH_DMASR_TPS_Closing_Pos (20U)
13565 #define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
13566 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
13567 #define ETH_DMASR_RPS_Pos (17U)
13568 #define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
13569 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
13570 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
13571 #define ETH_DMASR_RPS_Fetching_Pos (17U)
13572 #define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
13573 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
13574 #define ETH_DMASR_RPS_Waiting_Pos (17U)
13575 #define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
13576 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
13577 #define ETH_DMASR_RPS_Suspended_Pos (19U)
13578 #define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
13579 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
13580 #define ETH_DMASR_RPS_Closing_Pos (17U)
13581 #define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
13582 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
13583 #define ETH_DMASR_RPS_Queuing_Pos (17U)
13584 #define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
13585 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
13586 #define ETH_DMASR_NIS_Pos (16U)
13587 #define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
13588 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
13589 #define ETH_DMASR_AIS_Pos (15U)
13590 #define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
13591 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
13592 #define ETH_DMASR_ERS_Pos (14U)
13593 #define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
13594 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
13595 #define ETH_DMASR_FBES_Pos (13U)
13596 #define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
13597 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
13598 #define ETH_DMASR_ETS_Pos (10U)
13599 #define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
13600 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
13601 #define ETH_DMASR_RWTS_Pos (9U)
13602 #define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
13603 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
13604 #define ETH_DMASR_RPSS_Pos (8U)
13605 #define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
13606 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
13607 #define ETH_DMASR_RBUS_Pos (7U)
13608 #define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
13609 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
13610 #define ETH_DMASR_RS_Pos (6U)
13611 #define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
13612 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
13613 #define ETH_DMASR_TUS_Pos (5U)
13614 #define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
13615 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
13616 #define ETH_DMASR_ROS_Pos (4U)
13617 #define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
13618 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
13619 #define ETH_DMASR_TJTS_Pos (3U)
13620 #define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
13621 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
13622 #define ETH_DMASR_TBUS_Pos (2U)
13623 #define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
13624 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
13625 #define ETH_DMASR_TPSS_Pos (1U)
13626 #define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
13627 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
13628 #define ETH_DMASR_TS_Pos (0U)
13629 #define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
13630 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
13631 
13632 /* Bit definition for Ethernet DMA Operation Mode Register */
13633 #define ETH_DMAOMR_DTCEFD_Pos (26U)
13634 #define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
13635 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
13636 #define ETH_DMAOMR_RSF_Pos (25U)
13637 #define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
13638 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
13639 #define ETH_DMAOMR_DFRF_Pos (24U)
13640 #define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
13641 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
13642 #define ETH_DMAOMR_TSF_Pos (21U)
13643 #define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
13644 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
13645 #define ETH_DMAOMR_FTF_Pos (20U)
13646 #define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
13647 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
13648 #define ETH_DMAOMR_TTC_Pos (14U)
13649 #define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
13650 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
13651 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
13652 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
13653 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
13654 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
13655 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
13656 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
13657 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
13658 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
13659 #define ETH_DMAOMR_ST_Pos (13U)
13660 #define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
13661 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
13662 #define ETH_DMAOMR_FEF_Pos (7U)
13663 #define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
13664 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
13665 #define ETH_DMAOMR_FUGF_Pos (6U)
13666 #define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
13667 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
13668 #define ETH_DMAOMR_RTC_Pos (3U)
13669 #define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
13670 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
13671 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
13672 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
13673 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
13674 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
13675 #define ETH_DMAOMR_OSF_Pos (2U)
13676 #define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
13677 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
13678 #define ETH_DMAOMR_SR_Pos (1U)
13679 #define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
13680 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
13681 
13682 /* Bit definition for Ethernet DMA Interrupt Enable Register */
13683 #define ETH_DMAIER_NISE_Pos (16U)
13684 #define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
13685 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
13686 #define ETH_DMAIER_AISE_Pos (15U)
13687 #define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
13688 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
13689 #define ETH_DMAIER_ERIE_Pos (14U)
13690 #define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
13691 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
13692 #define ETH_DMAIER_FBEIE_Pos (13U)
13693 #define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
13694 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
13695 #define ETH_DMAIER_ETIE_Pos (10U)
13696 #define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
13697 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
13698 #define ETH_DMAIER_RWTIE_Pos (9U)
13699 #define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
13700 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
13701 #define ETH_DMAIER_RPSIE_Pos (8U)
13702 #define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
13703 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
13704 #define ETH_DMAIER_RBUIE_Pos (7U)
13705 #define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
13706 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
13707 #define ETH_DMAIER_RIE_Pos (6U)
13708 #define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
13709 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
13710 #define ETH_DMAIER_TUIE_Pos (5U)
13711 #define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
13712 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
13713 #define ETH_DMAIER_ROIE_Pos (4U)
13714 #define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
13715 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
13716 #define ETH_DMAIER_TJTIE_Pos (3U)
13717 #define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
13718 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
13719 #define ETH_DMAIER_TBUIE_Pos (2U)
13720 #define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
13721 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
13722 #define ETH_DMAIER_TPSIE_Pos (1U)
13723 #define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
13724 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
13725 #define ETH_DMAIER_TIE_Pos (0U)
13726 #define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
13727 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
13728 
13729 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
13730 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
13731 #define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
13732 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
13733 #define ETH_DMAMFBOCR_MFA_Pos (17U)
13734 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
13735 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
13736 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
13737 #define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
13738 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
13739 #define ETH_DMAMFBOCR_MFC_Pos (0U)
13740 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
13741 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
13742 
13743 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
13744 #define ETH_DMACHTDR_HTDAP_Pos (0U)
13745 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
13746 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
13747 
13748 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
13749 #define ETH_DMACHRDR_HRDAP_Pos (0U)
13750 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
13751 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
13752 
13753 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
13754 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
13755 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
13756 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
13757 
13758 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
13759 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
13760 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
13761 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
13762 
13763 /******************************************************************************/
13764 /* */
13765 /* USB_OTG */
13766 /* */
13767 /******************************************************************************/
13768 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
13769 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13770 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
13771 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
13772 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13773 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
13774 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
13775 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13776 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
13777 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
13778 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13779 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
13780 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
13781 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13782 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
13783 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
13784 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13785 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
13786 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
13787 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13788 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
13789 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
13790 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13791 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
13792 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
13793 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13794 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
13795 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
13796 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
13797 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
13798 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
13800 /******************** Bit definition forUSB_OTG_HCFG register ********************/
13801 
13802 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13803 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
13804 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
13805 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
13806 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
13807 #define USB_OTG_HCFG_FSLSS_Pos (2U)
13808 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
13809 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
13811 /******************** Bit definition for USB_OTG_DCFG register ********************/
13812 
13813 #define USB_OTG_DCFG_DSPD_Pos (0U)
13814 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
13815 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
13816 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
13817 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
13818 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13819 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
13820 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
13822 #define USB_OTG_DCFG_DAD_Pos (4U)
13823 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
13824 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
13825 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
13826 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
13827 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
13828 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
13829 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
13830 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
13831 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
13833 #define USB_OTG_DCFG_PFIVL_Pos (11U)
13834 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
13835 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
13836 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
13837 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
13839 #define USB_OTG_DCFG_XCVRDLY_Pos (14U)
13840 #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
13841 #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
13843 #define USB_OTG_DCFG_ERRATIM_Pos (15U)
13844 #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
13845 #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
13847 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13848 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13849 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
13850 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13851 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13853 /******************** Bit definition for USB_OTG_PCGCR register ********************/
13854 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13855 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
13856 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
13857 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13858 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
13859 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
13860 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13861 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
13862 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
13864 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
13865 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
13866 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
13867 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
13868 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13869 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
13870 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
13871 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13872 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
13873 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
13874 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13875 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
13876 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
13877 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13878 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
13879 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
13880 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13881 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
13882 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
13884 /******************** Bit definition for USB_OTG_DCTL register ********************/
13885 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
13886 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
13887 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
13888 #define USB_OTG_DCTL_SDIS_Pos (1U)
13889 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
13890 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
13891 #define USB_OTG_DCTL_GINSTS_Pos (2U)
13892 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
13893 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
13894 #define USB_OTG_DCTL_GONSTS_Pos (3U)
13895 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
13896 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
13898 #define USB_OTG_DCTL_TCTL_Pos (4U)
13899 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
13900 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
13901 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
13902 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
13903 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
13904 #define USB_OTG_DCTL_SGINAK_Pos (7U)
13905 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
13906 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
13907 #define USB_OTG_DCTL_CGINAK_Pos (8U)
13908 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
13909 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
13910 #define USB_OTG_DCTL_SGONAK_Pos (9U)
13911 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
13912 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
13913 #define USB_OTG_DCTL_CGONAK_Pos (10U)
13914 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
13915 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
13916 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13917 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
13918 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
13920 /******************** Bit definition for USB_OTG_HFIR register ********************/
13921 #define USB_OTG_HFIR_FRIVL_Pos (0U)
13922 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
13923 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
13925 /******************** Bit definition for USB_OTG_HFNUM register ********************/
13926 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
13927 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
13928 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
13929 #define USB_OTG_HFNUM_FTREM_Pos (16U)
13930 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
13931 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
13933 /******************** Bit definition for USB_OTG_DSTS register ********************/
13934 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13935 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
13936 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
13938 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13939 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
13940 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
13941 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
13942 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
13943 #define USB_OTG_DSTS_EERR_Pos (3U)
13944 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
13945 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
13946 #define USB_OTG_DSTS_FNSOF_Pos (8U)
13947 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
13948 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
13950 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
13951 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
13952 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
13953 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
13954 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13955 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13956 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
13957 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13958 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13959 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13960 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13961 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13962 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13963 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
13964 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
13965 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13966 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
13967 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
13968 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13969 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
13970 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
13972 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
13973 
13974 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13975 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13976 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
13977 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13978 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13979 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13980 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13981 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
13982 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
13983 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
13984 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
13985 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
13986 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
13987 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
13988 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
13989 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
13990 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
13991 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
13992 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
13993 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
13994 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
13995 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
13996 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
13997 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
13998 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
13999 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
14000 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
14001 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
14002 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
14003 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
14004 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
14005 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
14006 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
14007 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
14008 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
14009 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
14010 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
14011 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
14012 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
14013 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
14014 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
14015 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
14016 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
14017 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
14018 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
14019 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
14020 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
14021 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
14022 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
14023 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
14024 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
14025 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
14026 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
14027 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
14028 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
14029 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
14030 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
14031 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
14032 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
14033 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
14034 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
14036 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
14037 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
14038 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
14039 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
14040 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
14041 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
14042 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
14043 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
14044 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
14045 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
14046 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
14047 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
14048 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
14049 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
14050 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
14051 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
14054 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
14055 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14056 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
14057 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14058 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14059 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14060 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14061 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14062 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
14063 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
14064 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
14065 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
14066 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
14067 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
14069 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
14070 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
14071 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
14072 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
14073 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
14074 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
14075 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
14076 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
14077 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
14078 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
14079 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
14080 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
14081 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
14082 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
14083 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
14084 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
14085 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
14086 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
14087 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
14088 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
14089 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
14090 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
14091 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
14092 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
14093 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
14095 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
14096 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
14097 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
14098 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
14099 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
14100 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14101 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
14102 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14103 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14104 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14105 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14106 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14107 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14108 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14109 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14111 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
14112 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14113 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
14114 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14115 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14116 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14117 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14118 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14119 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14120 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14121 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14123 /******************** Bit definition for USB_OTG_HAINT register ********************/
14124 #define USB_OTG_HAINT_HAINT_Pos (0U)
14125 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
14126 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
14128 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
14129 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
14130 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
14131 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
14132 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
14133 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
14134 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
14135 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
14136 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
14137 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
14138 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
14139 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
14140 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
14141 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
14142 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
14143 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
14144 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
14145 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
14146 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
14147 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
14148 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
14149 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
14150 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
14151 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
14152 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
14153 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
14154 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
14155 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
14156 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
14157 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
14158 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
14159 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
14160 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
14161 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
14162 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
14163 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
14164 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
14165 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
14166 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
14167 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
14168 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
14169 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
14170 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
14171 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
14172 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
14173 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
14174 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
14175 #define USB_OTG_GINTSTS_SOF_Pos (3U)
14176 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
14177 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
14178 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
14179 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
14180 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
14181 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
14182 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
14183 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
14184 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
14185 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
14186 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
14187 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
14188 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
14189 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
14190 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
14191 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
14192 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
14193 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
14194 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
14195 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
14196 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
14197 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
14198 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
14199 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
14200 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
14201 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
14202 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
14203 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
14204 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
14205 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
14206 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
14207 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
14208 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
14209 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
14210 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
14211 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
14212 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
14213 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
14214 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
14215 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
14216 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
14217 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
14218 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
14219 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
14220 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
14221 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
14222 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
14223 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
14224 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
14225 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
14226 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
14227 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
14228 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
14229 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
14230 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
14231 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
14232 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
14233 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
14234 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
14235 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
14236 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
14237 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
14238 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14239 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
14240 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
14241 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14242 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
14243 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
14245 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
14246 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
14247 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
14248 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
14249 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14250 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
14251 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
14252 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
14253 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
14254 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
14255 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14256 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
14257 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
14258 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14259 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
14260 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
14261 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14262 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
14263 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
14264 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14265 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
14266 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
14267 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14268 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
14269 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
14270 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14271 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
14272 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
14273 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
14274 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
14275 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
14276 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14277 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
14278 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
14279 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14280 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
14281 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
14282 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14283 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
14284 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
14285 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14286 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
14287 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
14288 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14289 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
14290 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
14291 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14292 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
14293 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
14294 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14295 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
14296 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
14297 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14298 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
14299 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
14300 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14301 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
14302 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
14303 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14304 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
14305 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
14306 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
14307 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
14308 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
14309 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14310 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
14311 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
14312 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14313 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
14314 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
14315 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14316 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
14317 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
14318 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14319 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
14320 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
14321 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
14322 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
14323 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
14325 /******************** Bit definition for USB_OTG_DAINT register ********************/
14326 #define USB_OTG_DAINT_IEPINT_Pos (0U)
14327 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
14328 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
14329 #define USB_OTG_DAINT_OEPINT_Pos (16U)
14330 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
14331 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
14333 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14334 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14335 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
14336 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
14338 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14339 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14340 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
14341 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
14342 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14343 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
14344 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
14345 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
14346 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
14347 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
14348 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14349 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
14350 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
14352 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14353 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14354 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
14355 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
14356 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14357 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
14358 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
14360 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14361 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14362 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
14363 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
14365 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14366 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14367 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
14368 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
14370 /******************** Bit definition for OTG register ********************/
14371 #define USB_OTG_NPTXFSA_Pos (0U)
14372 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
14373 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
14374 #define USB_OTG_NPTXFD_Pos (16U)
14375 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
14376 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
14377 #define USB_OTG_TX0FSA_Pos (0U)
14378 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
14379 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
14380 #define USB_OTG_TX0FD_Pos (16U)
14381 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
14382 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
14384 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
14385 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14386 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
14387 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
14389 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14390 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14391 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
14392 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
14394 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14395 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14396 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
14397 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14398 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14399 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14400 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14401 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14402 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14403 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14404 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14406 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14407 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14408 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
14409 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14410 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14411 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14412 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14413 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14414 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14415 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14417 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14418 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14419 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
14420 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
14421 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14422 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
14423 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
14425 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14426 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14427 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
14428 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14429 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14430 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14431 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14432 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14433 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14434 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14435 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14436 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14437 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14438 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
14439 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
14441 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14442 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14443 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
14444 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14445 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14446 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14447 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14448 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14449 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14450 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14451 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14452 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14453 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14454 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
14455 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
14457 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14458 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14459 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
14460 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
14462 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
14463 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14464 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
14465 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
14466 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14467 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
14468 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
14470 /******************** Bit definition for USB_OTG_GCCFG register ********************/
14471 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14472 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
14473 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
14474 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
14475 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
14476 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
14477 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
14478 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
14479 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
14480 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
14481 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
14482 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
14483 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
14484 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
14485 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
14486 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
14487 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
14488 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
14490 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
14491 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14492 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
14493 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
14494 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14495 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
14496 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
14498 /******************** Bit definition for USB_OTG_CID register ********************/
14499 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14500 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
14501 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
14503 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14504 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14505 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
14506 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
14507 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14508 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
14509 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
14510 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14511 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
14512 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
14513 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14514 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
14515 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
14516 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14517 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
14518 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
14519 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14520 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
14521 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
14522 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14523 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
14524 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
14525 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14526 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
14527 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
14528 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14529 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
14530 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
14532 /******************** Bit definition for USB_OTG_HPRT register ********************/
14533 #define USB_OTG_HPRT_PCSTS_Pos (0U)
14534 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
14535 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
14536 #define USB_OTG_HPRT_PCDET_Pos (1U)
14537 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
14538 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
14539 #define USB_OTG_HPRT_PENA_Pos (2U)
14540 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
14541 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
14542 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
14543 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
14544 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
14545 #define USB_OTG_HPRT_POCA_Pos (4U)
14546 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
14547 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
14548 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
14549 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
14550 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
14551 #define USB_OTG_HPRT_PRES_Pos (6U)
14552 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
14553 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
14554 #define USB_OTG_HPRT_PSUSP_Pos (7U)
14555 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
14556 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
14557 #define USB_OTG_HPRT_PRST_Pos (8U)
14558 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
14559 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
14561 #define USB_OTG_HPRT_PLSTS_Pos (10U)
14562 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
14563 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
14564 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
14565 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
14566 #define USB_OTG_HPRT_PPWR_Pos (12U)
14567 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
14568 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
14570 #define USB_OTG_HPRT_PTCTL_Pos (13U)
14571 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
14572 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
14573 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
14574 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
14575 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
14576 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
14578 #define USB_OTG_HPRT_PSPD_Pos (17U)
14579 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
14580 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
14581 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
14582 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
14584 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14585 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14586 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
14587 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
14588 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14589 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
14590 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
14591 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14592 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
14593 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
14594 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14595 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
14596 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
14597 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14598 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
14599 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
14600 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14601 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
14602 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
14603 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14604 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
14605 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
14606 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14607 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
14608 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
14609 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14610 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
14611 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
14612 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14613 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
14614 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
14615 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14616 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
14617 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
14619 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14620 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14621 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
14622 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
14623 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14624 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
14625 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
14627 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14628 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14629 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
14630 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
14631 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14632 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
14633 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
14634 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14635 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
14636 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
14637 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14638 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
14639 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
14641 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14642 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14643 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
14644 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14645 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14646 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
14647 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
14648 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
14650 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14651 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14652 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
14653 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14654 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14655 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14656 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14657 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14658 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
14659 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
14660 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14661 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
14662 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
14663 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14664 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
14665 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
14666 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14667 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
14668 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
14669 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14670 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
14671 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
14672 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14673 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
14674 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
14676 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
14677 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14678 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
14679 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
14681 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14682 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
14683 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
14684 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
14685 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
14686 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
14687 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
14688 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14689 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
14690 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
14691 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14692 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
14693 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
14695 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14696 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
14697 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
14698 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
14699 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
14701 #define USB_OTG_HCCHAR_MC_Pos (20U)
14702 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
14703 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
14704 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
14705 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
14707 #define USB_OTG_HCCHAR_DAD_Pos (22U)
14708 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
14709 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
14710 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
14711 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
14712 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
14713 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
14714 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
14715 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
14716 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
14717 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14718 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
14719 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
14720 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14721 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
14722 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
14723 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
14724 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
14725 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
14727 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
14728 
14729 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14730 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
14731 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
14732 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14733 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14734 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14735 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14736 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14737 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14738 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14740 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14741 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
14742 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
14743 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14744 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14745 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14746 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14747 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14748 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14749 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14751 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14752 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14753 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
14754 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14755 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14756 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14757 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
14758 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
14759 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14760 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
14761 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
14763 /******************** Bit definition for USB_OTG_HCINT register ********************/
14764 #define USB_OTG_HCINT_XFRC_Pos (0U)
14765 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
14766 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
14767 #define USB_OTG_HCINT_CHH_Pos (1U)
14768 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
14769 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
14770 #define USB_OTG_HCINT_AHBERR_Pos (2U)
14771 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
14772 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
14773 #define USB_OTG_HCINT_STALL_Pos (3U)
14774 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
14775 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
14776 #define USB_OTG_HCINT_NAK_Pos (4U)
14777 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
14778 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
14779 #define USB_OTG_HCINT_ACK_Pos (5U)
14780 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
14781 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
14782 #define USB_OTG_HCINT_NYET_Pos (6U)
14783 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
14784 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
14785 #define USB_OTG_HCINT_TXERR_Pos (7U)
14786 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
14787 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
14788 #define USB_OTG_HCINT_BBERR_Pos (8U)
14789 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
14790 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
14791 #define USB_OTG_HCINT_FRMOR_Pos (9U)
14792 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
14793 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
14794 #define USB_OTG_HCINT_DTERR_Pos (10U)
14795 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
14796 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
14798 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
14799 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
14800 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
14801 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
14802 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14803 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
14804 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
14805 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
14806 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
14807 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
14808 #define USB_OTG_DIEPINT_TOC_Pos (3U)
14809 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
14810 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
14811 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14812 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
14813 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
14814 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
14815 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
14816 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
14817 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14818 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
14819 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
14820 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
14821 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
14822 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
14823 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14824 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
14825 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
14826 #define USB_OTG_DIEPINT_BNA_Pos (9U)
14827 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
14828 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
14829 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14830 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
14831 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
14832 #define USB_OTG_DIEPINT_BERR_Pos (12U)
14833 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
14834 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
14835 #define USB_OTG_DIEPINT_NAK_Pos (13U)
14836 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
14837 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
14839 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
14840 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14841 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
14842 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
14843 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14844 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
14845 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
14846 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14847 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
14848 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
14849 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14850 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
14851 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
14852 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14853 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
14854 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
14855 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14856 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
14857 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
14858 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
14859 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
14860 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
14861 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14862 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
14863 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
14864 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14865 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
14866 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
14867 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14868 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
14869 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
14870 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14871 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
14872 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
14874 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
14875 
14876 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14877 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
14878 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
14879 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14880 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
14881 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
14882 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14883 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
14884 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
14885 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
14886 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14887 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
14888 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
14889 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14890 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
14891 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
14892 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14893 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
14894 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
14895 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
14896 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
14897 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
14898 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
14899 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
14901 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
14902 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14903 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
14904 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
14906 /******************** Bit definition for USB_OTG_HCDMA register ********************/
14907 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14908 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
14909 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
14911 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
14912 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14913 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
14914 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
14916 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
14917 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14918 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
14919 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
14920 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14921 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
14922 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
14924 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
14925 
14926 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14927 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
14928 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
14929 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14930 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
14931 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
14932 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14933 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
14934 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
14935 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14936 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
14937 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
14938 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14939 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
14940 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
14941 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14942 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14943 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
14944 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14945 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14946 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14947 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
14948 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
14949 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
14950 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
14951 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
14952 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14953 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
14954 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
14955 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14956 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
14957 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
14958 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14959 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
14960 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
14961 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14962 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
14963 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
14965 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
14966 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
14967 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
14968 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
14969 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14970 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
14971 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
14972 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
14973 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
14974 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
14975 #define USB_OTG_DOEPINT_STUP_Pos (3U)
14976 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
14977 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
14978 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14979 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
14980 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
14981 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
14982 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
14983 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
14984 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
14985 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
14986 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
14987 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
14988 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
14989 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
14990 #define USB_OTG_DOEPINT_NAK_Pos (13U)
14991 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
14992 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
14993 #define USB_OTG_DOEPINT_NYET_Pos (14U)
14994 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
14995 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
14996 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
14997 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
14998 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
14999 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
15000 
15001 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
15002 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
15003 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
15004 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
15005 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
15006 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
15008 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
15009 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15010 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
15011 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15012 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15014 /******************** Bit definition for PCGCCTL register ********************/
15015 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
15016 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
15017 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
15018 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
15019 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
15020 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
15021 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
15022 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
15023 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
15025 /* Legacy define */
15026 /******************** Bit definition for OTG register ********************/
15027 #define USB_OTG_CHNUM_Pos (0U)
15028 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
15029 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
15030 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
15031 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
15032 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
15033 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
15034 #define USB_OTG_BCNT_Pos (4U)
15035 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
15036 #define USB_OTG_BCNT USB_OTG_BCNT_Msk
15038 #define USB_OTG_DPID_Pos (15U)
15039 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
15040 #define USB_OTG_DPID USB_OTG_DPID_Msk
15041 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
15042 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
15044 #define USB_OTG_PKTSTS_Pos (17U)
15045 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
15046 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
15047 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
15048 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
15049 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
15050 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
15052 #define USB_OTG_EPNUM_Pos (0U)
15053 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
15054 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
15055 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
15056 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
15057 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
15058 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
15060 #define USB_OTG_FRMNUM_Pos (21U)
15061 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
15062 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
15063 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
15064 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
15065 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
15066 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
15079 /******************************* ADC Instances ********************************/
15080 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
15081  ((INSTANCE) == ADC2) || \
15082  ((INSTANCE) == ADC3))
15083 
15084 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15085 
15086 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
15087 
15088 /******************************* CAN Instances ********************************/
15089 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
15090  ((INSTANCE) == CAN2))
15091 /******************************* CRC Instances ********************************/
15092 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15093 
15094 /******************************* DAC Instances ********************************/
15095 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
15096 
15097 /******************************* DCMI Instances *******************************/
15098 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
15099 
15100 /******************************** DMA Instances *******************************/
15101 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
15102  ((INSTANCE) == DMA1_Stream1) || \
15103  ((INSTANCE) == DMA1_Stream2) || \
15104  ((INSTANCE) == DMA1_Stream3) || \
15105  ((INSTANCE) == DMA1_Stream4) || \
15106  ((INSTANCE) == DMA1_Stream5) || \
15107  ((INSTANCE) == DMA1_Stream6) || \
15108  ((INSTANCE) == DMA1_Stream7) || \
15109  ((INSTANCE) == DMA2_Stream0) || \
15110  ((INSTANCE) == DMA2_Stream1) || \
15111  ((INSTANCE) == DMA2_Stream2) || \
15112  ((INSTANCE) == DMA2_Stream3) || \
15113  ((INSTANCE) == DMA2_Stream4) || \
15114  ((INSTANCE) == DMA2_Stream5) || \
15115  ((INSTANCE) == DMA2_Stream6) || \
15116  ((INSTANCE) == DMA2_Stream7))
15117 
15118 /******************************* GPIO Instances *******************************/
15119 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15120  ((INSTANCE) == GPIOB) || \
15121  ((INSTANCE) == GPIOC) || \
15122  ((INSTANCE) == GPIOD) || \
15123  ((INSTANCE) == GPIOE) || \
15124  ((INSTANCE) == GPIOF) || \
15125  ((INSTANCE) == GPIOG) || \
15126  ((INSTANCE) == GPIOH) || \
15127  ((INSTANCE) == GPIOI))
15128 
15129 /******************************** I2C Instances *******************************/
15130 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15131  ((INSTANCE) == I2C2) || \
15132  ((INSTANCE) == I2C3))
15133 
15134 /******************************* SMBUS Instances ******************************/
15135 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
15136 
15137 /******************************** I2S Instances *******************************/
15138 
15139 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
15140  ((INSTANCE) == SPI3))
15141 
15142 /*************************** I2S Extended Instances ***************************/
15143 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
15144  ((INSTANCE) == I2S3ext))
15145 /* Legacy Defines */
15146 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
15147 
15148 /******************************* RNG Instances ********************************/
15149 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
15150 
15151 /****************************** RTC Instances *********************************/
15152 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15153 
15154 
15155 /******************************** SPI Instances *******************************/
15156 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15157  ((INSTANCE) == SPI2) || \
15158  ((INSTANCE) == SPI3))
15159 
15160 
15161 /****************** TIM Instances : All supported instances *******************/
15162 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15163  ((INSTANCE) == TIM2) || \
15164  ((INSTANCE) == TIM3) || \
15165  ((INSTANCE) == TIM4) || \
15166  ((INSTANCE) == TIM5) || \
15167  ((INSTANCE) == TIM6) || \
15168  ((INSTANCE) == TIM7) || \
15169  ((INSTANCE) == TIM8) || \
15170  ((INSTANCE) == TIM9) || \
15171  ((INSTANCE) == TIM10)|| \
15172  ((INSTANCE) == TIM11)|| \
15173  ((INSTANCE) == TIM12)|| \
15174  ((INSTANCE) == TIM13)|| \
15175  ((INSTANCE) == TIM14))
15176 
15177 /************* TIM Instances : at least 1 capture/compare channel *************/
15178 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15179  ((INSTANCE) == TIM2) || \
15180  ((INSTANCE) == TIM3) || \
15181  ((INSTANCE) == TIM4) || \
15182  ((INSTANCE) == TIM5) || \
15183  ((INSTANCE) == TIM8) || \
15184  ((INSTANCE) == TIM9) || \
15185  ((INSTANCE) == TIM10) || \
15186  ((INSTANCE) == TIM11) || \
15187  ((INSTANCE) == TIM12) || \
15188  ((INSTANCE) == TIM13) || \
15189  ((INSTANCE) == TIM14))
15190 
15191 /************ TIM Instances : at least 2 capture/compare channels *************/
15192 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15193  ((INSTANCE) == TIM2) || \
15194  ((INSTANCE) == TIM3) || \
15195  ((INSTANCE) == TIM4) || \
15196  ((INSTANCE) == TIM5) || \
15197  ((INSTANCE) == TIM8) || \
15198  ((INSTANCE) == TIM9) || \
15199  ((INSTANCE) == TIM12))
15200 
15201 /************ TIM Instances : at least 3 capture/compare channels *************/
15202 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15203  ((INSTANCE) == TIM2) || \
15204  ((INSTANCE) == TIM3) || \
15205  ((INSTANCE) == TIM4) || \
15206  ((INSTANCE) == TIM5) || \
15207  ((INSTANCE) == TIM8))
15208 
15209 /************ TIM Instances : at least 4 capture/compare channels *************/
15210 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15211  ((INSTANCE) == TIM2) || \
15212  ((INSTANCE) == TIM3) || \
15213  ((INSTANCE) == TIM4) || \
15214  ((INSTANCE) == TIM5) || \
15215  ((INSTANCE) == TIM8))
15216 
15217 /******************** TIM Instances : Advanced-control timers *****************/
15218 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15219  ((INSTANCE) == TIM8))
15220 
15221 /******************* TIM Instances : Timer input XOR function *****************/
15222 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15223  ((INSTANCE) == TIM2) || \
15224  ((INSTANCE) == TIM3) || \
15225  ((INSTANCE) == TIM4) || \
15226  ((INSTANCE) == TIM5) || \
15227  ((INSTANCE) == TIM8))
15228 
15229 /****************** TIM Instances : DMA requests generation (UDE) *************/
15230 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15231  ((INSTANCE) == TIM2) || \
15232  ((INSTANCE) == TIM3) || \
15233  ((INSTANCE) == TIM4) || \
15234  ((INSTANCE) == TIM5) || \
15235  ((INSTANCE) == TIM6) || \
15236  ((INSTANCE) == TIM7) || \
15237  ((INSTANCE) == TIM8))
15238 
15239 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
15240 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15241  ((INSTANCE) == TIM2) || \
15242  ((INSTANCE) == TIM3) || \
15243  ((INSTANCE) == TIM4) || \
15244  ((INSTANCE) == TIM5) || \
15245  ((INSTANCE) == TIM8))
15246 
15247 /************ TIM Instances : DMA requests generation (COMDE) *****************/
15248 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15249  ((INSTANCE) == TIM2) || \
15250  ((INSTANCE) == TIM3) || \
15251  ((INSTANCE) == TIM4) || \
15252  ((INSTANCE) == TIM5) || \
15253  ((INSTANCE) == TIM8))
15254 
15255 /******************** TIM Instances : DMA burst feature ***********************/
15256 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15257  ((INSTANCE) == TIM2) || \
15258  ((INSTANCE) == TIM3) || \
15259  ((INSTANCE) == TIM4) || \
15260  ((INSTANCE) == TIM5) || \
15261  ((INSTANCE) == TIM8))
15262 
15263 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15264 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15265  ((INSTANCE) == TIM2) || \
15266  ((INSTANCE) == TIM3) || \
15267  ((INSTANCE) == TIM4) || \
15268  ((INSTANCE) == TIM5) || \
15269  ((INSTANCE) == TIM6) || \
15270  ((INSTANCE) == TIM7) || \
15271  ((INSTANCE) == TIM8))
15272 
15273 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15274 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15275  ((INSTANCE) == TIM2) || \
15276  ((INSTANCE) == TIM3) || \
15277  ((INSTANCE) == TIM4) || \
15278  ((INSTANCE) == TIM5) || \
15279  ((INSTANCE) == TIM8) || \
15280  ((INSTANCE) == TIM9) || \
15281  ((INSTANCE) == TIM12))
15282 /********************** TIM Instances : 32 bit Counter ************************/
15283 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15284  ((INSTANCE) == TIM5))
15285 
15286 /***************** TIM Instances : external trigger input availabe ************/
15287 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15288  ((INSTANCE) == TIM2) || \
15289  ((INSTANCE) == TIM3) || \
15290  ((INSTANCE) == TIM4) || \
15291  ((INSTANCE) == TIM5) || \
15292  ((INSTANCE) == TIM8))
15293 
15294 /****************** TIM Instances : remapping capability **********************/
15295 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
15296  ((INSTANCE) == TIM5) || \
15297  ((INSTANCE) == TIM11))
15298 
15299 /******************* TIM Instances : output(s) available **********************/
15300 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15301  ((((INSTANCE) == TIM1) && \
15302  (((CHANNEL) == TIM_CHANNEL_1) || \
15303  ((CHANNEL) == TIM_CHANNEL_2) || \
15304  ((CHANNEL) == TIM_CHANNEL_3) || \
15305  ((CHANNEL) == TIM_CHANNEL_4))) \
15306  || \
15307  (((INSTANCE) == TIM2) && \
15308  (((CHANNEL) == TIM_CHANNEL_1) || \
15309  ((CHANNEL) == TIM_CHANNEL_2) || \
15310  ((CHANNEL) == TIM_CHANNEL_3) || \
15311  ((CHANNEL) == TIM_CHANNEL_4))) \
15312  || \
15313  (((INSTANCE) == TIM3) && \
15314  (((CHANNEL) == TIM_CHANNEL_1) || \
15315  ((CHANNEL) == TIM_CHANNEL_2) || \
15316  ((CHANNEL) == TIM_CHANNEL_3) || \
15317  ((CHANNEL) == TIM_CHANNEL_4))) \
15318  || \
15319  (((INSTANCE) == TIM4) && \
15320  (((CHANNEL) == TIM_CHANNEL_1) || \
15321  ((CHANNEL) == TIM_CHANNEL_2) || \
15322  ((CHANNEL) == TIM_CHANNEL_3) || \
15323  ((CHANNEL) == TIM_CHANNEL_4))) \
15324  || \
15325  (((INSTANCE) == TIM5) && \
15326  (((CHANNEL) == TIM_CHANNEL_1) || \
15327  ((CHANNEL) == TIM_CHANNEL_2) || \
15328  ((CHANNEL) == TIM_CHANNEL_3) || \
15329  ((CHANNEL) == TIM_CHANNEL_4))) \
15330  || \
15331  (((INSTANCE) == TIM8) && \
15332  (((CHANNEL) == TIM_CHANNEL_1) || \
15333  ((CHANNEL) == TIM_CHANNEL_2) || \
15334  ((CHANNEL) == TIM_CHANNEL_3) || \
15335  ((CHANNEL) == TIM_CHANNEL_4))) \
15336  || \
15337  (((INSTANCE) == TIM9) && \
15338  (((CHANNEL) == TIM_CHANNEL_1) || \
15339  ((CHANNEL) == TIM_CHANNEL_2))) \
15340  || \
15341  (((INSTANCE) == TIM10) && \
15342  (((CHANNEL) == TIM_CHANNEL_1))) \
15343  || \
15344  (((INSTANCE) == TIM11) && \
15345  (((CHANNEL) == TIM_CHANNEL_1))) \
15346  || \
15347  (((INSTANCE) == TIM12) && \
15348  (((CHANNEL) == TIM_CHANNEL_1) || \
15349  ((CHANNEL) == TIM_CHANNEL_2))) \
15350  || \
15351  (((INSTANCE) == TIM13) && \
15352  (((CHANNEL) == TIM_CHANNEL_1))) \
15353  || \
15354  (((INSTANCE) == TIM14) && \
15355  (((CHANNEL) == TIM_CHANNEL_1))))
15356 
15357 /************ TIM Instances : complementary output(s) available ***************/
15358 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15359  ((((INSTANCE) == TIM1) && \
15360  (((CHANNEL) == TIM_CHANNEL_1) || \
15361  ((CHANNEL) == TIM_CHANNEL_2) || \
15362  ((CHANNEL) == TIM_CHANNEL_3))) \
15363  || \
15364  (((INSTANCE) == TIM8) && \
15365  (((CHANNEL) == TIM_CHANNEL_1) || \
15366  ((CHANNEL) == TIM_CHANNEL_2) || \
15367  ((CHANNEL) == TIM_CHANNEL_3))))
15368 
15369 /****************** TIM Instances : supporting counting mode selection ********/
15370 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15371  ((INSTANCE) == TIM2) || \
15372  ((INSTANCE) == TIM3) || \
15373  ((INSTANCE) == TIM4) || \
15374  ((INSTANCE) == TIM5) || \
15375  ((INSTANCE) == TIM8))
15376 
15377 /****************** TIM Instances : supporting clock division *****************/
15378 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15379  ((INSTANCE) == TIM2) || \
15380  ((INSTANCE) == TIM3) || \
15381  ((INSTANCE) == TIM4) || \
15382  ((INSTANCE) == TIM5) || \
15383  ((INSTANCE) == TIM8) || \
15384  ((INSTANCE) == TIM9) || \
15385  ((INSTANCE) == TIM10)|| \
15386  ((INSTANCE) == TIM11)|| \
15387  ((INSTANCE) == TIM12)|| \
15388  ((INSTANCE) == TIM13)|| \
15389  ((INSTANCE) == TIM14))
15390 
15391 /****************** TIM Instances : supporting commutation event generation ***/
15392 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15393  ((INSTANCE) == TIM8))
15394 
15395 
15396 /****************** TIM Instances : supporting OCxREF clear *******************/
15397 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15398  ((INSTANCE) == TIM2) || \
15399  ((INSTANCE) == TIM3) || \
15400  ((INSTANCE) == TIM4) || \
15401  ((INSTANCE) == TIM5) || \
15402  ((INSTANCE) == TIM8))
15403 
15404 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15405 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15406  ((INSTANCE) == TIM2) || \
15407  ((INSTANCE) == TIM3) || \
15408  ((INSTANCE) == TIM4) || \
15409  ((INSTANCE) == TIM5) || \
15410  ((INSTANCE) == TIM8) || \
15411  ((INSTANCE) == TIM9) || \
15412  ((INSTANCE) == TIM12))
15413 
15414 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15415 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15416  ((INSTANCE) == TIM2) || \
15417  ((INSTANCE) == TIM3) || \
15418  ((INSTANCE) == TIM4) || \
15419  ((INSTANCE) == TIM5) || \
15420  ((INSTANCE) == TIM8))
15421 
15422 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
15423 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15424  ((INSTANCE) == TIM2) || \
15425  ((INSTANCE) == TIM3) || \
15426  ((INSTANCE) == TIM4) || \
15427  ((INSTANCE) == TIM5) || \
15428  ((INSTANCE) == TIM8) || \
15429  ((INSTANCE) == TIM9) || \
15430  ((INSTANCE) == TIM12))
15431 
15432 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
15433 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15434  ((INSTANCE) == TIM2) || \
15435  ((INSTANCE) == TIM3) || \
15436  ((INSTANCE) == TIM4) || \
15437  ((INSTANCE) == TIM5) || \
15438  ((INSTANCE) == TIM8) || \
15439  ((INSTANCE) == TIM9) || \
15440  ((INSTANCE) == TIM12))
15441 
15442 /****************** TIM Instances : supporting repetition counter *************/
15443 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15444  ((INSTANCE) == TIM8))
15445 
15446 /****************** TIM Instances : supporting encoder interface **************/
15447 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15448  ((INSTANCE) == TIM2) || \
15449  ((INSTANCE) == TIM3) || \
15450  ((INSTANCE) == TIM4) || \
15451  ((INSTANCE) == TIM5) || \
15452  ((INSTANCE) == TIM8) || \
15453  ((INSTANCE) == TIM9) || \
15454  ((INSTANCE) == TIM12))
15455 /****************** TIM Instances : supporting Hall sensor interface **********/
15456 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15457  ((INSTANCE) == TIM2) || \
15458  ((INSTANCE) == TIM3) || \
15459  ((INSTANCE) == TIM4) || \
15460  ((INSTANCE) == TIM5) || \
15461  ((INSTANCE) == TIM8))
15462 /****************** TIM Instances : supporting the break function *************/
15463 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15464  ((INSTANCE) == TIM8))
15465 
15466 /******************** USART Instances : Synchronous mode **********************/
15467 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15468  ((INSTANCE) == USART2) || \
15469  ((INSTANCE) == USART3) || \
15470  ((INSTANCE) == USART6))
15471 
15472 /******************** UART Instances : Half-Duplex mode **********************/
15473 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15474  ((INSTANCE) == USART2) || \
15475  ((INSTANCE) == USART3) || \
15476  ((INSTANCE) == UART4) || \
15477  ((INSTANCE) == UART5) || \
15478  ((INSTANCE) == USART6))
15479 
15480 /* Legacy defines */
15481 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15482 
15483 /****************** UART Instances : Hardware Flow control ********************/
15484 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15485  ((INSTANCE) == USART2) || \
15486  ((INSTANCE) == USART3) || \
15487  ((INSTANCE) == USART6))
15488 /******************** UART Instances : LIN mode **********************/
15489 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15490 
15491 /********************* UART Instances : Smart card mode ***********************/
15492 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15493  ((INSTANCE) == USART2) || \
15494  ((INSTANCE) == USART3) || \
15495  ((INSTANCE) == USART6))
15496 
15497 /*********************** UART Instances : IRDA mode ***************************/
15498 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15499  ((INSTANCE) == USART2) || \
15500  ((INSTANCE) == USART3) || \
15501  ((INSTANCE) == UART4) || \
15502  ((INSTANCE) == UART5) || \
15503  ((INSTANCE) == USART6))
15504 
15505 
15506 /*********************** PCD Instances ****************************************/
15507 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15508  ((INSTANCE) == USB_OTG_HS))
15509 
15510 /*********************** HCD Instances ****************************************/
15511 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15512  ((INSTANCE) == USB_OTG_HS))
15513 
15514 /****************************** SDIO Instances ********************************/
15515 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15516 
15517 /****************************** IWDG Instances ********************************/
15518 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15519 
15520 /****************************** WWDG Instances ********************************/
15521 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15522 
15523 /****************************** USB Exported Constants ************************/
15524 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
15525 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
15526 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
15527 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
15528 
15529 /*
15530  * @brief Specific devices reset values definitions
15531  */
15532 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
15533 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
15534 
15535 #define RCC_MAX_FREQUENCY 168000000U
15536 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
15537 #define RCC_MAX_FREQUENCY_SCALE2 144000000U
15538 #define RCC_PLLVCO_OUTPUT_MIN 100000000U
15539 #define RCC_PLLVCO_INPUT_MIN 950000U
15540 #define RCC_PLLVCO_INPUT_MAX 2100000U
15541 #define RCC_PLLVCO_OUTPUT_MAX 432000000U
15543 #define RCC_PLLN_MIN_VALUE 50U
15544 #define RCC_PLLN_MAX_VALUE 432U
15545 
15546 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U
15547 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U
15548 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U
15549 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U
15550 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U
15552 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U
15553 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U
15554 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U
15555 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U
15557 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
15558 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
15559 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
15560 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
15561 /******************************************************************************/
15562 /* For a painless codes migration between the STM32F4xx device product */
15563 /* lines, the aliases defined below are put in place to overcome the */
15564 /* differences in the interrupt handlers and IRQn definitions. */
15565 /* No need to update developed interrupt code when moving across */
15566 /* product lines within the same STM32F4 Family */
15567 /******************************************************************************/
15568 /* Aliases for __IRQn */
15569 #define FMC_IRQn FSMC_IRQn
15570 
15571 /* Aliases for __IRQHandler */
15572 #define FMC_IRQHandler FSMC_IRQHandler
15573 
15586 #ifdef __cplusplus
15587 }
15588 #endif /* __cplusplus */
15589 
15590 #endif /* __STM32F407xx_H */
15591 
15592 
15593 
15594 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f407xx.h:713
ADC_TypeDef::JOFR4
__IO uint32_t JOFR4
Definition: stm32f407xx.h:189
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f407xx.h:267
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32f407xx.h:80
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32f407xx.h:536
ETH_TypeDef::DMACHRBAR
__IO uint32_t DMACHRBAR
Definition: stm32f407xx.h:436
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32f407xx.h:655
RNG_IRQn
@ RNG_IRQn
Definition: stm32f407xx.h:157
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f407xx.h:195
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition: stm32f407xx.h:140
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f407xx.h:711
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:716
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f407xx.h:206
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f407xx.h:184
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32f407xx.h:652
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f407xx.h:231
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:462
DCMI_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32f407xx.h:331
ETH_TypeDef::DMABMR
__IO uint32_t DMABMR
Definition: stm32f407xx.h:422
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
USB_OTG_DeviceTypeDef::DINEP1MSK
__IO uint32_t DINEP1MSK
Definition: stm32f407xx.h:838
SDIO_IRQn
@ SDIO_IRQn
Definition: stm32f407xx.h:127
USB_OTG_GlobalTypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition: stm32f407xx.h:799
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32f407xx.h:135
USB_OTG_HostChannelTypeDef::HCSPLT
__IO uint32_t HCSPLT
Definition: stm32f407xx.h:892
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:639
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32f407xx.h:185
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f407xx.h:196
ETH_TypeDef::MACPMTCSR
__IO uint32_t MACPMTCSR
Definition: stm32f407xx.h:380
ETH_TypeDef::MMCRGUFCR
__IO uint32_t MMCRGUFCR
Definition: stm32f407xx.h:408
DMA_TypeDef::LISR
__IO uint32_t LISR
Definition: stm32f407xx.h:358
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f407xx.h:758
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f407xx.h:601
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f407xx.h:346
FSMC_Bank2_3_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f407xx.h:506
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32f407xx.h:82
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32f407xx.h:145
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f407xx.h:731
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f407xx.h:232
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:775
USB_OTG_OUTEndpointTypeDef::DOEPCTL
__IO uint32_t DOEPCTL
Definition: stm32f407xx.h:863
ETH_TypeDef::RESERVED8
__IO uint32_t RESERVED8
Definition: stm32f407xx.h:419
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32f407xx.h:529
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32f407xx.h:91
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32f407xx.h:666
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32f407xx.h:207
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:735
USB_OTG_OUTEndpointTypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition: stm32f407xx.h:868
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition: stm32f407xx.h:142
ETH_TypeDef::MACMIIAR
__IO uint32_t MACMIIAR
Definition: stm32f407xx.h:374
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f407xx.h:242
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f407xx.h:253
USB_OTG_DeviceTypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition: stm32f407xx.h:832
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:579
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32f407xx.h:661
ETH_TypeDef::PTPTSSR
__IO uint32_t PTPTSSR
Definition: stm32f407xx.h:420
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition: stm32f407xx.h:449
DMA_TypeDef
Definition: stm32f407xx.h:356
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition: stm32f407xx.h:614
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32f407xx.h:192
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32f407xx.h:665
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32f407xx.h:736
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32f407xx.h:734
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition: stm32f407xx.h:447
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition: stm32f407xx.h:854
USB_OTG_GlobalTypeDef::GINTMSK
__IO uint32_t GINTMSK
Definition: stm32f407xx.h:802
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32f407xx.h:748
ETH_TypeDef::DMARSWTR
__IO uint32_t DMARSWTR
Definition: stm32f407xx.h:431
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f407xx.h:625
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f407xx.h:123
ADC_TypeDef::LTR
__IO uint32_t LTR
Definition: stm32f407xx.h:191
DCMI_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32f407xx.h:333
USB_OTG_GlobalTypeDef::GRXSTSR
__IO uint32_t GRXSTSR
Definition: stm32f407xx.h:803
ETH_TypeDef::PTPTSLR
__IO uint32_t PTPTSLR
Definition: stm32f407xx.h:413
ETH_TypeDef::MMCRFAECR
__IO uint32_t MMCRFAECR
Definition: stm32f407xx.h:406
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f407xx.h:866
ETH_TypeDef::MMCCR
__IO uint32_t MMCCR
Definition: stm32f407xx.h:394
USART_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:760
ETH_TypeDef::MACA3LR
__IO uint32_t MACA3LR
Definition: stm32f407xx.h:392
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f407xx.h:514
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32f407xx.h:673
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32f407xx.h:85
USB_OTG_GlobalTypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition: stm32f407xx.h:798
ETH_TypeDef::MACFCR
__IO uint32_t MACFCR
Definition: stm32f407xx.h:376
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32f407xx.h:298
USB_OTG_DeviceTypeDef::DSTS
__IO uint32_t DSTS
Definition: stm32f407xx.h:823
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition: stm32f407xx.h:721
RTC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32f407xx.h:656
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f407xx.h:219
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32f407xx.h:645
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32f407xx.h:669
DCMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32f407xx.h:332
CAN_TypeDef
Controller Area Network.
Definition: stm32f407xx.h:250
USB_OTG_GlobalTypeDef::GINTSTS
__IO uint32_t GINTSTS
Definition: stm32f407xx.h:801
FSMC_Bank4_TypeDef::PCR4
__IO uint32_t PCR4
Definition: stm32f407xx.h:516
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32f407xx.h:644
USB_OTG_DeviceTypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition: stm32f407xx.h:831
USB_OTG_DeviceTypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition: stm32f407xx.h:834
ETH_TypeDef::MMCTGFSCCR
__IO uint32_t MMCTGFSCCR
Definition: stm32f407xx.h:400
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32f407xx.h:151
ADC_TypeDef::JOFR3
__IO uint32_t JOFR3
Definition: stm32f407xx.h:188
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32f407xx.h:718
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f407xx.h:271
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition: stm32f407xx.h:98
USB_OTG_INEndpointTypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition: stm32f407xx.h:853
USART_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:761
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32f407xx.h:110
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f407xx.h:824
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32f407xx.h:608
I2C_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f407xx.h:566
ETH_TypeDef::DMARDLAR
__IO uint32_t DMARDLAR
Definition: stm32f407xx.h:425
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32f407xx.h:664
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32f407xx.h:74
DCMI_TypeDef::CWSTRTR
__IO uint32_t CWSTRTR
Definition: stm32f407xx.h:337
ETH_TypeDef::MACIMR
__IO uint32_t MACIMR
Definition: stm32f407xx.h:384
FLASH_TypeDef::OPTCR
__IO uint32_t OPTCR
Definition: stm32f407xx.h:464
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32f407xx.h:147
ETH_TypeDef::MACA1LR
__IO uint32_t MACA1LR
Definition: stm32f407xx.h:388
USB_OTG_DeviceTypeDef::DTHRCTL
__IO uint32_t DTHRCTL
Definition: stm32f407xx.h:833
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f407xx.h:763
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition: stm32f407xx.h:190
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f407xx.h:557
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32f407xx.h:660
ETH_TypeDef::PTPTSAR
__IO uint32_t PTPTSAR
Definition: stm32f407xx.h:416
FSMC_Bank2_3_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f407xx.h:495
ETH_TypeDef::PTPTSCR
__IO uint32_t PTPTSCR
Definition: stm32f407xx.h:410
USB_OTG_GlobalTypeDef::HNPTXSTS
__IO uint32_t HNPTXSTS
Definition: stm32f407xx.h:807
ETH_TypeDef::DMASR
__IO uint32_t DMASR
Definition: stm32f407xx.h:427
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32f407xx.h:107
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f407xx.h:714
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32f407xx.h:649
SDIO_TypeDef::RESP3
const __IO uint32_t RESP3
Definition: stm32f407xx.h:692
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f407xx.h:315
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:788
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f407xx.h:875
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f407xx.h:606
ETH_TypeDef::MACFFR
__IO uint32_t MACFFR
Definition: stm32f407xx.h:371
USB_OTG_INEndpointTypeDef::DIEPCTL
__IO uint32_t DIEPCTL
Definition: stm32f407xx.h:848
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32f407xx.h:86
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32f407xx.h:296
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32f407xx.h:125
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32f407xx.h:461
USB_OTG_GlobalTypeDef::CID
__IO uint32_t CID
Definition: stm32f407xx.h:810
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f407xx.h:640
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f407xx.h:258
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32f407xx.h:657
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32f407xx.h:674
FSMC_Bank4_TypeDef::PIO4
__IO uint32_t PIO4
Definition: stm32f407xx.h:520
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f407xx.h:846
SDIO_TypeDef::RESPCMD
const __IO uint32_t RESPCMD
Definition: stm32f407xx.h:689
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f407xx.h:751
FSMC_Bank2_3_TypeDef::SR3
__IO uint32_t SR3
Definition: stm32f407xx.h:503
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32f407xx.h:320
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f407xx.h:739
USB_OTG_HostTypeDef::HAINT
__IO uint32_t HAINT
Definition: stm32f407xx.h:882
DMA_Stream_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:348
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32f407xx.h:676
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32f407xx.h:672
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f407xx.h:221
RCC_TypeDef::APB2LPENR
__IO uint32_t APB2LPENR
Definition: stm32f407xx.h:622
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32f407xx.h:87
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32f407xx.h:535
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:638
DMA_TypeDef::HISR
__IO uint32_t HISR
Definition: stm32f407xx.h:359
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f407xx.h:732
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:318
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32f407xx.h:101
DMA_Stream_TypeDef::M1AR
__IO uint32_t M1AR
Definition: stm32f407xx.h:352
USB_OTG_HostChannelTypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition: stm32f407xx.h:894
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32f407xx.h:72
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f407xx.h:450
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32f407xx.h:641
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32f407xx.h:750
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32f407xx.h:533
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32f407xx.h:460
USB_OTG_DeviceTypeDef::DEACHMSK
__IO uint32_t DEACHMSK
Definition: stm32f407xx.h:836
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: stm32f407xx.h:883
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f407xx.h:285
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition: stm32f407xx.h:186
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f407xx.h:264
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:786
ETH_TypeDef::MACCR
__IO uint32_t MACCR
Definition: stm32f407xx.h:370
FSMC_Bank4_TypeDef::PATT4
__IO uint32_t PATT4
Definition: stm32f407xx.h:519
FLASH_TypeDef::OPTCR1
__IO uint32_t OPTCR1
Definition: stm32f407xx.h:465
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32f407xx.h:199
USB_OTG_GlobalTypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition: stm32f407xx.h:800
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f407xx.h:233
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32f407xx.h:150
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32f407xx.h:611
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:777
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f407xx.h:445
ETH_TypeDef::DMAOMR
__IO uint32_t DMAOMR
Definition: stm32f407xx.h:428
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32f407xx.h:766
ETH_TypeDef::DMARPDR
__IO uint32_t DMARPDR
Definition: stm32f407xx.h:424
USB_OTG_GlobalTypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition: stm32f407xx.h:812
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f407xx.h:776
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f407xx.h:255
USART3_IRQn
@ USART3_IRQn
Definition: stm32f407xx.h:117
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32f407xx.h:667
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32f407xx.h:671
ETH_TypeDef::PTPTSHUR
__IO uint32_t PTPTSHUR
Definition: stm32f407xx.h:414
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32f407xx.h:733
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32f407xx.h:741
UART4_IRQn
@ UART4_IRQn
Definition: stm32f407xx.h:130
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f407xx.h:746
TIM_TypeDef
TIM.
Definition: stm32f407xx.h:729
SDIO_TypeDef
SD host Interface.
Definition: stm32f407xx.h:683
USB_OTG_DeviceTypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition: stm32f407xx.h:828
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f407xx.h:574
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f407xx.h:794
USART6_IRQn
@ USART6_IRQn
Definition: stm32f407xx.h:149
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f407xx.h:620
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f407xx.h:861
USB_OTG_INEndpointTypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition: stm32f407xx.h:852
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32f407xx.h:113
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition: stm32f407xx.h:100
DCMI_TypeDef::CWSIZER
__IO uint32_t CWSIZER
Definition: stm32f407xx.h:338
SDIO_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition: stm32f407xx.h:694
SDIO_TypeDef::ARG
__IO uint32_t ARG
Definition: stm32f407xx.h:687
RTC_TypeDef::CALIBR
__IO uint32_t CALIBR
Definition: stm32f407xx.h:643
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32f407xx.h:138
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32f407xx.h:105
FSMC_Bank4_TypeDef::SR4
__IO uint32_t SR4
Definition: stm32f407xx.h:517
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32f407xx.h:302
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f407xx.h:265
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:308
CRC_TypeDef
CRC calculation unit.
Definition: stm32f407xx.h:280
ETH_TypeDef::DMAIER
__IO uint32_t DMAIER
Definition: stm32f407xx.h:429
PWR_TypeDef
Power Control.
Definition: stm32f407xx.h:587
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32f407xx.h:304
SDIO_TypeDef::MASK
__IO uint32_t MASK
Definition: stm32f407xx.h:700
ETH_TypeDef::MMCTIMR
__IO uint32_t MMCTIMR
Definition: stm32f407xx.h:398
SDIO_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition: stm32f407xx.h:686
DCMI_TypeDef::ESUR
__IO uint32_t ESUR
Definition: stm32f407xx.h:336
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f407xx.h:597
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f407xx.h:270
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f407xx.h:183
ETH_TypeDef::PTPTSLUR
__IO uint32_t PTPTSLUR
Definition: stm32f407xx.h:415
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32f407xx.h:70
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:200
FSMC_Bank2_3_TypeDef::PMEM3
__IO uint32_t PMEM3
Definition: stm32f407xx.h:504
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f407xx.h:205
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32f407xx.h:128
ETH_TypeDef::MMCRFCECR
__IO uint32_t MMCRFCECR
Definition: stm32f407xx.h:405
PVD_IRQn
@ PVD_IRQn
Definition: stm32f407xx.h:79
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:599
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32f407xx.h:106
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:787
USB_OTG_GlobalTypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition: stm32f407xx.h:805
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition: stm32f407xx.h:103
USB_OTG_DeviceTypeDef::DEACHINT
__IO uint32_t DEACHINT
Definition: stm32f407xx.h:835
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition: stm32f407xx.h:448
USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: stm32f407xx.h:806
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32f407xx.h:76
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f407xx.h:269
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32f407xx.h:132
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition: stm32f407xx.h:99
SDIO_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f407xx.h:699
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:295
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f407xx.h:66
RCC_IRQn
@ RCC_IRQn
Definition: stm32f407xx.h:83
I2C_TypeDef::SR1
__IO uint32_t SR1
Definition: stm32f407xx.h:564
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32f407xx.h:675
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32f407xx.h:610
FSMC_Bank2_3_TypeDef::PCR2
__IO uint32_t PCR2
Definition: stm32f407xx.h:494
ADC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:181
USB_OTG_HostChannelTypeDef::HCINT
__IO uint32_t HCINT
Definition: stm32f407xx.h:893
ETH_TypeDef::PTPSSIR
__IO uint32_t PTPSSIR
Definition: stm32f407xx.h:411
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f407xx.h:268
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition: stm32f407xx.h:607
USB_OTG_DeviceTypeDef::DAINT
__IO uint32_t DAINT
Definition: stm32f407xx.h:827
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32f407xx.h:152
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32f407xx.h:317
DMA_Stream_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f407xx.h:353
FPU_IRQn
@ FPU_IRQn
Definition: stm32f407xx.h:158
ADC_TypeDef
Analog to Digital Converter
Definition: stm32f407xx.h:179
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:463
FSMC_Bank2_3_TypeDef::PATT3
__IO uint32_t PATT3
Definition: stm32f407xx.h:505
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f407xx.h:749
ETH_TypeDef::MMCRIMR
__IO uint32_t MMCRIMR
Definition: stm32f407xx.h:397
ETH_TypeDef::MACMIIDR
__IO uint32_t MACMIIDR
Definition: stm32f407xx.h:375
ETH_TypeDef::DMACHRDR
__IO uint32_t DMACHRDR
Definition: stm32f407xx.h:434
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32f407xx.h:459
USART1_IRQn
@ USART1_IRQn
Definition: stm32f407xx.h:115
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32f407xx.h:118
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:286
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f407xx.h:257
ETH_TypeDef::MMCTGFMSCCR
__IO uint32_t MMCTGFMSCCR
Definition: stm32f407xx.h:401
ETH_TypeDef::DMATDLAR
__IO uint32_t DMATDLAR
Definition: stm32f407xx.h:426
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f407xx.h:443
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32f407xx.h:89
ETH_TypeDef::MACA0HR
__IO uint32_t MACA0HR
Definition: stm32f407xx.h:385
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32f407xx.h:765
DMA_Stream_TypeDef::PAR
__IO uint32_t PAR
Definition: stm32f407xx.h:350
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f407xx.h:764
PWR_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f407xx.h:590
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32f407xx.h:109
USB_OTG_HostChannelTypeDef::HCDMA
__IO uint32_t HCDMA
Definition: stm32f407xx.h:896
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32f407xx.h:133
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32f407xx.h:637
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f407xx.h:864
PWR_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:589
SDIO_TypeDef::RESP2
const __IO uint32_t RESP2
Definition: stm32f407xx.h:691
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f407xx.h:889
SDIO_TypeDef::FIFOCNT
const __IO uint32_t FIFOCNT
Definition: stm32f407xx.h:702
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32f407xx.h:301
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32f407xx.h:124
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f407xx.h:561
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32f407xx.h:720
RCC_TypeDef::PLLI2SCFGR
__IO uint32_t PLLI2SCFGR
Definition: stm32f407xx.h:628
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f407xx.h:240
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32f407xx.h:719
RCC_TypeDef::APB1LPENR
__IO uint32_t APB1LPENR
Definition: stm32f407xx.h:621
ETH_IRQn
@ ETH_IRQn
Definition: stm32f407xx.h:139
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32f407xx.h:624
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f407xx.h:578
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32f407xx.h:650
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f407xx.h:266
SDIO_TypeDef::RESP1
const __IO uint32_t RESP1
Definition: stm32f407xx.h:690
USB_OTG_HostTypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition: stm32f407xx.h:881
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32f407xx.h:148
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32f407xx.h:642
DBGMCU_TypeDef::APB1FZ
__IO uint32_t APB1FZ
Definition: stm32f407xx.h:319
USB_OTG_GlobalTypeDef::GRXSTSP
__IO uint32_t GRXSTSP
Definition: stm32f407xx.h:804
FSMC_Bank4_TypeDef::PMEM4
__IO uint32_t PMEM4
Definition: stm32f407xx.h:518
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition: stm32f407xx.h:829
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32f407xx.h:122
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32f407xx.h:112
USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
__IO uint32_t DOEPTSIZ
Definition: stm32f407xx.h:867
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32f407xx.h:306
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f407xx.h:220
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32f407xx.h:612
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32f407xx.h:546
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32f407xx.h:71
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32f407xx.h:305
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32f407xx.h:193
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f407xx.h:259
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32f407xx.h:108
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32f407xx.h:154
ETH_TypeDef::DMACHTBAR
__IO uint32_t DMACHTBAR
Definition: stm32f407xx.h:435
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition: stm32f407xx.h:144
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition: stm32f407xx.h:141
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f407xx.h:527
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32f407xx.h:605
FSMC_IRQn
@ FSMC_IRQn
Definition: stm32f407xx.h:126
USB_OTG_INEndpointTypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition: stm32f407xx.h:850
FSMC_Bank2_3_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f407xx.h:492
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32f407xx.h:303
FSMC_Bank2_3_TypeDef::ECCR2
__IO uint32_t ECCR2
Definition: stm32f407xx.h:499
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f407xx.h:293
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32f407xx.h:534
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f407xx.h:762
FSMC_Bank2_3_TypeDef::PCR3
__IO uint32_t PCR3
Definition: stm32f407xx.h:502
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef::Reserved9
uint32_t Reserved9
Definition: stm32f407xx.h:830
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32f407xx.h:114
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f407xx.h:738
USB_OTG_GlobalTypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition: stm32f407xx.h:797
ADC_IRQn
@ ADC_IRQn
Definition: stm32f407xx.h:96
ETH_TypeDef::MACA2HR
__IO uint32_t MACA2HR
Definition: stm32f407xx.h:389
USB_OTG_OUTEndpointTypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition: stm32f407xx.h:865
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f407xx.h:740
ETH_TypeDef::PTPTSHR
__IO uint32_t PTPTSHR
Definition: stm32f407xx.h:412
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f407xx.h:773
USB_OTG_DeviceTypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition: stm32f407xx.h:826
ADC_Common_TypeDef
Definition: stm32f407xx.h:203
DCMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:329
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32f407xx.h:134
ETH_TypeDef::DMAMFBOCR
__IO uint32_t DMAMFBOCR
Definition: stm32f407xx.h:430
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32f407xx.h:299
DMA_Stream_TypeDef::NDTR
__IO uint32_t NDTR
Definition: stm32f407xx.h:349
SDIO_TypeDef::STA
const __IO uint32_t STA
Definition: stm32f407xx.h:698
SDIO_TypeDef::DLEN
__IO uint32_t DLEN
Definition: stm32f407xx.h:695
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32f407xx.h:95
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:282
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32f407xx.h:88
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f407xx.h:737
ETH_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f407xx.h:381
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32f407xx.h:73
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32f407xx.h:662
I2C_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f407xx.h:565
RCC_TypeDef::AHB3LPENR
__IO uint32_t AHB3LPENR
Definition: stm32f407xx.h:619
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:327
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32f407xx.h:136
USB_OTG_HostChannelTypeDef::HCTSIZ
__IO uint32_t HCTSIZ
Definition: stm32f407xx.h:895
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32f407xx.h:654
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition: stm32f407xx.h:97
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32f407xx.h:194
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32f407xx.h:668
USB_OTG_DeviceTypeDef::DCTL
__IO uint32_t DCTL
Definition: stm32f407xx.h:822
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f407xx.h:849
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32f407xx.h:659
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f407xx.h:743
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32f407xx.h:153
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32f407xx.h:90
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition: stm32f407xx.h:446
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32f407xx.h:670
ETH_TypeDef::MMCTIR
__IO uint32_t MMCTIR
Definition: stm32f407xx.h:396
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32f407xx.h:603
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition: stm32f407xx.h:855
ETH_TypeDef::MACDBGR
__IO uint32_t MACDBGR
Definition: stm32f407xx.h:382
DCMI_TypeDef::ESCR
__IO uint32_t ESCR
Definition: stm32f407xx.h:335
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f407xx.h:104
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f407xx.h:474
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32f407xx.h:663
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f407xx.h:742
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32f407xx.h:155
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32f407xx.h:197
ETH_TypeDef::MACA3HR
__IO uint32_t MACA3HR
Definition: stm32f407xx.h:391
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f407xx.h:819
ADC_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f407xx.h:182
FSMC_Bank2_3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f407xx.h:498
ETH_TypeDef::MACVLANTR
__IO uint32_t MACVLANTR
Definition: stm32f407xx.h:377
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32f407xx.h:647
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f407xx.h:744
SDIO_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition: stm32f407xx.h:696
SDIO_TypeDef::FIFO
__IO uint32_t FIFO
Definition: stm32f407xx.h:704
ETH_TypeDef::PTPTTHR
__IO uint32_t PTPTTHR
Definition: stm32f407xx.h:417
USB_OTG_GlobalTypeDef::GCCFG
__IO uint32_t GCCFG
Definition: stm32f407xx.h:809
USB_OTG_DeviceTypeDef::DCFG
__IO uint32_t DCFG
Definition: stm32f407xx.h:821
DCMI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:339
ETH_TypeDef::MACA0LR
__IO uint32_t MACA0LR
Definition: stm32f407xx.h:386
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32f407xx.h:651
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32f407xx.h:84
USB_OTG_HostTypeDef::HCFG
__IO uint32_t HCFG
Definition: stm32f407xx.h:877
ETH_TypeDef::MACA1HR
__IO uint32_t MACA1HR
Definition: stm32f407xx.h:387
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32f407xx.h:93
ETH_TypeDef::MACHTHR
__IO uint32_t MACHTHR
Definition: stm32f407xx.h:372
DCMI_IRQn
@ DCMI_IRQn
Definition: stm32f407xx.h:156
USB_OTG_HostTypeDef::HFNUM
__IO uint32_t HFNUM
Definition: stm32f407xx.h:879
ETH_TypeDef::MACHTLR
__IO uint32_t MACHTLR
Definition: stm32f407xx.h:373
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32f407xx.h:531
DMA_Stream_TypeDef::M0AR
__IO uint32_t M0AR
Definition: stm32f407xx.h:351
RCC_TypeDef::AHB2LPENR
__IO uint32_t AHB2LPENR
Definition: stm32f407xx.h:618
RCC_TypeDef::SSCGR
__IO uint32_t SSCGR
Definition: stm32f407xx.h:627
USB_OTG_HostChannelTypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition: stm32f407xx.h:891
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32f407xx.h:307
FSMC_Bank2_3_TypeDef::ECCR3
__IO uint32_t ECCR3
Definition: stm32f407xx.h:507
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:715
USB_OTG_GlobalTypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition: stm32f407xx.h:796
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32f407xx.h:78
DMA_TypeDef::LIFCR
__IO uint32_t LIFCR
Definition: stm32f407xx.h:360
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32f407xx.h:75
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f407xx.h:256
I2C_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:563
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f407xx.h:284
ETH_TypeDef::PTPTTLR
__IO uint32_t PTPTTLR
Definition: stm32f407xx.h:418
I2C_TypeDef::TRISE
__IO uint32_t TRISE
Definition: stm32f407xx.h:567
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32f407xx.h:119
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32f407xx.h:94
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32f407xx.h:69
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f407xx.h:483
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition: stm32f407xx.h:602
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition: stm32f407xx.h:840
ETH_TypeDef::DMATPDR
__IO uint32_t DMATPDR
Definition: stm32f407xx.h:423
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32f407xx.h:146
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32f407xx.h:532
FSMC_Bank2_3_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f407xx.h:500
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f407xx.h:218
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition: stm32f407xx.h:120
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32f407xx.h:92
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32f407xx.h:530
SDIO_TypeDef::DCOUNT
const __IO uint32_t DCOUNT
Definition: stm32f407xx.h:697
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32f407xx.h:81
USB_OTG_HostTypeDef::HFIR
__IO uint32_t HFIR
Definition: stm32f407xx.h:878
ETH_TypeDef::MACSR
__IO uint32_t MACSR
Definition: stm32f407xx.h:383
SYSCFG_TypeDef::CMPCR
__IO uint32_t CMPCR
Definition: stm32f407xx.h:550
FLASH_TypeDef
FLASH Registers.
Definition: stm32f407xx.h:457
SDIO_TypeDef::RESP4
const __IO uint32_t RESP4
Definition: stm32f407xx.h:693
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32f407xx.h:198
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32f407xx.h:129
USART2_IRQn
@ USART2_IRQn
Definition: stm32f407xx.h:116
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition: stm32f407xx.h:837
DCMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f407xx.h:334
ETH_TypeDef::MACRWUFFR
__IO uint32_t MACRWUFFR
Definition: stm32f407xx.h:379
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f407xx.h:562
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f407xx.h:544
DMA_TypeDef::HIFCR
__IO uint32_t HIFCR
Definition: stm32f407xx.h:361
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32f407xx.h:615
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f407xx.h:254
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:368
USB_OTG_INEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f407xx.h:851
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32f407xx.h:658
FSMC_Bank2_3_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f407xx.h:501
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f407xx.h:216
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32f407xx.h:600
ETH_TypeDef::MACA2LR
__IO uint32_t MACA2LR
Definition: stm32f407xx.h:390
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f407xx.h:576
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f407xx.h:283
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f407xx.h:747
UART5_IRQn
@ UART5_IRQn
Definition: stm32f407xx.h:131
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f407xx.h:228
SDIO_TypeDef::CMD
__IO uint32_t CMD
Definition: stm32f407xx.h:688
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32f407xx.h:137
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32f407xx.h:717
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32f407xx.h:300
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f407xx.h:243
RTC_TypeDef::TAFCR
__IO uint32_t TAFCR
Definition: stm32f407xx.h:653
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f407xx.h:230
FSMC_Bank2_3_TypeDef::PATT2
__IO uint32_t PATT2
Definition: stm32f407xx.h:497
FSMC_Bank2_3_TypeDef::PMEM2
__IO uint32_t PMEM2
Definition: stm32f407xx.h:496
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f407xx.h:252
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32f407xx.h:111
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32f407xx.h:121
SYSCFG_TypeDef::PMC
__IO uint32_t PMC
Definition: stm32f407xx.h:547
RTC_TypeDef
Real-Time Clock.
Definition: stm32f407xx.h:635
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f407xx.h:745
RNG_TypeDef
RNG.
Definition: stm32f407xx.h:784
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition: stm32f407xx.h:102
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition: stm32f407xx.h:143
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32f407xx.h:297
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f407xx.h:560
RCC_TypeDef::AHB1LPENR
__IO uint32_t AHB1LPENR
Definition: stm32f407xx.h:617
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32f407xx.h:646
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32f407xx.h:648
USB_OTG_DeviceTypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition: stm32f407xx.h:825
ADC_TypeDef::JOFR2
__IO uint32_t JOFR2
Definition: stm32f407xx.h:187
SDIO_TypeDef::POWER
__IO uint32_t POWER
Definition: stm32f407xx.h:685
ETH_TypeDef::DMACHTDR
__IO uint32_t DMACHTDR
Definition: stm32f407xx.h:433
DCMI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:330
ETH_TypeDef::MMCRIR
__IO uint32_t MMCRIR
Definition: stm32f407xx.h:395
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f407xx.h:613
ETH_TypeDef::MMCTGFCR
__IO uint32_t MMCTGFCR
Definition: stm32f407xx.h:403
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32f407xx.h:604
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f407xx.h:577
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f407xx.h:559
USB_OTG_HostTypeDef::Reserved40C
uint32_t Reserved40C
Definition: stm32f407xx.h:880

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:51