Modules | Classes
System Control Block (SCB)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC)

Type definitions for the System Control Block Registers. More...

Collaboration diagram for System Control Block (SCB):

Modules

 System Controls not in SCB (SCnSCB)
 Type definitions for the System Control and ID Register not in the SCB.
 

Classes

struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLBASE_Pos   29U
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLBASE_Pos   29U
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLBASE_Pos   29U
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLBASE_Pos   29U
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 

Detailed Description

Type definitions for the System Control Block Registers.

Macro Definition Documentation

◆ SCB_ABFSR_AHBP_Msk [1/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 900 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_AHBP_Msk [2/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 900 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Msk [3/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 900 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Msk [4/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 900 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Msk [5/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 900 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Msk [6/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 900 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Msk [7/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 988 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AHBP_Msk [8/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 988 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AHBP_Msk [9/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 988 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AHBP_Msk [10/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 988 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AHBP_Msk [11/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 988 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AHBP_Msk [12/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 988 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AHBP_Msk [13/13]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 989 of file core_armv81mml.h.

◆ SCB_ABFSR_AHBP_Pos [1/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 899 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos [2/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 899 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos [3/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 899 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos [4/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 899 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos [5/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 899 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos [6/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 899 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos [7/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 987 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AHBP_Pos [8/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 987 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AHBP_Pos [9/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 987 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AHBP_Pos [10/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 987 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AHBP_Pos [11/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 987 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AHBP_Pos [12/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 987 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AHBP_Pos [13/13]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 988 of file core_armv81mml.h.

◆ SCB_ABFSR_AXIM_Msk [1/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 897 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk [2/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 897 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk [3/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 897 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk [4/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 897 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk [5/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 897 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk [6/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 897 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk [7/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 985 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIM_Msk [8/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 985 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIM_Msk [9/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 985 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIM_Msk [10/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 985 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIM_Msk [11/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 985 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIM_Msk [12/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 985 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIM_Msk [13/13]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 986 of file core_armv81mml.h.

◆ SCB_ABFSR_AXIM_Pos [1/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 896 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos [2/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 896 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos [3/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 896 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos [4/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 896 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos [5/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 896 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos [6/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 896 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos [7/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 984 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIM_Pos [8/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 984 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIM_Pos [9/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 984 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIM_Pos [10/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 984 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIM_Pos [11/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 984 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIM_Pos [12/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 984 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIM_Pos [13/13]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 985 of file core_armv81mml.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [1/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 891 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [2/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 891 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [3/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 891 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [4/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 891 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [5/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 891 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [6/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 891 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [7/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 979 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [8/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 979 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [9/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 979 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [10/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 979 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [11/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 979 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [12/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 979 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [13/13]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 980 of file core_armv81mml.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [1/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 890 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [2/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 890 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [3/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 890 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [4/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 890 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [5/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 890 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [6/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 890 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [7/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 978 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [8/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 978 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [9/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 978 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [10/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 978 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [11/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 978 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [12/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 978 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [13/13]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 979 of file core_armv81mml.h.

◆ SCB_ABFSR_DTCM_Msk [1/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 903 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk [2/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 903 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk [3/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 903 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk [4/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 903 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk [5/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 903 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk [6/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 903 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk [7/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 991 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_DTCM_Msk [8/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 991 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_DTCM_Msk [9/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 991 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_DTCM_Msk [10/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 991 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_DTCM_Msk [11/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 991 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_DTCM_Msk [12/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 991 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_DTCM_Msk [13/13]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 992 of file core_armv81mml.h.

◆ SCB_ABFSR_DTCM_Pos [1/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 902 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos [2/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 902 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos [3/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 902 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos [4/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 902 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos [5/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 902 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos [6/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 902 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos [7/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 990 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_DTCM_Pos [8/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 990 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_DTCM_Pos [9/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 990 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_DTCM_Pos [10/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 990 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_DTCM_Pos [11/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 990 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_DTCM_Pos [12/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 990 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_DTCM_Pos [13/13]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 991 of file core_armv81mml.h.

◆ SCB_ABFSR_EPPB_Msk [1/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 894 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk [2/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 894 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk [3/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 894 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk [4/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 894 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk [5/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 894 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk [6/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 894 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk [7/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 982 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_EPPB_Msk [8/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 982 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_EPPB_Msk [9/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 982 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_EPPB_Msk [10/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 982 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_EPPB_Msk [11/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 982 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_EPPB_Msk [12/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 982 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_EPPB_Msk [13/13]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 983 of file core_armv81mml.h.

◆ SCB_ABFSR_EPPB_Pos [1/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 893 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos [2/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 893 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos [3/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 893 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos [4/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 893 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos [5/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 893 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos [6/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 893 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos [7/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 981 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_EPPB_Pos [8/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 981 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_EPPB_Pos [9/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 981 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_EPPB_Pos [10/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 981 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_EPPB_Pos [11/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 981 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_EPPB_Pos [12/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 981 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_EPPB_Pos [13/13]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 982 of file core_armv81mml.h.

◆ SCB_ABFSR_ITCM_Msk [1/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 906 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk [2/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 906 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk [3/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 906 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk [4/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 906 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk [5/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 906 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk [6/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 906 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk [7/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 994 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_ITCM_Msk [8/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 994 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_ITCM_Msk [9/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 994 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_ITCM_Msk [10/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 994 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_ITCM_Msk [11/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 994 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_ITCM_Msk [12/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 994 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_ITCM_Msk [13/13]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 995 of file core_armv81mml.h.

◆ SCB_ABFSR_ITCM_Pos [1/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 905 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos [2/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 905 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos [3/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 905 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos [4/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 905 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos [5/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 905 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos [6/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 905 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos [7/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 993 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_ITCM_Pos [8/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 993 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_ITCM_Pos [9/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 993 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_ITCM_Pos [10/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 993 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_ITCM_Pos [11/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 993 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ABFSR_ITCM_Pos [12/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 993 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ABFSR_ITCM_Pos [13/13]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 994 of file core_armv81mml.h.

◆ SCB_AHBPCR_EN_Msk [1/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 867 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Msk [2/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 867 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Msk [3/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 867 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Msk [4/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 867 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Msk [5/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 867 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBPCR_EN_Msk [6/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 867 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Msk [7/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 955 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_EN_Msk [8/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 955 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_EN_Msk [9/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 955 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_EN_Msk [10/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 955 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_EN_Msk [11/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 955 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_EN_Msk [12/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 955 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_EN_Msk [13/13]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 956 of file core_armv81mml.h.

◆ SCB_AHBPCR_EN_Pos [1/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 866 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Pos [2/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 866 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Pos [3/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 866 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Pos [4/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 866 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Pos [5/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 866 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBPCR_EN_Pos [6/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 866 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_EN_Pos [7/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 954 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_EN_Pos [8/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 954 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_EN_Pos [9/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 954 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_EN_Pos [10/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 954 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_EN_Pos [11/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 954 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_EN_Pos [12/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 954 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_EN_Pos [13/13]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 955 of file core_armv81mml.h.

◆ SCB_AHBPCR_SZ_Msk [1/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 864 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk [2/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 864 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk [3/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 864 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk [4/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 864 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk [5/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 864 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk [6/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 864 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk [7/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 952 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_SZ_Msk [8/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 952 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_SZ_Msk [9/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 952 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_SZ_Msk [10/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 952 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_SZ_Msk [11/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 952 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_SZ_Msk [12/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 952 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_SZ_Msk [13/13]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 953 of file core_armv81mml.h.

◆ SCB_AHBPCR_SZ_Pos [1/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 863 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos [2/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 863 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos [3/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 863 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos [4/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 863 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos [5/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 863 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos [6/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 863 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos [7/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 951 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_SZ_Pos [8/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 951 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_SZ_Pos [9/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 951 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_SZ_Pos [10/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 951 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_SZ_Pos [11/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 951 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBPCR_SZ_Pos [12/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 951 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBPCR_SZ_Pos [13/13]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 952 of file core_armv81mml.h.

◆ SCB_AHBSCR_CTL_Msk [1/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 887 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk [2/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 887 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk [3/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 887 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk [4/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 887 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk [5/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 887 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk [6/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 887 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk [7/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 975 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_CTL_Msk [8/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 975 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_CTL_Msk [9/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 975 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_CTL_Msk [10/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 975 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_CTL_Msk [11/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 975 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_CTL_Msk [12/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 975 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_CTL_Msk [13/13]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 976 of file core_armv81mml.h.

◆ SCB_AHBSCR_CTL_Pos [1/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 886 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos [2/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 886 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos [3/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 886 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos [4/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 886 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos [5/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 886 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos [6/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 886 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos [7/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 974 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_CTL_Pos [8/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 974 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_CTL_Pos [9/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 974 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_CTL_Pos [10/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 974 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_CTL_Pos [11/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 974 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_CTL_Pos [12/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 974 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_CTL_Pos [13/13]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 975 of file core_armv81mml.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [1/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 881 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [2/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 881 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [3/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 881 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [4/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 881 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [5/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 881 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [6/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 881 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [7/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 969 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [8/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 969 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [9/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 969 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [10/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 969 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [11/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 969 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [12/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 969 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [13/13]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 970 of file core_armv81mml.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [1/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 880 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [2/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 880 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [3/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 880 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [4/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 880 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [5/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 880 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [6/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 880 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [7/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 968 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [8/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 968 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [9/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 968 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [10/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 968 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [11/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 968 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [12/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 968 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [13/13]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 969 of file core_armv81mml.h.

◆ SCB_AHBSCR_TPRI_Msk [1/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 884 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk [2/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 884 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk [3/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 884 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk [4/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 884 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk [5/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 884 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk [6/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 884 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk [7/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 972 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_TPRI_Msk [8/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 972 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_TPRI_Msk [9/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 972 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_TPRI_Msk [10/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 972 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_TPRI_Msk [11/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 972 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_TPRI_Msk [12/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 972 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_TPRI_Msk [13/13]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 973 of file core_armv81mml.h.

◆ SCB_AHBSCR_TPRI_Pos [1/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 883 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos [2/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 883 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos [3/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 883 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos [4/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 883 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos [5/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 883 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos [6/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 883 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos [7/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 971 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_TPRI_Pos [8/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 971 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_TPRI_Pos [9/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 971 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_TPRI_Pos [10/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 971 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_TPRI_Pos [11/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 971 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AHBSCR_TPRI_Pos [12/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 971 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AHBSCR_TPRI_Pos [13/13]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 972 of file core_armv81mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [1/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [2/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [3/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [4/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [5/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [6/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [7/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [8/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [9/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 617 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [10/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 617 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [11/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 617 of file core_cm35p.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [12/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 625 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [13/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 625 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [14/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 625 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [15/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 625 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [16/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 625 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [17/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 625 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [18/18]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 626 of file core_armv81mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [1/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [2/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [3/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [4/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [5/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [6/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [7/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [8/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [9/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 616 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [10/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 616 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [11/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 616 of file core_cm35p.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [12/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 624 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [13/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 624 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [14/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 624 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [15/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 624 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [16/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 624 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [17/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 624 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [18/18]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 625 of file core_armv81mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [1/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Msk [2/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Msk [3/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Msk [4/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Msk [5/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Msk [6/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Msk [7/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Msk [8/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Msk [9/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 418 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Msk [10/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 418 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Msk [11/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 418 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Msk [12/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 418 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Msk [13/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 430 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Msk [14/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 430 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Msk [15/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 430 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Msk [16/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 430 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Msk [17/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 463 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Msk [18/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 463 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Msk [19/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 463 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Msk [20/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 463 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Msk [21/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 466 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Msk [22/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 466 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Msk [23/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 466 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Msk [24/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 466 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Msk [25/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Msk [26/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Msk [27/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Msk [28/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Msk [29/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Msk [30/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Msk [31/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Msk [32/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Msk [33/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 524 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [34/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 524 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [35/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 524 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [36/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 524 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [37/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 524 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [38/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 524 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [39/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 568 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [40/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 568 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [41/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 568 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [42/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 568 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [43/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 568 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [44/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 568 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [45/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 611 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [46/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 611 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Msk [47/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 611 of file core_cm35p.h.

◆ SCB_AIRCR_ENDIANESS_Msk [48/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 619 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Msk [49/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 619 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Msk [50/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 619 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Msk [51/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 619 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [52/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 619 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [53/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 619 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [54/54]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 620 of file core_armv81mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [1/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Pos [2/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Pos [3/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Pos [4/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Pos [5/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Pos [6/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Pos [7/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Pos [8/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Pos [9/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 417 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Pos [10/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 417 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Pos [11/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 417 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Pos [12/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 417 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Pos [13/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 429 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Pos [14/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 429 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Pos [15/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 429 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Pos [16/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 429 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Pos [17/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 462 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Pos [18/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 462 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Pos [19/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 462 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Pos [20/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 462 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Pos [21/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 465 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Pos [22/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 465 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Pos [23/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 465 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Pos [24/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 465 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Pos [25/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Pos [26/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Pos [27/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Pos [28/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Pos [29/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Pos [30/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Pos [31/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Pos [32/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Pos [33/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 523 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [34/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 523 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [35/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 523 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [36/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 523 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [37/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 523 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [38/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 523 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [39/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 567 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [40/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 567 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [41/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 567 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [42/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 567 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [43/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 567 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [44/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 567 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [45/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 610 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [46/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 610 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Pos [47/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 610 of file core_cm35p.h.

◆ SCB_AIRCR_ENDIANESS_Pos [48/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 618 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Pos [49/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 618 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Pos [50/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 618 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Pos [51/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 618 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [52/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 618 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [53/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 618 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [54/54]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 619 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [1/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 466 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Msk [2/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 466 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Msk [3/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 466 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Msk [4/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 466 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Msk [5/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 469 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Msk [6/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 469 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Msk [7/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 469 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Msk [8/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 469 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Msk [9/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 527 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [10/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 527 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [11/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 527 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [12/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 527 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [13/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 527 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [14/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 527 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [15/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 571 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [16/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 571 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [17/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 571 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [18/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 571 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [19/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 571 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [20/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 571 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [21/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 620 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [22/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 620 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Msk [23/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 620 of file core_cm35p.h.

◆ SCB_AIRCR_PRIGROUP_Msk [24/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 628 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Msk [25/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 628 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Msk [26/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 628 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Msk [27/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 628 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [28/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 628 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [29/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 628 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [30/30]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 629 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [1/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 465 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Pos [2/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 465 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Pos [3/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 465 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Pos [4/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 465 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Pos [5/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 468 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Pos [6/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 468 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Pos [7/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 468 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Pos [8/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 468 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Pos [9/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 526 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [10/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 526 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [11/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 526 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [12/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 526 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [13/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 526 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [14/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 526 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [15/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 570 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [16/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 570 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [17/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 570 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [18/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 570 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [19/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 570 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [20/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 570 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [21/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 619 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [22/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 619 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Pos [23/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 619 of file core_cm35p.h.

◆ SCB_AIRCR_PRIGROUP_Pos [24/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 627 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Pos [25/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 627 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Pos [26/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 627 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Pos [27/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 627 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [28/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 627 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [29/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 627 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [30/30]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 628 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIS_Msk [1/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_PRIS_Msk [2/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Msk [3/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_PRIS_Msk [4/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Msk [5/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_PRIS_Msk [6/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_PRIS_Msk [7/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Msk [8/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Msk [9/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 614 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Msk [10/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 614 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIS_Msk [11/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 614 of file core_cm35p.h.

◆ SCB_AIRCR_PRIS_Msk [12/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 622 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIS_Msk [13/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 622 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIS_Msk [14/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 622 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIS_Msk [15/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 622 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Msk [16/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 622 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Msk [17/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 622 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Msk [18/18]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 623 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIS_Pos [1/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 470 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_PRIS_Pos [2/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 470 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Pos [3/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 470 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_PRIS_Pos [4/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 470 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Pos [5/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 470 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_PRIS_Pos [6/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 470 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_PRIS_Pos [7/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 470 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Pos [8/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 470 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Pos [9/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 613 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Pos [10/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 613 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIS_Pos [11/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 613 of file core_cm35p.h.

◆ SCB_AIRCR_PRIS_Pos [12/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 621 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIS_Pos [13/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 621 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIS_Pos [14/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 621 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_PRIS_Pos [15/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 621 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Pos [16/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 621 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Pos [17/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 621 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Pos [18/18]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 622 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [1/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [2/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [3/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [4/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [5/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [6/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [7/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [8/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [9/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 421 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [10/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 421 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [11/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 421 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [12/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 421 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [13/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 433 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [14/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 433 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [15/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 433 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [16/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 433 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [17/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 469 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [18/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 469 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [19/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 469 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [20/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 469 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [21/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 472 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [22/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 472 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [23/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 472 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [24/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 472 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [25/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [26/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [27/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [28/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [29/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [30/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [31/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [32/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [33/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 530 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [34/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 530 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [35/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 530 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [36/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 530 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [37/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 530 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [38/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 530 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [39/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 574 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [40/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 574 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [41/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 574 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [42/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 574 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [43/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 574 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [44/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 574 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [45/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 626 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [46/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 626 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [47/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 626 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [48/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 634 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [49/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 634 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [50/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 634 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [51/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 634 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [52/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 634 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [53/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 634 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [54/54]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 635 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [1/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [2/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [3/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [4/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [5/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [6/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [7/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [8/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [9/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 420 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [10/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 420 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [11/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 420 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [12/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 420 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [13/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 432 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [14/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 432 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [15/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 432 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [16/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 432 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [17/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 468 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [18/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 468 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [19/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 468 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [20/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 468 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [21/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 471 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [22/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 471 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [23/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 471 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [24/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 471 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [25/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [26/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [27/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [28/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [29/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [30/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [31/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [32/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [33/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 529 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [34/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 529 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [35/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 529 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [36/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 529 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [37/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 529 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [38/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 529 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [39/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 573 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [40/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 573 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [41/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 573 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [42/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 573 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [43/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 573 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [44/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 573 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [45/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 625 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [46/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 625 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [47/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 625 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [48/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 633 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [49/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 633 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [50/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 633 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [51/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 633 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [52/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 633 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [53/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 633 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [54/54]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 634 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [1/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [2/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [3/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [4/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [5/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [6/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [7/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [8/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [9/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 623 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [10/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 623 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [11/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 623 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [12/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 631 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [13/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 631 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [14/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 631 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [15/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 631 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [16/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 631 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [17/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 631 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [18/18]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 632 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [1/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [2/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [3/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [4/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [5/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [6/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [7/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [8/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [9/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 622 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [10/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 622 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [11/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 622 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [12/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 630 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [13/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 630 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [14/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 630 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [15/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 630 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [16/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 630 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [17/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 630 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [18/18]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 631 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [3/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [4/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [5/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [6/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [7/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [8/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [9/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 424 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [10/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 424 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [11/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 424 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [12/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 424 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [13/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 436 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [14/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 436 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [15/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 436 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [16/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 436 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [17/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 472 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [18/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 472 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [19/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 472 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [20/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 472 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [21/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 475 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [22/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 475 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [23/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 475 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [24/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 475 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [25/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [26/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [27/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [28/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [29/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [30/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [31/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [32/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [33/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 533 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [34/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 533 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [35/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 533 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [36/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 533 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [37/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 533 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [38/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 533 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [39/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 577 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [40/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 577 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [41/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 577 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [42/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 577 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [43/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 577 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [44/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 577 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [45/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 629 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [46/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 629 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [47/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 629 of file core_cm35p.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [48/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 637 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [49/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 637 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [50/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 637 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [51/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 637 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [52/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 637 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [53/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 637 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [54/54]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 638 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [3/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [4/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [5/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [6/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [7/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [8/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [9/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 423 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [10/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 423 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [11/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 423 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [12/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 423 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [13/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 435 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [14/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 435 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [15/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 435 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [16/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 435 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [17/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 471 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [18/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 471 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [19/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 471 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [20/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 471 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [21/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 474 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [22/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 474 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [23/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 474 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [24/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 474 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [25/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [26/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [27/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [28/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [29/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [30/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [31/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [32/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [33/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 532 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [34/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 532 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [35/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 532 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [36/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 532 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [37/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 532 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [38/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 532 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [39/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 576 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [40/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 576 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [41/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 576 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [42/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 576 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [43/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 576 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [44/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 576 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [45/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 628 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [46/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 628 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [47/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 628 of file core_cm35p.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [48/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 636 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [49/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 636 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [50/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 636 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [51/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 636 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [52/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 636 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [53/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 636 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [54/54]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 637 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [1/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Msk [2/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Msk [3/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Msk [4/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Msk [5/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Msk [6/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Msk [7/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Msk [8/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Msk [9/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 412 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Msk [10/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 412 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Msk [11/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 412 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Msk [12/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 412 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Msk [13/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 424 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Msk [14/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 424 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Msk [15/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 424 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Msk [16/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 424 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Msk [17/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 457 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Msk [18/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 457 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Msk [19/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 457 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Msk [20/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 457 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Msk [21/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 460 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Msk [22/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 460 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Msk [23/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 460 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Msk [24/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 460 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Msk [25/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Msk [26/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Msk [27/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Msk [28/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Msk [29/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Msk [30/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Msk [31/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Msk [32/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Msk [33/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 518 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [34/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 518 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [35/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 518 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [36/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 518 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [37/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 518 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [38/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 518 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [39/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 562 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [40/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 562 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [41/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 562 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [42/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 562 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [43/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 562 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [44/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 562 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [45/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 605 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [46/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 605 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Msk [47/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 605 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEY_Msk [48/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 613 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Msk [49/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 613 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Msk [50/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 613 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Msk [51/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 613 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [52/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 613 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [53/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 613 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [54/54]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 614 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [1/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Pos [2/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Pos [3/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Pos [4/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Pos [5/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Pos [6/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Pos [7/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Pos [8/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Pos [9/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 411 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Pos [10/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 411 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Pos [11/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 411 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Pos [12/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 411 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Pos [13/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 423 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Pos [14/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 423 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Pos [15/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 423 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Pos [16/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 423 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Pos [17/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 456 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Pos [18/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 456 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Pos [19/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 456 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Pos [20/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 456 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Pos [21/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 459 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Pos [22/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 459 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Pos [23/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 459 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Pos [24/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 459 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Pos [25/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Pos [26/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Pos [27/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Pos [28/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Pos [29/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Pos [30/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Pos [31/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Pos [32/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Pos [33/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 517 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [34/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 517 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [35/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 517 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [36/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 517 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [37/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 517 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [38/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 517 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [39/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 561 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [40/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 561 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [41/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 561 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [42/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 561 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [43/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 561 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [44/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 561 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [45/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 604 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [46/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 604 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Pos [47/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 604 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEY_Pos [48/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 612 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Pos [49/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 612 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Pos [50/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 612 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Pos [51/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 612 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [52/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 612 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [53/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 612 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [54/54]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 613 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [3/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [4/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [5/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [6/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [7/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [8/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [9/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 415 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [10/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 415 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [11/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 415 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [12/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 415 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [13/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 427 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [14/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 427 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [15/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 427 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [16/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 427 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [17/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 460 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [18/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 460 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [19/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 460 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [20/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 460 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [21/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 463 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [22/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 463 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [23/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 463 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [24/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 463 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [25/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [26/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [27/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [28/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [29/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [30/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [31/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [32/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [33/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 521 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [34/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 521 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [35/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 521 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [36/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 521 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [37/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 521 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [38/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 521 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [39/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 565 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [40/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 565 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [41/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 565 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [42/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 565 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [43/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 565 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [44/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 565 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [45/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 608 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [46/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 608 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [47/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 608 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [48/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 616 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [49/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 616 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [50/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 616 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [51/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 616 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [52/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 616 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [53/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 616 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [54/54]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 617 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [3/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [4/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [5/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [6/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [7/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [8/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [9/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 414 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [10/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 414 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [11/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 414 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [12/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 414 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [13/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 426 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [14/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 426 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [15/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 426 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [16/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 426 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [17/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 459 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [18/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 459 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [19/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 459 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [20/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 459 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [21/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 462 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [22/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 462 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [23/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 462 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [24/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 462 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [25/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [26/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [27/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [28/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [29/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [30/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [31/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [32/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [33/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 520 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [34/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 520 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [35/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 520 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [36/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 520 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [37/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 520 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [38/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 520 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [39/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 564 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [40/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 564 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [41/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 564 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [42/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 564 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [43/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 564 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [44/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 564 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [45/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 607 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [46/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 607 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [47/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 607 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [48/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 615 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [49/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 615 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [50/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 615 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [51/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 615 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [52/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 615 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [53/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 615 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [54/54]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 616 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTRESET_Msk [1/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 475 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Msk [2/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 475 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Msk [3/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 475 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Msk [4/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 475 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Msk [5/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 478 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Msk [6/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 478 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Msk [7/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 478 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Msk [8/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 478 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Msk [9/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 536 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [10/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 536 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [11/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 536 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [12/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 536 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [13/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 536 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [14/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 536 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [15/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 580 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Msk [16/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 580 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Msk [17/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 580 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Msk [18/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 580 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Msk [19/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 580 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Msk [20/20]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 580 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [1/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 474 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Pos [2/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 474 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Pos [3/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 474 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Pos [4/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 474 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Pos [5/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 477 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Pos [6/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 477 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Pos [7/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 477 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Pos [8/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 477 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Pos [9/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 535 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [10/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 535 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [11/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 535 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [12/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 535 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [13/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 535 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [14/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 535 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [15/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 579 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [16/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 579 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [17/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 579 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [18/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 579 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [19/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 579 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [20/20]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 579 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Msk [1/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 874 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Msk [2/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 874 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Msk [3/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 874 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Msk [4/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 874 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Msk [5/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 874 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CACR_ECCEN_Msk [6/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 874 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Msk [7/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 962 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_ECCEN_Msk [8/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 962 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_ECCEN_Msk [9/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 962 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_ECCEN_Msk [10/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 962 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_ECCEN_Msk [11/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 962 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_ECCEN_Msk [12/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 962 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_ECCEN_Msk [13/13]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 963 of file core_armv81mml.h.

◆ SCB_CACR_ECCEN_Pos [1/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 873 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Pos [2/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 873 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Pos [3/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 873 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Pos [4/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 873 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Pos [5/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 873 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CACR_ECCEN_Pos [6/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 873 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_ECCEN_Pos [7/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 961 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_ECCEN_Pos [8/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 961 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_ECCEN_Pos [9/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 961 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_ECCEN_Pos [10/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 961 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_ECCEN_Pos [11/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 961 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_ECCEN_Pos [12/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 961 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_ECCEN_Pos [13/13]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

Definition at line 962 of file core_armv81mml.h.

◆ SCB_CACR_FORCEWT_Msk [1/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 871 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk [2/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 871 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk [3/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 871 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk [4/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 871 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk [5/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 871 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk [6/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 871 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk [7/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 959 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_FORCEWT_Msk [8/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 959 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_FORCEWT_Msk [9/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 959 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_FORCEWT_Msk [10/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 959 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_FORCEWT_Msk [11/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 959 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_FORCEWT_Msk [12/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 959 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_FORCEWT_Msk [13/13]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 960 of file core_armv81mml.h.

◆ SCB_CACR_FORCEWT_Pos [1/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 870 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos [2/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 870 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos [3/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 870 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos [4/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 870 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos [5/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 870 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos [6/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 870 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos [7/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 958 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_FORCEWT_Pos [8/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 958 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_FORCEWT_Pos [9/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 958 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_FORCEWT_Pos [10/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 958 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_FORCEWT_Pos [11/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 958 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_FORCEWT_Pos [12/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 958 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_FORCEWT_Pos [13/13]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 959 of file core_armv81mml.h.

◆ SCB_CACR_SIWT_Msk [1/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 877 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Msk [2/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 877 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Msk [3/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 877 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Msk [4/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 877 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Msk [5/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 877 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CACR_SIWT_Msk [6/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 877 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Msk [7/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 965 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_SIWT_Msk [8/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 965 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_SIWT_Msk [9/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 965 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_SIWT_Msk [10/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 965 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_SIWT_Msk [11/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 965 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_SIWT_Msk [12/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 965 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_SIWT_Msk [13/13]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 966 of file core_armv81mml.h.

◆ SCB_CACR_SIWT_Pos [1/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 876 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Pos [2/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 876 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Pos [3/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 876 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Pos [4/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 876 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CACR_SIWT_Pos [5/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 876 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Pos [6/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 876 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CACR_SIWT_Pos [7/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 964 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_SIWT_Pos [8/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 964 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_SIWT_Pos [9/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 964 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_SIWT_Pos [10/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 964 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_SIWT_Pos [11/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 964 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CACR_SIWT_Pos [12/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 964 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CACR_SIWT_Pos [13/13]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 965 of file core_armv81mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [1/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 492 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Msk [2/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 492 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Msk [3/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 492 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Msk [4/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 492 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Msk [5/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 495 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Msk [6/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 495 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Msk [7/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 495 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Msk [8/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 495 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Msk [9/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Msk [10/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Msk [11/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Msk [12/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Msk [13/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Msk [14/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Msk [15/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Msk [16/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Msk [17/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 553 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [18/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 553 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [19/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 553 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [20/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 553 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [21/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 553 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [22/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 553 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [23/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 606 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [24/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 606 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [25/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 606 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [26/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 606 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [27/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 606 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [28/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 606 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [29/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 658 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [30/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 658 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Msk [31/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 658 of file core_cm35p.h.

◆ SCB_CCR_BFHFNMIGN_Msk [32/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 666 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [33/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 666 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Msk [34/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 666 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Msk [35/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 666 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Msk [36/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 666 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [37/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 666 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [38/38]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 667 of file core_armv81mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [1/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 491 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Pos [2/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 491 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Pos [3/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 491 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Pos [4/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 491 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Pos [5/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 494 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Pos [6/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 494 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Pos [7/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 494 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Pos [8/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 494 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Pos [9/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Pos [10/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Pos [11/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Pos [12/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Pos [13/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Pos [14/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Pos [15/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Pos [16/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Pos [17/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 552 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [18/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 552 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [19/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 552 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [20/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 552 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [21/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 552 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [22/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 552 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [23/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 605 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Pos [24/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 605 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Pos [25/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 605 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Pos [26/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 605 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Pos [27/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 605 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Pos [28/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 605 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Pos [29/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 657 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [30/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 657 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Pos [31/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 657 of file core_cm35p.h.

◆ SCB_CCR_BFHFNMIGN_Pos [32/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 665 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Pos [33/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 665 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Pos [34/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 665 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Pos [35/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 665 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [36/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 665 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [37/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 665 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [38/38]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 666 of file core_armv81mml.h.

◆ SCB_CCR_BP_Msk [1/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 500 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BP_Msk [2/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 500 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BP_Msk [3/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 500 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BP_Msk [4/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 500 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BP_Msk [5/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 500 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BP_Msk [6/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 500 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BP_Msk [7/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 500 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BP_Msk [8/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 500 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BP_Msk [9/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 594 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Msk [10/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 594 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Msk [11/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 594 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Msk [12/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 594 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Msk [13/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 594 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Msk [14/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 594 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_BP_Msk [15/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 646 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BP_Msk [16/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 646 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BP_Msk [17/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 646 of file core_cm35p.h.

◆ SCB_CCR_BP_Msk [18/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 654 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BP_Msk [19/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 654 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BP_Msk [20/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 654 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BP_Msk [21/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 654 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BP_Msk [22/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 654 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BP_Msk [23/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 654 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BP_Msk [24/24]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 655 of file core_armv81mml.h.

◆ SCB_CCR_BP_Pos [1/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 499 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BP_Pos [2/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 499 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BP_Pos [3/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 499 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BP_Pos [4/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 499 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BP_Pos [5/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 499 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BP_Pos [6/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 499 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_BP_Pos [7/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 499 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BP_Pos [8/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 499 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_BP_Pos [9/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: Branch prediction enable bit Position

Definition at line 593 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Pos [10/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: Branch prediction enable bit Position

Definition at line 593 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Pos [11/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: Branch prediction enable bit Position

Definition at line 593 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Pos [12/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: Branch prediction enable bit Position

Definition at line 593 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Pos [13/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: Branch prediction enable bit Position

Definition at line 593 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_BP_Pos [14/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: Branch prediction enable bit Position

Definition at line 593 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_BP_Pos [15/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 645 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BP_Pos [16/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 645 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BP_Pos [17/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 645 of file core_cm35p.h.

◆ SCB_CCR_BP_Pos [18/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 653 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BP_Pos [19/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 653 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BP_Pos [20/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 653 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_BP_Pos [21/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 653 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BP_Pos [22/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 653 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BP_Pos [23/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 653 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_BP_Pos [24/24]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 654 of file core_armv81mml.h.

◆ SCB_CCR_DC_Msk [1/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 506 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DC_Msk [2/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 506 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DC_Msk [3/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 506 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DC_Msk [4/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 506 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DC_Msk [5/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 506 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DC_Msk [6/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 506 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DC_Msk [7/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 506 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DC_Msk [8/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 506 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DC_Msk [9/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 600 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Msk [10/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 600 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Msk [11/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 600 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Msk [12/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 600 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Msk [13/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 600 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Msk [14/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 600 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_DC_Msk [15/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 652 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DC_Msk [16/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 652 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DC_Msk [17/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 652 of file core_cm35p.h.

◆ SCB_CCR_DC_Msk [18/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 660 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DC_Msk [19/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 660 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DC_Msk [20/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 660 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DC_Msk [21/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 660 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DC_Msk [22/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 660 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DC_Msk [23/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 660 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DC_Msk [24/24]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 661 of file core_armv81mml.h.

◆ SCB_CCR_DC_Pos [1/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 505 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DC_Pos [2/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 505 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DC_Pos [3/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 505 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DC_Pos [4/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 505 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DC_Pos [5/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 505 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DC_Pos [6/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 505 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DC_Pos [7/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 505 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DC_Pos [8/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 505 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DC_Pos [9/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: Cache enable bit Position

Definition at line 599 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Pos [10/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: Cache enable bit Position

Definition at line 599 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Pos [11/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: Cache enable bit Position

Definition at line 599 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Pos [12/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: Cache enable bit Position

Definition at line 599 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Pos [13/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: Cache enable bit Position

Definition at line 599 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_DC_Pos [14/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: Cache enable bit Position

Definition at line 599 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DC_Pos [15/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 651 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DC_Pos [16/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 651 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DC_Pos [17/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 651 of file core_cm35p.h.

◆ SCB_CCR_DC_Pos [18/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 659 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DC_Pos [19/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 659 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DC_Pos [20/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 659 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DC_Pos [21/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 659 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DC_Pos [22/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 659 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DC_Pos [23/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 659 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DC_Pos [24/24]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 660 of file core_armv81mml.h.

◆ SCB_CCR_DIV_0_TRP_Msk [1/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 495 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Msk [2/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 495 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Msk [3/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 495 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Msk [4/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 495 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Msk [5/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 498 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Msk [6/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 498 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Msk [7/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 498 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Msk [8/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 498 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Msk [9/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 515 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Msk [10/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 515 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Msk [11/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 515 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Msk [12/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 515 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Msk [13/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 515 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Msk [14/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 515 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Msk [15/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 515 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Msk [16/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 515 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Msk [17/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 556 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Msk [18/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 556 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Msk [19/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 556 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Msk [20/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 556 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Msk [21/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 556 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Msk [22/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 556 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Msk [23/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 609 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Msk [24/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 609 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Msk [25/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 609 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Msk [26/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 609 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Msk [27/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 609 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Msk [28/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 609 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Msk [29/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 661 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Msk [30/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 661 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Msk [31/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 661 of file core_cm35p.h.

◆ SCB_CCR_DIV_0_TRP_Msk [32/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 669 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Msk [33/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 669 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Msk [34/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 669 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Msk [35/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 669 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Msk [36/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 669 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Msk [37/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 669 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Msk [38/38]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 670 of file core_armv81mml.h.

◆ SCB_CCR_DIV_0_TRP_Pos [1/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 494 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Pos [2/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 494 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Pos [3/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 494 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Pos [4/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 494 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Pos [5/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 497 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Pos [6/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 497 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Pos [7/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 497 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Pos [8/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 497 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Pos [9/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 514 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Pos [10/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 514 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Pos [11/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 514 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Pos [12/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 514 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Pos [13/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 514 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Pos [14/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 514 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Pos [15/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 514 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Pos [16/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 514 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Pos [17/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 555 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Pos [18/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 555 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Pos [19/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 555 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Pos [20/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 555 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Pos [21/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 555 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Pos [22/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 555 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Pos [23/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 608 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Pos [24/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 608 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Pos [25/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 608 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Pos [26/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 608 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Pos [27/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 608 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Pos [28/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 608 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Pos [29/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 660 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Pos [30/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 660 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Pos [31/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 660 of file core_cm35p.h.

◆ SCB_CCR_DIV_0_TRP_Pos [32/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 668 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Pos [33/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 668 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Pos [34/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 668 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Pos [35/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 668 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Pos [36/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 668 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Pos [37/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 668 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Pos [38/38]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 669 of file core_armv81mml.h.

◆ SCB_CCR_IC_Msk [1/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 503 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_IC_Msk [2/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 503 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_IC_Msk [3/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 503 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_IC_Msk [4/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 503 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_IC_Msk [5/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 503 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_IC_Msk [6/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 503 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_IC_Msk [7/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 503 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_IC_Msk [8/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 503 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_IC_Msk [9/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 597 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Msk [10/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 597 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Msk [11/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 597 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Msk [12/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 597 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Msk [13/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 597 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_IC_Msk [14/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 597 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Msk [15/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 649 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_IC_Msk [16/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 649 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_IC_Msk [17/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 649 of file core_cm35p.h.

◆ SCB_CCR_IC_Msk [18/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 657 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_IC_Msk [19/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 657 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_IC_Msk [20/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 657 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_IC_Msk [21/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 657 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_IC_Msk [22/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 657 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_IC_Msk [23/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 657 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_IC_Msk [24/24]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 658 of file core_armv81mml.h.

◆ SCB_CCR_IC_Pos [1/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 502 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_IC_Pos [2/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 502 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_IC_Pos [3/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 502 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_IC_Pos [4/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 502 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_IC_Pos [5/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 502 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_IC_Pos [6/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 502 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_IC_Pos [7/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 502 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_IC_Pos [8/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 502 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_IC_Pos [9/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: Instruction cache enable bit Position

Definition at line 596 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Pos [10/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: Instruction cache enable bit Position

Definition at line 596 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Pos [11/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: Instruction cache enable bit Position

Definition at line 596 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Pos [12/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: Instruction cache enable bit Position

Definition at line 596 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Pos [13/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: Instruction cache enable bit Position

Definition at line 596 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_IC_Pos [14/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: Instruction cache enable bit Position

Definition at line 596 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_IC_Pos [15/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 648 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_IC_Pos [16/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 648 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_IC_Pos [17/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 648 of file core_cm35p.h.

◆ SCB_CCR_IC_Pos [18/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 656 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_IC_Pos [19/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 656 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_IC_Pos [20/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 656 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_IC_Pos [21/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 656 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_IC_Pos [22/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 656 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_IC_Pos [23/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 656 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_IC_Pos [24/24]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 657 of file core_armv81mml.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [1/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 504 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [2/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 504 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [3/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 504 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [4/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 504 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [5/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 507 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [6/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 507 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [7/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 507 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [8/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 507 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [9/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 565 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [10/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 565 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [11/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 565 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [12/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 565 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [13/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 565 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [14/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 565 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [15/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 618 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [16/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 618 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [17/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 618 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [18/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 618 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [19/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 618 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [20/20]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 618 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [1/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 503 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [2/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 503 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [3/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 503 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [4/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 503 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [5/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 506 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [6/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 506 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [7/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 506 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [8/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 506 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [9/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 564 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [10/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 564 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [11/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 564 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [12/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 564 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [13/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 564 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [14/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 564 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [15/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 617 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [16/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 617 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [17/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 617 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [18/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 617 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [19/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 617 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [20/20]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 617 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [1/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_STKALIGN_Msk [2/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_STKALIGN_Msk [3/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_STKALIGN_Msk [4/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_STKALIGN_Msk [5/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_STKALIGN_Msk [6/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_STKALIGN_Msk [7/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_STKALIGN_Msk [8/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_STKALIGN_Msk [9/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 438 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_STKALIGN_Msk [10/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 438 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_STKALIGN_Msk [11/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 438 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_STKALIGN_Msk [12/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 438 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_STKALIGN_Msk [13/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 450 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Msk [14/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 450 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Msk [15/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 450 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Msk [16/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 450 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Msk [17/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 489 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_STKALIGN_Msk [18/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 489 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_STKALIGN_Msk [19/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 489 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_STKALIGN_Msk [20/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 489 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_STKALIGN_Msk [21/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 492 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_STKALIGN_Msk [22/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 492 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_STKALIGN_Msk [23/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 492 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_STKALIGN_Msk [24/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 492 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_STKALIGN_Msk [25/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 550 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [26/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 550 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [27/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 550 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [28/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 550 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [29/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 550 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [30/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 550 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [31/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 603 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [32/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 603 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [33/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 603 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [34/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 603 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [35/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 603 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [36/36]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 603 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [1/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_STKALIGN_Pos [2/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_STKALIGN_Pos [3/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_STKALIGN_Pos [4/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_STKALIGN_Pos [5/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_STKALIGN_Pos [6/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_STKALIGN_Pos [7/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_STKALIGN_Pos [8/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_STKALIGN_Pos [9/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 437 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_STKALIGN_Pos [10/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 437 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_STKALIGN_Pos [11/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 437 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_STKALIGN_Pos [12/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 437 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_STKALIGN_Pos [13/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 449 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Pos [14/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 449 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Pos [15/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 449 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Pos [16/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 449 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Pos [17/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 488 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_STKALIGN_Pos [18/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 488 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_STKALIGN_Pos [19/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 488 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_STKALIGN_Pos [20/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 488 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_STKALIGN_Pos [21/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 491 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_STKALIGN_Pos [22/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 491 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_STKALIGN_Pos [23/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 491 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_STKALIGN_Pos [24/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 491 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_STKALIGN_Pos [25/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 549 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [26/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 549 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [27/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 549 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [28/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 549 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [29/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 549 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [30/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 549 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [31/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 602 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [32/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 602 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [33/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 602 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [34/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 602 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [35/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 602 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [36/36]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 602 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [1/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [2/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [3/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [4/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [5/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [6/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [7/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [8/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [9/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 655 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [10/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 655 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [11/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 655 of file core_cm35p.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [12/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 663 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [13/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 663 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [14/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 663 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [15/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 663 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [16/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 663 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [17/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 663 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [18/18]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 664 of file core_armv81mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [1/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [2/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [3/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [4/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [5/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [6/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [7/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [8/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [9/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 654 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [10/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 654 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [11/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 654 of file core_cm35p.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [12/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 662 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [13/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 662 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [14/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 662 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [15/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 662 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [16/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 662 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [17/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 662 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [18/18]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 663 of file core_armv81mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [1/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [2/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [3/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [4/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [5/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [6/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [7/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [8/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [9/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 441 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [10/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 441 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [11/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 441 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [12/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 441 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [13/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 453 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [14/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 453 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [15/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 453 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [16/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 453 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [17/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 498 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [18/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 498 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [19/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 498 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [20/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 498 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [21/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 501 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [22/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 501 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [23/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 501 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [24/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 501 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [25/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [26/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [27/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [28/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [29/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [30/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [31/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [32/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [33/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 559 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [34/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 559 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [35/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 559 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [36/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 559 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [37/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 559 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [38/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 559 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [39/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 612 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [40/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 612 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [41/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 612 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [42/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 612 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [43/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 612 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [44/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 612 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [45/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 664 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [46/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 664 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [47/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 664 of file core_cm35p.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [48/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 672 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [49/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 672 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [50/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 672 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [51/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 672 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [52/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 672 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [53/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 672 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [54/54]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 673 of file core_armv81mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [1/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [2/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [3/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [4/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [5/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [6/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [7/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [8/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [9/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 440 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [10/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 440 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [11/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 440 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [12/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 440 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [13/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 452 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [14/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 452 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [15/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 452 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [16/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 452 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [17/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 497 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [18/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 497 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [19/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 497 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [20/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 497 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [21/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 500 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [22/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 500 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [23/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 500 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [24/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 500 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [25/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [26/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [27/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [28/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [29/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [30/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [31/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [32/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [33/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 558 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [34/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 558 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [35/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 558 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [36/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 558 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [37/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 558 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [38/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 558 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [39/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 611 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [40/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 611 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [41/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 611 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [42/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 611 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [43/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 611 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [44/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 611 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [45/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 663 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [46/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 663 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [47/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 663 of file core_cm35p.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [48/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 671 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [49/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 671 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [50/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 671 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [51/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 671 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [52/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 671 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [53/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 671 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [54/54]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 672 of file core_armv81mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [1/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 501 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Msk [2/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 501 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Msk [3/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 501 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Msk [4/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 501 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Msk [5/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 504 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Msk [6/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 504 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Msk [7/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 504 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Msk [8/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 504 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Msk [9/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Msk [10/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Msk [11/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Msk [12/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Msk [13/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Msk [14/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Msk [15/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Msk [16/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Msk [17/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 562 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [18/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 562 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [19/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 562 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [20/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 562 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [21/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 562 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [22/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 562 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [23/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 615 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [24/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 615 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [25/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 615 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [26/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 615 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [27/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 615 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [28/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 615 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [29/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 667 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [30/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 667 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Msk [31/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 667 of file core_cm35p.h.

◆ SCB_CCR_USERSETMPEND_Msk [32/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 675 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [33/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 675 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Msk [34/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 675 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Msk [35/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 675 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Msk [36/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 675 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [37/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 675 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [38/38]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 676 of file core_armv81mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [1/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 500 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Pos [2/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 500 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Pos [3/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 500 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Pos [4/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 500 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Pos [5/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 503 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Pos [6/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 503 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Pos [7/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 503 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Pos [8/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 503 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Pos [9/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Pos [10/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Pos [11/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Pos [12/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Pos [13/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Pos [14/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Pos [15/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Pos [16/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Pos [17/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 561 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [18/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 561 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [19/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 561 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [20/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 561 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [21/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 561 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [22/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 561 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [23/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 614 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [24/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 614 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [25/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 614 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [26/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 614 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [27/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 614 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [28/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 614 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [29/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 666 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [30/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 666 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Pos [31/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 666 of file core_cm35p.h.

◆ SCB_CCR_USERSETMPEND_Pos [32/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 674 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [33/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 674 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Pos [34/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 674 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Pos [35/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 674 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Pos [36/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 674 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [37/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 674 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [38/38]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 675 of file core_armv81mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [1/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 799 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [2/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 799 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [3/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 799 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [4/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 799 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [5/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 799 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [6/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 799 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [7/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 879 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [8/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 879 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [9/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 879 of file core_cm35p.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [10/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 887 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [11/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 887 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [12/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 887 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [13/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 887 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [14/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 887 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [15/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 887 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [16/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 888 of file core_armv81mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [1/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 798 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [2/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 798 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [3/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 798 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [4/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 798 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [5/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 798 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [6/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 798 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [7/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 878 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [8/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 878 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [9/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 878 of file core_cm35p.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [10/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 886 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [11/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 886 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [12/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 886 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [13/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 886 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [14/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 886 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [15/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 886 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [16/16]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 887 of file core_armv81mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [1/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 802 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk [2/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 802 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk [3/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 802 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk [4/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 802 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk [5/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 802 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk [6/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 802 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk [7/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 882 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [8/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 882 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Msk [9/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 882 of file core_cm35p.h.

◆ SCB_CCSIDR_LINESIZE_Msk [10/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 890 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [11/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 890 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [12/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 890 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Msk [13/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 890 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Msk [14/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 890 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Msk [15/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 890 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [16/16]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 891 of file core_armv81mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [1/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 801 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos [2/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 801 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos [3/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 801 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos [4/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 801 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos [5/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 801 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos [6/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 801 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos [7/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 881 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [8/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 881 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Pos [9/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 881 of file core_cm35p.h.

◆ SCB_CCSIDR_LINESIZE_Pos [10/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 889 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [11/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 889 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [12/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 889 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Pos [13/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 889 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Pos [14/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 889 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Pos [15/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 889 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [16/16]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 890 of file core_armv81mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [1/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 796 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk [2/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 796 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk [3/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 796 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk [4/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 796 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk [5/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 796 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk [6/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 796 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk [7/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 876 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Msk [8/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 876 of file core_cm35p.h.

◆ SCB_CCSIDR_NUMSETS_Msk [9/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 876 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [10/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 884 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [11/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 884 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [12/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 884 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Msk [13/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 884 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Msk [14/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 884 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Msk [15/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 884 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [16/16]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 885 of file core_armv81mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [1/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 795 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos [2/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 795 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos [3/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 795 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos [4/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 795 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos [5/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 795 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos [6/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 795 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos [7/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 875 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [8/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 875 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Pos [9/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 875 of file core_cm35p.h.

◆ SCB_CCSIDR_NUMSETS_Pos [10/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 883 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [11/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 883 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [12/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 883 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Pos [13/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 883 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Pos [14/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 883 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Pos [15/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 883 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [16/16]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 884 of file core_armv81mml.h.

◆ SCB_CCSIDR_RA_Msk [1/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 790 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Msk [2/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 790 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_RA_Msk [3/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 790 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Msk [4/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 790 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Msk [5/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 790 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Msk [6/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 790 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Msk [7/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 870 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_RA_Msk [8/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 870 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_RA_Msk [9/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 870 of file core_cm35p.h.

◆ SCB_CCSIDR_RA_Msk [10/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 878 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_RA_Msk [11/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 878 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_RA_Msk [12/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 878 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_RA_Msk [13/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 878 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_RA_Msk [14/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 878 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_RA_Msk [15/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 878 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_RA_Msk [16/16]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 879 of file core_armv81mml.h.

◆ SCB_CCSIDR_RA_Pos [1/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 789 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Pos [2/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 789 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_RA_Pos [3/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 789 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Pos [4/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 789 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Pos [5/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 789 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Pos [6/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 789 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_RA_Pos [7/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 869 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_RA_Pos [8/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 869 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_RA_Pos [9/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 869 of file core_cm35p.h.

◆ SCB_CCSIDR_RA_Pos [10/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 877 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_RA_Pos [11/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 877 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_RA_Pos [12/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 877 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_RA_Pos [13/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 877 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_RA_Pos [14/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 877 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_RA_Pos [15/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 877 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_RA_Pos [16/16]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 878 of file core_armv81mml.h.

◆ SCB_CCSIDR_WA_Msk [1/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 793 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Msk [2/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 793 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Msk [3/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 793 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_WA_Msk [4/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 793 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Msk [5/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 793 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Msk [6/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 793 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Msk [7/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 873 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WA_Msk [8/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 873 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WA_Msk [9/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 873 of file core_cm35p.h.

◆ SCB_CCSIDR_WA_Msk [10/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 881 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WA_Msk [11/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 881 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WA_Msk [12/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 881 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WA_Msk [13/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 881 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WA_Msk [14/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 881 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WA_Msk [15/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 881 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WA_Msk [16/16]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 882 of file core_armv81mml.h.

◆ SCB_CCSIDR_WA_Pos [1/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 792 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Pos [2/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 792 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_WA_Pos [3/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 792 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Pos [4/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 792 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Pos [5/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 792 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Pos [6/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 792 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WA_Pos [7/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 872 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WA_Pos [8/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 872 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WA_Pos [9/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 872 of file core_cm35p.h.

◆ SCB_CCSIDR_WA_Pos [10/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 880 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WA_Pos [11/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 880 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WA_Pos [12/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 880 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WA_Pos [13/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 880 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WA_Pos [14/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 880 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WA_Pos [15/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 880 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WA_Pos [16/16]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 881 of file core_armv81mml.h.

◆ SCB_CCSIDR_WB_Msk [1/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 787 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Msk [2/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 787 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_WB_Msk [3/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 787 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Msk [4/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 787 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Msk [5/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 787 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Msk [6/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 787 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Msk [7/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 867 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WB_Msk [8/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 867 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WB_Msk [9/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 867 of file core_cm35p.h.

◆ SCB_CCSIDR_WB_Msk [10/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 875 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WB_Msk [11/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 875 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WB_Msk [12/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 875 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WB_Msk [13/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 875 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WB_Msk [14/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 875 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WB_Msk [15/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 875 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WB_Msk [16/16]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 876 of file core_armv81mml.h.

◆ SCB_CCSIDR_WB_Pos [1/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 786 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Pos [2/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 786 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_WB_Pos [3/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 786 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Pos [4/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 786 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Pos [5/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 786 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Pos [6/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 786 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WB_Pos [7/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 866 of file core_cm35p.h.

◆ SCB_CCSIDR_WB_Pos [8/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 866 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WB_Pos [9/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 866 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WB_Pos [10/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 874 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WB_Pos [11/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 874 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WB_Pos [12/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 874 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WB_Pos [13/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 874 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WB_Pos [14/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 874 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WB_Pos [15/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 874 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WB_Pos [16/16]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 875 of file core_armv81mml.h.

◆ SCB_CCSIDR_WT_Msk [1/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 784 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Msk [2/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 784 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_WT_Msk [3/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 784 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Msk [4/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 784 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Msk [5/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 784 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Msk [6/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 784 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Msk [7/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 864 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WT_Msk [8/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 864 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WT_Msk [9/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 864 of file core_cm35p.h.

◆ SCB_CCSIDR_WT_Msk [10/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 872 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WT_Msk [11/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 872 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WT_Msk [12/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 872 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WT_Msk [13/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 872 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WT_Msk [14/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 872 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WT_Msk [15/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 872 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WT_Msk [16/16]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 873 of file core_armv81mml.h.

◆ SCB_CCSIDR_WT_Pos [1/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 783 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Pos [2/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 783 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CCSIDR_WT_Pos [3/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 783 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Pos [4/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 783 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Pos [5/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 783 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Pos [6/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 783 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CCSIDR_WT_Pos [7/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 863 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WT_Pos [8/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 863 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WT_Pos [9/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 863 of file core_cm35p.h.

◆ SCB_CCSIDR_WT_Pos [10/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 871 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WT_Pos [11/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 871 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WT_Pos [12/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 871 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WT_Pos [13/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 871 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WT_Pos [14/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 871 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CCSIDR_WT_Pos [15/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 871 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CCSIDR_WT_Pos [16/16]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 872 of file core_armv81mml.h.

◆ SCB_CFSR_BFARVALID_Msk [1/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 577 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BFARVALID_Msk [2/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 577 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BFARVALID_Msk [3/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 577 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BFARVALID_Msk [4/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 577 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BFARVALID_Msk [5/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 580 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BFARVALID_Msk [6/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 580 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BFARVALID_Msk [7/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 580 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BFARVALID_Msk [8/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 580 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BFARVALID_Msk [9/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 641 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Msk [10/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 641 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Msk [11/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 641 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Msk [12/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 641 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Msk [13/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 641 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Msk [14/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 641 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Msk [15/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 694 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [16/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 694 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [17/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 694 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [18/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 694 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [19/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 694 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [20/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 694 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [21/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 761 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Msk [22/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 761 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BFARVALID_Msk [23/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 761 of file core_cm35p.h.

◆ SCB_CFSR_BFARVALID_Msk [24/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 769 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Msk [25/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 769 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BFARVALID_Msk [26/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 769 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BFARVALID_Msk [27/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 769 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BFARVALID_Msk [28/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 769 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Msk [29/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 769 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Msk [30/30]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 770 of file core_armv81mml.h.

◆ SCB_CFSR_BFARVALID_Pos [1/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 576 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BFARVALID_Pos [2/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 576 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BFARVALID_Pos [3/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 576 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BFARVALID_Pos [4/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 576 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BFARVALID_Pos [5/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 579 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BFARVALID_Pos [6/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 579 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BFARVALID_Pos [7/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 579 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BFARVALID_Pos [8/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 579 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BFARVALID_Pos [9/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 640 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Pos [10/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 640 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Pos [11/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 640 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Pos [12/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 640 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Pos [13/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 640 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Pos [14/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 640 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BFARVALID_Pos [15/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 693 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Pos [16/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 693 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Pos [17/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 693 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Pos [18/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 693 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Pos [19/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 693 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Pos [20/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 693 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BFARVALID_Pos [21/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 760 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Pos [22/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 760 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BFARVALID_Pos [23/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 760 of file core_cm35p.h.

◆ SCB_CFSR_BFARVALID_Pos [24/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 768 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Pos [25/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 768 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BFARVALID_Pos [26/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 768 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BFARVALID_Pos [27/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 768 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BFARVALID_Pos [28/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 768 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Pos [29/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 768 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Pos [30/30]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 769 of file core_armv81mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [1/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 554 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [2/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 554 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [3/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 554 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [4/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 554 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [5/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 557 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [6/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 557 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [7/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 557 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [8/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 557 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [9/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 615 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [10/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 615 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [11/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 615 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [12/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 615 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [13/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 615 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [14/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 615 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [15/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 668 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [16/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 668 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [17/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 668 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [18/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 668 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [19/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 668 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [20/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 668 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [21/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 735 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [22/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 735 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [23/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 735 of file core_cm35p.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [24/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 743 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [25/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 743 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [26/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 743 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [27/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 743 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [28/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 743 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [29/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 743 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [30/30]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 744 of file core_armv81mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [1/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 553 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [2/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 553 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [3/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 553 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [4/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 553 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [5/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 556 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [6/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 556 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [7/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 556 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [8/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 556 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [9/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 614 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [10/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 614 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [11/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 614 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [12/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 614 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [13/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 614 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [14/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 614 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [15/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 667 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [16/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 667 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [17/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 667 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [18/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 667 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [19/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 667 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [20/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 667 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [21/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 734 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [22/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 734 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [23/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 734 of file core_cm35p.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [24/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 742 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [25/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 742 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [26/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 742 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [27/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 742 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [28/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 742 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [29/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 742 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [30/30]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 743 of file core_armv81mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [1/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 570 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Msk [2/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 570 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Msk [3/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 570 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Msk [4/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 570 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Msk [5/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 573 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Msk [6/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 573 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Msk [7/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 573 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Msk [8/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 573 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Msk [9/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 634 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Msk [10/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 634 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Msk [11/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 634 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Msk [12/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 634 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Msk [13/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 634 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Msk [14/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 634 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Msk [15/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 687 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Msk [16/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 687 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Msk [17/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 687 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Msk [18/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 687 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Msk [19/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 687 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Msk [20/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 687 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Msk [21/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 754 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [22/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 754 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Msk [23/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 754 of file core_cm35p.h.

◆ SCB_CFSR_DACCVIOL_Msk [24/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 762 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [25/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 762 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Msk [26/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 762 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Msk [27/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 762 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [28/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 762 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Msk [29/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 762 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [30/30]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 763 of file core_armv81mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [1/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 569 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Pos [2/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 569 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Pos [3/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 569 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Pos [4/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 569 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Pos [5/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 572 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Pos [6/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 572 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Pos [7/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 572 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Pos [8/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 572 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Pos [9/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 633 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Pos [10/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 633 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Pos [11/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 633 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Pos [12/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 633 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Pos [13/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 633 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Pos [14/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 633 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Pos [15/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 686 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Pos [16/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 686 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Pos [17/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 686 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Pos [18/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 686 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Pos [19/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 686 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Pos [20/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 686 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Pos [21/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 753 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [22/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 753 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Pos [23/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 753 of file core_cm35p.h.

◆ SCB_CFSR_DACCVIOL_Pos [24/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 761 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [25/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 761 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Pos [26/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 761 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Pos [27/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 761 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Pos [28/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 761 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [29/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 761 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [30/30]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 762 of file core_armv81mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [1/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 596 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Msk [2/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 596 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Msk [3/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 596 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Msk [4/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 596 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Msk [5/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 599 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Msk [6/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 599 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Msk [7/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 599 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Msk [8/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 599 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Msk [9/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 663 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Msk [10/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 663 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Msk [11/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 663 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Msk [12/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 663 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Msk [13/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 663 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Msk [14/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 663 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Msk [15/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 716 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Msk [16/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 716 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Msk [17/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 716 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Msk [18/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 716 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Msk [19/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 716 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Msk [20/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 716 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Msk [21/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 783 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [22/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 783 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Msk [23/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 783 of file core_cm35p.h.

◆ SCB_CFSR_DIVBYZERO_Msk [24/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 791 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [25/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 791 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Msk [26/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 791 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Msk [27/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 791 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Msk [28/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 791 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [29/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 791 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [30/30]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 792 of file core_armv81mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [1/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 595 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Pos [2/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 595 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Pos [3/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 595 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Pos [4/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 595 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Pos [5/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 598 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Pos [6/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 598 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Pos [7/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 598 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Pos [8/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 598 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Pos [9/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 662 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Pos [10/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 662 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Pos [11/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 662 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Pos [12/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 662 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Pos [13/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 662 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Pos [14/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 662 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Pos [15/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 715 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Pos [16/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 715 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Pos [17/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 715 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Pos [18/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 715 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Pos [19/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 715 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Pos [20/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 715 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Pos [21/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 782 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [22/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 782 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Pos [23/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 782 of file core_cm35p.h.

◆ SCB_CFSR_DIVBYZERO_Pos [24/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 790 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [25/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 790 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Pos [26/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 790 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Pos [27/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 790 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Pos [28/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 790 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [29/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 790 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [30/30]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 791 of file core_armv81mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [1/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 573 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Msk [2/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 573 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Msk [3/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 573 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Msk [4/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 573 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Msk [5/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 576 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Msk [6/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 576 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Msk [7/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 576 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Msk [8/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 576 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Msk [9/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 637 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Msk [10/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 637 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Msk [11/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 637 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Msk [12/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 637 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Msk [13/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 637 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Msk [14/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 637 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Msk [15/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 690 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Msk [16/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 690 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Msk [17/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 690 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Msk [18/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 690 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Msk [19/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 690 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Msk [20/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 690 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Msk [21/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 757 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [22/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 757 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Msk [23/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 757 of file core_cm35p.h.

◆ SCB_CFSR_IACCVIOL_Msk [24/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 765 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [25/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 765 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Msk [26/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 765 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Msk [27/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 765 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Msk [28/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 765 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [29/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 765 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [30/30]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 766 of file core_armv81mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [1/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 572 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Pos [2/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 572 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Pos [3/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 572 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Pos [4/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 572 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Pos [5/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 575 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Pos [6/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 575 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Pos [7/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 575 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Pos [8/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 575 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Pos [9/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 636 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Pos [10/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 636 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Pos [11/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 636 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Pos [12/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 636 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Pos [13/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 636 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Pos [14/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 636 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Pos [15/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 689 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Pos [16/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 689 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Pos [17/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 689 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Pos [18/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 689 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Pos [19/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 689 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Pos [20/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 689 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Pos [21/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 756 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Pos [22/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 756 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [23/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 756 of file core_cm35p.h.

◆ SCB_CFSR_IACCVIOL_Pos [24/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 764 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [25/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 764 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Pos [26/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 764 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Pos [27/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 764 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Pos [28/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 764 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [29/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 764 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [30/30]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 765 of file core_armv81mml.h.

◆ SCB_CFSR_IBUSERR_Msk [1/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 592 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IBUSERR_Msk [2/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 592 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IBUSERR_Msk [3/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 592 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IBUSERR_Msk [4/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 592 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IBUSERR_Msk [5/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 595 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IBUSERR_Msk [6/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 595 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IBUSERR_Msk [7/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 595 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IBUSERR_Msk [8/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 595 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IBUSERR_Msk [9/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 659 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Msk [10/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 659 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Msk [11/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 659 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Msk [12/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 659 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Msk [13/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 659 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Msk [14/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 659 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Msk [15/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 712 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Msk [16/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 712 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Msk [17/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 712 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Msk [18/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 712 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Msk [19/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 712 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Msk [20/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 712 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Msk [21/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 779 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Msk [22/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 779 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IBUSERR_Msk [23/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 779 of file core_cm35p.h.

◆ SCB_CFSR_IBUSERR_Msk [24/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 787 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Msk [25/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 787 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IBUSERR_Msk [26/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 787 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IBUSERR_Msk [27/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 787 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IBUSERR_Msk [28/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 787 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Msk [29/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 787 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Msk [30/30]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 788 of file core_armv81mml.h.

◆ SCB_CFSR_IBUSERR_Pos [1/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 591 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IBUSERR_Pos [2/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 591 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IBUSERR_Pos [3/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 591 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IBUSERR_Pos [4/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 591 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IBUSERR_Pos [5/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 594 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IBUSERR_Pos [6/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 594 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IBUSERR_Pos [7/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 594 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IBUSERR_Pos [8/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 594 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IBUSERR_Pos [9/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 658 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Pos [10/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 658 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Pos [11/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 658 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Pos [12/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 658 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Pos [13/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 658 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Pos [14/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 658 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IBUSERR_Pos [15/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 711 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Pos [16/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 711 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Pos [17/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 711 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Pos [18/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 711 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Pos [19/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 711 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Pos [20/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 711 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IBUSERR_Pos [21/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 778 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IBUSERR_Pos [22/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 778 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Pos [23/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 778 of file core_cm35p.h.

◆ SCB_CFSR_IBUSERR_Pos [24/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 786 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Pos [25/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 786 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IBUSERR_Pos [26/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 786 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IBUSERR_Pos [27/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 786 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IBUSERR_Pos [28/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 786 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Pos [29/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 786 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Pos [30/30]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 787 of file core_armv81mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [1/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 586 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Msk [2/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 586 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Msk [3/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 586 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Msk [4/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 586 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Msk [5/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 589 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Msk [6/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 589 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Msk [7/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 589 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Msk [8/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 589 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Msk [9/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 653 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Msk [10/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 653 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Msk [11/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 653 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Msk [12/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 653 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Msk [13/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 653 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Msk [14/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 653 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Msk [15/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 706 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Msk [16/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 706 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Msk [17/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 706 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Msk [18/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 706 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Msk [19/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 706 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Msk [20/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 706 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Msk [21/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 773 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [22/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 773 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Msk [23/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 773 of file core_cm35p.h.

◆ SCB_CFSR_IMPRECISERR_Msk [24/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 781 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [25/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 781 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Msk [26/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 781 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Msk [27/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 781 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Msk [28/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 781 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [29/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 781 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [30/30]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 782 of file core_armv81mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [1/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 585 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Pos [2/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 585 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Pos [3/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 585 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Pos [4/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 585 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Pos [5/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 588 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Pos [6/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 588 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Pos [7/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 588 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Pos [8/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 588 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Pos [9/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 652 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Pos [10/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 652 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Pos [11/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 652 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Pos [12/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 652 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Pos [13/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 652 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Pos [14/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 652 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Pos [15/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 705 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Pos [16/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 705 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Pos [17/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 705 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Pos [18/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 705 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Pos [19/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 705 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Pos [20/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 705 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Pos [21/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 772 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [22/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 772 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Pos [23/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 772 of file core_cm35p.h.

◆ SCB_CFSR_IMPRECISERR_Pos [24/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 780 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [25/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 780 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Pos [26/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 780 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Pos [27/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 780 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Pos [28/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 780 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [29/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 780 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [30/30]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 781 of file core_armv81mml.h.

◆ SCB_CFSR_INVPC_Msk [1/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 605 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVPC_Msk [2/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 605 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVPC_Msk [3/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 605 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVPC_Msk [4/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 605 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVPC_Msk [5/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 608 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVPC_Msk [6/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 608 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVPC_Msk [7/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 608 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVPC_Msk [8/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 608 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVPC_Msk [9/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 672 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Msk [10/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 672 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Msk [11/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 672 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Msk [12/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 672 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Msk [13/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 672 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Msk [14/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 672 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Msk [15/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 725 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_INVPC_Msk [16/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 725 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Msk [17/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 725 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Msk [18/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 725 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Msk [19/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 725 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Msk [20/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 725 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Msk [21/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 795 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVPC_Msk [22/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 795 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVPC_Msk [23/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 795 of file core_cm35p.h.

◆ SCB_CFSR_INVPC_Msk [24/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 803 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVPC_Msk [25/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 803 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVPC_Msk [26/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 803 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVPC_Msk [27/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 803 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVPC_Msk [28/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 803 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVPC_Msk [29/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 803 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVPC_Msk [30/30]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 804 of file core_armv81mml.h.

◆ SCB_CFSR_INVPC_Pos [1/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 604 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVPC_Pos [2/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 604 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVPC_Pos [3/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 604 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVPC_Pos [4/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 604 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVPC_Pos [5/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 607 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVPC_Pos [6/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 607 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVPC_Pos [7/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 607 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVPC_Pos [8/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 607 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVPC_Pos [9/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 671 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Pos [10/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 671 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Pos [11/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 671 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Pos [12/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 671 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Pos [13/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 671 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Pos [14/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 671 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVPC_Pos [15/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 724 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_INVPC_Pos [16/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 724 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Pos [17/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 724 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Pos [18/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 724 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Pos [19/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 724 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Pos [20/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 724 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVPC_Pos [21/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 794 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVPC_Pos [22/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 794 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVPC_Pos [23/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 794 of file core_cm35p.h.

◆ SCB_CFSR_INVPC_Pos [24/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 802 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVPC_Pos [25/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 802 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVPC_Pos [26/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 802 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVPC_Pos [27/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 802 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVPC_Pos [28/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 802 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVPC_Pos [29/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 802 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVPC_Pos [30/30]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 803 of file core_armv81mml.h.

◆ SCB_CFSR_INVSTATE_Msk [1/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 608 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVSTATE_Msk [2/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 608 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVSTATE_Msk [3/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 608 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVSTATE_Msk [4/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 608 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVSTATE_Msk [5/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 611 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVSTATE_Msk [6/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 611 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVSTATE_Msk [7/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 611 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVSTATE_Msk [8/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 611 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVSTATE_Msk [9/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 675 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Msk [10/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 675 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Msk [11/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 675 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Msk [12/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 675 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Msk [13/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 675 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Msk [14/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 675 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Msk [15/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 728 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Msk [16/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 728 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Msk [17/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 728 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Msk [18/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 728 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Msk [19/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 728 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Msk [20/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 728 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Msk [21/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 798 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Msk [22/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 798 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVSTATE_Msk [23/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 798 of file core_cm35p.h.

◆ SCB_CFSR_INVSTATE_Msk [24/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 806 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Msk [25/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 806 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVSTATE_Msk [26/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 806 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVSTATE_Msk [27/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 806 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVSTATE_Msk [28/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 806 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Msk [29/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 806 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Msk [30/30]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 807 of file core_armv81mml.h.

◆ SCB_CFSR_INVSTATE_Pos [1/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 607 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVSTATE_Pos [2/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 607 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVSTATE_Pos [3/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 607 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVSTATE_Pos [4/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 607 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_INVSTATE_Pos [5/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 610 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVSTATE_Pos [6/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 610 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVSTATE_Pos [7/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 610 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVSTATE_Pos [8/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 610 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_INVSTATE_Pos [9/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 674 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Pos [10/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 674 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Pos [11/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 674 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Pos [12/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 674 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Pos [13/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 674 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Pos [14/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 674 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_INVSTATE_Pos [15/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 727 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Pos [16/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 727 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Pos [17/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 727 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Pos [18/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 727 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Pos [19/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 727 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Pos [20/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 727 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_INVSTATE_Pos [21/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 797 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Pos [22/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 797 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVSTATE_Pos [23/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 797 of file core_cm35p.h.

◆ SCB_CFSR_INVSTATE_Pos [24/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 805 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Pos [25/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 805 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVSTATE_Pos [26/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 805 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVSTATE_Pos [27/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 805 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_INVSTATE_Pos [28/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 805 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Pos [29/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 805 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Pos [30/30]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 806 of file core_armv81mml.h.

◆ SCB_CFSR_LSPERR_Msk [1/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 644 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Msk [2/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 644 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Msk [3/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 644 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Msk [4/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 644 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Msk [5/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 644 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Msk [6/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 644 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Msk [7/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 697 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Msk [8/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 697 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Msk [9/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 697 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Msk [10/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 697 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Msk [11/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 697 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Msk [12/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 697 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_LSPERR_Msk [13/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 764 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Msk [14/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 764 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_LSPERR_Msk [15/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 764 of file core_cm35p.h.

◆ SCB_CFSR_LSPERR_Msk [16/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 772 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Msk [17/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 772 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_LSPERR_Msk [18/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 772 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_LSPERR_Msk [19/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 772 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_LSPERR_Msk [20/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 772 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Msk [21/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 772 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Msk [22/22]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 773 of file core_armv81mml.h.

◆ SCB_CFSR_LSPERR_Pos [1/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 643 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Pos [2/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 643 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Pos [3/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 643 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Pos [4/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 643 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Pos [5/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 643 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Pos [6/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 643 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_LSPERR_Pos [7/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 696 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Pos [8/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 696 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Pos [9/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 696 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Pos [10/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 696 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Pos [11/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 696 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_LSPERR_Pos [12/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 696 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_LSPERR_Pos [13/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 763 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_LSPERR_Pos [14/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 763 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Pos [15/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 763 of file core_cm35p.h.

◆ SCB_CFSR_LSPERR_Pos [16/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 771 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Pos [17/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 771 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_LSPERR_Pos [18/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 771 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_LSPERR_Pos [19/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 771 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_LSPERR_Pos [20/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 771 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Pos [21/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 771 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Pos [22/22]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 772 of file core_armv81mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [1/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 557 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [2/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 557 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [3/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 557 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [4/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 557 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [5/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 560 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [6/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 560 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [7/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 560 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [8/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 560 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [9/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 618 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [10/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 618 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [11/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 618 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [12/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 618 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [13/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 618 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [14/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 618 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [15/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 671 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [16/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 671 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [17/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 671 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [18/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 671 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [19/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 671 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [20/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 671 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [21/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 738 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [22/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 738 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [23/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 738 of file core_cm35p.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [24/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 746 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [25/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 746 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [26/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 746 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [27/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 746 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [28/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 746 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [29/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 746 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [30/30]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 747 of file core_armv81mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [1/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 556 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [2/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 556 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [3/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 556 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [4/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 556 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [5/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 559 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [6/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 559 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [7/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 559 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [8/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 559 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [9/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 617 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [10/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 617 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [11/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 617 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [12/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 617 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [13/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 617 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [14/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 617 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [15/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 670 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [16/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 670 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [17/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 670 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [18/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 670 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [19/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 670 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [20/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 670 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [21/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 737 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [22/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 737 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [23/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 737 of file core_cm35p.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [24/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 745 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [25/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 745 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [26/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 745 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [27/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 745 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [28/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 745 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [29/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 745 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [30/30]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 746 of file core_armv81mml.h.

◆ SCB_CFSR_MLSPERR_Msk [1/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 625 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Msk [2/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 625 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Msk [3/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 625 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Msk [4/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 625 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Msk [5/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 625 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Msk [6/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 625 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Msk [7/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 678 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Msk [8/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 678 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Msk [9/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 678 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Msk [10/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 678 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Msk [11/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 678 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Msk [12/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 678 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Msk [13/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 745 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Msk [14/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 745 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MLSPERR_Msk [15/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 745 of file core_cm35p.h.

◆ SCB_CFSR_MLSPERR_Msk [16/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 753 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Msk [17/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 753 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MLSPERR_Msk [18/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 753 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MLSPERR_Msk [19/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 753 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MLSPERR_Msk [20/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 753 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Msk [21/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 753 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Msk [22/22]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 754 of file core_armv81mml.h.

◆ SCB_CFSR_MLSPERR_Pos [1/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 624 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Pos [2/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 624 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Pos [3/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 624 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Pos [4/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 624 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Pos [5/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 624 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Pos [6/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 624 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MLSPERR_Pos [7/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 677 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Pos [8/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 677 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Pos [9/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 677 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Pos [10/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 677 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Pos [11/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 677 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Pos [12/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 677 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MLSPERR_Pos [13/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 744 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Pos [14/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 744 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MLSPERR_Pos [15/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 744 of file core_cm35p.h.

◆ SCB_CFSR_MLSPERR_Pos [16/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 752 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Pos [17/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 752 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MLSPERR_Pos [18/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 752 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MLSPERR_Pos [19/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 752 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MLSPERR_Pos [20/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 752 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Pos [21/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 752 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Pos [22/22]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 753 of file core_armv81mml.h.

◆ SCB_CFSR_MMARVALID_Msk [1/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 561 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MMARVALID_Msk [2/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 561 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MMARVALID_Msk [3/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 561 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MMARVALID_Msk [4/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 561 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MMARVALID_Msk [5/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 564 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MMARVALID_Msk [6/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 564 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MMARVALID_Msk [7/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 564 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MMARVALID_Msk [8/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 564 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MMARVALID_Msk [9/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 622 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Msk [10/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 622 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Msk [11/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 622 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Msk [12/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 622 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Msk [13/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 622 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Msk [14/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 622 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Msk [15/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 675 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [16/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 675 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [17/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 675 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [18/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 675 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [19/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 675 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [20/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 675 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [21/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 742 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Msk [22/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 742 of file core_cm35p.h.

◆ SCB_CFSR_MMARVALID_Msk [23/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 742 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MMARVALID_Msk [24/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 750 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Msk [25/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 750 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MMARVALID_Msk [26/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 750 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MMARVALID_Msk [27/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 750 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MMARVALID_Msk [28/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 750 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Msk [29/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 750 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Msk [30/30]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 751 of file core_armv81mml.h.

◆ SCB_CFSR_MMARVALID_Pos [1/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 560 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MMARVALID_Pos [2/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 560 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MMARVALID_Pos [3/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 560 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MMARVALID_Pos [4/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 560 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MMARVALID_Pos [5/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 563 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MMARVALID_Pos [6/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 563 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MMARVALID_Pos [7/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 563 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MMARVALID_Pos [8/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 563 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MMARVALID_Pos [9/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 621 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Pos [10/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 621 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Pos [11/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 621 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Pos [12/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 621 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Pos [13/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 621 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Pos [14/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 621 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MMARVALID_Pos [15/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 674 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Pos [16/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 674 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Pos [17/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 674 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Pos [18/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 674 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Pos [19/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 674 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Pos [20/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 674 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MMARVALID_Pos [21/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 741 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Pos [22/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 741 of file core_cm35p.h.

◆ SCB_CFSR_MMARVALID_Pos [23/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 741 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MMARVALID_Pos [24/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 749 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Pos [25/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 749 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MMARVALID_Pos [26/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 749 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MMARVALID_Pos [27/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 749 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MMARVALID_Pos [28/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 749 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Pos [29/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 749 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Pos [30/30]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 750 of file core_armv81mml.h.

◆ SCB_CFSR_MSTKERR_Msk [1/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 564 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MSTKERR_Msk [2/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 564 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MSTKERR_Msk [3/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 564 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MSTKERR_Msk [4/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 564 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MSTKERR_Msk [5/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 567 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MSTKERR_Msk [6/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 567 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MSTKERR_Msk [7/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 567 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MSTKERR_Msk [8/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 567 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MSTKERR_Msk [9/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 628 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Msk [10/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 628 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Msk [11/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 628 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Msk [12/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 628 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Msk [13/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 628 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Msk [14/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 628 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Msk [15/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 681 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Msk [16/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 681 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Msk [17/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 681 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Msk [18/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 681 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Msk [19/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 681 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Msk [20/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 681 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Msk [21/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 748 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Msk [22/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 748 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MSTKERR_Msk [23/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 748 of file core_cm35p.h.

◆ SCB_CFSR_MSTKERR_Msk [24/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 756 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Msk [25/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 756 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MSTKERR_Msk [26/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 756 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MSTKERR_Msk [27/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 756 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MSTKERR_Msk [28/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 756 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Msk [29/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 756 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Msk [30/30]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 757 of file core_armv81mml.h.

◆ SCB_CFSR_MSTKERR_Pos [1/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 563 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MSTKERR_Pos [2/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 563 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MSTKERR_Pos [3/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 563 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MSTKERR_Pos [4/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 563 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MSTKERR_Pos [5/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 566 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MSTKERR_Pos [6/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 566 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MSTKERR_Pos [7/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 566 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MSTKERR_Pos [8/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 566 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MSTKERR_Pos [9/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 627 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Pos [10/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 627 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Pos [11/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 627 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Pos [12/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 627 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Pos [13/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 627 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Pos [14/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 627 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MSTKERR_Pos [15/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 680 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Pos [16/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 680 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Pos [17/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 680 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Pos [18/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 680 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Pos [19/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 680 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Pos [20/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 680 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MSTKERR_Pos [21/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 747 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Pos [22/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 747 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MSTKERR_Pos [23/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 747 of file core_cm35p.h.

◆ SCB_CFSR_MSTKERR_Pos [24/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 755 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Pos [25/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 755 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MSTKERR_Pos [26/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 755 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MSTKERR_Pos [27/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 755 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MSTKERR_Pos [28/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 755 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Pos [29/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 755 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Pos [30/30]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 756 of file core_armv81mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [1/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 567 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Msk [2/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 567 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Msk [3/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 567 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Msk [4/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 567 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Msk [5/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 570 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Msk [6/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 570 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Msk [7/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 570 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Msk [8/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 570 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Msk [9/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 631 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Msk [10/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 631 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Msk [11/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 631 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Msk [12/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 631 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Msk [13/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 631 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Msk [14/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 631 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Msk [15/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 684 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Msk [16/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 684 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Msk [17/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 684 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Msk [18/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 684 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Msk [19/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 684 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Msk [20/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 684 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Msk [21/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 751 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [22/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 751 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Msk [23/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 751 of file core_cm35p.h.

◆ SCB_CFSR_MUNSTKERR_Msk [24/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 759 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [25/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 759 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Msk [26/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 759 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Msk [27/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 759 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Msk [28/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 759 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [29/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 759 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [30/30]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 760 of file core_armv81mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [1/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 566 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Pos [2/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 566 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Pos [3/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 566 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Pos [4/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 566 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Pos [5/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 569 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Pos [6/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 569 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Pos [7/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 569 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Pos [8/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 569 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Pos [9/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 630 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Pos [10/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 630 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Pos [11/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 630 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Pos [12/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 630 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Pos [13/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 630 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Pos [14/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 630 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Pos [15/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 683 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Pos [16/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 683 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Pos [17/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 683 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Pos [18/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 683 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Pos [19/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 683 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Pos [20/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 683 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Pos [21/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 750 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [22/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 750 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Pos [23/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 750 of file core_cm35p.h.

◆ SCB_CFSR_MUNSTKERR_Pos [24/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 758 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [25/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 758 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Pos [26/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 758 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Pos [27/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 758 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Pos [28/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 758 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [29/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 758 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [30/30]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 759 of file core_armv81mml.h.

◆ SCB_CFSR_NOCP_Msk [1/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 602 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_NOCP_Msk [2/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 602 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_NOCP_Msk [3/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 602 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_NOCP_Msk [4/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 602 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_NOCP_Msk [5/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 605 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_NOCP_Msk [6/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 605 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_NOCP_Msk [7/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 605 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_NOCP_Msk [8/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 605 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_NOCP_Msk [9/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 669 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Msk [10/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 669 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Msk [11/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 669 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Msk [12/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 669 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Msk [13/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 669 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Msk [14/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 669 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Msk [15/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 722 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_NOCP_Msk [16/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 722 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Msk [17/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 722 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Msk [18/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 722 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Msk [19/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 722 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Msk [20/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 722 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Msk [21/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 792 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_NOCP_Msk [22/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 792 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_NOCP_Msk [23/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 792 of file core_cm35p.h.

◆ SCB_CFSR_NOCP_Msk [24/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 800 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_NOCP_Msk [25/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 800 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_NOCP_Msk [26/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 800 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_NOCP_Msk [27/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 800 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_NOCP_Msk [28/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 800 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_NOCP_Msk [29/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 800 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_NOCP_Msk [30/30]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 801 of file core_armv81mml.h.

◆ SCB_CFSR_NOCP_Pos [1/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 601 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_NOCP_Pos [2/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 601 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_NOCP_Pos [3/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 601 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_NOCP_Pos [4/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 601 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_NOCP_Pos [5/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 604 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_NOCP_Pos [6/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 604 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_NOCP_Pos [7/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 604 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_NOCP_Pos [8/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 604 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_NOCP_Pos [9/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 668 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Pos [10/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 668 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Pos [11/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 668 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Pos [12/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 668 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Pos [13/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 668 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Pos [14/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 668 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_NOCP_Pos [15/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 721 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Pos [16/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 721 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_NOCP_Pos [17/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 721 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Pos [18/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 721 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Pos [19/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 721 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Pos [20/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 721 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_NOCP_Pos [21/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 791 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_NOCP_Pos [22/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 791 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_NOCP_Pos [23/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 791 of file core_cm35p.h.

◆ SCB_CFSR_NOCP_Pos [24/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 799 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_NOCP_Pos [25/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 799 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_NOCP_Pos [26/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 799 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_NOCP_Pos [27/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 799 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_NOCP_Pos [28/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 799 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_NOCP_Pos [29/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 799 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_NOCP_Pos [30/30]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 800 of file core_armv81mml.h.

◆ SCB_CFSR_PRECISERR_Msk [1/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 589 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_PRECISERR_Msk [2/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 589 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_PRECISERR_Msk [3/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 589 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_PRECISERR_Msk [4/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 589 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_PRECISERR_Msk [5/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 592 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_PRECISERR_Msk [6/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 592 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_PRECISERR_Msk [7/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 592 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_PRECISERR_Msk [8/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 592 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_PRECISERR_Msk [9/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 656 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Msk [10/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 656 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Msk [11/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 656 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Msk [12/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 656 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Msk [13/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 656 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Msk [14/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 656 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Msk [15/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 709 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Msk [16/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 709 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Msk [17/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 709 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Msk [18/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 709 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Msk [19/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 709 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Msk [20/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 709 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Msk [21/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 776 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Msk [22/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 776 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_PRECISERR_Msk [23/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 776 of file core_cm35p.h.

◆ SCB_CFSR_PRECISERR_Msk [24/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 784 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Msk [25/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 784 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_PRECISERR_Msk [26/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 784 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_PRECISERR_Msk [27/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 784 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_PRECISERR_Msk [28/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 784 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Msk [29/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 784 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Msk [30/30]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 785 of file core_armv81mml.h.

◆ SCB_CFSR_PRECISERR_Pos [1/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 588 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_PRECISERR_Pos [2/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 588 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_PRECISERR_Pos [3/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 588 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_PRECISERR_Pos [4/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 588 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_PRECISERR_Pos [5/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 591 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_PRECISERR_Pos [6/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 591 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_PRECISERR_Pos [7/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 591 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_PRECISERR_Pos [8/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 591 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_PRECISERR_Pos [9/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 655 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Pos [10/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 655 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Pos [11/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 655 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Pos [12/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 655 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Pos [13/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 655 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Pos [14/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 655 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_PRECISERR_Pos [15/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 708 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Pos [16/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 708 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Pos [17/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 708 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Pos [18/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 708 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Pos [19/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 708 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Pos [20/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 708 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_PRECISERR_Pos [21/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 775 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Pos [22/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 775 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_PRECISERR_Pos [23/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 775 of file core_cm35p.h.

◆ SCB_CFSR_PRECISERR_Pos [24/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 783 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Pos [25/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 783 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_PRECISERR_Pos [26/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 783 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_PRECISERR_Pos [27/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 783 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_PRECISERR_Pos [28/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 783 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Pos [29/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 783 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Pos [30/30]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 784 of file core_armv81mml.h.

◆ SCB_CFSR_STKERR_Msk [1/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 580 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_STKERR_Msk [2/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 580 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_STKERR_Msk [3/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 580 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_STKERR_Msk [4/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 580 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_STKERR_Msk [5/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 583 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_STKERR_Msk [6/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 583 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_STKERR_Msk [7/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 583 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_STKERR_Msk [8/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 583 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_STKERR_Msk [9/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 647 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Msk [10/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 647 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Msk [11/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 647 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Msk [12/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 647 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Msk [13/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 647 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Msk [14/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 647 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Msk [15/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 700 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Msk [16/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 700 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Msk [17/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 700 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Msk [18/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 700 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Msk [19/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 700 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Msk [20/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 700 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_STKERR_Msk [21/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 767 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKERR_Msk [22/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 767 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKERR_Msk [23/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 767 of file core_cm35p.h.

◆ SCB_CFSR_STKERR_Msk [24/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 775 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKERR_Msk [25/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 775 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKERR_Msk [26/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 775 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKERR_Msk [27/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 775 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKERR_Msk [28/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 775 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKERR_Msk [29/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 775 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKERR_Msk [30/30]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 776 of file core_armv81mml.h.

◆ SCB_CFSR_STKERR_Pos [1/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 579 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_STKERR_Pos [2/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 579 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_STKERR_Pos [3/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 579 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_STKERR_Pos [4/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 579 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_STKERR_Pos [5/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 582 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_STKERR_Pos [6/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 582 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_STKERR_Pos [7/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 582 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_STKERR_Pos [8/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 582 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_STKERR_Pos [9/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 646 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Pos [10/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 646 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Pos [11/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 646 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Pos [12/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 646 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Pos [13/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 646 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Pos [14/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 646 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_STKERR_Pos [15/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 699 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Pos [16/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 699 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Pos [17/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 699 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Pos [18/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 699 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Pos [19/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 699 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_STKERR_Pos [20/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 699 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_STKERR_Pos [21/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 766 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKERR_Pos [22/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 766 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKERR_Pos [23/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 766 of file core_cm35p.h.

◆ SCB_CFSR_STKERR_Pos [24/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 774 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKERR_Pos [25/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 774 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKERR_Pos [26/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 774 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKERR_Pos [27/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 774 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKERR_Pos [28/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 774 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKERR_Pos [29/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 774 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKERR_Pos [30/30]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 775 of file core_armv81mml.h.

◆ SCB_CFSR_STKOF_Msk [1/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 789 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKOF_Msk [2/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 789 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKOF_Msk [3/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 789 of file core_cm35p.h.

◆ SCB_CFSR_STKOF_Msk [4/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 797 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKOF_Msk [5/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 797 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKOF_Msk [6/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 797 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKOF_Msk [7/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 797 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKOF_Msk [8/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 797 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKOF_Msk [9/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 797 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKOF_Msk [10/10]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 798 of file core_armv81mml.h.

◆ SCB_CFSR_STKOF_Pos [1/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 788 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKOF_Pos [2/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 788 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKOF_Pos [3/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 788 of file core_cm35p.h.

◆ SCB_CFSR_STKOF_Pos [4/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 796 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKOF_Pos [5/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 796 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKOF_Pos [6/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 796 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKOF_Pos [7/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 796 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_STKOF_Pos [8/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 796 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKOF_Pos [9/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 796 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_STKOF_Pos [10/10]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 797 of file core_armv81mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [1/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 599 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Msk [2/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 599 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Msk [3/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 599 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Msk [4/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 599 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Msk [5/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 602 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Msk [6/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 602 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Msk [7/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 602 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Msk [8/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 602 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Msk [9/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 666 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Msk [10/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 666 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Msk [11/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 666 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Msk [12/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 666 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Msk [13/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 666 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Msk [14/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 666 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Msk [15/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 719 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Msk [16/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 719 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Msk [17/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 719 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Msk [18/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 719 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Msk [19/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 719 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Msk [20/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 719 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Msk [21/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 786 of file core_cm35p.h.

◆ SCB_CFSR_UNALIGNED_Msk [22/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 786 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Msk [23/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 786 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [24/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 794 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [25/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 794 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Msk [26/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 794 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Msk [27/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 794 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Msk [28/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 794 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [29/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 794 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [30/30]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 795 of file core_armv81mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [1/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 598 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Pos [2/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 598 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Pos [3/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 598 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Pos [4/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 598 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Pos [5/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 601 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Pos [6/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 601 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Pos [7/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 601 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Pos [8/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 601 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Pos [9/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 665 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Pos [10/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 665 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Pos [11/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 665 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Pos [12/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 665 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Pos [13/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 665 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Pos [14/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 665 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Pos [15/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 718 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Pos [16/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 718 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Pos [17/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 718 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Pos [18/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 718 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Pos [19/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 718 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Pos [20/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 718 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Pos [21/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 785 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [22/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 785 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Pos [23/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 785 of file core_cm35p.h.

◆ SCB_CFSR_UNALIGNED_Pos [24/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 793 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [25/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 793 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Pos [26/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 793 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Pos [27/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 793 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Pos [28/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 793 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [29/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 793 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [30/30]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 794 of file core_armv81mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [1/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 611 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [2/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 611 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [3/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 611 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [4/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 611 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [5/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 614 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [6/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 614 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [7/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 614 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [8/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 614 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [9/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 678 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [10/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 678 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [11/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 678 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [12/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 678 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [13/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 678 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [14/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 678 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [15/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 731 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [16/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 731 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [17/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 731 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [18/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 731 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [19/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 731 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [20/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 731 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [21/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 801 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [22/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 801 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [23/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 801 of file core_cm35p.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [24/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 809 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [25/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 809 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [26/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 809 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [27/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 809 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [28/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 809 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [29/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 809 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [30/30]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 810 of file core_armv81mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [1/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 610 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [2/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 610 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [3/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 610 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [4/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 610 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [5/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 613 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [6/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 613 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [7/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 613 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [8/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 613 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [9/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 677 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [10/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 677 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [11/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 677 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [12/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 677 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [13/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 677 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [14/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 677 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [15/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 730 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [16/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 730 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [17/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 730 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [18/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 730 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [19/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 730 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [20/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 730 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [21/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 800 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [22/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 800 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [23/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 800 of file core_cm35p.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [24/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 808 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [25/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 808 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [26/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 808 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [27/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 808 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [28/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 808 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [29/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 808 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [30/30]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 809 of file core_armv81mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [1/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 583 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Msk [2/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 583 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Msk [3/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 583 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Msk [4/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 583 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Msk [5/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 586 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Msk [6/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 586 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Msk [7/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 586 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Msk [8/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 586 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Msk [9/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 650 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Msk [10/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 650 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Msk [11/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 650 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Msk [12/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 650 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Msk [13/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 650 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Msk [14/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 650 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Msk [15/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 703 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Msk [16/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 703 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Msk [17/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 703 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Msk [18/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 703 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Msk [19/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 703 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Msk [20/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 703 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Msk [21/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 770 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [22/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 770 of file core_cm35p.h.

◆ SCB_CFSR_UNSTKERR_Msk [23/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 770 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Msk [24/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 778 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [25/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 778 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Msk [26/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 778 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Msk [27/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 778 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [28/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 778 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Msk [29/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 778 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [30/30]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 779 of file core_armv81mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [1/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 582 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Pos [2/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 582 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Pos [3/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 582 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Pos [4/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 582 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Pos [5/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 585 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Pos [6/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 585 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Pos [7/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 585 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Pos [8/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 585 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Pos [9/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 649 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Pos [10/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 649 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Pos [11/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 649 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Pos [12/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 649 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Pos [13/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 649 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Pos [14/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 649 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Pos [15/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 702 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Pos [16/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 702 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Pos [17/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 702 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Pos [18/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 702 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Pos [19/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 702 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Pos [20/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 702 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Pos [21/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 769 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Pos [22/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 769 of file core_cm35p.h.

◆ SCB_CFSR_UNSTKERR_Pos [23/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 769 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [24/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 777 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [25/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 777 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Pos [26/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 777 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Pos [27/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 777 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Pos [28/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 777 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [29/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 777 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [30/30]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 778 of file core_armv81mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [1/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 551 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Msk [2/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 551 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Msk [3/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 551 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Msk [4/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 551 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Msk [5/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 554 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Msk [6/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 554 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Msk [7/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 554 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Msk [8/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 554 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Msk [9/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 612 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [10/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 612 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [11/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 612 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [12/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 612 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [13/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 612 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [14/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 612 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [15/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 665 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [16/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 665 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [17/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 665 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [18/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 665 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [19/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 665 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [20/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 665 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [21/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 732 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [22/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 732 of file core_cm35p.h.

◆ SCB_CFSR_USGFAULTSR_Msk [23/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 732 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Msk [24/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 740 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [25/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 740 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Msk [26/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 740 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Msk [27/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 740 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Msk [28/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 740 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [29/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 740 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [30/30]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 741 of file core_armv81mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [1/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 550 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Pos [2/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 550 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Pos [3/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 550 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Pos [4/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 550 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Pos [5/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 553 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Pos [6/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 553 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Pos [7/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 553 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Pos [8/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 553 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Pos [9/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 611 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [10/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 611 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [11/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 611 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [12/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 611 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [13/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 611 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [14/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 611 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [15/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 664 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [16/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 664 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [17/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 664 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [18/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 664 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [19/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 664 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [20/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 664 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [21/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 731 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [22/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 731 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Pos [23/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 731 of file core_cm35p.h.

◆ SCB_CFSR_USGFAULTSR_Pos [24/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 739 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [25/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 739 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Pos [26/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 739 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Pos [27/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 739 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Pos [28/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 739 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [29/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 739 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [30/30]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 740 of file core_armv81mml.h.

◆ SCB_CLIDR_LOC_Msk [1/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 764 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Msk [2/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 764 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CLIDR_LOC_Msk [3/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 764 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Msk [4/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 764 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Msk [5/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 764 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Msk [6/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 764 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Msk [7/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 844 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOC_Msk [8/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 844 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOC_Msk [9/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 844 of file core_cm35p.h.

◆ SCB_CLIDR_LOC_Msk [10/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 852 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOC_Msk [11/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 852 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOC_Msk [12/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 852 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOC_Msk [13/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 852 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOC_Msk [14/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 852 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOC_Msk [15/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 852 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOC_Msk [16/16]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 853 of file core_armv81mml.h.

◆ SCB_CLIDR_LOC_Pos [1/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 763 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Pos [2/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 763 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CLIDR_LOC_Pos [3/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 763 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Pos [4/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 763 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Pos [5/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 763 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Pos [6/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 763 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOC_Pos [7/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 843 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOC_Pos [8/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 843 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOC_Pos [9/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 843 of file core_cm35p.h.

◆ SCB_CLIDR_LOC_Pos [10/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 851 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOC_Pos [11/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 851 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOC_Pos [12/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 851 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOC_Pos [13/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 851 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOC_Pos [14/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 851 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOC_Pos [15/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 851 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOC_Pos [16/16]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 852 of file core_armv81mml.h.

◆ SCB_CLIDR_LOUU_Msk [1/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 761 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk [2/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 761 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk [3/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 761 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk [4/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 761 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk [5/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 761 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk [6/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 761 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk [7/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 841 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Msk [8/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 841 of file core_cm35p.h.

◆ SCB_CLIDR_LOUU_Msk [9/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 841 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOUU_Msk [10/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 849 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Msk [11/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 849 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Msk [12/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 849 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOUU_Msk [13/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 849 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOUU_Msk [14/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 849 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOUU_Msk [15/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 849 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Msk [16/16]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 850 of file core_armv81mml.h.

◆ SCB_CLIDR_LOUU_Pos [1/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 760 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos [2/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 760 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos [3/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 760 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos [4/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 760 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos [5/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 760 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos [6/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 760 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos [7/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 840 of file core_cm35p.h.

◆ SCB_CLIDR_LOUU_Pos [8/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 840 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Pos [9/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 840 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOUU_Pos [10/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 848 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Pos [11/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 848 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Pos [12/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 848 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOUU_Pos [13/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 848 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOUU_Pos [14/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 848 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CLIDR_LOUU_Pos [15/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 848 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Pos [16/16]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 849 of file core_armv81mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [1/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [2/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [3/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [4/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [5/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [6/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [7/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [8/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [9/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 370 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [10/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 370 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [11/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 370 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [12/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 370 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [13/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 380 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [14/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 380 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [15/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 380 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [16/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 380 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [17/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [18/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [19/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [20/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [21/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [22/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [23/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [24/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [25/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 407 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [26/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 407 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [27/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 407 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [28/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 407 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [29/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 409 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [30/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 409 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [31/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 409 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [32/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 409 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [33/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 473 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [34/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 473 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [35/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 473 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [36/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 473 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [37/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 473 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [38/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 473 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [39/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 517 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [40/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 517 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [41/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 517 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [42/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 517 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [43/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 517 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [44/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 517 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [45/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 551 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [46/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 551 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [47/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 551 of file core_cm35p.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [48/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 559 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [49/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 559 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [50/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 559 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [51/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 559 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [52/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 559 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [53/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 559 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [54/54]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 560 of file core_armv81mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [1/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [2/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [3/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [4/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [5/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [6/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [7/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [8/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [9/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 369 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [10/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 369 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [11/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 369 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [12/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 369 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [13/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 379 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [14/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 379 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [15/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 379 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [16/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 379 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [17/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [18/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [19/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [20/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [21/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [22/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [23/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [24/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [25/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 406 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [26/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 406 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [27/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 406 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [28/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 406 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [29/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 408 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [30/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 408 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [31/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 408 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [32/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 408 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [33/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 472 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [34/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 472 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [35/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 472 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [36/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 472 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [37/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 472 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [38/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 472 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [39/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 516 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [40/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 516 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [41/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 516 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [42/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 516 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [43/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 516 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [44/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 516 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [45/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 550 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [46/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 550 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [47/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 550 of file core_cm35p.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [48/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 558 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [49/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 558 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [50/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 558 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [51/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 558 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [52/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 558 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [53/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 558 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [54/54]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 559 of file core_armv81mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [1/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [2/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [3/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [4/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [5/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [6/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [7/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [8/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [9/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 364 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [10/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 364 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [11/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 364 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [12/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 364 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [13/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 374 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [14/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 374 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [15/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 374 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [16/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 374 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [17/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [18/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [19/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [20/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [21/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [22/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [23/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [24/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [25/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 401 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [26/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 401 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [27/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 401 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [28/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 401 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [29/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 403 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [30/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 403 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [31/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 403 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [32/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 403 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [33/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 467 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [34/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 467 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [35/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 467 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [36/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 467 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [37/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 467 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [38/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 467 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [39/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 511 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [40/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 511 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [41/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 511 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [42/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 511 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [43/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 511 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [44/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 511 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [45/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 545 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [46/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 545 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [47/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 545 of file core_cm35p.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [48/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 553 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [49/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 553 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [50/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 553 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [51/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 553 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [52/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 553 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [53/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 553 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [54/54]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 554 of file core_armv81mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [1/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [2/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [3/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [4/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [5/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [6/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [7/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [8/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [9/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 363 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [10/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 363 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [11/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 363 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [12/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 363 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [13/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 373 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [14/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 373 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [15/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 373 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [16/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 373 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [17/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [18/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [19/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [20/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [21/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [22/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [23/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [24/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [25/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 400 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [26/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 400 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [27/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 400 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [28/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 400 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [29/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 402 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [30/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 402 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [31/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 402 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [32/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 402 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [33/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 466 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [34/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 466 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [35/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 466 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [36/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 466 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [37/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 466 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [38/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 466 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [39/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 510 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [40/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 510 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [41/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 510 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [42/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 510 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [43/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 510 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [44/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 510 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [45/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 544 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [46/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 544 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [47/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 544 of file core_cm35p.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [48/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 552 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [49/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 552 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [50/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 552 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [51/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 552 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [52/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 552 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [53/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 552 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [54/54]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 553 of file core_armv81mml.h.

◆ SCB_CPUID_PARTNO_Msk [1/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_PARTNO_Msk [2/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_PARTNO_Msk [3/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_PARTNO_Msk [4/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_PARTNO_Msk [5/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_PARTNO_Msk [6/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_PARTNO_Msk [7/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_PARTNO_Msk [8/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_PARTNO_Msk [9/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 373 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_PARTNO_Msk [10/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 373 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_PARTNO_Msk [11/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 373 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_PARTNO_Msk [12/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 373 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_PARTNO_Msk [13/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 383 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Msk [14/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 383 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Msk [15/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 383 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Msk [16/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 383 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Msk [17/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Msk [18/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_PARTNO_Msk [19/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Msk [20/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_PARTNO_Msk [21/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_PARTNO_Msk [22/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_PARTNO_Msk [23/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Msk [24/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Msk [25/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 410 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_PARTNO_Msk [26/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 410 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_PARTNO_Msk [27/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 410 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_PARTNO_Msk [28/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 410 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_PARTNO_Msk [29/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 412 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_PARTNO_Msk [30/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 412 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_PARTNO_Msk [31/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 412 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_PARTNO_Msk [32/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 412 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_PARTNO_Msk [33/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 476 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Msk [34/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 476 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Msk [35/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 476 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Msk [36/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 476 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Msk [37/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 476 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Msk [38/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 476 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Msk [39/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 520 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_PARTNO_Msk [40/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 520 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Msk [41/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 520 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Msk [42/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 520 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Msk [43/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 520 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Msk [44/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 520 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Msk [45/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 554 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Msk [46/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 554 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_PARTNO_Msk [47/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 554 of file core_cm35p.h.

◆ SCB_CPUID_PARTNO_Msk [48/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 562 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_PARTNO_Msk [49/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 562 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_PARTNO_Msk [50/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 562 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Msk [51/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 562 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Msk [52/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 562 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Msk [53/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 562 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_PARTNO_Msk [54/54]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 563 of file core_armv81mml.h.

◆ SCB_CPUID_PARTNO_Pos [1/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_PARTNO_Pos [2/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_PARTNO_Pos [3/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_PARTNO_Pos [4/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_PARTNO_Pos [5/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_PARTNO_Pos [6/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_PARTNO_Pos [7/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_PARTNO_Pos [8/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_PARTNO_Pos [9/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 372 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_PARTNO_Pos [10/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 372 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_PARTNO_Pos [11/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 372 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_PARTNO_Pos [12/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 372 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_PARTNO_Pos [13/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 382 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Pos [14/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 382 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Pos [15/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 382 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Pos [16/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 382 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Pos [17/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 408 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_PARTNO_Pos [18/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 408 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_PARTNO_Pos [19/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 408 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Pos [20/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 408 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_PARTNO_Pos [21/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 408 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_PARTNO_Pos [22/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 408 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Pos [23/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 408 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Pos [24/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 408 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Pos [25/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 409 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_PARTNO_Pos [26/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 409 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_PARTNO_Pos [27/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 409 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_PARTNO_Pos [28/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 409 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_PARTNO_Pos [29/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 411 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_PARTNO_Pos [30/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 411 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_PARTNO_Pos [31/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 411 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_PARTNO_Pos [32/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 411 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_PARTNO_Pos [33/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 475 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Pos [34/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 475 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Pos [35/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 475 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Pos [36/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 475 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Pos [37/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 475 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Pos [38/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 475 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_PARTNO_Pos [39/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 519 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Pos [40/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 519 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Pos [41/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 519 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Pos [42/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 519 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Pos [43/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 519 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_PARTNO_Pos [44/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 519 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_PARTNO_Pos [45/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 553 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Pos [46/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 553 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_PARTNO_Pos [47/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 553 of file core_cm35p.h.

◆ SCB_CPUID_PARTNO_Pos [48/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 561 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_PARTNO_Pos [49/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 561 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_PARTNO_Pos [50/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 561 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Pos [51/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 561 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Pos [52/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 561 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Pos [53/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 561 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_PARTNO_Pos [54/54]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 562 of file core_armv81mml.h.

◆ SCB_CPUID_REVISION_Msk [1/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_REVISION_Msk [2/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_REVISION_Msk [3/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_REVISION_Msk [4/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_REVISION_Msk [5/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_REVISION_Msk [6/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_REVISION_Msk [7/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_REVISION_Msk [8/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_REVISION_Msk [9/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 376 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_REVISION_Msk [10/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 376 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_REVISION_Msk [11/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 376 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_REVISION_Msk [12/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 376 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_REVISION_Msk [13/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 386 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_REVISION_Msk [14/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 386 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_REVISION_Msk [15/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 386 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_REVISION_Msk [16/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 386 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_REVISION_Msk [17/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Msk [18/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_REVISION_Msk [19/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_REVISION_Msk [20/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Msk [21/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_REVISION_Msk [22/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_REVISION_Msk [23/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Msk [24/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Msk [25/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 413 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_REVISION_Msk [26/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 413 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_REVISION_Msk [27/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 413 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_REVISION_Msk [28/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 413 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_REVISION_Msk [29/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 415 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_REVISION_Msk [30/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 415 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_REVISION_Msk [31/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 415 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_REVISION_Msk [32/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 415 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_REVISION_Msk [33/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 479 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Msk [34/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 479 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Msk [35/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 479 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Msk [36/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 479 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Msk [37/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 479 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Msk [38/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 479 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Msk [39/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 523 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Msk [40/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 523 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_REVISION_Msk [41/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 523 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Msk [42/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 523 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Msk [43/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 523 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Msk [44/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 523 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Msk [45/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 557 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_REVISION_Msk [46/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 557 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_REVISION_Msk [47/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 557 of file core_cm35p.h.

◆ SCB_CPUID_REVISION_Msk [48/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 565 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_REVISION_Msk [49/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 565 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_REVISION_Msk [50/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 565 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_REVISION_Msk [51/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 565 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_REVISION_Msk [52/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 565 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_REVISION_Msk [53/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 565 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_REVISION_Msk [54/54]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 566 of file core_armv81mml.h.

◆ SCB_CPUID_REVISION_Pos [1/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_REVISION_Pos [2/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_REVISION_Pos [3/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_REVISION_Pos [4/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_REVISION_Pos [5/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_REVISION_Pos [6/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_REVISION_Pos [7/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_REVISION_Pos [8/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_REVISION_Pos [9/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 375 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_REVISION_Pos [10/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 375 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_REVISION_Pos [11/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 375 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_REVISION_Pos [12/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 375 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_REVISION_Pos [13/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 385 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_REVISION_Pos [14/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 385 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_REVISION_Pos [15/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 385 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_REVISION_Pos [16/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 385 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_REVISION_Pos [17/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 411 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Pos [18/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 411 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_REVISION_Pos [19/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 411 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_REVISION_Pos [20/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 411 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Pos [21/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 411 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_REVISION_Pos [22/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 411 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_REVISION_Pos [23/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 411 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Pos [24/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 411 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Pos [25/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 412 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_REVISION_Pos [26/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 412 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_REVISION_Pos [27/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 412 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_REVISION_Pos [28/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 412 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_REVISION_Pos [29/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 414 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_REVISION_Pos [30/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 414 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_REVISION_Pos [31/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 414 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_REVISION_Pos [32/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 414 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_REVISION_Pos [33/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 478 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Pos [34/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 478 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Pos [35/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 478 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Pos [36/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 478 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Pos [37/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 478 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Pos [38/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 478 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_REVISION_Pos [39/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 522 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Pos [40/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 522 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_REVISION_Pos [41/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 522 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Pos [42/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 522 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Pos [43/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 522 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Pos [44/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 522 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_REVISION_Pos [45/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 556 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_REVISION_Pos [46/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 556 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_REVISION_Pos [47/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 556 of file core_cm35p.h.

◆ SCB_CPUID_REVISION_Pos [48/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 564 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_REVISION_Pos [49/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 564 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_REVISION_Pos [50/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 564 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_REVISION_Pos [51/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 564 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_REVISION_Pos [52/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 564 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_REVISION_Pos [53/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 564 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_REVISION_Pos [54/54]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 565 of file core_armv81mml.h.

◆ SCB_CPUID_VARIANT_Msk [1/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_VARIANT_Msk [2/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_VARIANT_Msk [3/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_VARIANT_Msk [4/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_VARIANT_Msk [5/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_VARIANT_Msk [6/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_VARIANT_Msk [7/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_VARIANT_Msk [8/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_VARIANT_Msk [9/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 367 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_VARIANT_Msk [10/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 367 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_VARIANT_Msk [11/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 367 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_VARIANT_Msk [12/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 367 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_VARIANT_Msk [13/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 377 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Msk [14/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 377 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Msk [15/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 377 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Msk [16/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 377 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Msk [17/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_VARIANT_Msk [18/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Msk [19/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_VARIANT_Msk [20/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_VARIANT_Msk [21/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_VARIANT_Msk [22/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Msk [23/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Msk [24/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Msk [25/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 404 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_VARIANT_Msk [26/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 404 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_VARIANT_Msk [27/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 404 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_VARIANT_Msk [28/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 404 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_VARIANT_Msk [29/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 406 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_VARIANT_Msk [30/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 406 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_VARIANT_Msk [31/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 406 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_VARIANT_Msk [32/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 406 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_VARIANT_Msk [33/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 470 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Msk [34/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 470 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Msk [35/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 470 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Msk [36/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 470 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Msk [37/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 470 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Msk [38/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 470 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Msk [39/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 514 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_VARIANT_Msk [40/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 514 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Msk [41/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 514 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Msk [42/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 514 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Msk [43/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 514 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Msk [44/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 514 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Msk [45/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 548 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Msk [46/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 548 of file core_cm35p.h.

◆ SCB_CPUID_VARIANT_Msk [47/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 548 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_VARIANT_Msk [48/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 556 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_VARIANT_Msk [49/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 556 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_VARIANT_Msk [50/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 556 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Msk [51/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 556 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Msk [52/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 556 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Msk [53/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 556 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_VARIANT_Msk [54/54]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 557 of file core_armv81mml.h.

◆ SCB_CPUID_VARIANT_Pos [1/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_VARIANT_Pos [2/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_VARIANT_Pos [3/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_VARIANT_Pos [4/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_VARIANT_Pos [5/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_VARIANT_Pos [6/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_VARIANT_Pos [7/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_CPUID_VARIANT_Pos [8/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_CPUID_VARIANT_Pos [9/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 366 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_VARIANT_Pos [10/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 366 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_VARIANT_Pos [11/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 366 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_VARIANT_Pos [12/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 366 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_CPUID_VARIANT_Pos [13/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 376 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Pos [14/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 376 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Pos [15/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 376 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Pos [16/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 376 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Pos [17/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 402 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_VARIANT_Pos [18/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 402 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_VARIANT_Pos [19/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 402 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_VARIANT_Pos [20/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 402 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_CPUID_VARIANT_Pos [21/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 402 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Pos [22/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 402 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Pos [23/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 402 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Pos [24/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 402 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Pos [25/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 403 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_VARIANT_Pos [26/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 403 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_VARIANT_Pos [27/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 403 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_VARIANT_Pos [28/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 403 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_CPUID_VARIANT_Pos [29/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 405 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_VARIANT_Pos [30/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 405 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_VARIANT_Pos [31/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 405 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_VARIANT_Pos [32/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 405 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_CPUID_VARIANT_Pos [33/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 469 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Pos [34/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 469 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Pos [35/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 469 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Pos [36/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 469 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Pos [37/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 469 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Pos [38/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 469 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_CPUID_VARIANT_Pos [39/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 513 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Pos [40/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 513 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Pos [41/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 513 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Pos [42/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 513 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Pos [43/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 513 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CPUID_VARIANT_Pos [44/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 513 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CPUID_VARIANT_Pos [45/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 547 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_VARIANT_Pos [46/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 547 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Pos [47/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 547 of file core_cm35p.h.

◆ SCB_CPUID_VARIANT_Pos [48/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 555 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_VARIANT_Pos [49/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 555 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Pos [50/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 555 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_VARIANT_Pos [51/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 555 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Pos [52/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 555 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Pos [53/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 555 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CPUID_VARIANT_Pos [54/54]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 556 of file core_armv81mml.h.

◆ SCB_CSSELR_IND_Msk [1/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 809 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Msk [2/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 809 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Msk [3/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 809 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Msk [4/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 809 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Msk [5/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 809 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CSSELR_IND_Msk [6/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 809 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Msk [7/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 889 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_IND_Msk [8/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 889 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_IND_Msk [9/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 889 of file core_cm35p.h.

◆ SCB_CSSELR_IND_Msk [10/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 897 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_IND_Msk [11/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 897 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_IND_Msk [12/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 897 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_IND_Msk [13/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 897 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_IND_Msk [14/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 897 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_IND_Msk [15/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 897 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_IND_Msk [16/16]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 898 of file core_armv81mml.h.

◆ SCB_CSSELR_IND_Pos [1/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 808 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Pos [2/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 808 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CSSELR_IND_Pos [3/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 808 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Pos [4/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 808 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Pos [5/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 808 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Pos [6/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 808 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_IND_Pos [7/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 888 of file core_cm35p.h.

◆ SCB_CSSELR_IND_Pos [8/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 888 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_IND_Pos [9/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 888 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_IND_Pos [10/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 896 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_IND_Pos [11/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 896 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_IND_Pos [12/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 896 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_IND_Pos [13/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 896 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_IND_Pos [14/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 896 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_IND_Pos [15/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 896 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_IND_Pos [16/16]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 897 of file core_armv81mml.h.

◆ SCB_CSSELR_LEVEL_Msk [1/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 806 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Msk [2/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 806 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Msk [3/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 806 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Msk [4/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 806 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Msk [5/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 806 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Msk [6/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 806 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Msk [7/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 886 of file core_cm35p.h.

◆ SCB_CSSELR_LEVEL_Msk [8/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 886 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Msk [9/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 886 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_LEVEL_Msk [10/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 894 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Msk [11/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 894 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Msk [12/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 894 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_LEVEL_Msk [13/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 894 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_LEVEL_Msk [14/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 894 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_LEVEL_Msk [15/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 894 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Msk [16/16]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 895 of file core_armv81mml.h.

◆ SCB_CSSELR_LEVEL_Pos [1/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 805 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Pos [2/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 805 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Pos [3/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 805 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Pos [4/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 805 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Pos [5/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 805 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Pos [6/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 805 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CSSELR_LEVEL_Pos [7/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 885 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_LEVEL_Pos [8/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 885 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Pos [9/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 885 of file core_cm35p.h.

◆ SCB_CSSELR_LEVEL_Pos [10/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 893 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Pos [11/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 893 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Pos [12/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 893 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_LEVEL_Pos [13/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 893 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_LEVEL_Pos [14/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 893 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CSSELR_LEVEL_Pos [15/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 893 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Pos [16/16]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 894 of file core_armv81mml.h.

◆ SCB_CTR_CWG_Msk [1/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 771 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Msk [2/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 771 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_CWG_Msk [3/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 771 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Msk [4/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 771 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Msk [5/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 771 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Msk [6/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 771 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Msk [7/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 851 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_CWG_Msk [8/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 851 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_CWG_Msk [9/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 851 of file core_cm35p.h.

◆ SCB_CTR_CWG_Msk [10/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 859 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_CWG_Msk [11/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 859 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_CWG_Msk [12/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 859 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_CWG_Msk [13/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 859 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_CWG_Msk [14/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 859 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_CWG_Msk [15/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 859 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_CWG_Msk [16/16]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 860 of file core_armv81mml.h.

◆ SCB_CTR_CWG_Pos [1/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 770 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Pos [2/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 770 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_CWG_Pos [3/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 770 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Pos [4/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 770 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Pos [5/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 770 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Pos [6/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 770 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_CWG_Pos [7/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 850 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_CWG_Pos [8/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 850 of file core_cm35p.h.

◆ SCB_CTR_CWG_Pos [9/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 850 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_CWG_Pos [10/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 858 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_CWG_Pos [11/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 858 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_CWG_Pos [12/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 858 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_CWG_Pos [13/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 858 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_CWG_Pos [14/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 858 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_CWG_Pos [15/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 858 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_CWG_Pos [16/16]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 859 of file core_armv81mml.h.

◆ SCB_CTR_DMINLINE_Msk [1/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 777 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Msk [2/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 777 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_DMINLINE_Msk [3/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 777 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Msk [4/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 777 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Msk [5/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 777 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Msk [6/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 777 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Msk [7/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 857 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Msk [8/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 857 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_DMINLINE_Msk [9/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 857 of file core_cm35p.h.

◆ SCB_CTR_DMINLINE_Msk [10/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 865 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Msk [11/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 865 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Msk [12/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 865 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_DMINLINE_Msk [13/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 865 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_DMINLINE_Msk [14/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 865 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_DMINLINE_Msk [15/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 865 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Msk [16/16]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 866 of file core_armv81mml.h.

◆ SCB_CTR_DMINLINE_Pos [1/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 776 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Pos [2/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 776 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_DMINLINE_Pos [3/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 776 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Pos [4/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 776 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Pos [5/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 776 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Pos [6/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 776 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_DMINLINE_Pos [7/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 856 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Pos [8/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 856 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_DMINLINE_Pos [9/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 856 of file core_cm35p.h.

◆ SCB_CTR_DMINLINE_Pos [10/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 864 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Pos [11/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 864 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Pos [12/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 864 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_DMINLINE_Pos [13/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 864 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_DMINLINE_Pos [14/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 864 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_DMINLINE_Pos [15/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 864 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Pos [16/16]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 865 of file core_armv81mml.h.

◆ SCB_CTR_ERG_Msk [1/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 774 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Msk [2/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 774 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Msk [3/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 774 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_ERG_Msk [4/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 774 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Msk [5/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 774 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Msk [6/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 774 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Msk [7/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 854 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_ERG_Msk [8/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 854 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_ERG_Msk [9/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 854 of file core_cm35p.h.

◆ SCB_CTR_ERG_Msk [10/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 862 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_ERG_Msk [11/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 862 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_ERG_Msk [12/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 862 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_ERG_Msk [13/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 862 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_ERG_Msk [14/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 862 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_ERG_Msk [15/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 862 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_ERG_Msk [16/16]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 863 of file core_armv81mml.h.

◆ SCB_CTR_ERG_Pos [1/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 773 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Pos [2/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 773 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Pos [3/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 773 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_ERG_Pos [4/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 773 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Pos [5/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 773 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Pos [6/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 773 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_ERG_Pos [7/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 853 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_ERG_Pos [8/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 853 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_ERG_Pos [9/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 853 of file core_cm35p.h.

◆ SCB_CTR_ERG_Pos [10/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 861 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_ERG_Pos [11/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 861 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_ERG_Pos [12/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 861 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_ERG_Pos [13/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 861 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_ERG_Pos [14/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 861 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_ERG_Pos [15/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 861 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_ERG_Pos [16/16]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 862 of file core_armv81mml.h.

◆ SCB_CTR_FORMAT_Msk [1/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 768 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Msk [2/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 768 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Msk [3/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 768 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Msk [4/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 768 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_FORMAT_Msk [5/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 768 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Msk [6/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 768 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Msk [7/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 848 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_FORMAT_Msk [8/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 848 of file core_cm35p.h.

◆ SCB_CTR_FORMAT_Msk [9/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 848 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_FORMAT_Msk [10/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 856 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_FORMAT_Msk [11/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 856 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_FORMAT_Msk [12/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 856 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_FORMAT_Msk [13/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 856 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_FORMAT_Msk [14/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 856 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_FORMAT_Msk [15/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 856 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_FORMAT_Msk [16/16]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 857 of file core_armv81mml.h.

◆ SCB_CTR_FORMAT_Pos [1/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 767 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Pos [2/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 767 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Pos [3/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 767 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_FORMAT_Pos [4/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 767 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Pos [5/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 767 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Pos [6/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 767 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_FORMAT_Pos [7/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 847 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_FORMAT_Pos [8/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 847 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_FORMAT_Pos [9/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 847 of file core_cm35p.h.

◆ SCB_CTR_FORMAT_Pos [10/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 855 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_FORMAT_Pos [11/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 855 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_FORMAT_Pos [12/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 855 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_FORMAT_Pos [13/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 855 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_FORMAT_Pos [14/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 855 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_FORMAT_Pos [15/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 855 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_FORMAT_Pos [16/16]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 856 of file core_armv81mml.h.

◆ SCB_CTR_IMINLINE_Msk [1/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 780 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Msk [2/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 780 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Msk [3/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 780 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Msk [4/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 780 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Msk [5/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 780 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_IMINLINE_Msk [6/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 780 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Msk [7/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 860 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_IMINLINE_Msk [8/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 860 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Msk [9/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 860 of file core_cm35p.h.

◆ SCB_CTR_IMINLINE_Msk [10/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 868 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Msk [11/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 868 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Msk [12/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 868 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_IMINLINE_Msk [13/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 868 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_IMINLINE_Msk [14/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 868 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_IMINLINE_Msk [15/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 868 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Msk [16/16]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 869 of file core_armv81mml.h.

◆ SCB_CTR_IMINLINE_Pos [1/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 779 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Pos [2/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 779 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Pos [3/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 779 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Pos [4/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 779 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_CTR_IMINLINE_Pos [5/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 779 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Pos [6/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 779 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_CTR_IMINLINE_Pos [7/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 859 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Pos [8/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 859 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_IMINLINE_Pos [9/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 859 of file core_cm35p.h.

◆ SCB_CTR_IMINLINE_Pos [10/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 867 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Pos [11/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 867 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Pos [12/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 867 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_IMINLINE_Pos [13/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 867 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_IMINLINE_Pos [14/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 867 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_CTR_IMINLINE_Pos [15/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 867 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Pos [16/16]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 868 of file core_armv81mml.h.

◆ SCB_DCCISW_SET_Msk [1/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 834 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Msk [2/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 834 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCCISW_SET_Msk [3/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 834 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Msk [4/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 834 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Msk [5/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 834 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Msk [6/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 834 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Msk [7/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 914 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_SET_Msk [8/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 914 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_SET_Msk [9/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 914 of file core_cm35p.h.

◆ SCB_DCCISW_SET_Msk [10/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 922 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_SET_Msk [11/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 922 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_SET_Msk [12/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 922 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_SET_Msk [13/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 922 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_SET_Msk [14/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 922 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_SET_Msk [15/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 922 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_SET_Msk [16/16]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 923 of file core_armv81mml.h.

◆ SCB_DCCISW_SET_Pos [1/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 833 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Pos [2/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 833 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCCISW_SET_Pos [3/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 833 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Pos [4/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 833 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Pos [5/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 833 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Pos [6/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 833 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_SET_Pos [7/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 913 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_SET_Pos [8/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 913 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_SET_Pos [9/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 913 of file core_cm35p.h.

◆ SCB_DCCISW_SET_Pos [10/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 921 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_SET_Pos [11/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 921 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_SET_Pos [12/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 921 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_SET_Pos [13/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 921 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_SET_Pos [14/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 921 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_SET_Pos [15/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 921 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_SET_Pos [16/16]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 922 of file core_armv81mml.h.

◆ SCB_DCCISW_WAY_Msk [1/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 831 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Msk [2/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 831 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Msk [3/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 831 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Msk [4/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 831 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Msk [5/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 831 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCCISW_WAY_Msk [6/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 831 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Msk [7/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 911 of file core_cm35p.h.

◆ SCB_DCCISW_WAY_Msk [8/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 911 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_WAY_Msk [9/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 911 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_WAY_Msk [10/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 919 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_WAY_Msk [11/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 919 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_WAY_Msk [12/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 919 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_WAY_Msk [13/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 919 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_WAY_Msk [14/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 919 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_WAY_Msk [15/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 919 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_WAY_Msk [16/16]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 920 of file core_armv81mml.h.

◆ SCB_DCCISW_WAY_Pos [1/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 830 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Pos [2/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 830 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Pos [3/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 830 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Pos [4/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 830 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Pos [5/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 830 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCCISW_WAY_Pos [6/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 830 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCISW_WAY_Pos [7/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 910 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_WAY_Pos [8/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 910 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_WAY_Pos [9/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 910 of file core_cm35p.h.

◆ SCB_DCCISW_WAY_Pos [10/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 918 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_WAY_Pos [11/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 918 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_WAY_Pos [12/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 918 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_WAY_Pos [13/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 918 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_WAY_Pos [14/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 918 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCISW_WAY_Pos [15/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 918 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCISW_WAY_Pos [16/16]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 919 of file core_armv81mml.h.

◆ SCB_DCCSW_SET_Msk [1/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 827 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Msk [2/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 827 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Msk [3/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 827 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Msk [4/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 827 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCCSW_SET_Msk [5/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 827 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Msk [6/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 827 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Msk [7/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 907 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_SET_Msk [8/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 907 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_SET_Msk [9/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 907 of file core_cm35p.h.

◆ SCB_DCCSW_SET_Msk [10/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 915 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_SET_Msk [11/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 915 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_SET_Msk [12/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 915 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_SET_Msk [13/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 915 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_SET_Msk [14/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 915 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_SET_Msk [15/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 915 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_SET_Msk [16/16]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 916 of file core_armv81mml.h.

◆ SCB_DCCSW_SET_Pos [1/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 826 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Pos [2/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 826 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCCSW_SET_Pos [3/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 826 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Pos [4/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 826 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Pos [5/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 826 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Pos [6/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 826 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_SET_Pos [7/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 906 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_SET_Pos [8/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 906 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_SET_Pos [9/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 906 of file core_cm35p.h.

◆ SCB_DCCSW_SET_Pos [10/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 914 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_SET_Pos [11/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 914 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_SET_Pos [12/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 914 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_SET_Pos [13/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 914 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_SET_Pos [14/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 914 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_SET_Pos [15/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 914 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_SET_Pos [16/16]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 915 of file core_armv81mml.h.

◆ SCB_DCCSW_WAY_Msk [1/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 824 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Msk [2/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 824 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Msk [3/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 824 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Msk [4/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 824 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Msk [5/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 824 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCCSW_WAY_Msk [6/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 824 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Msk [7/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 904 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_WAY_Msk [8/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 904 of file core_cm35p.h.

◆ SCB_DCCSW_WAY_Msk [9/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 904 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_WAY_Msk [10/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 912 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_WAY_Msk [11/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 912 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_WAY_Msk [12/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 912 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_WAY_Msk [13/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 912 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_WAY_Msk [14/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 912 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_WAY_Msk [15/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 912 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_WAY_Msk [16/16]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 913 of file core_armv81mml.h.

◆ SCB_DCCSW_WAY_Pos [1/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 823 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Pos [2/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 823 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Pos [3/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 823 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCCSW_WAY_Pos [4/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 823 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Pos [5/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 823 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Pos [6/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 823 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCCSW_WAY_Pos [7/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 903 of file core_cm35p.h.

◆ SCB_DCCSW_WAY_Pos [8/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 903 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_WAY_Pos [9/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 903 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_WAY_Pos [10/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 911 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_WAY_Pos [11/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 911 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_WAY_Pos [12/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 911 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_WAY_Pos [13/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 911 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_WAY_Pos [14/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 911 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCCSW_WAY_Pos [15/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 911 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCCSW_WAY_Pos [16/16]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 912 of file core_armv81mml.h.

◆ SCB_DCISW_SET_Msk [1/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 820 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Msk [2/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 820 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Msk [3/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 820 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Msk [4/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 820 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCISW_SET_Msk [5/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 820 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Msk [6/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 820 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Msk [7/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 900 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_SET_Msk [8/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 900 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_SET_Msk [9/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 900 of file core_cm35p.h.

◆ SCB_DCISW_SET_Msk [10/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 908 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_SET_Msk [11/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 908 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_SET_Msk [12/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 908 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_SET_Msk [13/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 908 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_SET_Msk [14/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 908 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_SET_Msk [15/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 908 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_SET_Msk [16/16]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 909 of file core_armv81mml.h.

◆ SCB_DCISW_SET_Pos [1/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 819 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Pos [2/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 819 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Pos [3/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 819 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Pos [4/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 819 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCISW_SET_Pos [5/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 819 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Pos [6/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 819 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_SET_Pos [7/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 899 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_SET_Pos [8/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 899 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_SET_Pos [9/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 899 of file core_cm35p.h.

◆ SCB_DCISW_SET_Pos [10/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 907 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_SET_Pos [11/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 907 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_SET_Pos [12/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 907 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_SET_Pos [13/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 907 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_SET_Pos [14/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 907 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_SET_Pos [15/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 907 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_SET_Pos [16/16]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 908 of file core_armv81mml.h.

◆ SCB_DCISW_WAY_Msk [1/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 817 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Msk [2/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 817 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Msk [3/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 817 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Msk [4/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 817 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Msk [5/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 817 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCISW_WAY_Msk [6/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 817 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Msk [7/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 897 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_WAY_Msk [8/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 897 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_WAY_Msk [9/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 897 of file core_cm35p.h.

◆ SCB_DCISW_WAY_Msk [10/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 905 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_WAY_Msk [11/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 905 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_WAY_Msk [12/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 905 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_WAY_Msk [13/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 905 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_WAY_Msk [14/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 905 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_WAY_Msk [15/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 905 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_WAY_Msk [16/16]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 906 of file core_armv81mml.h.

◆ SCB_DCISW_WAY_Pos [1/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 816 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Pos [2/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 816 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Pos [3/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 816 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DCISW_WAY_Pos [4/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 816 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Pos [5/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 816 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Pos [6/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 816 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DCISW_WAY_Pos [7/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 896 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_WAY_Pos [8/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 896 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_WAY_Pos [9/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 896 of file core_cm35p.h.

◆ SCB_DCISW_WAY_Pos [10/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 904 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_WAY_Pos [11/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 904 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_WAY_Pos [12/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 904 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DCISW_WAY_Pos [13/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 904 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_WAY_Pos [14/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 904 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_WAY_Pos [15/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 904 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DCISW_WAY_Pos [16/16]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 905 of file core_armv81mml.h.

◆ SCB_DFSR_BKPT_Msk [1/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 634 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_BKPT_Msk [2/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 634 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_BKPT_Msk [3/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 634 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_BKPT_Msk [4/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 634 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_BKPT_Msk [5/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 637 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_BKPT_Msk [6/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 637 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_BKPT_Msk [7/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 637 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_BKPT_Msk [8/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 637 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_BKPT_Msk [9/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 701 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Msk [10/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 701 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Msk [11/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 701 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Msk [12/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 701 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Msk [13/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 701 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Msk [14/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 701 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Msk [15/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 754 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [16/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 754 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [17/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 754 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [18/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 754 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [19/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 754 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [20/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 754 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [21/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 824 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_BKPT_Msk [22/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 824 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_BKPT_Msk [23/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 824 of file core_cm35p.h.

◆ SCB_DFSR_BKPT_Msk [24/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 832 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_BKPT_Msk [25/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 832 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_BKPT_Msk [26/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 832 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_BKPT_Msk [27/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 832 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_BKPT_Msk [28/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 832 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_BKPT_Msk [29/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 832 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_BKPT_Msk [30/30]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 833 of file core_armv81mml.h.

◆ SCB_DFSR_BKPT_Pos [1/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 633 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_BKPT_Pos [2/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 633 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_BKPT_Pos [3/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 633 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_BKPT_Pos [4/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 633 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_BKPT_Pos [5/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 636 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_BKPT_Pos [6/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 636 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_BKPT_Pos [7/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 636 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_BKPT_Pos [8/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 636 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_BKPT_Pos [9/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 700 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Pos [10/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 700 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Pos [11/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 700 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Pos [12/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 700 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Pos [13/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 700 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Pos [14/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 700 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_BKPT_Pos [15/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 753 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_BKPT_Pos [16/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 753 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Pos [17/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 753 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Pos [18/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 753 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Pos [19/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 753 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Pos [20/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 753 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_BKPT_Pos [21/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 823 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_BKPT_Pos [22/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 823 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_BKPT_Pos [23/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 823 of file core_cm35p.h.

◆ SCB_DFSR_BKPT_Pos [24/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 831 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_BKPT_Pos [25/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 831 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_BKPT_Pos [26/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 831 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_BKPT_Pos [27/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 831 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_BKPT_Pos [28/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 831 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_BKPT_Pos [29/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 831 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_BKPT_Pos [30/30]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 832 of file core_armv81mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [1/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 631 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Msk [2/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 631 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Msk [3/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 631 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Msk [4/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 631 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Msk [5/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 634 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Msk [6/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 634 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Msk [7/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 634 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Msk [8/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 634 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Msk [9/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 698 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Msk [10/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 698 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Msk [11/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 698 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Msk [12/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 698 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Msk [13/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 698 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Msk [14/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 698 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Msk [15/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 751 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Msk [16/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 751 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Msk [17/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 751 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Msk [18/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 751 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Msk [19/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 751 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Msk [20/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 751 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Msk [21/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 821 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [22/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 821 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Msk [23/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 821 of file core_cm35p.h.

◆ SCB_DFSR_DWTTRAP_Msk [24/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 829 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [25/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 829 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [26/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 829 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Msk [27/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 829 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Msk [28/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 829 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Msk [29/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 829 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [30/30]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 830 of file core_armv81mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [1/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 630 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Pos [2/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 630 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Pos [3/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 630 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Pos [4/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 630 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Pos [5/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 633 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Pos [6/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 633 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Pos [7/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 633 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Pos [8/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 633 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Pos [9/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 697 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Pos [10/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 697 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Pos [11/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 697 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Pos [12/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 697 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Pos [13/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 697 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Pos [14/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 697 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Pos [15/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 750 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Pos [16/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 750 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Pos [17/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 750 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Pos [18/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 750 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Pos [19/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 750 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Pos [20/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 750 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Pos [21/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 820 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [22/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 820 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Pos [23/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 820 of file core_cm35p.h.

◆ SCB_DFSR_DWTTRAP_Pos [24/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 828 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [25/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 828 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [26/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 828 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Pos [27/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 828 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Pos [28/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 828 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [29/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 828 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Pos [30/30]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 829 of file core_armv81mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [1/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 625 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Msk [2/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 625 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Msk [3/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 625 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Msk [4/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 625 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Msk [5/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 628 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Msk [6/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 628 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Msk [7/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 628 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Msk [8/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 628 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Msk [9/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 692 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Msk [10/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 692 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Msk [11/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 692 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Msk [12/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 692 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Msk [13/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 692 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Msk [14/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 692 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Msk [15/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 745 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Msk [16/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 745 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Msk [17/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 745 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Msk [18/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 745 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Msk [19/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 745 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Msk [20/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 745 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Msk [21/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 815 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [22/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 815 of file core_cm35p.h.

◆ SCB_DFSR_EXTERNAL_Msk [23/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 815 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Msk [24/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 823 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [25/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 823 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [26/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 823 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Msk [27/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 823 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Msk [28/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 823 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Msk [29/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 823 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [30/30]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 824 of file core_armv81mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [1/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 624 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Pos [2/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 624 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Pos [3/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 624 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Pos [4/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 624 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Pos [5/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 627 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Pos [6/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 627 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Pos [7/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 627 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Pos [8/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 627 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Pos [9/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 691 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Pos [10/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 691 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Pos [11/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 691 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Pos [12/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 691 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Pos [13/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 691 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Pos [14/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 691 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Pos [15/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 744 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Pos [16/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 744 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Pos [17/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 744 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Pos [18/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 744 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Pos [19/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 744 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Pos [20/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 744 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Pos [21/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 814 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [22/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 814 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Pos [23/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 814 of file core_cm35p.h.

◆ SCB_DFSR_EXTERNAL_Pos [24/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 822 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [25/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 822 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Pos [26/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 822 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Pos [27/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 822 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Pos [28/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 822 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [29/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 822 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [30/30]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 823 of file core_armv81mml.h.

◆ SCB_DFSR_HALTED_Msk [1/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 637 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_HALTED_Msk [2/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 637 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_HALTED_Msk [3/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 637 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_HALTED_Msk [4/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 637 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_HALTED_Msk [5/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 640 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_HALTED_Msk [6/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 640 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_HALTED_Msk [7/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 640 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_HALTED_Msk [8/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 640 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_HALTED_Msk [9/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 704 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Msk [10/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 704 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Msk [11/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 704 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Msk [12/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 704 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Msk [13/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 704 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Msk [14/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 704 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Msk [15/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 757 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Msk [16/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 757 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Msk [17/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 757 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_HALTED_Msk [18/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 757 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Msk [19/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 757 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Msk [20/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 757 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Msk [21/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 827 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_HALTED_Msk [22/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 827 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_HALTED_Msk [23/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 827 of file core_cm35p.h.

◆ SCB_DFSR_HALTED_Msk [24/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 835 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_HALTED_Msk [25/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 835 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_HALTED_Msk [26/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 835 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_HALTED_Msk [27/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 835 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_HALTED_Msk [28/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 835 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_HALTED_Msk [29/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 835 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_HALTED_Msk [30/30]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 836 of file core_armv81mml.h.

◆ SCB_DFSR_HALTED_Pos [1/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 636 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_HALTED_Pos [2/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 636 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_HALTED_Pos [3/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 636 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_HALTED_Pos [4/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 636 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_HALTED_Pos [5/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 639 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_HALTED_Pos [6/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 639 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_HALTED_Pos [7/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 639 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_HALTED_Pos [8/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 639 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_HALTED_Pos [9/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 703 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Pos [10/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 703 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Pos [11/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 703 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Pos [12/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 703 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Pos [13/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 703 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Pos [14/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 703 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_HALTED_Pos [15/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 756 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Pos [16/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 756 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Pos [17/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 756 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Pos [18/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 756 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Pos [19/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 756 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_HALTED_Pos [20/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 756 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_HALTED_Pos [21/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 826 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_HALTED_Pos [22/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 826 of file core_cm35p.h.

◆ SCB_DFSR_HALTED_Pos [23/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 826 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_HALTED_Pos [24/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 834 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_HALTED_Pos [25/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 834 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_HALTED_Pos [26/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 834 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_HALTED_Pos [27/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 834 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_HALTED_Pos [28/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 834 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_HALTED_Pos [29/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 834 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_HALTED_Pos [30/30]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 835 of file core_armv81mml.h.

◆ SCB_DFSR_VCATCH_Msk [1/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 628 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_VCATCH_Msk [2/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 628 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_VCATCH_Msk [3/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 628 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_VCATCH_Msk [4/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 628 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_VCATCH_Msk [5/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 631 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_VCATCH_Msk [6/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 631 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_VCATCH_Msk [7/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 631 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_VCATCH_Msk [8/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 631 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_VCATCH_Msk [9/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 695 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Msk [10/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 695 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Msk [11/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 695 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Msk [12/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 695 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Msk [13/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 695 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Msk [14/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 695 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Msk [15/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 748 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Msk [16/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 748 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_VCATCH_Msk [17/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 748 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Msk [18/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 748 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Msk [19/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 748 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Msk [20/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 748 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Msk [21/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 818 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Msk [22/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 818 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_VCATCH_Msk [23/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 818 of file core_cm35p.h.

◆ SCB_DFSR_VCATCH_Msk [24/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 826 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Msk [25/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 826 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Msk [26/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 826 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_VCATCH_Msk [27/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 826 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_VCATCH_Msk [28/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 826 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_VCATCH_Msk [29/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 826 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Msk [30/30]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 827 of file core_armv81mml.h.

◆ SCB_DFSR_VCATCH_Pos [1/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 627 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_VCATCH_Pos [2/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 627 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_VCATCH_Pos [3/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 627 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_VCATCH_Pos [4/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 627 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_DFSR_VCATCH_Pos [5/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 630 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_VCATCH_Pos [6/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 630 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_VCATCH_Pos [7/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 630 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_VCATCH_Pos [8/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 630 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_DFSR_VCATCH_Pos [9/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 694 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Pos [10/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 694 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Pos [11/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 694 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Pos [12/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 694 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Pos [13/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 694 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Pos [14/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 694 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_DFSR_VCATCH_Pos [15/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 747 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DFSR_VCATCH_Pos [16/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 747 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Pos [17/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 747 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Pos [18/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 747 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Pos [19/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 747 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Pos [20/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 747 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DFSR_VCATCH_Pos [21/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 817 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_VCATCH_Pos [22/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 817 of file core_cm35p.h.

◆ SCB_DFSR_VCATCH_Pos [23/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 817 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Pos [24/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 825 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Pos [25/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 825 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Pos [26/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 825 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_VCATCH_Pos [27/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 825 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_VCATCH_Pos [28/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 825 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Pos [29/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 825 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DFSR_VCATCH_Pos [30/30]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 826 of file core_armv81mml.h.

◆ SCB_DTCMCR_EN_Msk [1/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 860 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DTCMCR_EN_Msk [2/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 860 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Msk [3/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 860 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Msk [4/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 860 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Msk [5/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 860 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Msk [6/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 860 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Msk [7/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 948 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_EN_Msk [8/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 948 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_EN_Msk [9/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 948 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_EN_Msk [10/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 948 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_EN_Msk [11/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 948 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_EN_Msk [12/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 948 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_EN_Msk [13/13]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 949 of file core_armv81mml.h.

◆ SCB_DTCMCR_EN_Pos [1/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 859 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Pos [2/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 859 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Pos [3/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 859 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DTCMCR_EN_Pos [4/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 859 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Pos [5/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 859 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Pos [6/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 859 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_EN_Pos [7/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 947 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_EN_Pos [8/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 947 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_EN_Pos [9/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 947 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_EN_Pos [10/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 947 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_EN_Pos [11/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 947 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_EN_Pos [12/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 947 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_EN_Pos [13/13]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 948 of file core_armv81mml.h.

◆ SCB_DTCMCR_RETEN_Msk [1/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 854 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Msk [2/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 854 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Msk [3/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 854 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Msk [4/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 854 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Msk [5/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 854 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Msk [6/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 854 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Msk [7/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 942 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RETEN_Msk [8/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 942 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RETEN_Msk [9/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 942 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RETEN_Msk [10/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 942 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RETEN_Msk [11/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 942 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RETEN_Msk [12/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 942 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RETEN_Msk [13/13]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 943 of file core_armv81mml.h.

◆ SCB_DTCMCR_RETEN_Pos [1/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 853 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Pos [2/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 853 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Pos [3/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 853 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Pos [4/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 853 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Pos [5/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 853 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Pos [6/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 853 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RETEN_Pos [7/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 941 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RETEN_Pos [8/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 941 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RETEN_Pos [9/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 941 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RETEN_Pos [10/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 941 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RETEN_Pos [11/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 941 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RETEN_Pos [12/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 941 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RETEN_Pos [13/13]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 942 of file core_armv81mml.h.

◆ SCB_DTCMCR_RMW_Msk [1/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 857 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DTCMCR_RMW_Msk [2/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 857 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Msk [3/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 857 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Msk [4/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 857 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Msk [5/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 857 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Msk [6/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 857 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Msk [7/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 945 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RMW_Msk [8/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 945 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RMW_Msk [9/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 945 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RMW_Msk [10/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 945 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RMW_Msk [11/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 945 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RMW_Msk [12/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 945 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RMW_Msk [13/13]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 946 of file core_armv81mml.h.

◆ SCB_DTCMCR_RMW_Pos [1/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 856 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Pos [2/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 856 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Pos [3/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 856 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Pos [4/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 856 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DTCMCR_RMW_Pos [5/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 856 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Pos [6/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 856 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_RMW_Pos [7/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 944 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RMW_Pos [8/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 944 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RMW_Pos [9/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 944 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RMW_Pos [10/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 944 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RMW_Pos [11/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 944 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_RMW_Pos [12/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 944 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_RMW_Pos [13/13]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 945 of file core_armv81mml.h.

◆ SCB_DTCMCR_SZ_Msk [1/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 851 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Msk [2/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 851 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Msk [3/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 851 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Msk [4/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 851 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Msk [5/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 851 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DTCMCR_SZ_Msk [6/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 851 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Msk [7/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 939 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_SZ_Msk [8/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 939 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_SZ_Msk [9/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 939 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_SZ_Msk [10/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 939 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_SZ_Msk [11/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 939 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_SZ_Msk [12/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 939 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_SZ_Msk [13/13]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 940 of file core_armv81mml.h.

◆ SCB_DTCMCR_SZ_Pos [1/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 850 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Pos [2/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 850 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Pos [3/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 850 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Pos [4/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 850 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_DTCMCR_SZ_Pos [5/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 850 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Pos [6/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 850 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_DTCMCR_SZ_Pos [7/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 938 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_SZ_Pos [8/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 938 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_SZ_Pos [9/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 938 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_SZ_Pos [10/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 938 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_SZ_Pos [11/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 938 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_DTCMCR_SZ_Pos [12/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 938 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_DTCMCR_SZ_Pos [13/13]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 939 of file core_armv81mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [1/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 615 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Msk [2/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 615 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Msk [3/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 615 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Msk [4/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 615 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Msk [5/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 618 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Msk [6/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 618 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Msk [7/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 618 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Msk [8/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 618 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Msk [9/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 682 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Msk [10/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 682 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Msk [11/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 682 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Msk [12/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 682 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Msk [13/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 682 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Msk [14/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 682 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Msk [15/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 735 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [16/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 735 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [17/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 735 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [18/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 735 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [19/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 735 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [20/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 735 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [21/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 805 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Msk [22/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 805 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [23/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 805 of file core_cm35p.h.

◆ SCB_HFSR_DEBUGEVT_Msk [24/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 813 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [25/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 813 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Msk [26/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 813 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Msk [27/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 813 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Msk [28/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 813 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [29/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 813 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [30/30]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 814 of file core_armv81mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [1/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 614 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Pos [2/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 614 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Pos [3/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 614 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Pos [4/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 614 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Pos [5/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 617 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Pos [6/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 617 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Pos [7/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 617 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Pos [8/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 617 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Pos [9/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 681 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Pos [10/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 681 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Pos [11/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 681 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Pos [12/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 681 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Pos [13/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 681 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Pos [14/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 681 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Pos [15/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 734 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Pos [16/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 734 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Pos [17/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 734 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Pos [18/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 734 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Pos [19/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 734 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Pos [20/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 734 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Pos [21/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 804 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [22/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 804 of file core_cm35p.h.

◆ SCB_HFSR_DEBUGEVT_Pos [23/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 804 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Pos [24/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 812 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Pos [25/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 812 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Pos [26/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 812 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Pos [27/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 812 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [28/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 812 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [29/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 812 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [30/30]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 813 of file core_armv81mml.h.

◆ SCB_HFSR_FORCED_Msk [1/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 618 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_FORCED_Msk [2/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 618 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_FORCED_Msk [3/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 618 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_FORCED_Msk [4/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 618 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_FORCED_Msk [5/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 621 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_FORCED_Msk [6/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 621 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_FORCED_Msk [7/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 621 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_FORCED_Msk [8/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 621 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_FORCED_Msk [9/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 685 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Msk [10/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 685 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Msk [11/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 685 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Msk [12/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 685 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Msk [13/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 685 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Msk [14/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 685 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Msk [15/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 738 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Msk [16/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 738 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_HFSR_FORCED_Msk [17/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 738 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Msk [18/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 738 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Msk [19/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 738 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Msk [20/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 738 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Msk [21/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 808 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_FORCED_Msk [22/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 808 of file core_cm35p.h.

◆ SCB_HFSR_FORCED_Msk [23/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 808 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_FORCED_Msk [24/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 816 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_FORCED_Msk [25/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 816 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_FORCED_Msk [26/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 816 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_FORCED_Msk [27/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 816 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_FORCED_Msk [28/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 816 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_FORCED_Msk [29/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 816 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_FORCED_Msk [30/30]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 817 of file core_armv81mml.h.

◆ SCB_HFSR_FORCED_Pos [1/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 617 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_FORCED_Pos [2/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 617 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_FORCED_Pos [3/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 617 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_FORCED_Pos [4/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 617 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_FORCED_Pos [5/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 620 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_FORCED_Pos [6/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 620 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_FORCED_Pos [7/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 620 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_FORCED_Pos [8/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 620 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_FORCED_Pos [9/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 684 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Pos [10/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 684 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Pos [11/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 684 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Pos [12/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 684 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Pos [13/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 684 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Pos [14/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 684 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_FORCED_Pos [15/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 737 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Pos [16/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 737 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Pos [17/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 737 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Pos [18/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 737 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Pos [19/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 737 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_FORCED_Pos [20/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 737 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_HFSR_FORCED_Pos [21/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 807 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_FORCED_Pos [22/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 807 of file core_cm35p.h.

◆ SCB_HFSR_FORCED_Pos [23/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 807 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_FORCED_Pos [24/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 815 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_FORCED_Pos [25/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 815 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_FORCED_Pos [26/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 815 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_FORCED_Pos [27/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 815 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_FORCED_Pos [28/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 815 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_FORCED_Pos [29/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 815 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_FORCED_Pos [30/30]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 816 of file core_armv81mml.h.

◆ SCB_HFSR_VECTTBL_Msk [1/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 621 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_VECTTBL_Msk [2/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 621 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_VECTTBL_Msk [3/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 621 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_VECTTBL_Msk [4/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 621 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_VECTTBL_Msk [5/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 624 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_VECTTBL_Msk [6/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 624 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_VECTTBL_Msk [7/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 624 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_VECTTBL_Msk [8/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 624 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_VECTTBL_Msk [9/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 688 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Msk [10/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 688 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Msk [11/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 688 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Msk [12/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 688 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Msk [13/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 688 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Msk [14/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 688 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Msk [15/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 741 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Msk [16/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 741 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Msk [17/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 741 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Msk [18/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 741 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Msk [19/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 741 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Msk [20/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 741 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Msk [21/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 811 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_VECTTBL_Msk [22/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 811 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Msk [23/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 811 of file core_cm35p.h.

◆ SCB_HFSR_VECTTBL_Msk [24/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 819 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Msk [25/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 819 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_VECTTBL_Msk [26/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 819 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_VECTTBL_Msk [27/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 819 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_VECTTBL_Msk [28/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 819 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Msk [29/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 819 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Msk [30/30]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 820 of file core_armv81mml.h.

◆ SCB_HFSR_VECTTBL_Pos [1/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 620 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_VECTTBL_Pos [2/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 620 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_VECTTBL_Pos [3/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 620 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_VECTTBL_Pos [4/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 620 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_HFSR_VECTTBL_Pos [5/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 623 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_VECTTBL_Pos [6/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 623 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_VECTTBL_Pos [7/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 623 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_VECTTBL_Pos [8/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 623 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_HFSR_VECTTBL_Pos [9/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 687 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Pos [10/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 687 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Pos [11/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 687 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Pos [12/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 687 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Pos [13/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 687 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Pos [14/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 687 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_HFSR_VECTTBL_Pos [15/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 740 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Pos [16/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 740 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Pos [17/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 740 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Pos [18/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 740 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Pos [19/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 740 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Pos [20/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 740 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_HFSR_VECTTBL_Pos [21/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 810 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_VECTTBL_Pos [22/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 810 of file core_cm35p.h.

◆ SCB_HFSR_VECTTBL_Pos [23/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 810 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Pos [24/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 818 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Pos [25/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 818 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_VECTTBL_Pos [26/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 818 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_VECTTBL_Pos [27/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 818 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_HFSR_VECTTBL_Pos [28/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 818 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Pos [29/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 818 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Pos [30/30]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 819 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [1/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Msk [2/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Msk [3/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Msk [4/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Msk [5/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Msk [6/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Msk [7/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Msk [8/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Msk [9/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 398 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Msk [10/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 398 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Msk [11/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 398 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Msk [12/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 398 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Msk [13/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 408 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Msk [14/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 408 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Msk [15/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 408 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Msk [16/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 408 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Msk [17/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 435 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Msk [18/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 435 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Msk [19/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 435 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Msk [20/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 435 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Msk [21/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 437 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Msk [22/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 437 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Msk [23/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 437 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Msk [24/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 437 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Msk [25/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Msk [26/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Msk [27/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Msk [28/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Msk [29/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Msk [30/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Msk [31/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Msk [32/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Msk [33/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 501 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Msk [34/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 501 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Msk [35/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 501 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Msk [36/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 501 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Msk [37/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 501 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Msk [38/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 501 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Msk [39/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 545 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Msk [40/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 545 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Msk [41/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 545 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Msk [42/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 545 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Msk [43/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 545 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Msk [44/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 545 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Msk [45/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 588 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [46/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 588 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Msk [47/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 588 of file core_cm35p.h.

◆ SCB_ICSR_ISRPENDING_Msk [48/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 596 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Msk [49/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 596 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Msk [50/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 596 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [51/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 596 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Msk [52/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 596 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [53/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 596 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [54/54]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 597 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [1/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Pos [2/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Pos [3/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Pos [4/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Pos [5/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Pos [6/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Pos [7/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Pos [8/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Pos [9/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 397 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Pos [10/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 397 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Pos [11/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 397 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Pos [12/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 397 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Pos [13/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 407 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Pos [14/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 407 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Pos [15/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 407 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Pos [16/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 407 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Pos [17/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 434 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Pos [18/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 434 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Pos [19/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 434 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Pos [20/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 434 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Pos [21/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 436 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Pos [22/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 436 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Pos [23/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 436 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Pos [24/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 436 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Pos [25/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Pos [26/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Pos [27/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Pos [28/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Pos [29/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Pos [30/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Pos [31/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Pos [32/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Pos [33/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 500 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Pos [34/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 500 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Pos [35/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 500 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Pos [36/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 500 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Pos [37/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 500 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Pos [38/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 500 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Pos [39/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 544 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Pos [40/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 544 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Pos [41/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 544 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Pos [42/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 544 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Pos [43/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 544 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Pos [44/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 544 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Pos [45/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 587 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [46/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 587 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Pos [47/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 587 of file core_cm35p.h.

◆ SCB_ICSR_ISRPENDING_Pos [48/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 595 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Pos [49/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 595 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Pos [50/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 595 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Pos [51/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 595 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [52/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 595 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [53/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 595 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [54/54]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 596 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [1/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [2/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [3/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [4/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [5/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [6/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [7/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [8/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [9/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 395 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [10/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 395 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [11/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 395 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [12/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 395 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [13/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 405 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [14/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 405 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [15/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 405 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [16/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 405 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [17/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 432 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [18/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 432 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [19/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 432 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [20/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 432 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [21/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 434 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [22/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 434 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [23/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 434 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [24/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 434 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [25/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [26/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [27/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [28/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [29/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [30/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [31/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [32/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [33/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 498 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [34/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 498 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [35/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 498 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [36/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 498 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [37/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 498 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [38/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 498 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [39/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 542 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [40/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 542 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [41/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 542 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [42/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 542 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [43/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 542 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [44/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 542 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [45/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 585 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [46/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 585 of file core_cm35p.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [47/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 585 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [48/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 593 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [49/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 593 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [50/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 593 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [51/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 593 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [52/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 593 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [53/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 593 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [54/54]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 594 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [1/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [2/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [3/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [4/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [5/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [6/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [7/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [8/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [9/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 394 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [10/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 394 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [11/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 394 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [12/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 394 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [13/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 404 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [14/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 404 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [15/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 404 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [16/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 404 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [17/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 431 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [18/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 431 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [19/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 431 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [20/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 431 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [21/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 433 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [22/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 433 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [23/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 433 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [24/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 433 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [25/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [26/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [27/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [28/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [29/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [30/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [31/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [32/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [33/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 497 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [34/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 497 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [35/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 497 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [36/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 497 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [37/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 497 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [38/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 497 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [39/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 541 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [40/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 541 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [41/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 541 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [42/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 541 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [43/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 541 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [44/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 541 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [45/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 584 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [46/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 584 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [47/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 584 of file core_cm35p.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [48/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 592 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [49/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 592 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [50/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 592 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [51/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 592 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [52/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 592 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [53/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 592 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [54/54]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 593 of file core_armv81mml.h.

◆ SCB_ICSR_NMIPENDSET_Msk [1/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 372 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Msk [2/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 372 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Msk [3/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 372 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Msk [4/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 372 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Msk [5/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 372 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Msk [6/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 372 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Msk [7/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 372 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Msk [8/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 372 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Msk [9/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 380 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Msk [10/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 380 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Msk [11/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 380 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Msk [12/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 380 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Msk [13/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 390 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Msk [14/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 390 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Msk [15/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 390 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Msk [16/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 390 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Msk [17/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 417 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Msk [18/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 417 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Msk [19/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 417 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Msk [20/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 417 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Msk [21/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 419 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Msk [22/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 419 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Msk [23/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 419 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Msk [24/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 419 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Msk [25/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 419 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Msk [26/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 419 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Msk [27/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 419 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Msk [28/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 419 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Msk [29/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 419 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Msk [30/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 419 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Msk [31/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 419 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Msk [32/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 419 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Msk [33/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 483 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Msk [34/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 483 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Msk [35/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 483 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Msk [36/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 483 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Msk [37/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 483 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Msk [38/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 483 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Msk [39/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 527 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Msk [40/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 527 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Msk [41/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 527 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Msk [42/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 527 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Msk [43/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 527 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Msk [44/54]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 527 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Msk [45/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 564 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Msk [46/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 564 of file core_cm35p.h.

◆ SCB_ICSR_NMIPENDSET_Msk [47/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 564 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Msk [48/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 572 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Msk [49/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 572 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Msk [50/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 572 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Msk [51/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 572 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Msk [52/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 572 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Msk [53/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 572 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Msk [54/54]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 573 of file core_armv81mml.h.

◆ SCB_ICSR_NMIPENDSET_Pos [1/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 371 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Pos [2/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 371 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Pos [3/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 371 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Pos [4/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 371 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Pos [5/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 371 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Pos [6/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 371 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Pos [7/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 371 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Pos [8/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 371 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Pos [9/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 379 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Pos [10/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 379 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Pos [11/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 379 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Pos [12/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 379 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Pos [13/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 389 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Pos [14/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 389 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Pos [15/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 389 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Pos [16/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 389 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Pos [17/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 416 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Pos [18/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 416 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Pos [19/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 416 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Pos [20/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 416 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Pos [21/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 418 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Pos [22/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 418 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Pos [23/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 418 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Pos [24/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 418 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Pos [25/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 418 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Pos [26/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 418 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Pos [27/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 418 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Pos [28/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 418 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Pos [29/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 418 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Pos [30/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 418 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Pos [31/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 418 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Pos [32/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 418 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Pos [33/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 482 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Pos [34/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 482 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Pos [35/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 482 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Pos [36/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 482 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Pos [37/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 482 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Pos [38/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 482 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Pos [39/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 526 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Pos [40/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 526 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Pos [41/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 526 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Pos [42/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 526 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Pos [43/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 526 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Pos [44/54]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

Definition at line 526 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Pos [45/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 563 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Pos [46/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 563 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Pos [47/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 563 of file core_cm35p.h.

◆ SCB_ICSR_NMIPENDSET_Pos [48/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 571 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Pos [49/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 571 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Pos [50/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 571 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Pos [51/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 571 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Pos [52/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 571 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Pos [53/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 571 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Pos [54/54]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 572 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [1/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Msk [2/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Msk [3/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Msk [4/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Msk [5/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Msk [6/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Msk [7/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Msk [8/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Msk [9/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 567 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [10/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 567 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Msk [11/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 567 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMICLR_Msk [12/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 575 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Msk [13/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 575 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [14/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 575 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Msk [15/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 575 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [16/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 575 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [17/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 575 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Msk [18/18]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 576 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [1/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Pos [2/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Pos [3/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Pos [4/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Pos [5/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Pos [6/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Pos [7/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Pos [8/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Pos [9/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 566 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [10/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 566 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Pos [11/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 566 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMICLR_Pos [12/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 574 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Pos [13/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 574 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Pos [14/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 574 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [15/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 574 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [16/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 574 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [17/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 574 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Pos [18/18]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 575 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [1/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Msk [2/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Msk [3/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Msk [4/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Msk [5/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Msk [6/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Msk [7/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Msk [8/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Msk [9/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 561 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [10/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 561 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMISET_Msk [11/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 561 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Msk [12/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 569 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [13/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 569 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Msk [14/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 569 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [15/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 569 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [16/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 569 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Msk [17/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 569 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Msk [18/18]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 570 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [1/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Pos [2/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Pos [3/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Pos [4/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Pos [5/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Pos [6/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Pos [7/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Pos [8/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Pos [9/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 560 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Pos [10/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 560 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMISET_Pos [11/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 560 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [12/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 568 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Pos [13/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 568 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Pos [14/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 568 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Pos [15/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 568 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [16/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 568 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [17/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 568 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [18/18]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 569 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [1/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Msk [2/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Msk [3/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Msk [4/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Msk [5/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Msk [6/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Msk [7/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Msk [8/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Msk [9/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 392 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Msk [10/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 392 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Msk [11/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 392 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Msk [12/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 392 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Msk [13/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 402 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Msk [14/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 402 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Msk [15/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 402 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Msk [16/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 402 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Msk [17/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 429 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Msk [18/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 429 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Msk [19/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 429 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Msk [20/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 429 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Msk [21/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 431 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Msk [22/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 431 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Msk [23/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 431 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Msk [24/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 431 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Msk [25/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Msk [26/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Msk [27/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Msk [28/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Msk [29/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Msk [30/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Msk [31/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Msk [32/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Msk [33/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 495 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Msk [34/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 495 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Msk [35/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 495 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Msk [36/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 495 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Msk [37/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 495 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Msk [38/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 495 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Msk [39/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 539 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Msk [40/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 539 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Msk [41/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 539 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Msk [42/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 539 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Msk [43/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 539 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Msk [44/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 539 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Msk [45/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 579 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [46/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 579 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Msk [47/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 579 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTCLR_Msk [48/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 587 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Msk [49/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 587 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [50/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 587 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [51/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 587 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Msk [52/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 587 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [53/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 587 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Msk [54/54]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 588 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [1/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Pos [2/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Pos [3/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Pos [4/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Pos [5/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Pos [6/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Pos [7/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Pos [8/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Pos [9/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 391 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Pos [10/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 391 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Pos [11/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 391 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Pos [12/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 391 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Pos [13/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 401 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Pos [14/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 401 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Pos [15/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 401 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Pos [16/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 401 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Pos [17/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 428 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Pos [18/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 428 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Pos [19/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 428 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Pos [20/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 428 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Pos [21/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 430 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Pos [22/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 430 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Pos [23/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 430 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Pos [24/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 430 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Pos [25/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Pos [26/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Pos [27/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Pos [28/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Pos [29/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Pos [30/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Pos [31/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Pos [32/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Pos [33/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 494 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Pos [34/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 494 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Pos [35/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 494 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Pos [36/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 494 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Pos [37/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 494 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Pos [38/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 494 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Pos [39/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 538 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Pos [40/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 538 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Pos [41/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 538 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Pos [42/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 538 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Pos [43/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 538 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Pos [44/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 538 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Pos [45/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 578 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [46/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 578 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTCLR_Pos [47/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 578 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Pos [48/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 586 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Pos [49/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 586 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Pos [50/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 586 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [51/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 586 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Pos [52/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 586 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [53/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 586 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [54/54]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 587 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [1/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Msk [2/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Msk [3/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Msk [4/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Msk [5/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Msk [6/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Msk [7/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Msk [8/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Msk [9/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 389 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Msk [10/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 389 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Msk [11/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 389 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Msk [12/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 389 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Msk [13/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 399 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Msk [14/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 399 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Msk [15/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 399 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Msk [16/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 399 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Msk [17/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 426 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Msk [18/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 426 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Msk [19/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 426 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Msk [20/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 426 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Msk [21/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 428 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Msk [22/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 428 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Msk [23/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 428 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Msk [24/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 428 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Msk [25/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Msk [26/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Msk [27/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Msk [28/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Msk [29/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Msk [30/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Msk [31/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Msk [32/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Msk [33/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 492 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Msk [34/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 492 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Msk [35/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 492 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Msk [36/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 492 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Msk [37/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 492 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Msk [38/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 492 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Msk [39/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 536 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Msk [40/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 536 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Msk [41/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 536 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Msk [42/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 536 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Msk [43/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 536 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Msk [44/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 536 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Msk [45/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 576 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [46/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 576 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTSET_Msk [47/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 576 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Msk [48/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 584 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Msk [49/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 584 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Msk [50/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 584 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Msk [51/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 584 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [52/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 584 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [53/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 584 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [54/54]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 585 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [1/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Pos [2/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Pos [3/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Pos [4/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Pos [5/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Pos [6/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Pos [7/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Pos [8/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Pos [9/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 388 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Pos [10/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 388 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Pos [11/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 388 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Pos [12/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 388 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Pos [13/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 398 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Pos [14/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 398 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Pos [15/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 398 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Pos [16/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 398 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Pos [17/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 425 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Pos [18/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 425 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Pos [19/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 425 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Pos [20/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 425 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Pos [21/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 427 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Pos [22/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 427 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Pos [23/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 427 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Pos [24/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 427 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Pos [25/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Pos [26/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Pos [27/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Pos [28/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Pos [29/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Pos [30/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Pos [31/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Pos [32/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Pos [33/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 491 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Pos [34/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 491 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Pos [35/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 491 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Pos [36/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 491 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Pos [37/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 491 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Pos [38/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 491 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Pos [39/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 535 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Pos [40/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 535 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Pos [41/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 535 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Pos [42/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 535 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Pos [43/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 535 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Pos [44/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 535 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Pos [45/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 575 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTSET_Pos [46/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 575 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Pos [47/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 575 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [48/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 583 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Pos [49/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 583 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Pos [50/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 583 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Pos [51/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 583 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [52/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 583 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [53/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 583 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [54/54]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 584 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [1/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Msk [2/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Msk [3/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Msk [4/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Msk [5/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Msk [6/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Msk [7/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Msk [8/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Msk [9/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 386 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Msk [10/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 386 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Msk [11/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 386 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Msk [12/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 386 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Msk [13/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 396 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Msk [14/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 396 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Msk [15/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 396 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Msk [16/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 396 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Msk [17/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 423 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Msk [18/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 423 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Msk [19/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 423 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Msk [20/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 423 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Msk [21/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 425 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Msk [22/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 425 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Msk [23/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 425 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Msk [24/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 425 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Msk [25/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Msk [26/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Msk [27/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Msk [28/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Msk [29/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Msk [30/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Msk [31/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Msk [32/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Msk [33/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 489 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Msk [34/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 489 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Msk [35/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 489 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Msk [36/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 489 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Msk [37/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 489 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Msk [38/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 489 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Msk [39/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 533 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Msk [40/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 533 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Msk [41/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 533 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Msk [42/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 533 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Msk [43/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 533 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Msk [44/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 533 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Msk [45/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 573 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVCLR_Msk [46/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 573 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Msk [47/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 573 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [48/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 581 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Msk [49/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 581 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Msk [50/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 581 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [51/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 581 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [52/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 581 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [53/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 581 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Msk [54/54]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 582 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [1/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Pos [2/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Pos [3/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Pos [4/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Pos [5/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Pos [6/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Pos [7/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Pos [8/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Pos [9/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 385 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Pos [10/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 385 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Pos [11/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 385 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Pos [12/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 385 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Pos [13/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 395 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Pos [14/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 395 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Pos [15/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 395 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Pos [16/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 395 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Pos [17/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 422 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Pos [18/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 422 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Pos [19/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 422 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Pos [20/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 422 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Pos [21/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 424 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Pos [22/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 424 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Pos [23/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 424 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Pos [24/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 424 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Pos [25/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Pos [26/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Pos [27/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Pos [28/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Pos [29/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Pos [30/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Pos [31/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Pos [32/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Pos [33/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 488 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Pos [34/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 488 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Pos [35/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 488 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Pos [36/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 488 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Pos [37/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 488 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Pos [38/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 488 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Pos [39/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 532 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Pos [40/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 532 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Pos [41/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 532 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Pos [42/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 532 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Pos [43/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 532 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Pos [44/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 532 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Pos [45/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 572 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Pos [46/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 572 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [47/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 572 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVCLR_Pos [48/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 580 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Pos [49/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 580 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Pos [50/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 580 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [51/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 580 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Pos [52/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 580 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [53/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 580 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [54/54]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 581 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [1/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Msk [2/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Msk [3/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Msk [4/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Msk [5/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Msk [6/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Msk [7/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Msk [8/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Msk [9/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 383 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Msk [10/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 383 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Msk [11/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 383 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Msk [12/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 383 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Msk [13/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 393 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Msk [14/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 393 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Msk [15/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 393 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Msk [16/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 393 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Msk [17/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 420 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Msk [18/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 420 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Msk [19/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 420 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Msk [20/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 420 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Msk [21/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 422 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Msk [22/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 422 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Msk [23/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 422 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Msk [24/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 422 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Msk [25/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Msk [26/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Msk [27/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Msk [28/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Msk [29/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Msk [30/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Msk [31/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Msk [32/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Msk [33/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 486 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Msk [34/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 486 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Msk [35/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 486 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Msk [36/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 486 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Msk [37/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 486 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Msk [38/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 486 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Msk [39/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 530 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Msk [40/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 530 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Msk [41/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 530 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Msk [42/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 530 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Msk [43/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 530 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Msk [44/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 530 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Msk [45/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 570 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Msk [46/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 570 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [47/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 570 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVSET_Msk [48/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 578 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [49/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 578 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [50/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 578 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [51/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 578 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Msk [52/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 578 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Msk [53/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 578 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Msk [54/54]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 579 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [1/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Pos [2/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Pos [3/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Pos [4/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Pos [5/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Pos [6/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Pos [7/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Pos [8/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Pos [9/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 382 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Pos [10/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 382 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Pos [11/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 382 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Pos [12/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 382 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Pos [13/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 392 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Pos [14/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 392 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Pos [15/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 392 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Pos [16/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 392 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Pos [17/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 419 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Pos [18/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 419 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Pos [19/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 419 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Pos [20/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 419 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Pos [21/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 421 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Pos [22/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 421 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Pos [23/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 421 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Pos [24/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 421 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Pos [25/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Pos [26/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Pos [27/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Pos [28/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Pos [29/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Pos [30/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Pos [31/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Pos [32/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Pos [33/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 485 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Pos [34/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 485 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Pos [35/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 485 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Pos [36/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 485 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Pos [37/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 485 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Pos [38/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 485 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Pos [39/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 529 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Pos [40/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 529 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Pos [41/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 529 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Pos [42/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 529 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Pos [43/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 529 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Pos [44/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 529 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Pos [45/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 569 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Pos [46/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 569 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVSET_Pos [47/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 569 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [48/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 577 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Pos [49/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 577 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [50/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 577 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Pos [51/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 577 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [52/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 577 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [53/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 577 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Pos [54/54]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 578 of file core_armv81mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [1/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 441 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Msk [2/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 441 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Msk [3/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 441 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Msk [4/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 441 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Msk [5/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 443 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Msk [6/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 443 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Msk [7/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 443 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Msk [8/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 443 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Msk [9/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Msk [10/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Msk [11/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Msk [12/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Msk [13/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Msk [14/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Msk [15/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Msk [16/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Msk [17/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 507 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Msk [18/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 507 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Msk [19/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 507 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Msk [20/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 507 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Msk [21/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 507 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Msk [22/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 507 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Msk [23/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 551 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Msk [24/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 551 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Msk [25/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 551 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Msk [26/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 551 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Msk [27/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 551 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Msk [28/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 551 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Msk [29/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 594 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [30/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 594 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Msk [31/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 594 of file core_cm35p.h.

◆ SCB_ICSR_RETTOBASE_Msk [32/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 602 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Msk [33/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 602 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [34/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 602 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Msk [35/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 602 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Msk [36/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 602 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [37/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 602 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [38/38]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 603 of file core_armv81mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [1/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 440 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Pos [2/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 440 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Pos [3/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 440 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Pos [4/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 440 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Pos [5/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 442 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Pos [6/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 442 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Pos [7/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 442 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Pos [8/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 442 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Pos [9/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Pos [10/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Pos [11/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Pos [12/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Pos [13/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Pos [14/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Pos [15/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Pos [16/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Pos [17/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 506 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Pos [18/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 506 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Pos [19/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 506 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Pos [20/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 506 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Pos [21/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 506 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Pos [22/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 506 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Pos [23/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 550 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Pos [24/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 550 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Pos [25/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 550 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Pos [26/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 550 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Pos [27/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 550 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Pos [28/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 550 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Pos [29/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 593 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Pos [30/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 593 of file core_cm35p.h.

◆ SCB_ICSR_RETTOBASE_Pos [31/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 593 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [32/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 601 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Pos [33/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 601 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Pos [34/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 601 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Pos [35/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 601 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [36/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 601 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [37/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 601 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [38/38]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 602 of file core_armv81mml.h.

◆ SCB_ICSR_STTNS_Msk [1/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Msk [2/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_STTNS_Msk [3/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Msk [4/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_STTNS_Msk [5/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Msk [6/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_STTNS_Msk [7/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_STTNS_Msk [8/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Msk [9/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 582 of file core_cm35p.h.

◆ SCB_ICSR_STTNS_Msk [10/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 582 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_STTNS_Msk [11/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 582 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_STTNS_Msk [12/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 590 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_STTNS_Msk [13/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 590 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_STTNS_Msk [14/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 590 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_STTNS_Msk [15/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 590 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_STTNS_Msk [16/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 590 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_STTNS_Msk [17/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 590 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_STTNS_Msk [18/18]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 591 of file core_armv81mml.h.

◆ SCB_ICSR_STTNS_Pos [1/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_STTNS_Pos [2/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Pos [3/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Pos [4/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_STTNS_Pos [5/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_STTNS_Pos [6/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_STTNS_Pos [7/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Pos [8/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Pos [9/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 581 of file core_cm35p.h.

◆ SCB_ICSR_STTNS_Pos [10/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 581 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_STTNS_Pos [11/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 581 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_STTNS_Pos [12/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 589 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_STTNS_Pos [13/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 589 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_STTNS_Pos [14/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 589 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_STTNS_Pos [15/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 589 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_STTNS_Pos [16/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 589 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_STTNS_Pos [17/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 589 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_STTNS_Pos [18/18]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 590 of file core_armv81mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [1/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Msk [2/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Msk [3/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Msk [4/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Msk [5/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Msk [6/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Msk [7/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Msk [8/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Msk [9/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 404 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Msk [10/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 404 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Msk [11/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 404 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Msk [12/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 404 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Msk [13/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 414 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Msk [14/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 414 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Msk [15/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 414 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Msk [16/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 414 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Msk [17/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 444 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Msk [18/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 444 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Msk [19/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 444 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Msk [20/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 444 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Msk [21/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 446 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Msk [22/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 446 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Msk [23/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 446 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Msk [24/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 446 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Msk [25/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Msk [26/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Msk [27/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Msk [28/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Msk [29/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Msk [30/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Msk [31/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Msk [32/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Msk [33/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 510 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Msk [34/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 510 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Msk [35/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 510 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Msk [36/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 510 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Msk [37/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 510 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Msk [38/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 510 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Msk [39/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 554 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Msk [40/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 554 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Msk [41/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 554 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Msk [42/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 554 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Msk [43/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 554 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Msk [44/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 554 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Msk [45/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 597 of file core_cm35p.h.

◆ SCB_ICSR_VECTACTIVE_Msk [46/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 597 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [47/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 597 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Msk [48/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 605 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [49/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 605 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Msk [50/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 605 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Msk [51/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 605 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [52/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 605 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Msk [53/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 605 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [54/54]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 606 of file core_armv81mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [1/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Pos [2/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Pos [3/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Pos [4/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Pos [5/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Pos [6/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Pos [7/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Pos [8/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Pos [9/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 403 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Pos [10/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 403 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Pos [11/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 403 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Pos [12/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 403 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Pos [13/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 413 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Pos [14/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 413 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Pos [15/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 413 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Pos [16/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 413 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Pos [17/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 443 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Pos [18/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 443 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Pos [19/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 443 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Pos [20/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 443 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Pos [21/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 445 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Pos [22/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 445 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Pos [23/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 445 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Pos [24/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 445 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Pos [25/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Pos [26/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Pos [27/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Pos [28/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Pos [29/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Pos [30/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Pos [31/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Pos [32/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Pos [33/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 509 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Pos [34/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 509 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Pos [35/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 509 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Pos [36/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 509 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Pos [37/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 509 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Pos [38/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 509 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Pos [39/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 553 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Pos [40/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 553 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Pos [41/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 553 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Pos [42/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 553 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Pos [43/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 553 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Pos [44/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 553 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Pos [45/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 596 of file core_cm35p.h.

◆ SCB_ICSR_VECTACTIVE_Pos [46/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 596 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Pos [47/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 596 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [48/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 604 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Pos [49/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 604 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [50/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 604 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Pos [51/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 604 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [52/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 604 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Pos [53/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 604 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [54/54]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 605 of file core_armv81mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [1/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Msk [2/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Msk [3/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Msk [4/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Msk [5/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Msk [6/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Msk [7/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Msk [8/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Msk [9/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 401 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Msk [10/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 401 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Msk [11/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 401 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Msk [12/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 401 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Msk [13/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 411 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Msk [14/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 411 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Msk [15/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 411 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Msk [16/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 411 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Msk [17/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 438 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Msk [18/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 438 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Msk [19/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 438 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Msk [20/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 438 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Msk [21/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 440 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Msk [22/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 440 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Msk [23/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 440 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Msk [24/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 440 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Msk [25/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Msk [26/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Msk [27/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Msk [28/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Msk [29/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Msk [30/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Msk [31/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Msk [32/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Msk [33/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 504 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Msk [34/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 504 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Msk [35/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 504 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Msk [36/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 504 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Msk [37/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 504 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Msk [38/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 504 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Msk [39/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 548 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Msk [40/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 548 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Msk [41/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 548 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Msk [42/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 548 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Msk [43/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 548 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Msk [44/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 548 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Msk [45/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 591 of file core_cm35p.h.

◆ SCB_ICSR_VECTPENDING_Msk [46/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 591 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [47/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 591 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Msk [48/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 599 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Msk [49/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 599 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Msk [50/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 599 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [51/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 599 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [52/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 599 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Msk [53/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 599 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [54/54]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 600 of file core_armv81mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [1/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Pos [2/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Pos [3/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Pos [4/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Pos [5/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Pos [6/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Pos [7/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Pos [8/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Pos [9/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 400 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Pos [10/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 400 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Pos [11/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 400 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Pos [12/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 400 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Pos [13/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 410 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Pos [14/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 410 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Pos [15/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 410 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Pos [16/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 410 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Pos [17/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 437 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Pos [18/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 437 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Pos [19/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 437 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Pos [20/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 437 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Pos [21/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 439 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Pos [22/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 439 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Pos [23/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 439 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Pos [24/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 439 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Pos [25/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Pos [26/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Pos [27/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Pos [28/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Pos [29/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Pos [30/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Pos [31/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Pos [32/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Pos [33/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 503 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Pos [34/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 503 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Pos [35/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 503 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Pos [36/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 503 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Pos [37/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 503 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Pos [38/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 503 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Pos [39/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 547 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Pos [40/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 547 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Pos [41/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 547 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Pos [42/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 547 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Pos [43/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 547 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Pos [44/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 547 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Pos [45/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 590 of file core_cm35p.h.

◆ SCB_ICSR_VECTPENDING_Pos [46/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 590 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [47/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 590 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Pos [48/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 598 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Pos [49/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 598 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Pos [50/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 598 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [51/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 598 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [52/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 598 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [53/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 598 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Pos [54/54]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 599 of file core_armv81mml.h.

◆ SCB_ITCMCR_EN_Msk [1/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 847 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Msk [2/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 847 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ITCMCR_EN_Msk [3/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 847 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Msk [4/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 847 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Msk [5/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 847 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Msk [6/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 847 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Msk [7/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 935 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_EN_Msk [8/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 935 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_EN_Msk [9/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 935 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_EN_Msk [10/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 935 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_EN_Msk [11/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 935 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_EN_Msk [12/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 935 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_EN_Msk [13/13]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 936 of file core_armv81mml.h.

◆ SCB_ITCMCR_EN_Pos [1/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 846 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ITCMCR_EN_Pos [2/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 846 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Pos [3/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 846 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Pos [4/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 846 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Pos [5/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 846 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Pos [6/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 846 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_EN_Pos [7/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 934 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_EN_Pos [8/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 934 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_EN_Pos [9/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 934 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_EN_Pos [10/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 934 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_EN_Pos [11/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 934 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_EN_Pos [12/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 934 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_EN_Pos [13/13]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 935 of file core_armv81mml.h.

◆ SCB_ITCMCR_RETEN_Msk [1/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 841 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Msk [2/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 841 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Msk [3/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 841 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Msk [4/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 841 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Msk [5/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 841 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Msk [6/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 841 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Msk [7/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 929 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RETEN_Msk [8/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 929 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RETEN_Msk [9/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 929 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RETEN_Msk [10/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 929 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RETEN_Msk [11/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 929 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RETEN_Msk [12/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 929 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RETEN_Msk [13/13]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 930 of file core_armv81mml.h.

◆ SCB_ITCMCR_RETEN_Pos [1/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 840 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Pos [2/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 840 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Pos [3/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 840 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Pos [4/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 840 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Pos [5/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 840 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Pos [6/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 840 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ITCMCR_RETEN_Pos [7/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 928 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RETEN_Pos [8/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 928 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RETEN_Pos [9/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 928 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RETEN_Pos [10/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 928 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RETEN_Pos [11/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 928 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RETEN_Pos [12/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 928 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RETEN_Pos [13/13]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 929 of file core_armv81mml.h.

◆ SCB_ITCMCR_RMW_Msk [1/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 844 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Msk [2/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 844 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Msk [3/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 844 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Msk [4/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 844 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Msk [5/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 844 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ITCMCR_RMW_Msk [6/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 844 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Msk [7/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 932 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RMW_Msk [8/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 932 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RMW_Msk [9/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 932 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RMW_Msk [10/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 932 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RMW_Msk [11/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 932 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RMW_Msk [12/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 932 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RMW_Msk [13/13]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 933 of file core_armv81mml.h.

◆ SCB_ITCMCR_RMW_Pos [1/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 843 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Pos [2/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 843 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Pos [3/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 843 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Pos [4/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 843 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ITCMCR_RMW_Pos [5/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 843 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Pos [6/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 843 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_RMW_Pos [7/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 931 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RMW_Pos [8/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 931 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RMW_Pos [9/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 931 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RMW_Pos [10/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 931 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RMW_Pos [11/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 931 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_RMW_Pos [12/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 931 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_RMW_Pos [13/13]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 932 of file core_armv81mml.h.

◆ SCB_ITCMCR_SZ_Msk [1/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 838 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Msk [2/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 838 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Msk [3/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 838 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Msk [4/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 838 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ITCMCR_SZ_Msk [5/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 838 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Msk [6/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 838 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Msk [7/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 926 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_SZ_Msk [8/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 926 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_SZ_Msk [9/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 926 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_SZ_Msk [10/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 926 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_SZ_Msk [11/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 926 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_SZ_Msk [12/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 926 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_SZ_Msk [13/13]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 927 of file core_armv81mml.h.

◆ SCB_ITCMCR_SZ_Pos [1/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 837 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Pos [2/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 837 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Pos [3/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 837 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Pos [4/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 837 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_ITCMCR_SZ_Pos [5/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 837 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Pos [6/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 837 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_ITCMCR_SZ_Pos [7/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 925 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_SZ_Pos [8/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 925 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_SZ_Pos [9/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 925 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_SZ_Pos [10/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 925 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_ITCMCR_SZ_Pos [11/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 925 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_SZ_Pos [12/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 925 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_ITCMCR_SZ_Pos [13/13]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 926 of file core_armv81mml.h.

◆ SCB_NSACR_CP10_Msk [1/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 834 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP10_Msk [2/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 834 of file core_cm35p.h.

◆ SCB_NSACR_CP10_Msk [3/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 834 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP10_Msk [4/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 842 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP10_Msk [5/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 842 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP10_Msk [6/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 842 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP10_Msk [7/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 842 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP10_Msk [8/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 842 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP10_Msk [9/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 842 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP10_Msk [10/10]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 843 of file core_armv81mml.h.

◆ SCB_NSACR_CP10_Pos [1/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 833 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP10_Pos [2/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 833 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP10_Pos [3/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 833 of file core_cm35p.h.

◆ SCB_NSACR_CP10_Pos [4/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 841 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP10_Pos [5/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 841 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP10_Pos [6/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 841 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP10_Pos [7/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 841 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP10_Pos [8/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 841 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP10_Pos [9/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 841 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP10_Pos [10/10]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 842 of file core_armv81mml.h.

◆ SCB_NSACR_CP11_Msk [1/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 831 of file core_cm35p.h.

◆ SCB_NSACR_CP11_Msk [2/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 831 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP11_Msk [3/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 831 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP11_Msk [4/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 839 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP11_Msk [5/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 839 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP11_Msk [6/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 839 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP11_Msk [7/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 839 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP11_Msk [8/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 839 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP11_Msk [9/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 839 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP11_Msk [10/10]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 840 of file core_armv81mml.h.

◆ SCB_NSACR_CP11_Pos [1/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 830 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP11_Pos [2/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 830 of file core_cm35p.h.

◆ SCB_NSACR_CP11_Pos [3/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 830 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP11_Pos [4/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 838 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP11_Pos [5/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 838 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP11_Pos [6/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 838 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP11_Pos [7/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 838 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CP11_Pos [8/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 838 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP11_Pos [9/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 838 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CP11_Pos [10/10]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 839 of file core_armv81mml.h.

◆ SCB_NSACR_CPn_Msk [1/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 837 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CPn_Msk [2/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 837 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CPn_Msk [3/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 837 of file core_cm35p.h.

◆ SCB_NSACR_CPn_Msk [4/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 845 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CPn_Msk [5/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 845 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CPn_Msk [6/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 845 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CPn_Msk [7/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 845 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CPn_Msk [8/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 845 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CPn_Msk [9/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 845 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CPn_Msk [10/10]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 846 of file core_armv81mml.h.

◆ SCB_NSACR_CPn_Pos [1/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 836 of file core_cm35p.h.

◆ SCB_NSACR_CPn_Pos [2/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 836 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CPn_Pos [3/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 836 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CPn_Pos [4/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 844 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CPn_Pos [5/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 844 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CPn_Pos [6/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 844 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CPn_Pos [7/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 844 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CPn_Pos [8/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 844 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_NSACR_CPn_Pos [9/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 844 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_NSACR_CPn_Pos [10/10]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 845 of file core_armv81mml.h.

◆ SCB_SCR_SEVONPEND_Msk [1/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SEVONPEND_Msk [2/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SEVONPEND_Msk [3/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SEVONPEND_Msk [4/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SEVONPEND_Msk [5/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SEVONPEND_Msk [6/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SEVONPEND_Msk [7/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SEVONPEND_Msk [8/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SEVONPEND_Msk [9/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 428 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SEVONPEND_Msk [10/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 428 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SEVONPEND_Msk [11/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 428 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SEVONPEND_Msk [12/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 428 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SEVONPEND_Msk [13/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 440 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Msk [14/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 440 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Msk [15/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 440 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Msk [16/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 440 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Msk [17/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 479 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SEVONPEND_Msk [18/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 479 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SEVONPEND_Msk [19/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 479 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SEVONPEND_Msk [20/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 479 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SEVONPEND_Msk [21/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 482 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SEVONPEND_Msk [22/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 482 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SEVONPEND_Msk [23/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 482 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SEVONPEND_Msk [24/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 482 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SEVONPEND_Msk [25/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SEVONPEND_Msk [26/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SEVONPEND_Msk [27/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SEVONPEND_Msk [28/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Msk [29/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Msk [30/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SEVONPEND_Msk [31/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Msk [32/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Msk [33/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 540 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Msk [34/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 540 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Msk [35/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 540 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Msk [36/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 540 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Msk [37/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 540 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Msk [38/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 540 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Msk [39/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 584 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Msk [40/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 584 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Msk [41/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 584 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Msk [42/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 584 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Msk [43/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 584 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Msk [44/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 584 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Msk [45/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 633 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SEVONPEND_Msk [46/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 633 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Msk [47/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 633 of file core_cm35p.h.

◆ SCB_SCR_SEVONPEND_Msk [48/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 641 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Msk [49/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 641 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SEVONPEND_Msk [50/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 641 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SEVONPEND_Msk [51/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 641 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SEVONPEND_Msk [52/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 641 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Msk [53/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 641 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Msk [54/54]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 642 of file core_armv81mml.h.

◆ SCB_SCR_SEVONPEND_Pos [1/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SEVONPEND_Pos [2/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SEVONPEND_Pos [3/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SEVONPEND_Pos [4/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SEVONPEND_Pos [5/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SEVONPEND_Pos [6/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SEVONPEND_Pos [7/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SEVONPEND_Pos [8/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SEVONPEND_Pos [9/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 427 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SEVONPEND_Pos [10/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 427 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SEVONPEND_Pos [11/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 427 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SEVONPEND_Pos [12/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 427 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SEVONPEND_Pos [13/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 439 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Pos [14/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 439 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Pos [15/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 439 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Pos [16/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 439 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Pos [17/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 478 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SEVONPEND_Pos [18/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 478 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SEVONPEND_Pos [19/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 478 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SEVONPEND_Pos [20/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 478 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SEVONPEND_Pos [21/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 481 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SEVONPEND_Pos [22/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 481 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SEVONPEND_Pos [23/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 481 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SEVONPEND_Pos [24/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 481 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SEVONPEND_Pos [25/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SEVONPEND_Pos [26/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SEVONPEND_Pos [27/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SEVONPEND_Pos [28/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Pos [29/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Pos [30/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SEVONPEND_Pos [31/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Pos [32/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Pos [33/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 539 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Pos [34/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 539 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Pos [35/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 539 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Pos [36/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 539 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Pos [37/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 539 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Pos [38/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 539 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SEVONPEND_Pos [39/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 583 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Pos [40/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 583 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Pos [41/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 583 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Pos [42/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 583 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Pos [43/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 583 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Pos [44/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 583 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SEVONPEND_Pos [45/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 632 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SEVONPEND_Pos [46/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 632 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Pos [47/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 632 of file core_cm35p.h.

◆ SCB_SCR_SEVONPEND_Pos [48/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 640 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Pos [49/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 640 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Pos [50/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 640 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SEVONPEND_Pos [51/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 640 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Pos [52/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 640 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SEVONPEND_Pos [53/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 640 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SEVONPEND_Pos [54/54]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 641 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [1/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Msk [2/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Msk [3/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Msk [4/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Msk [5/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Msk [6/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Msk [7/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Msk [8/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Msk [9/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 431 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Msk [10/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 431 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Msk [11/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 431 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Msk [12/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 431 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Msk [13/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 443 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Msk [14/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 443 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Msk [15/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 443 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Msk [16/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 443 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Msk [17/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 482 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Msk [18/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 482 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Msk [19/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 482 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Msk [20/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 482 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Msk [21/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 485 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Msk [22/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 485 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Msk [23/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 485 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Msk [24/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 485 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Msk [25/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Msk [26/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Msk [27/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Msk [28/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Msk [29/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Msk [30/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Msk [31/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Msk [32/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Msk [33/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 543 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Msk [34/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 543 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Msk [35/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 543 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Msk [36/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 543 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Msk [37/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 543 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Msk [38/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 543 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Msk [39/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 587 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Msk [40/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 587 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Msk [41/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 587 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Msk [42/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 587 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Msk [43/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 587 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Msk [44/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 587 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Msk [45/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 639 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [46/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 639 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Msk [47/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 639 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEP_Msk [48/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 647 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Msk [49/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 647 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Msk [50/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 647 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Msk [51/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 647 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [52/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 647 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [53/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 647 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [54/54]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 648 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [1/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Pos [2/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Pos [3/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Pos [4/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Pos [5/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Pos [6/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Pos [7/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Pos [8/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Pos [9/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 430 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Pos [10/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 430 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Pos [11/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 430 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Pos [12/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 430 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Pos [13/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 442 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Pos [14/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 442 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Pos [15/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 442 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Pos [16/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 442 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Pos [17/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 481 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Pos [18/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 481 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Pos [19/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 481 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Pos [20/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 481 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Pos [21/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 484 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Pos [22/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 484 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Pos [23/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 484 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Pos [24/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 484 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Pos [25/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Pos [26/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Pos [27/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Pos [28/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Pos [29/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Pos [30/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Pos [31/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Pos [32/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Pos [33/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 542 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Pos [34/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 542 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Pos [35/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 542 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Pos [36/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 542 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Pos [37/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 542 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Pos [38/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 542 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Pos [39/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 586 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Pos [40/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 586 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Pos [41/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 586 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Pos [42/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 586 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Pos [43/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 586 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Pos [44/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 586 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Pos [45/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 638 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEP_Pos [46/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 638 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Pos [47/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 638 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [48/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 646 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Pos [49/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 646 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Pos [50/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 646 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [51/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 646 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Pos [52/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 646 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [53/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 646 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [54/54]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 647 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [1/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [2/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [3/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [4/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [5/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [6/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [7/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [8/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [9/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 636 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [10/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 636 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [11/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 636 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [12/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 644 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [13/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 644 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [14/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 644 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [15/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 644 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [16/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 644 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [17/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 644 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [18/18]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 645 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [1/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [2/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [3/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [4/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [5/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [6/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [7/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [8/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [9/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 635 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [10/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 635 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [11/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 635 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [12/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 643 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [13/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 643 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [14/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 643 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [15/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 643 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [16/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 643 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [17/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 643 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [18/18]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 644 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [1/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [2/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [3/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [4/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [5/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [6/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [7/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [8/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [9/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 434 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [10/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 434 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [11/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 434 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [12/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 434 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [13/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 446 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [14/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 446 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [15/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 446 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [16/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 446 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [17/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 485 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [18/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 485 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [19/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 485 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [20/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 485 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [21/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 488 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [22/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 488 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [23/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 488 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [24/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 488 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [25/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [26/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [27/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [28/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [29/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [30/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [31/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [32/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [33/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 546 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [34/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 546 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [35/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 546 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [36/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 546 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [37/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 546 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [38/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 546 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [39/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 590 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [40/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 590 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [41/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 590 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [42/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 590 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [43/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 590 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [44/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 590 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [45/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 642 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [46/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 642 of file core_cm35p.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [47/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 642 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [48/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 650 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [49/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 650 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [50/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 650 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [51/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 650 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [52/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 650 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [53/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 650 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [54/54]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 651 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [1/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [2/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [3/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [4/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [5/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [6/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [7/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [8/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [9/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 433 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [10/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 433 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [11/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 433 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [12/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 433 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [13/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 445 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [14/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 445 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [15/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 445 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [16/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 445 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [17/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 484 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [18/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 484 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [19/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 484 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [20/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 484 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [21/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 487 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [22/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 487 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [23/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 487 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [24/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 487 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [25/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [26/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [27/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [28/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [29/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [30/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [31/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [32/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [33/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 545 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [34/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 545 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [35/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 545 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [36/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 545 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [37/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 545 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [38/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 545 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [39/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 589 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [40/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 589 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [41/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 589 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [42/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 589 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [43/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 589 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [44/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 589 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [45/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 641 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [46/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 641 of file core_cm35p.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [47/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 641 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [48/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 649 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [49/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 649 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [50/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 649 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [51/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 649 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [52/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 649 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [53/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 649 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [54/54]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 650 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [1/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 544 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [2/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 544 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [3/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 544 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [4/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 544 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [5/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 547 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [6/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 547 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [7/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 547 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [8/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 547 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [9/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 605 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [10/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 605 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [11/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 605 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [12/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 605 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [13/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 605 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [14/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 605 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [15/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 658 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [16/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 658 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [17/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 658 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [18/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 658 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [19/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 658 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [20/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 658 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [21/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 725 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [22/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 725 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [23/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 725 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [24/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 733 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [25/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 733 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [26/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 733 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [27/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 733 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [28/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 733 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [29/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 733 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [30/30]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 734 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [1/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 543 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [2/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 543 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [3/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 543 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [4/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 543 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [5/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 546 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [6/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 546 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [7/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 546 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [8/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 546 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [9/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 604 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [10/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 604 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [11/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 604 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [12/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 604 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [13/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 604 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [14/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 604 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [15/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 657 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [16/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 657 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [17/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 657 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [18/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 657 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [19/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 657 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [20/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 657 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [21/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 724 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [22/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 724 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [23/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 724 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [24/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 732 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [25/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 732 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [26/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 732 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [27/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 732 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [28/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 732 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [29/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 732 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [30/30]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 733 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [1/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 511 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [2/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 511 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [3/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 511 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [4/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 511 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [5/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 514 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [6/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 514 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [7/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 514 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [8/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 514 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [9/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 572 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [10/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 572 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [11/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 572 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [12/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 572 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [13/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 572 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [14/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 572 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [15/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 625 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [16/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 625 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [17/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 625 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [18/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 625 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [19/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 625 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [20/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 625 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [21/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 683 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [22/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 683 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [23/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 683 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [24/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 691 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [25/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 691 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [26/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 691 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [27/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 691 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [28/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 691 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [29/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 691 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [30/30]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 692 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [1/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 510 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [2/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 510 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [3/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 510 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [4/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 510 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [5/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 513 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [6/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 513 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [7/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 513 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [8/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 513 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [9/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 571 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [10/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 571 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [11/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 571 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [12/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 571 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [13/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 571 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [14/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 571 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [15/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 624 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [16/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 624 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [17/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 624 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [18/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 624 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [19/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 624 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [20/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 624 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [21/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 682 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [22/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 682 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [23/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 682 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [24/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 690 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [25/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 690 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [26/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 690 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [27/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 690 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [28/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 690 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [29/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 690 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [30/30]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 691 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [1/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 520 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [2/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 520 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [3/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 520 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [4/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 520 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [5/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 523 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [6/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 523 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [7/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 523 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [8/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 523 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [9/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 581 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [10/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 581 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [11/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 581 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [12/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 581 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [13/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 581 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [14/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 581 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [15/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 634 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [16/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 634 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [17/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 634 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [18/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 634 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [19/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 634 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [20/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 634 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [21/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 692 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [22/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 692 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [23/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 692 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [24/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 700 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [25/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 700 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [26/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 700 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [27/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 700 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [28/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 700 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [29/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 700 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [30/30]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 701 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [1/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 519 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [2/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 519 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [3/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 519 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [4/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 519 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [5/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 522 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [6/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 522 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [7/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 522 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [8/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 522 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [9/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 580 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [10/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 580 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [11/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 580 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [12/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 580 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [13/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 580 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [14/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 580 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [15/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 633 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [16/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 633 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [17/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 633 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [18/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 633 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [19/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 633 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [20/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 633 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [21/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 691 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [22/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 691 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [23/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 691 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [24/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 699 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [25/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 699 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [26/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 699 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [27/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 699 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [28/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 699 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [29/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 699 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [30/30]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 700 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [1/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [2/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [3/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [4/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [5/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [6/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [7/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [8/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [9/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 722 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [10/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 722 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [11/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 722 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [12/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 730 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [13/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 730 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [14/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 730 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [15/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 730 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [16/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 730 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [17/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 730 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [18/18]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 731 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [1/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [2/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [3/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [4/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [5/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [6/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [7/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [8/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [9/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 721 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [10/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 721 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [11/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 721 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [12/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 729 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [13/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 729 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [14/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 729 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [15/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 729 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [16/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 729 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [17/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 729 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [18/18]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 730 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [1/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [2/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [3/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [4/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [5/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [6/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [7/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [8/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [9/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 671 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [10/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 671 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [11/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 671 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [12/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 679 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [13/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 679 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [14/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 679 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [15/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 679 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [16/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 679 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [17/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 679 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [18/18]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 680 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [1/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [2/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [3/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [4/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [5/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [6/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [7/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [8/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [9/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 670 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [10/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 670 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [11/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 670 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [12/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 678 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [13/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 678 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [14/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 678 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [15/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 678 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [16/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 678 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [17/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 678 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [18/18]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 679 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [1/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 547 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [2/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 547 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [3/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 547 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [4/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 547 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [5/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 550 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [6/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 550 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [7/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 550 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [8/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 550 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [9/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 608 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [10/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 608 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [11/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 608 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [12/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 608 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [13/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 608 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [14/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 608 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [15/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 661 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [16/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 661 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [17/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 661 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [18/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 661 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [19/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 661 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [20/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 661 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [21/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 728 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [22/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 728 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [23/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 728 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [24/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 736 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [25/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 736 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [26/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 736 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [27/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 736 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [28/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 736 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [29/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 736 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [30/30]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 737 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [1/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 546 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [2/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 546 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [3/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 546 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [4/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 546 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [5/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 549 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [6/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 549 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [7/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 549 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [8/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 549 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [9/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 607 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [10/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 607 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [11/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 607 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [12/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 607 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [13/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 607 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [14/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 607 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [15/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 660 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [16/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 660 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [17/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 660 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [18/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 660 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [19/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 660 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [20/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 660 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [21/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 727 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [22/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 727 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [23/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 727 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [24/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 735 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [25/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 735 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [26/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 735 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [27/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 735 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [28/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 735 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [29/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 735 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [30/30]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 736 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [1/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 514 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [2/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 514 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [3/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 514 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [4/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 514 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [5/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 517 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [6/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 517 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [7/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 517 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [8/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 517 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [9/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 575 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [10/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 575 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [11/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 575 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [12/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 575 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [13/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 575 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [14/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 575 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [15/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 628 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [16/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 628 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [17/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 628 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [18/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 628 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [19/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 628 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [20/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 628 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [21/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 686 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [22/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 686 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [23/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 686 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [24/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 694 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [25/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 694 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [26/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 694 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [27/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 694 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [28/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 694 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [29/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 694 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [30/30]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 695 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [1/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 513 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [2/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 513 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [3/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 513 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [4/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 513 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [5/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 516 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [6/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 516 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [7/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 516 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [8/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 516 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [9/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 574 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [10/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 574 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [11/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 574 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [12/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 574 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [13/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 574 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [14/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 574 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [15/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 627 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [16/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 627 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [17/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 627 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [18/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 627 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [19/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 627 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [20/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 627 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [21/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 685 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [22/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 685 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [23/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 685 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [24/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 693 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [25/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 693 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [26/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 693 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [27/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 693 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [28/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 693 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [29/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 693 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [30/30]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 694 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [1/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 523 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [2/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 523 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [3/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 523 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [4/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 523 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [5/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 526 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [6/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 526 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [7/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 526 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [8/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 526 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [9/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 584 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [10/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 584 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [11/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 584 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [12/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 584 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [13/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 584 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [14/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 584 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [15/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 637 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [16/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 637 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [17/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 637 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [18/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 637 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [19/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 637 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [20/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 637 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [21/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 695 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [22/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 695 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [23/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 695 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [24/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 703 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [25/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 703 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [26/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 703 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [27/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 703 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [28/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 703 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [29/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 703 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [30/30]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 704 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [1/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 522 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [2/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 522 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [3/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 522 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [4/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 522 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [5/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 525 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [6/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 525 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [7/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 525 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [8/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 525 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [9/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 583 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [10/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 583 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [11/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 583 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [12/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 583 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [13/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 583 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [14/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 583 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [15/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 636 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [16/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 636 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [17/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 636 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [18/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 636 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [19/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 636 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [20/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 636 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [21/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 694 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [22/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 694 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [23/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 694 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [24/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 702 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [25/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 702 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [26/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 702 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [27/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 702 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [28/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 702 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [29/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 702 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [30/30]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 703 of file core_armv81mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [1/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 535 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Msk [2/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 535 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Msk [3/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 535 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Msk [4/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 535 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Msk [5/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 538 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Msk [6/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 538 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Msk [7/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 538 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Msk [8/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 538 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Msk [9/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 596 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Msk [10/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 596 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Msk [11/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 596 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Msk [12/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 596 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Msk [13/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 596 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Msk [14/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 596 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Msk [15/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 649 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Msk [16/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 649 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Msk [17/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 649 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Msk [18/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 649 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Msk [19/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 649 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Msk [20/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 649 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Msk [21/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 707 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Msk [22/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 707 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [23/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 707 of file core_cm35p.h.

◆ SCB_SHCSR_MONITORACT_Msk [24/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 715 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Msk [25/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 715 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [26/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 715 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Msk [27/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 715 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [28/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 715 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Msk [29/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 715 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [30/30]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 716 of file core_armv81mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [1/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 534 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Pos [2/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 534 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Pos [3/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 534 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Pos [4/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 534 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Pos [5/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 537 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Pos [6/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 537 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Pos [7/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 537 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Pos [8/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 537 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Pos [9/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 595 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Pos [10/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 595 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Pos [11/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 595 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Pos [12/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 595 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Pos [13/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 595 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Pos [14/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 595 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Pos [15/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 648 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Pos [16/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 648 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Pos [17/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 648 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Pos [18/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 648 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Pos [19/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 648 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Pos [20/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 648 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Pos [21/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 706 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [22/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 706 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Pos [23/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 706 of file core_cm35p.h.

◆ SCB_SHCSR_MONITORACT_Pos [24/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 714 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [25/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 714 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Pos [26/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 714 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [27/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 714 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [28/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 714 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Pos [29/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 714 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Pos [30/30]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 715 of file core_armv81mml.h.

◆ SCB_SHCSR_NMIACT_Msk [1/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_NMIACT_Msk [2/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_NMIACT_Msk [3/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Msk [4/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Msk [5/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Msk [6/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_NMIACT_Msk [7/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_NMIACT_Msk [8/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Msk [9/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 713 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_NMIACT_Msk [10/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 713 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Msk [11/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 713 of file core_cm35p.h.

◆ SCB_SHCSR_NMIACT_Msk [12/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 721 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Msk [13/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 721 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_NMIACT_Msk [14/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 721 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Msk [15/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 721 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Msk [16/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 721 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_NMIACT_Msk [17/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 721 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_NMIACT_Msk [18/18]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 722 of file core_armv81mml.h.

◆ SCB_SHCSR_NMIACT_Pos [1/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Pos [2/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_NMIACT_Pos [3/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Pos [4/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_NMIACT_Pos [5/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_NMIACT_Pos [6/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Pos [7/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_NMIACT_Pos [8/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Pos [9/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 712 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Pos [10/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 712 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_NMIACT_Pos [11/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 712 of file core_cm35p.h.

◆ SCB_SHCSR_NMIACT_Pos [12/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 720 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_NMIACT_Pos [13/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 720 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Pos [14/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 720 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Pos [15/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 720 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_NMIACT_Pos [16/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 720 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Pos [17/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 720 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_NMIACT_Pos [18/18]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 721 of file core_armv81mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [1/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 532 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Msk [2/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 532 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Msk [3/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 532 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Msk [4/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 532 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Msk [5/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Msk [6/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Msk [7/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Msk [8/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Msk [9/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Msk [10/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Msk [11/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Msk [12/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Msk [13/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 535 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Msk [14/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 535 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Msk [15/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 535 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Msk [16/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 535 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Msk [17/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 593 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Msk [18/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 593 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Msk [19/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 593 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Msk [20/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 593 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Msk [21/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 593 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Msk [22/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 593 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Msk [23/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 646 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Msk [24/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 646 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Msk [25/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 646 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Msk [26/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 646 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Msk [27/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 646 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Msk [28/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 646 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Msk [29/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 704 of file core_cm35p.h.

◆ SCB_SHCSR_PENDSVACT_Msk [30/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 704 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Msk [31/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 704 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [32/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 712 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [33/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 712 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [34/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 712 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Msk [35/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 712 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [36/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 712 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Msk [37/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 712 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Msk [38/38]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 713 of file core_armv81mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [1/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 531 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Pos [2/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 531 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Pos [3/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 531 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Pos [4/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 531 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Pos [5/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Pos [6/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Pos [7/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Pos [8/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Pos [9/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Pos [10/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Pos [11/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Pos [12/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Pos [13/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 534 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Pos [14/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 534 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Pos [15/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 534 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Pos [16/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 534 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Pos [17/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 592 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Pos [18/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 592 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Pos [19/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 592 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Pos [20/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 592 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Pos [21/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 592 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Pos [22/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 592 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Pos [23/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 645 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Pos [24/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 645 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Pos [25/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 645 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Pos [26/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 645 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Pos [27/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 645 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Pos [28/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 645 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Pos [29/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 703 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [30/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 703 of file core_cm35p.h.

◆ SCB_SHCSR_PENDSVACT_Pos [31/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 703 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Pos [32/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 711 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [33/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 711 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [34/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 711 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Pos [35/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 711 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Pos [36/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 711 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [37/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 711 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Pos [38/38]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 712 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [1/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 716 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [2/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 716 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [3/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 716 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [4/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 724 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [5/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 724 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [6/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 724 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [7/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 724 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [8/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 724 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [9/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 724 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [10/10]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 725 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [1/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 715 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [2/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 715 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [3/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 715 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [4/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 723 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [5/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 723 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [6/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 723 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [7/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 723 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [8/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 723 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [9/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 723 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [10/10]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 724 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [1/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 677 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [2/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 677 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [3/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 677 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [4/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 685 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [5/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 685 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [6/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 685 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [7/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 685 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [8/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 685 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [9/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 685 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [10/10]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 686 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [1/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 676 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [2/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 676 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [3/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 676 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [4/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 684 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [5/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 684 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [6/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 684 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [7/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 684 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [8/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 684 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [9/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 684 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [10/10]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 685 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [1/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 674 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [2/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 674 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [3/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 674 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [4/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 682 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [5/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 682 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [6/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 682 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [7/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 682 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [8/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 682 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [9/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 682 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [10/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 683 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [1/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 673 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [2/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 673 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [3/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 673 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [4/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 681 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [5/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 681 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [6/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 681 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [7/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 681 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [8/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 681 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [9/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 681 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [10/10]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 682 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [1/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Msk [2/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Msk [3/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Msk [4/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Msk [5/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Msk [6/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Msk [7/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Msk [8/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Msk [9/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 538 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Msk [10/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 538 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Msk [11/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 538 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Msk [12/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 538 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Msk [13/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 541 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Msk [14/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 541 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Msk [15/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 541 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Msk [16/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 541 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Msk [17/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 599 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Msk [18/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 599 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Msk [19/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 599 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Msk [20/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 599 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Msk [21/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 599 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Msk [22/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 599 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Msk [23/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 652 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Msk [24/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 652 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Msk [25/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 652 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Msk [26/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 652 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Msk [27/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 652 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Msk [28/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 652 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Msk [29/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 710 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLACT_Msk [30/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 710 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Msk [31/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 710 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [32/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 718 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [33/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 718 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Msk [34/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 718 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Msk [35/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 718 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Msk [36/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 718 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [37/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 718 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [38/38]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 719 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [1/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Pos [2/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Pos [3/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Pos [4/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Pos [5/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Pos [6/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Pos [7/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Pos [8/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Pos [9/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 537 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Pos [10/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 537 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Pos [11/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 537 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Pos [12/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 537 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Pos [13/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 540 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Pos [14/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 540 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Pos [15/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 540 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Pos [16/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 540 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Pos [17/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 598 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Pos [18/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 598 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Pos [19/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 598 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Pos [20/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 598 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Pos [21/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 598 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Pos [22/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 598 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Pos [23/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 651 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Pos [24/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 651 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Pos [25/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 651 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Pos [26/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 651 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Pos [27/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 651 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Pos [28/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 651 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Pos [29/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 709 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLACT_Pos [30/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 709 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Pos [31/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 709 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [32/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 717 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [33/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 717 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Pos [34/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 717 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [35/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 717 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Pos [36/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 717 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Pos [37/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 717 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [38/38]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 718 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [1/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [2/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [3/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [4/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [5/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [6/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [7/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [8/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [9/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 445 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [10/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 445 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [11/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 445 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [12/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 445 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [13/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 457 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [14/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 457 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [15/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 457 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [16/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 457 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [17/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 517 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [18/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 517 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [19/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 517 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [20/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 517 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [21/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 520 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [22/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 520 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [23/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 520 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [24/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 520 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [25/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [26/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [27/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [28/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [29/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [30/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [31/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [32/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [33/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 578 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [34/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 578 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [35/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 578 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [36/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 578 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [37/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 578 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [38/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 578 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [39/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 631 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [40/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 631 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [41/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 631 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [42/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 631 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [43/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 631 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [44/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 631 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [45/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 689 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [46/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 689 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [47/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 689 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [48/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 697 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [49/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 697 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [50/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 697 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [51/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 697 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [52/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 697 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [53/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 697 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [54/54]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 698 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [1/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [2/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [3/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [4/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [5/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [6/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [7/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [8/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [9/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 444 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [10/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 444 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [11/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 444 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [12/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 444 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [13/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 456 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [14/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 456 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [15/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 456 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [16/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 456 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [17/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 516 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [18/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 516 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [19/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 516 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [20/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 516 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [21/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 519 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [22/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 519 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [23/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 519 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [24/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 519 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [25/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [26/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [27/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [28/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [29/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [30/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [31/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [32/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [33/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 577 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [34/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 577 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [35/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 577 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [36/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 577 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [37/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 577 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [38/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 577 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [39/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 630 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [40/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 630 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [41/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 630 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [42/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 630 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [43/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 630 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [44/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 630 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [45/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 688 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [46/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 688 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [47/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 688 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [48/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 696 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [49/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 696 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [50/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 696 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [51/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 696 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [52/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 696 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [53/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 696 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [54/54]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 697 of file core_armv81mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [1/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 529 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [2/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 529 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [3/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 529 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [4/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 529 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [5/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [6/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [7/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [8/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [9/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [10/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [11/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [12/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [13/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 532 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [14/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 532 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [15/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 532 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [16/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 532 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [17/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 590 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [18/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 590 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [19/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 590 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [20/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 590 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [21/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 590 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [22/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 590 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [23/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 643 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [24/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 643 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [25/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 643 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [26/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 643 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [27/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 643 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [28/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 643 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [29/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 701 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [30/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 701 of file core_cm35p.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [31/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 701 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [32/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 709 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [33/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 709 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [34/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 709 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [35/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 709 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [36/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 709 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [37/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 709 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [38/38]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 710 of file core_armv81mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [1/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 528 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [2/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 528 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [3/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 528 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [4/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 528 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [5/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [6/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [7/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [8/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [9/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [10/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [11/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [12/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [13/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 531 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [14/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 531 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [15/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 531 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [16/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 531 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [17/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 589 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [18/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 589 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [19/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 589 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [20/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 589 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [21/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 589 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [22/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 589 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [23/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 642 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [24/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 642 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [25/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 642 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [26/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 642 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [27/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 642 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [28/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 642 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [29/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 700 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [30/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 700 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [31/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 700 of file core_cm35p.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [32/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 708 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [33/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 708 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [34/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 708 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [35/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 708 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [36/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 708 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [37/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 708 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [38/38]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 709 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [1/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 541 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [2/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 541 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [3/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 541 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [4/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 541 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [5/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 544 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [6/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 544 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [7/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 544 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [8/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 544 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [9/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 602 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [10/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 602 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [11/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 602 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [12/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 602 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [13/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 602 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [14/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 602 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [15/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 655 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [16/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 655 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [17/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 655 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [18/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 655 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [19/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 655 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [20/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 655 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [21/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 719 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [22/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 719 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [23/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 719 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [24/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 727 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [25/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 727 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [26/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 727 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [27/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 727 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [28/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 727 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [29/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 727 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [30/30]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 728 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [1/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 540 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [2/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 540 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [3/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 540 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [4/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 540 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [5/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 543 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [6/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 543 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [7/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 543 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [8/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 543 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [9/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 601 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [10/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 601 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [11/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 601 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [12/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 601 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [13/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 601 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [14/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 601 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [15/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 654 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [16/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 654 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [17/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 654 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [18/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 654 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [19/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 654 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [20/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 654 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [21/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 718 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [22/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 718 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [23/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 718 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [24/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 726 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [25/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 726 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [26/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 726 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [27/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 726 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [28/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 726 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [29/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 726 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [30/30]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 727 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [1/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 508 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [2/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 508 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [3/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 508 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [4/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 508 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [5/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 511 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [6/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 511 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [7/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 511 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [8/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 511 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [9/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 569 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [10/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 569 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [11/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 569 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [12/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 569 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [13/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 569 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [14/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 569 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [15/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 622 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [16/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 622 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [17/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 622 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [18/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 622 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [19/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 622 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [20/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 622 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [21/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 680 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [22/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 680 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [23/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 680 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [24/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 688 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [25/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 688 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [26/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 688 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [27/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 688 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [28/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 688 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [29/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 688 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [30/30]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 689 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [1/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 507 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [2/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 507 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [3/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 507 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [4/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 507 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [5/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 510 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [6/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 510 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [7/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 510 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [8/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 510 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [9/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 568 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [10/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 568 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [11/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 568 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [12/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 568 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [13/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 568 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [14/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 568 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [15/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 621 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [16/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 621 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [17/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 621 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [18/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 621 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [19/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 621 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [20/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 621 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [21/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 679 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [22/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 679 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [23/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 679 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [24/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 687 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [25/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 687 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [26/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 687 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [27/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 687 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [28/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 687 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [29/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 687 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [30/30]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 688 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [1/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 526 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [2/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 526 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [3/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 526 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [4/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 526 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [5/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 529 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [6/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 529 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [7/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 529 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [8/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 529 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [9/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 587 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [10/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 587 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [11/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 587 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [12/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 587 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [13/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 587 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [14/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 587 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [15/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 640 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [16/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 640 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [17/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 640 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [18/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 640 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [19/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 640 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [20/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 640 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [21/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 698 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [22/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 698 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [23/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 698 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [24/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 706 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [25/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 706 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [26/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 706 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [27/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 706 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [28/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 706 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [29/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 706 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [30/30]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 707 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [1/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 525 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [2/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 525 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [3/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 525 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [4/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 525 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [5/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 528 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [6/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 528 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [7/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 528 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [8/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 528 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [9/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 586 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [10/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 586 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [11/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 586 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [12/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 586 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [13/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 586 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [14/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 586 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [15/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 639 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [16/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 639 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [17/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 639 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [18/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 639 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [19/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 639 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [20/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 639 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [21/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 697 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [22/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 697 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [23/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 697 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [24/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 705 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [25/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 705 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [26/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 705 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [27/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 705 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [28/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 705 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [29/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 705 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [30/30]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 706 of file core_armv81mml.h.

◆ SCB_STIR_INTID_Msk [1/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 813 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Msk [2/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 813 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_STIR_INTID_Msk [3/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 813 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Msk [4/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 813 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Msk [5/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 813 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Msk [6/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 813 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Msk [7/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 893 of file core_cm35p.h.

◆ SCB_STIR_INTID_Msk [8/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 893 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_STIR_INTID_Msk [9/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 893 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_STIR_INTID_Msk [10/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 901 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_STIR_INTID_Msk [11/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 901 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_STIR_INTID_Msk [12/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 901 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_STIR_INTID_Msk [13/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 901 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_STIR_INTID_Msk [14/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 901 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_STIR_INTID_Msk [15/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 901 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_STIR_INTID_Msk [16/16]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 902 of file core_armv81mml.h.

◆ SCB_STIR_INTID_Pos [1/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 812 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Pos [2/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 812 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Pos [3/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 812 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_STIR_INTID_Pos [4/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 812 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Pos [5/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 812 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Pos [6/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 812 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_STIR_INTID_Pos [7/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 892 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_STIR_INTID_Pos [8/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 892 of file core_cm35p.h.

◆ SCB_STIR_INTID_Pos [9/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 892 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_STIR_INTID_Pos [10/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 900 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_STIR_INTID_Pos [11/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 900 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_STIR_INTID_Pos [12/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 900 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_STIR_INTID_Pos [13/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 900 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_STIR_INTID_Pos [14/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 900 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_STIR_INTID_Pos [15/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 900 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_STIR_INTID_Pos [16/16]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 901 of file core_armv81mml.h.

◆ SCB_VTOR_TBLBASE_Msk [1/4]

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

Definition at line 450 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLBASE_Msk [2/4]

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

Definition at line 450 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLBASE_Msk [3/4]

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

Definition at line 450 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLBASE_Msk [4/4]

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

Definition at line 450 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLBASE_Pos [1/4]

#define SCB_VTOR_TBLBASE_Pos   29U

SCB VTOR: TBLBASE Position

Definition at line 449 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLBASE_Pos [2/4]

#define SCB_VTOR_TBLBASE_Pos   29U

SCB VTOR: TBLBASE Position

Definition at line 449 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLBASE_Pos [3/4]

#define SCB_VTOR_TBLBASE_Pos   29U

SCB VTOR: TBLBASE Position

Definition at line 449 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLBASE_Pos [4/4]

#define SCB_VTOR_TBLBASE_Pos   29U

SCB VTOR: TBLBASE Position

Definition at line 449 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Msk [1/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 408 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_VTOR_TBLOFF_Msk [2/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 408 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_VTOR_TBLOFF_Msk [3/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 408 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_VTOR_TBLOFF_Msk [4/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 408 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_VTOR_TBLOFF_Msk [5/34]

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 453 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Msk [6/34]

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 453 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Msk [7/34]

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 453 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Msk [8/34]

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 453 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Msk [9/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 455 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_VTOR_TBLOFF_Msk [10/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 455 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_VTOR_TBLOFF_Msk [11/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 455 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_VTOR_TBLOFF_Msk [12/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 455 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_VTOR_TBLOFF_Msk [13/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 514 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Msk [14/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 514 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Msk [15/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 514 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Msk [16/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 514 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Msk [17/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 514 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Msk [18/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 514 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Msk [19/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 558 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Msk [20/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 558 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Msk [21/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 558 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Msk [22/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 558 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Msk [23/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 558 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Msk [24/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 558 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Msk [25/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 601 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Msk [26/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 601 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_VTOR_TBLOFF_Msk [27/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 601 of file core_cm35p.h.

◆ SCB_VTOR_TBLOFF_Msk [28/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 609 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_VTOR_TBLOFF_Msk [29/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 609 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Msk [30/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 609 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_VTOR_TBLOFF_Msk [31/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 609 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_VTOR_TBLOFF_Msk [32/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 609 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Msk [33/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 609 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Msk [34/34]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 610 of file core_armv81mml.h.

◆ SCB_VTOR_TBLOFF_Pos [1/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 407 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_VTOR_TBLOFF_Pos [2/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 407 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_VTOR_TBLOFF_Pos [3/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 407 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_VTOR_TBLOFF_Pos [4/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 407 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc000.h.

◆ SCB_VTOR_TBLOFF_Pos [5/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 452 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Pos [6/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 452 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Pos [7/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 452 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Pos [8/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 452 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ SCB_VTOR_TBLOFF_Pos [9/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 454 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_VTOR_TBLOFF_Pos [10/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 454 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_VTOR_TBLOFF_Pos [11/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 454 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_VTOR_TBLOFF_Pos [12/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 454 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ SCB_VTOR_TBLOFF_Pos [13/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 513 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Pos [14/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 513 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Pos [15/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 513 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Pos [16/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 513 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Pos [17/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 513 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Pos [18/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 513 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ SCB_VTOR_TBLOFF_Pos [19/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 557 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Pos [20/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 557 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Pos [21/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 557 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Pos [22/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 557 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Pos [23/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 557 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Pos [24/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 557 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ SCB_VTOR_TBLOFF_Pos [25/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 600 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_VTOR_TBLOFF_Pos [26/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 600 of file core_cm35p.h.

◆ SCB_VTOR_TBLOFF_Pos [27/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 600 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Pos [28/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 608 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Pos [29/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 608 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Pos [30/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 608 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_VTOR_TBLOFF_Pos [31/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 608 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_VTOR_TBLOFF_Pos [32/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 608 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ SCB_VTOR_TBLOFF_Pos [33/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 608 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Pos [34/34]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 609 of file core_armv81mml.h.


picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:04