stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_CM3_H_GENERIC
32 #define __CORE_CM3_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 /* CMSIS CM3 definitions */
66 #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
69  __CM3_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (3U)
76 #define __FPU_USED 0U
77 
78 #if defined ( __CC_ARM )
79  #if defined __TARGET_FPU_VFP
80  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81  #endif
82 
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84  #if defined __ARM_PCS_VFP
85  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86  #endif
87 
88 #elif defined ( __GNUC__ )
89  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91  #endif
92 
93 #elif defined ( __ICCARM__ )
94  #if defined __ARMVFP__
95  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96  #endif
97 
98 #elif defined ( __TI_ARM__ )
99  #if defined __TI_VFP_SUPPORT__
100  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101  #endif
102 
103 #elif defined ( __TASKING__ )
104  #if defined __FPU_VFP__
105  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #endif
107 
108 #elif defined ( __CSMC__ )
109  #if ( __CSMC__ & 0x400U)
110  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111  #endif
112 
113 #endif
114 
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116 
117 
118 #ifdef __cplusplus
119 }
120 #endif
121 
122 #endif /* __CORE_CM3_H_GENERIC */
123 
124 #ifndef __CMSIS_GENERIC
125 
126 #ifndef __CORE_CM3_H_DEPENDANT
127 #define __CORE_CM3_H_DEPENDANT
128 
129 #ifdef __cplusplus
130  extern "C" {
131 #endif
132 
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135  #ifndef __CM3_REV
136  #define __CM3_REV 0x0200U
137  #warning "__CM3_REV not defined in device header file; using default!"
138  #endif
139 
140  #ifndef __MPU_PRESENT
141  #define __MPU_PRESENT 0U
142  #warning "__MPU_PRESENT not defined in device header file; using default!"
143  #endif
144 
145  #ifndef __NVIC_PRIO_BITS
146  #define __NVIC_PRIO_BITS 3U
147  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
148  #endif
149 
150  #ifndef __Vendor_SysTickConfig
151  #define __Vendor_SysTickConfig 0U
152  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
153  #endif
154 #endif
155 
156 /* IO definitions (access restrictions to peripheral registers) */
164 #ifdef __cplusplus
165  #define __I volatile
166 #else
167  #define __I volatile const
168 #endif
169 #define __O volatile
170 #define __IO volatile
172 /* following defines should be used for structure members */
173 #define __IM volatile const
174 #define __OM volatile
175 #define __IOM volatile
177 
181 /*******************************************************************************
182  * Register Abstraction
183  Core Register contain:
184  - Core Register
185  - Core NVIC Register
186  - Core SCB Register
187  - Core SysTick Register
188  - Core Debug Register
189  - Core MPU Register
190  ******************************************************************************/
191 
206 typedef union
207 {
208  struct
209  {
210  uint32_t _reserved0:27;
211  uint32_t Q:1;
212  uint32_t V:1;
213  uint32_t C:1;
214  uint32_t Z:1;
215  uint32_t N:1;
216  } b;
217  uint32_t w;
218 } APSR_Type;
219 
220 /* APSR Register Definitions */
221 #define APSR_N_Pos 31U
222 #define APSR_N_Msk (1UL << APSR_N_Pos)
224 #define APSR_Z_Pos 30U
225 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
227 #define APSR_C_Pos 29U
228 #define APSR_C_Msk (1UL << APSR_C_Pos)
230 #define APSR_V_Pos 28U
231 #define APSR_V_Msk (1UL << APSR_V_Pos)
233 #define APSR_Q_Pos 27U
234 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
240 typedef union
241 {
242  struct
243  {
244  uint32_t ISR:9;
245  uint32_t _reserved0:23;
246  } b;
247  uint32_t w;
248 } IPSR_Type;
249 
250 /* IPSR Register Definitions */
251 #define IPSR_ISR_Pos 0U
252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
258 typedef union
259 {
260  struct
261  {
262  uint32_t ISR:9;
263  uint32_t _reserved0:1;
264  uint32_t ICI_IT_1:6;
265  uint32_t _reserved1:8;
266  uint32_t T:1;
267  uint32_t ICI_IT_2:2;
268  uint32_t Q:1;
269  uint32_t V:1;
270  uint32_t C:1;
271  uint32_t Z:1;
272  uint32_t N:1;
273  } b;
274  uint32_t w;
275 } xPSR_Type;
276 
277 /* xPSR Register Definitions */
278 #define xPSR_N_Pos 31U
279 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
281 #define xPSR_Z_Pos 30U
282 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
284 #define xPSR_C_Pos 29U
285 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
287 #define xPSR_V_Pos 28U
288 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
290 #define xPSR_Q_Pos 27U
291 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
293 #define xPSR_ICI_IT_2_Pos 25U
294 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
296 #define xPSR_T_Pos 24U
297 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
299 #define xPSR_ICI_IT_1_Pos 10U
300 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
302 #define xPSR_ISR_Pos 0U
303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
309 typedef union
310 {
311  struct
312  {
313  uint32_t nPRIV:1;
314  uint32_t SPSEL:1;
315  uint32_t _reserved1:30;
316  } b;
317  uint32_t w;
318 } CONTROL_Type;
319 
320 /* CONTROL Register Definitions */
321 #define CONTROL_SPSEL_Pos 1U
322 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
324 #define CONTROL_nPRIV_Pos 0U
325 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
327 
340 typedef struct
341 {
342  __IOM uint32_t ISER[8U];
343  uint32_t RESERVED0[24U];
344  __IOM uint32_t ICER[8U];
345  uint32_t RSERVED1[24U];
346  __IOM uint32_t ISPR[8U];
347  uint32_t RESERVED2[24U];
348  __IOM uint32_t ICPR[8U];
349  uint32_t RESERVED3[24U];
350  __IOM uint32_t IABR[8U];
351  uint32_t RESERVED4[56U];
352  __IOM uint8_t IP[240U];
353  uint32_t RESERVED5[644U];
354  __OM uint32_t STIR;
355 } NVIC_Type;
356 
357 /* Software Triggered Interrupt Register Definitions */
358 #define NVIC_STIR_INTID_Pos 0U
359 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
361 
374 typedef struct
375 {
376  __IM uint32_t CPUID;
377  __IOM uint32_t ICSR;
378  __IOM uint32_t VTOR;
379  __IOM uint32_t AIRCR;
380  __IOM uint32_t SCR;
381  __IOM uint32_t CCR;
382  __IOM uint8_t SHP[12U];
383  __IOM uint32_t SHCSR;
384  __IOM uint32_t CFSR;
385  __IOM uint32_t HFSR;
386  __IOM uint32_t DFSR;
387  __IOM uint32_t MMFAR;
388  __IOM uint32_t BFAR;
389  __IOM uint32_t AFSR;
390  __IM uint32_t PFR[2U];
391  __IM uint32_t DFR;
392  __IM uint32_t ADR;
393  __IM uint32_t MMFR[4U];
394  __IM uint32_t ISAR[5U];
395  uint32_t RESERVED0[5U];
396  __IOM uint32_t CPACR;
397 } SCB_Type;
398 
399 /* SCB CPUID Register Definitions */
400 #define SCB_CPUID_IMPLEMENTER_Pos 24U
401 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
403 #define SCB_CPUID_VARIANT_Pos 20U
404 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
406 #define SCB_CPUID_ARCHITECTURE_Pos 16U
407 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
409 #define SCB_CPUID_PARTNO_Pos 4U
410 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
412 #define SCB_CPUID_REVISION_Pos 0U
413 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
415 /* SCB Interrupt Control State Register Definitions */
416 #define SCB_ICSR_NMIPENDSET_Pos 31U
417 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
419 #define SCB_ICSR_PENDSVSET_Pos 28U
420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
422 #define SCB_ICSR_PENDSVCLR_Pos 27U
423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
425 #define SCB_ICSR_PENDSTSET_Pos 26U
426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
428 #define SCB_ICSR_PENDSTCLR_Pos 25U
429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
431 #define SCB_ICSR_ISRPREEMPT_Pos 23U
432 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
434 #define SCB_ICSR_ISRPENDING_Pos 22U
435 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
437 #define SCB_ICSR_VECTPENDING_Pos 12U
438 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
440 #define SCB_ICSR_RETTOBASE_Pos 11U
441 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
443 #define SCB_ICSR_VECTACTIVE_Pos 0U
444 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
446 /* SCB Vector Table Offset Register Definitions */
447 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
448 #define SCB_VTOR_TBLBASE_Pos 29U
449 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
451 #define SCB_VTOR_TBLOFF_Pos 7U
452 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
453 #else
454 #define SCB_VTOR_TBLOFF_Pos 7U
455 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
456 #endif
457 
458 /* SCB Application Interrupt and Reset Control Register Definitions */
459 #define SCB_AIRCR_VECTKEY_Pos 16U
460 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
462 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
463 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
465 #define SCB_AIRCR_ENDIANESS_Pos 15U
466 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
468 #define SCB_AIRCR_PRIGROUP_Pos 8U
469 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
471 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
472 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
474 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
475 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
477 #define SCB_AIRCR_VECTRESET_Pos 0U
478 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
480 /* SCB System Control Register Definitions */
481 #define SCB_SCR_SEVONPEND_Pos 4U
482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
484 #define SCB_SCR_SLEEPDEEP_Pos 2U
485 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
487 #define SCB_SCR_SLEEPONEXIT_Pos 1U
488 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
490 /* SCB Configuration Control Register Definitions */
491 #define SCB_CCR_STKALIGN_Pos 9U
492 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
494 #define SCB_CCR_BFHFNMIGN_Pos 8U
495 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
497 #define SCB_CCR_DIV_0_TRP_Pos 4U
498 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
500 #define SCB_CCR_UNALIGN_TRP_Pos 3U
501 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
503 #define SCB_CCR_USERSETMPEND_Pos 1U
504 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
506 #define SCB_CCR_NONBASETHRDENA_Pos 0U
507 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
509 /* SCB System Handler Control and State Register Definitions */
510 #define SCB_SHCSR_USGFAULTENA_Pos 18U
511 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
513 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
514 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
516 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
517 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
519 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
520 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
522 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
523 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
525 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
526 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
528 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
529 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
531 #define SCB_SHCSR_SYSTICKACT_Pos 11U
532 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
534 #define SCB_SHCSR_PENDSVACT_Pos 10U
535 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
537 #define SCB_SHCSR_MONITORACT_Pos 8U
538 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
540 #define SCB_SHCSR_SVCALLACT_Pos 7U
541 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
543 #define SCB_SHCSR_USGFAULTACT_Pos 3U
544 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
546 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
547 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
549 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
550 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
552 /* SCB Configurable Fault Status Register Definitions */
553 #define SCB_CFSR_USGFAULTSR_Pos 16U
554 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
556 #define SCB_CFSR_BUSFAULTSR_Pos 8U
557 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
559 #define SCB_CFSR_MEMFAULTSR_Pos 0U
560 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
562 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
563 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
564 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
566 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
567 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
569 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
570 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
572 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
573 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
575 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
576 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
578 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
579 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
580 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
582 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
583 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
585 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
586 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
588 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
589 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
591 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
592 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
594 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
595 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
597 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
598 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
599 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
601 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
602 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
604 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
605 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
607 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
608 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
610 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
611 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
613 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
614 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
616 /* SCB Hard Fault Status Register Definitions */
617 #define SCB_HFSR_DEBUGEVT_Pos 31U
618 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
620 #define SCB_HFSR_FORCED_Pos 30U
621 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
623 #define SCB_HFSR_VECTTBL_Pos 1U
624 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
626 /* SCB Debug Fault Status Register Definitions */
627 #define SCB_DFSR_EXTERNAL_Pos 4U
628 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
630 #define SCB_DFSR_VCATCH_Pos 3U
631 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
633 #define SCB_DFSR_DWTTRAP_Pos 2U
634 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
636 #define SCB_DFSR_BKPT_Pos 1U
637 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
639 #define SCB_DFSR_HALTED_Pos 0U
640 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
642 
655 typedef struct
656 {
657  uint32_t RESERVED0[1U];
658  __IM uint32_t ICTR;
659 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
660  __IOM uint32_t ACTLR;
661 #else
662  uint32_t RESERVED1[1U];
663 #endif
664 } SCnSCB_Type;
665 
666 /* Interrupt Controller Type Register Definitions */
667 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
668 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
670 /* Auxiliary Control Register Definitions */
671 
672 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
673 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
675 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U
676 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
678 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
679 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
681 
694 typedef struct
695 {
696  __IOM uint32_t CTRL;
697  __IOM uint32_t LOAD;
698  __IOM uint32_t VAL;
699  __IM uint32_t CALIB;
700 } SysTick_Type;
701 
702 /* SysTick Control / Status Register Definitions */
703 #define SysTick_CTRL_COUNTFLAG_Pos 16U
704 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
706 #define SysTick_CTRL_CLKSOURCE_Pos 2U
707 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
709 #define SysTick_CTRL_TICKINT_Pos 1U
710 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
712 #define SysTick_CTRL_ENABLE_Pos 0U
713 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
715 /* SysTick Reload Register Definitions */
716 #define SysTick_LOAD_RELOAD_Pos 0U
717 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
719 /* SysTick Current Register Definitions */
720 #define SysTick_VAL_CURRENT_Pos 0U
721 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
723 /* SysTick Calibration Register Definitions */
724 #define SysTick_CALIB_NOREF_Pos 31U
725 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
727 #define SysTick_CALIB_SKEW_Pos 30U
728 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
730 #define SysTick_CALIB_TENMS_Pos 0U
731 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
733 
746 typedef struct
747 {
748  __OM union
749  {
750  __OM uint8_t u8;
751  __OM uint16_t u16;
752  __OM uint32_t u32;
753  } PORT [32U];
754  uint32_t RESERVED0[864U];
755  __IOM uint32_t TER;
756  uint32_t RESERVED1[15U];
757  __IOM uint32_t TPR;
758  uint32_t RESERVED2[15U];
759  __IOM uint32_t TCR;
760  uint32_t RESERVED3[29U];
761  __OM uint32_t IWR;
762  __IM uint32_t IRR;
763  __IOM uint32_t IMCR;
764  uint32_t RESERVED4[43U];
765  __OM uint32_t LAR;
766  __IM uint32_t LSR;
767  uint32_t RESERVED5[6U];
768  __IM uint32_t PID4;
769  __IM uint32_t PID5;
770  __IM uint32_t PID6;
771  __IM uint32_t PID7;
772  __IM uint32_t PID0;
773  __IM uint32_t PID1;
774  __IM uint32_t PID2;
775  __IM uint32_t PID3;
776  __IM uint32_t CID0;
777  __IM uint32_t CID1;
778  __IM uint32_t CID2;
779  __IM uint32_t CID3;
780 } ITM_Type;
781 
782 /* ITM Trace Privilege Register Definitions */
783 #define ITM_TPR_PRIVMASK_Pos 0U
784 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
786 /* ITM Trace Control Register Definitions */
787 #define ITM_TCR_BUSY_Pos 23U
788 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
790 #define ITM_TCR_TraceBusID_Pos 16U
791 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
793 #define ITM_TCR_GTSFREQ_Pos 10U
794 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
796 #define ITM_TCR_TSPrescale_Pos 8U
797 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
799 #define ITM_TCR_SWOENA_Pos 4U
800 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
802 #define ITM_TCR_DWTENA_Pos 3U
803 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
805 #define ITM_TCR_SYNCENA_Pos 2U
806 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
808 #define ITM_TCR_TSENA_Pos 1U
809 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
811 #define ITM_TCR_ITMENA_Pos 0U
812 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
814 /* ITM Integration Write Register Definitions */
815 #define ITM_IWR_ATVALIDM_Pos 0U
816 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
818 /* ITM Integration Read Register Definitions */
819 #define ITM_IRR_ATREADYM_Pos 0U
820 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
822 /* ITM Integration Mode Control Register Definitions */
823 #define ITM_IMCR_INTEGRATION_Pos 0U
824 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
826 /* ITM Lock Status Register Definitions */
827 #define ITM_LSR_ByteAcc_Pos 2U
828 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
830 #define ITM_LSR_Access_Pos 1U
831 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
833 #define ITM_LSR_Present_Pos 0U
834 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
836  /* end of group CMSIS_ITM */
837 
838 
849 typedef struct
850 {
851  __IOM uint32_t CTRL;
852  __IOM uint32_t CYCCNT;
853  __IOM uint32_t CPICNT;
854  __IOM uint32_t EXCCNT;
855  __IOM uint32_t SLEEPCNT;
856  __IOM uint32_t LSUCNT;
857  __IOM uint32_t FOLDCNT;
858  __IM uint32_t PCSR;
859  __IOM uint32_t COMP0;
860  __IOM uint32_t MASK0;
861  __IOM uint32_t FUNCTION0;
862  uint32_t RESERVED0[1U];
863  __IOM uint32_t COMP1;
864  __IOM uint32_t MASK1;
865  __IOM uint32_t FUNCTION1;
866  uint32_t RESERVED1[1U];
867  __IOM uint32_t COMP2;
868  __IOM uint32_t MASK2;
869  __IOM uint32_t FUNCTION2;
870  uint32_t RESERVED2[1U];
871  __IOM uint32_t COMP3;
872  __IOM uint32_t MASK3;
873  __IOM uint32_t FUNCTION3;
874 } DWT_Type;
875 
876 /* DWT Control Register Definitions */
877 #define DWT_CTRL_NUMCOMP_Pos 28U
878 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
880 #define DWT_CTRL_NOTRCPKT_Pos 27U
881 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
883 #define DWT_CTRL_NOEXTTRIG_Pos 26U
884 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
886 #define DWT_CTRL_NOCYCCNT_Pos 25U
887 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
889 #define DWT_CTRL_NOPRFCNT_Pos 24U
890 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
892 #define DWT_CTRL_CYCEVTENA_Pos 22U
893 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
895 #define DWT_CTRL_FOLDEVTENA_Pos 21U
896 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
898 #define DWT_CTRL_LSUEVTENA_Pos 20U
899 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
901 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
902 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
904 #define DWT_CTRL_EXCEVTENA_Pos 18U
905 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
907 #define DWT_CTRL_CPIEVTENA_Pos 17U
908 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
910 #define DWT_CTRL_EXCTRCENA_Pos 16U
911 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
913 #define DWT_CTRL_PCSAMPLENA_Pos 12U
914 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
916 #define DWT_CTRL_SYNCTAP_Pos 10U
917 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
919 #define DWT_CTRL_CYCTAP_Pos 9U
920 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
922 #define DWT_CTRL_POSTINIT_Pos 5U
923 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
925 #define DWT_CTRL_POSTPRESET_Pos 1U
926 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
928 #define DWT_CTRL_CYCCNTENA_Pos 0U
929 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
931 /* DWT CPI Count Register Definitions */
932 #define DWT_CPICNT_CPICNT_Pos 0U
933 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
935 /* DWT Exception Overhead Count Register Definitions */
936 #define DWT_EXCCNT_EXCCNT_Pos 0U
937 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
939 /* DWT Sleep Count Register Definitions */
940 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
941 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
943 /* DWT LSU Count Register Definitions */
944 #define DWT_LSUCNT_LSUCNT_Pos 0U
945 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
947 /* DWT Folded-instruction Count Register Definitions */
948 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
949 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
951 /* DWT Comparator Mask Register Definitions */
952 #define DWT_MASK_MASK_Pos 0U
953 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
955 /* DWT Comparator Function Register Definitions */
956 #define DWT_FUNCTION_MATCHED_Pos 24U
957 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
959 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
960 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
962 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
963 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
965 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
966 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
968 #define DWT_FUNCTION_LNK1ENA_Pos 9U
969 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
971 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
972 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
974 #define DWT_FUNCTION_CYCMATCH_Pos 7U
975 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
977 #define DWT_FUNCTION_EMITRANGE_Pos 5U
978 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
980 #define DWT_FUNCTION_FUNCTION_Pos 0U
981 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
983  /* end of group CMSIS_DWT */
984 
985 
996 typedef struct
997 {
998  __IM uint32_t SSPSR;
999  __IOM uint32_t CSPSR;
1000  uint32_t RESERVED0[2U];
1001  __IOM uint32_t ACPR;
1002  uint32_t RESERVED1[55U];
1003  __IOM uint32_t SPPR;
1004  uint32_t RESERVED2[131U];
1005  __IM uint32_t FFSR;
1006  __IOM uint32_t FFCR;
1007  __IM uint32_t FSCR;
1008  uint32_t RESERVED3[759U];
1009  __IM uint32_t TRIGGER;
1010  __IM uint32_t FIFO0;
1011  __IM uint32_t ITATBCTR2;
1012  uint32_t RESERVED4[1U];
1013  __IM uint32_t ITATBCTR0;
1014  __IM uint32_t FIFO1;
1015  __IOM uint32_t ITCTRL;
1016  uint32_t RESERVED5[39U];
1017  __IOM uint32_t CLAIMSET;
1018  __IOM uint32_t CLAIMCLR;
1019  uint32_t RESERVED7[8U];
1020  __IM uint32_t DEVID;
1021  __IM uint32_t DEVTYPE;
1022 } TPI_Type;
1023 
1024 /* TPI Asynchronous Clock Prescaler Register Definitions */
1025 #define TPI_ACPR_PRESCALER_Pos 0U
1026 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1028 /* TPI Selected Pin Protocol Register Definitions */
1029 #define TPI_SPPR_TXMODE_Pos 0U
1030 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1032 /* TPI Formatter and Flush Status Register Definitions */
1033 #define TPI_FFSR_FtNonStop_Pos 3U
1034 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1036 #define TPI_FFSR_TCPresent_Pos 2U
1037 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1039 #define TPI_FFSR_FtStopped_Pos 1U
1040 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1042 #define TPI_FFSR_FlInProg_Pos 0U
1043 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1045 /* TPI Formatter and Flush Control Register Definitions */
1046 #define TPI_FFCR_TrigIn_Pos 8U
1047 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1049 #define TPI_FFCR_EnFCont_Pos 1U
1050 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1052 /* TPI TRIGGER Register Definitions */
1053 #define TPI_TRIGGER_TRIGGER_Pos 0U
1054 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1056 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1057 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1058 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1060 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1061 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1063 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1064 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1066 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1067 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1069 #define TPI_FIFO0_ETM2_Pos 16U
1070 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1072 #define TPI_FIFO0_ETM1_Pos 8U
1073 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1075 #define TPI_FIFO0_ETM0_Pos 0U
1076 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1078 /* TPI ITATBCTR2 Register Definitions */
1079 #define TPI_ITATBCTR2_ATREADY2_Pos 0U
1080 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
1082 #define TPI_ITATBCTR2_ATREADY1_Pos 0U
1083 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
1085 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1086 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1087 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1089 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1090 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1092 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1093 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1095 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1096 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1098 #define TPI_FIFO1_ITM2_Pos 16U
1099 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1101 #define TPI_FIFO1_ITM1_Pos 8U
1102 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1104 #define TPI_FIFO1_ITM0_Pos 0U
1105 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1107 /* TPI ITATBCTR0 Register Definitions */
1108 #define TPI_ITATBCTR0_ATREADY2_Pos 0U
1109 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
1111 #define TPI_ITATBCTR0_ATREADY1_Pos 0U
1112 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
1114 /* TPI Integration Mode Control Register Definitions */
1115 #define TPI_ITCTRL_Mode_Pos 0U
1116 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1118 /* TPI DEVID Register Definitions */
1119 #define TPI_DEVID_NRZVALID_Pos 11U
1120 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1122 #define TPI_DEVID_MANCVALID_Pos 10U
1123 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1125 #define TPI_DEVID_PTINVALID_Pos 9U
1126 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1128 #define TPI_DEVID_MinBufSz_Pos 6U
1129 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1131 #define TPI_DEVID_AsynClkIn_Pos 5U
1132 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1134 #define TPI_DEVID_NrTraceInput_Pos 0U
1135 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1137 /* TPI DEVTYPE Register Definitions */
1138 #define TPI_DEVTYPE_SubType_Pos 4U
1139 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1141 #define TPI_DEVTYPE_MajorType_Pos 0U
1142 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1144  /* end of group CMSIS_TPI */
1145 
1146 
1147 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1148 
1158 typedef struct
1159 {
1160  __IM uint32_t TYPE;
1161  __IOM uint32_t CTRL;
1162  __IOM uint32_t RNR;
1163  __IOM uint32_t RBAR;
1164  __IOM uint32_t RASR;
1165  __IOM uint32_t RBAR_A1;
1166  __IOM uint32_t RASR_A1;
1167  __IOM uint32_t RBAR_A2;
1168  __IOM uint32_t RASR_A2;
1169  __IOM uint32_t RBAR_A3;
1170  __IOM uint32_t RASR_A3;
1171 } MPU_Type;
1172 
1173 #define MPU_TYPE_RALIASES 4U
1174 
1175 /* MPU Type Register Definitions */
1176 #define MPU_TYPE_IREGION_Pos 16U
1177 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1179 #define MPU_TYPE_DREGION_Pos 8U
1180 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1182 #define MPU_TYPE_SEPARATE_Pos 0U
1183 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1185 /* MPU Control Register Definitions */
1186 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1187 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1189 #define MPU_CTRL_HFNMIENA_Pos 1U
1190 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1192 #define MPU_CTRL_ENABLE_Pos 0U
1193 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1195 /* MPU Region Number Register Definitions */
1196 #define MPU_RNR_REGION_Pos 0U
1197 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1199 /* MPU Region Base Address Register Definitions */
1200 #define MPU_RBAR_ADDR_Pos 5U
1201 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1203 #define MPU_RBAR_VALID_Pos 4U
1204 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1206 #define MPU_RBAR_REGION_Pos 0U
1207 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1209 /* MPU Region Attribute and Size Register Definitions */
1210 #define MPU_RASR_ATTRS_Pos 16U
1211 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1213 #define MPU_RASR_XN_Pos 28U
1214 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1216 #define MPU_RASR_AP_Pos 24U
1217 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1219 #define MPU_RASR_TEX_Pos 19U
1220 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1222 #define MPU_RASR_S_Pos 18U
1223 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1225 #define MPU_RASR_C_Pos 17U
1226 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1228 #define MPU_RASR_B_Pos 16U
1229 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1231 #define MPU_RASR_SRD_Pos 8U
1232 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1234 #define MPU_RASR_SIZE_Pos 1U
1235 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1237 #define MPU_RASR_ENABLE_Pos 0U
1238 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1240 
1241 #endif
1242 
1243 
1254 typedef struct
1255 {
1256  __IOM uint32_t DHCSR;
1257  __OM uint32_t DCRSR;
1258  __IOM uint32_t DCRDR;
1259  __IOM uint32_t DEMCR;
1260 } CoreDebug_Type;
1261 
1262 /* Debug Halting Control and Status Register Definitions */
1263 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1264 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1266 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1267 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1269 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1270 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1272 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1273 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1275 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1276 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1278 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1279 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1281 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1282 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1284 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1285 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1287 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1288 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1290 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1291 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1293 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1294 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1296 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1297 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1299 /* Debug Core Register Selector Register Definitions */
1300 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1301 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1303 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1304 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1306 /* Debug Exception and Monitor Control Register Definitions */
1307 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1308 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1310 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1311 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1313 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1314 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1316 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1317 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1319 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1320 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1322 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1323 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1325 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1326 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1328 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1329 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1331 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1332 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1334 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1335 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1337 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1338 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1340 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1341 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1343 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1344 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1346 
1362 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1363 
1370 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1371 
1382 /* Memory mapping of Core Hardware */
1383 #define SCS_BASE (0xE000E000UL)
1384 #define ITM_BASE (0xE0000000UL)
1385 #define DWT_BASE (0xE0001000UL)
1386 #define TPI_BASE (0xE0040000UL)
1387 #define CoreDebug_BASE (0xE000EDF0UL)
1388 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1389 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1390 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1392 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1393 #define SCB ((SCB_Type *) SCB_BASE )
1394 #define SysTick ((SysTick_Type *) SysTick_BASE )
1395 #define NVIC ((NVIC_Type *) NVIC_BASE )
1396 #define ITM ((ITM_Type *) ITM_BASE )
1397 #define DWT ((DWT_Type *) DWT_BASE )
1398 #define TPI ((TPI_Type *) TPI_BASE )
1399 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1401 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1402  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1403  #define MPU ((MPU_Type *) MPU_BASE )
1404 #endif
1405 
1410 /*******************************************************************************
1411  * Hardware Abstraction Layer
1412  Core Function Interface contains:
1413  - Core NVIC Functions
1414  - Core SysTick Functions
1415  - Core Debug Functions
1416  - Core Register Access Functions
1417  ******************************************************************************/
1424 /* ########################## NVIC functions #################################### */
1432 #ifdef CMSIS_NVIC_VIRTUAL
1433  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1434  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1435  #endif
1436  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1437 #else
1438  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1439  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1440  #define NVIC_EnableIRQ __NVIC_EnableIRQ
1441  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1442  #define NVIC_DisableIRQ __NVIC_DisableIRQ
1443  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1444  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1445  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1446  #define NVIC_GetActive __NVIC_GetActive
1447  #define NVIC_SetPriority __NVIC_SetPriority
1448  #define NVIC_GetPriority __NVIC_GetPriority
1449  #define NVIC_SystemReset __NVIC_SystemReset
1450 #endif /* CMSIS_NVIC_VIRTUAL */
1451 
1452 #ifdef CMSIS_VECTAB_VIRTUAL
1453  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1454  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1455  #endif
1456  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1457 #else
1458  #define NVIC_SetVector __NVIC_SetVector
1459  #define NVIC_GetVector __NVIC_GetVector
1460 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1461 
1462 #define NVIC_USER_IRQ_OFFSET 16
1463 
1464 
1465 /* The following EXC_RETURN values are saved the LR on exception entry */
1466 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1467 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1468 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1469 
1470 
1480 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1481 {
1482  uint32_t reg_value;
1483  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1484 
1485  reg_value = SCB->AIRCR; /* read old register configuration */
1486  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1487  reg_value = (reg_value |
1488  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1489  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1490  SCB->AIRCR = reg_value;
1491 }
1492 
1493 
1499 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1500 {
1501  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1502 }
1503 
1504 
1511 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1512 {
1513  if ((int32_t)(IRQn) >= 0)
1514  {
1515  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1516  }
1517 }
1518 
1519 
1528 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1529 {
1530  if ((int32_t)(IRQn) >= 0)
1531  {
1532  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1533  }
1534  else
1535  {
1536  return(0U);
1537  }
1538 }
1539 
1540 
1547 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1548 {
1549  if ((int32_t)(IRQn) >= 0)
1550  {
1551  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1552  __DSB();
1553  __ISB();
1554  }
1555 }
1556 
1557 
1566 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1567 {
1568  if ((int32_t)(IRQn) >= 0)
1569  {
1570  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1571  }
1572  else
1573  {
1574  return(0U);
1575  }
1576 }
1577 
1578 
1585 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1586 {
1587  if ((int32_t)(IRQn) >= 0)
1588  {
1589  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1590  }
1591 }
1592 
1593 
1600 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1601 {
1602  if ((int32_t)(IRQn) >= 0)
1603  {
1604  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1605  }
1606 }
1607 
1608 
1617 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1618 {
1619  if ((int32_t)(IRQn) >= 0)
1620  {
1621  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1622  }
1623  else
1624  {
1625  return(0U);
1626  }
1627 }
1628 
1629 
1639 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1640 {
1641  if ((int32_t)(IRQn) >= 0)
1642  {
1643  NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1644  }
1645  else
1646  {
1647  SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1648  }
1649 }
1650 
1651 
1661 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1662 {
1663 
1664  if ((int32_t)(IRQn) >= 0)
1665  {
1666  return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1667  }
1668  else
1669  {
1670  return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1671  }
1672 }
1673 
1674 
1686 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1687 {
1688  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1689  uint32_t PreemptPriorityBits;
1690  uint32_t SubPriorityBits;
1691 
1692  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1693  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1694 
1695  return (
1696  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1697  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1698  );
1699 }
1700 
1701 
1713 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1714 {
1715  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1716  uint32_t PreemptPriorityBits;
1717  uint32_t SubPriorityBits;
1718 
1719  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1720  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1721 
1722  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1723  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1724 }
1725 
1726 
1736 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1737 {
1738  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1739  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1740 }
1741 
1742 
1751 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1752 {
1753  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1754  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1755 }
1756 
1757 
1762 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1763 {
1764  __DSB(); /* Ensure all outstanding memory accesses included
1765  buffered write are completed before reset */
1766  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1767  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1768  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1769  __DSB(); /* Ensure completion of memory access */
1770 
1771  for(;;) /* wait until reset */
1772  {
1773  __NOP();
1774  }
1775 }
1776 
1779 /* ########################## MPU functions #################################### */
1780 
1781 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1782 
1783 #include "mpu_armv7.h"
1784 
1785 #endif
1786 
1787 /* ########################## FPU functions #################################### */
1803 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1804 {
1805  return 0U; /* No FPU */
1806 }
1807 
1808 
1813 /* ################################## SysTick function ############################################ */
1821 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1822 
1834 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1835 {
1836  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1837  {
1838  return (1UL); /* Reload value impossible */
1839  }
1840 
1841  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1842  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1843  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1844  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1845  SysTick_CTRL_TICKINT_Msk |
1846  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1847  return (0UL); /* Function successful */
1848 }
1849 
1850 #endif
1851 
1856 /* ##################################### Debug In/Output function ########################################### */
1864 extern volatile int32_t ITM_RxBuffer;
1865 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
1876 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1877 {
1878  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1879  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1880  {
1881  while (ITM->PORT[0U].u32 == 0UL)
1882  {
1883  __NOP();
1884  }
1885  ITM->PORT[0U].u8 = (uint8_t)ch;
1886  }
1887  return (ch);
1888 }
1889 
1890 
1897 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
1898 {
1899  int32_t ch = -1; /* no character available */
1900 
1901  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1902  {
1903  ch = ITM_RxBuffer;
1904  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1905  }
1906 
1907  return (ch);
1908 }
1909 
1910 
1917 __STATIC_INLINE int32_t ITM_CheckChar (void)
1918 {
1919 
1920  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1921  {
1922  return (0); /* no character available */
1923  }
1924  else
1925  {
1926  return (1); /* character available */
1927  }
1928 }
1929 
1935 #ifdef __cplusplus
1936 }
1937 #endif
1938 
1939 #endif /* __CORE_CM3_H_DEPENDANT */
1940 
1941 #endif /* __CMSIS_GENERIC */
xPSR_Type::@399::Q
uint32_t Q
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:268
SCB
#define SCB
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:1393
ITM_Type::@401::u8
__OM uint8_t u8
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:750
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2054
COMP2
#define COMP2
Definition: stm32h735xx.h:2592
CONTROL_Type::@400::SPSEL
uint32_t SPSEL
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:314
COMP1
#define COMP1
Definition: stm32h735xx.h:2591
xPSR_Type::@399::ICI_IT_2
uint32_t ICI_IT_2
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:267
__IM
#define __IM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:173
IRQn
IRQn
Definition: MIMXRT1052.h:78
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2106
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:707
cmsis_compiler.h
CMSIS compiler generic header file.
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:331
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:472
SCB_Type::DFR
__IM uint32_t DFR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:391
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:944
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:274
CONTROL_Type::@400::nPRIV
uint32_t nPRIV
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:313
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1031
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:933
ITM_Type::@401::u16
__OM uint16_t u16
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:751
APSR_Type::@397::C
uint32_t C
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:213
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1052.h:91
APSR_Type::@397::N
uint32_t N
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:215
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2079
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2701
__NOP
#define __NOP
No Operation.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:416
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2010
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1978
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:455
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:812
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:710
ITM
#define ITM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:1396
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1119
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1902
xPSR_Type::@399::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:263
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1993
__STATIC_INLINE
#define __STATIC_INLINE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:63
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
xPSR_Type::@399::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:265
xPSR_Type::@399::V
uint32_t V
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:269
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:717
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f407xx.h:66
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:386
APSR_Type::@397::Q
uint32_t Q
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:211
APSR_Type::@397::V
uint32_t V
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:212
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2129
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:459
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1871
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1940
NVIC
#define NVIC
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:1395
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2681
xPSR_Type::@399::ISR
uint32_t ISR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:262
xPSR_Type::@399::T
uint32_t T
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:266
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2145
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:1865
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1639
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:468
NVIC_SetPriority
#define NVIC_SetPriority
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:1447
xPSR_Type::@399::ICI_IT_1
uint32_t ICI_IT_1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:264
IPSR_Type::@398::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:245
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1269
xPSR_Type::@399::Z
uint32_t Z
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:271
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:713
CONTROL_Type::@400::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:315
__NO_RETURN
#define __NO_RETURN
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:69
__IOM
#define __IOM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:175
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:421
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1890
SysTick
#define SysTick
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:1394
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:1462
IPSR_Type::@398::ISR
uint32_t ISR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:244
APSR_Type::@397::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:210
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:921
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:469
cmsis_version.h
CMSIS Core(M) Version definitions.
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2156
__OM
#define __OM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:174
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2032
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2199
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1959
APSR_Type::@397::Z
uint32_t Z
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:214
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1052.h:266
xPSR_Type::@399::C
uint32_t C
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:270
ITM_Type::@401::u32
__OM uint32_t u32
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:752
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:979
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:313
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1921
SCB_Type::ADR
__IM uint32_t ADR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:392
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:460
xPSR_Type::@399::N
uint32_t N
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h:272

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:13:48