stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_CM23_H_GENERIC
32 #define __CORE_CM23_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 /* CMSIS definitions */
66 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
69  __CM23_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (23U)
76 #define __FPU_USED 0U
77 
78 #if defined ( __CC_ARM )
79  #if defined __TARGET_FPU_VFP
80  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81  #endif
82 
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84  #if defined __ARM_PCS_VFP
85  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86  #endif
87 
88 #elif defined ( __GNUC__ )
89  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91  #endif
92 
93 #elif defined ( __ICCARM__ )
94  #if defined __ARMVFP__
95  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96  #endif
97 
98 #elif defined ( __TI_ARM__ )
99  #if defined __TI_VFP_SUPPORT__
100  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101  #endif
102 
103 #elif defined ( __TASKING__ )
104  #if defined __FPU_VFP__
105  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #endif
107 
108 #elif defined ( __CSMC__ )
109  #if ( __CSMC__ & 0x400U)
110  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111  #endif
112 
113 #endif
114 
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116 
117 
118 #ifdef __cplusplus
119 }
120 #endif
121 
122 #endif /* __CORE_CM23_H_GENERIC */
123 
124 #ifndef __CMSIS_GENERIC
125 
126 #ifndef __CORE_CM23_H_DEPENDANT
127 #define __CORE_CM23_H_DEPENDANT
128 
129 #ifdef __cplusplus
130  extern "C" {
131 #endif
132 
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135  #ifndef __CM23_REV
136  #define __CM23_REV 0x0000U
137  #warning "__CM23_REV not defined in device header file; using default!"
138  #endif
139 
140  #ifndef __FPU_PRESENT
141  #define __FPU_PRESENT 0U
142  #warning "__FPU_PRESENT not defined in device header file; using default!"
143  #endif
144 
145  #ifndef __MPU_PRESENT
146  #define __MPU_PRESENT 0U
147  #warning "__MPU_PRESENT not defined in device header file; using default!"
148  #endif
149 
150  #ifndef __SAUREGION_PRESENT
151  #define __SAUREGION_PRESENT 0U
152  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
153  #endif
154 
155  #ifndef __VTOR_PRESENT
156  #define __VTOR_PRESENT 0U
157  #warning "__VTOR_PRESENT not defined in device header file; using default!"
158  #endif
159 
160  #ifndef __NVIC_PRIO_BITS
161  #define __NVIC_PRIO_BITS 2U
162  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
163  #endif
164 
165  #ifndef __Vendor_SysTickConfig
166  #define __Vendor_SysTickConfig 0U
167  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
168  #endif
169 
170  #ifndef __ETM_PRESENT
171  #define __ETM_PRESENT 0U
172  #warning "__ETM_PRESENT not defined in device header file; using default!"
173  #endif
174 
175  #ifndef __MTB_PRESENT
176  #define __MTB_PRESENT 0U
177  #warning "__MTB_PRESENT not defined in device header file; using default!"
178  #endif
179 
180 #endif
181 
182 /* IO definitions (access restrictions to peripheral registers) */
190 #ifdef __cplusplus
191  #define __I volatile
192 #else
193  #define __I volatile const
194 #endif
195 #define __O volatile
196 #define __IO volatile
198 /* following defines should be used for structure members */
199 #define __IM volatile const
200 #define __OM volatile
201 #define __IOM volatile
203 
207 /*******************************************************************************
208  * Register Abstraction
209  Core Register contain:
210  - Core Register
211  - Core NVIC Register
212  - Core SCB Register
213  - Core SysTick Register
214  - Core Debug Register
215  - Core MPU Register
216  - Core SAU Register
217  ******************************************************************************/
218 
233 typedef union
234 {
235  struct
236  {
237  uint32_t _reserved0:28;
238  uint32_t V:1;
239  uint32_t C:1;
240  uint32_t Z:1;
241  uint32_t N:1;
242  } b;
243  uint32_t w;
244 } APSR_Type;
245 
246 /* APSR Register Definitions */
247 #define APSR_N_Pos 31U
248 #define APSR_N_Msk (1UL << APSR_N_Pos)
250 #define APSR_Z_Pos 30U
251 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
253 #define APSR_C_Pos 29U
254 #define APSR_C_Msk (1UL << APSR_C_Pos)
256 #define APSR_V_Pos 28U
257 #define APSR_V_Msk (1UL << APSR_V_Pos)
263 typedef union
264 {
265  struct
266  {
267  uint32_t ISR:9;
268  uint32_t _reserved0:23;
269  } b;
270  uint32_t w;
271 } IPSR_Type;
272 
273 /* IPSR Register Definitions */
274 #define IPSR_ISR_Pos 0U
275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
281 typedef union
282 {
283  struct
284  {
285  uint32_t ISR:9;
286  uint32_t _reserved0:15;
287  uint32_t T:1;
288  uint32_t _reserved1:3;
289  uint32_t V:1;
290  uint32_t C:1;
291  uint32_t Z:1;
292  uint32_t N:1;
293  } b;
294  uint32_t w;
295 } xPSR_Type;
296 
297 /* xPSR Register Definitions */
298 #define xPSR_N_Pos 31U
299 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
301 #define xPSR_Z_Pos 30U
302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
304 #define xPSR_C_Pos 29U
305 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
307 #define xPSR_V_Pos 28U
308 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
310 #define xPSR_T_Pos 24U
311 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
313 #define xPSR_ISR_Pos 0U
314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
320 typedef union
321 {
322  struct
323  {
324  uint32_t nPRIV:1;
325  uint32_t SPSEL:1;
326  uint32_t _reserved1:30;
327  } b;
328  uint32_t w;
329 } CONTROL_Type;
330 
331 /* CONTROL Register Definitions */
332 #define CONTROL_SPSEL_Pos 1U
333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
335 #define CONTROL_nPRIV_Pos 0U
336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
338 
351 typedef struct
352 {
353  __IOM uint32_t ISER[16U];
354  uint32_t RESERVED0[16U];
355  __IOM uint32_t ICER[16U];
356  uint32_t RSERVED1[16U];
357  __IOM uint32_t ISPR[16U];
358  uint32_t RESERVED2[16U];
359  __IOM uint32_t ICPR[16U];
360  uint32_t RESERVED3[16U];
361  __IOM uint32_t IABR[16U];
362  uint32_t RESERVED4[16U];
363  __IOM uint32_t ITNS[16U];
364  uint32_t RESERVED5[16U];
365  __IOM uint32_t IPR[124U];
366 } NVIC_Type;
367 
381 typedef struct
382 {
383  __IM uint32_t CPUID;
384  __IOM uint32_t ICSR;
385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
386  __IOM uint32_t VTOR;
387 #else
388  uint32_t RESERVED0;
389 #endif
390  __IOM uint32_t AIRCR;
391  __IOM uint32_t SCR;
392  __IOM uint32_t CCR;
393  uint32_t RESERVED1;
394  __IOM uint32_t SHPR[2U];
395  __IOM uint32_t SHCSR;
396 } SCB_Type;
397 
398 /* SCB CPUID Register Definitions */
399 #define SCB_CPUID_IMPLEMENTER_Pos 24U
400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
402 #define SCB_CPUID_VARIANT_Pos 20U
403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
405 #define SCB_CPUID_ARCHITECTURE_Pos 16U
406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
408 #define SCB_CPUID_PARTNO_Pos 4U
409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
411 #define SCB_CPUID_REVISION_Pos 0U
412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
414 /* SCB Interrupt Control State Register Definitions */
415 #define SCB_ICSR_PENDNMISET_Pos 31U
416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
418 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
419 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
421 #define SCB_ICSR_PENDNMICLR_Pos 30U
422 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
424 #define SCB_ICSR_PENDSVSET_Pos 28U
425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
427 #define SCB_ICSR_PENDSVCLR_Pos 27U
428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
430 #define SCB_ICSR_PENDSTSET_Pos 26U
431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
433 #define SCB_ICSR_PENDSTCLR_Pos 25U
434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
436 #define SCB_ICSR_STTNS_Pos 24U
437 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
439 #define SCB_ICSR_ISRPREEMPT_Pos 23U
440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
442 #define SCB_ICSR_ISRPENDING_Pos 22U
443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
445 #define SCB_ICSR_VECTPENDING_Pos 12U
446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
448 #define SCB_ICSR_RETTOBASE_Pos 11U
449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
451 #define SCB_ICSR_VECTACTIVE_Pos 0U
452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
454 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
455 /* SCB Vector Table Offset Register Definitions */
456 #define SCB_VTOR_TBLOFF_Pos 7U
457 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
458 #endif
459 
460 /* SCB Application Interrupt and Reset Control Register Definitions */
461 #define SCB_AIRCR_VECTKEY_Pos 16U
462 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
464 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
465 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
467 #define SCB_AIRCR_ENDIANESS_Pos 15U
468 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
470 #define SCB_AIRCR_PRIS_Pos 14U
471 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
473 #define SCB_AIRCR_BFHFNMINS_Pos 13U
474 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
476 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
477 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
479 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
480 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
482 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
483 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
485 /* SCB System Control Register Definitions */
486 #define SCB_SCR_SEVONPEND_Pos 4U
487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
489 #define SCB_SCR_SLEEPDEEPS_Pos 3U
490 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
492 #define SCB_SCR_SLEEPDEEP_Pos 2U
493 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
495 #define SCB_SCR_SLEEPONEXIT_Pos 1U
496 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
498 /* SCB Configuration Control Register Definitions */
499 #define SCB_CCR_BP_Pos 18U
500 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
502 #define SCB_CCR_IC_Pos 17U
503 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
505 #define SCB_CCR_DC_Pos 16U
506 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
508 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
509 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
511 #define SCB_CCR_BFHFNMIGN_Pos 8U
512 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
514 #define SCB_CCR_DIV_0_TRP_Pos 4U
515 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
517 #define SCB_CCR_UNALIGN_TRP_Pos 3U
518 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
520 #define SCB_CCR_USERSETMPEND_Pos 1U
521 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
523 /* SCB System Handler Control and State Register Definitions */
524 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
525 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
527 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
528 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
530 #define SCB_SHCSR_SYSTICKACT_Pos 11U
531 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
533 #define SCB_SHCSR_PENDSVACT_Pos 10U
534 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
536 #define SCB_SHCSR_SVCALLACT_Pos 7U
537 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
539 #define SCB_SHCSR_NMIACT_Pos 5U
540 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
542 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
543 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
545 
558 typedef struct
559 {
560  __IOM uint32_t CTRL;
561  __IOM uint32_t LOAD;
562  __IOM uint32_t VAL;
563  __IM uint32_t CALIB;
564 } SysTick_Type;
565 
566 /* SysTick Control / Status Register Definitions */
567 #define SysTick_CTRL_COUNTFLAG_Pos 16U
568 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
570 #define SysTick_CTRL_CLKSOURCE_Pos 2U
571 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
573 #define SysTick_CTRL_TICKINT_Pos 1U
574 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
576 #define SysTick_CTRL_ENABLE_Pos 0U
577 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
579 /* SysTick Reload Register Definitions */
580 #define SysTick_LOAD_RELOAD_Pos 0U
581 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
583 /* SysTick Current Register Definitions */
584 #define SysTick_VAL_CURRENT_Pos 0U
585 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
587 /* SysTick Calibration Register Definitions */
588 #define SysTick_CALIB_NOREF_Pos 31U
589 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
591 #define SysTick_CALIB_SKEW_Pos 30U
592 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
594 #define SysTick_CALIB_TENMS_Pos 0U
595 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
597 
610 typedef struct
611 {
612  __IOM uint32_t CTRL;
613  uint32_t RESERVED0[6U];
614  __IM uint32_t PCSR;
615  __IOM uint32_t COMP0;
616  uint32_t RESERVED1[1U];
617  __IOM uint32_t FUNCTION0;
618  uint32_t RESERVED2[1U];
619  __IOM uint32_t COMP1;
620  uint32_t RESERVED3[1U];
621  __IOM uint32_t FUNCTION1;
622  uint32_t RESERVED4[1U];
623  __IOM uint32_t COMP2;
624  uint32_t RESERVED5[1U];
625  __IOM uint32_t FUNCTION2;
626  uint32_t RESERVED6[1U];
627  __IOM uint32_t COMP3;
628  uint32_t RESERVED7[1U];
629  __IOM uint32_t FUNCTION3;
630  uint32_t RESERVED8[1U];
631  __IOM uint32_t COMP4;
632  uint32_t RESERVED9[1U];
633  __IOM uint32_t FUNCTION4;
634  uint32_t RESERVED10[1U];
635  __IOM uint32_t COMP5;
636  uint32_t RESERVED11[1U];
637  __IOM uint32_t FUNCTION5;
638  uint32_t RESERVED12[1U];
639  __IOM uint32_t COMP6;
640  uint32_t RESERVED13[1U];
641  __IOM uint32_t FUNCTION6;
642  uint32_t RESERVED14[1U];
643  __IOM uint32_t COMP7;
644  uint32_t RESERVED15[1U];
645  __IOM uint32_t FUNCTION7;
646  uint32_t RESERVED16[1U];
647  __IOM uint32_t COMP8;
648  uint32_t RESERVED17[1U];
649  __IOM uint32_t FUNCTION8;
650  uint32_t RESERVED18[1U];
651  __IOM uint32_t COMP9;
652  uint32_t RESERVED19[1U];
653  __IOM uint32_t FUNCTION9;
654  uint32_t RESERVED20[1U];
655  __IOM uint32_t COMP10;
656  uint32_t RESERVED21[1U];
657  __IOM uint32_t FUNCTION10;
658  uint32_t RESERVED22[1U];
659  __IOM uint32_t COMP11;
660  uint32_t RESERVED23[1U];
661  __IOM uint32_t FUNCTION11;
662  uint32_t RESERVED24[1U];
663  __IOM uint32_t COMP12;
664  uint32_t RESERVED25[1U];
665  __IOM uint32_t FUNCTION12;
666  uint32_t RESERVED26[1U];
667  __IOM uint32_t COMP13;
668  uint32_t RESERVED27[1U];
669  __IOM uint32_t FUNCTION13;
670  uint32_t RESERVED28[1U];
671  __IOM uint32_t COMP14;
672  uint32_t RESERVED29[1U];
673  __IOM uint32_t FUNCTION14;
674  uint32_t RESERVED30[1U];
675  __IOM uint32_t COMP15;
676  uint32_t RESERVED31[1U];
677  __IOM uint32_t FUNCTION15;
678 } DWT_Type;
679 
680 /* DWT Control Register Definitions */
681 #define DWT_CTRL_NUMCOMP_Pos 28U
682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
684 #define DWT_CTRL_NOTRCPKT_Pos 27U
685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
687 #define DWT_CTRL_NOEXTTRIG_Pos 26U
688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
690 #define DWT_CTRL_NOCYCCNT_Pos 25U
691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
693 #define DWT_CTRL_NOPRFCNT_Pos 24U
694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
696 /* DWT Comparator Function Register Definitions */
697 #define DWT_FUNCTION_ID_Pos 27U
698 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
700 #define DWT_FUNCTION_MATCHED_Pos 24U
701 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
703 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
704 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
706 #define DWT_FUNCTION_ACTION_Pos 4U
707 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)
709 #define DWT_FUNCTION_MATCH_Pos 0U
710 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
712  /* end of group CMSIS_DWT */
713 
714 
725 typedef struct
726 {
727  __IM uint32_t SSPSR;
728  __IOM uint32_t CSPSR;
729  uint32_t RESERVED0[2U];
730  __IOM uint32_t ACPR;
731  uint32_t RESERVED1[55U];
732  __IOM uint32_t SPPR;
733  uint32_t RESERVED2[131U];
734  __IM uint32_t FFSR;
735  __IOM uint32_t FFCR;
736  __IOM uint32_t PSCR;
737  uint32_t RESERVED3[759U];
738  __IM uint32_t TRIGGER;
739  __IM uint32_t ITFTTD0;
740  __IOM uint32_t ITATBCTR2;
741  uint32_t RESERVED4[1U];
742  __IM uint32_t ITATBCTR0;
743  __IM uint32_t ITFTTD1;
744  __IOM uint32_t ITCTRL;
745  uint32_t RESERVED5[39U];
746  __IOM uint32_t CLAIMSET;
747  __IOM uint32_t CLAIMCLR;
748  uint32_t RESERVED7[8U];
749  __IM uint32_t DEVID;
750  __IM uint32_t DEVTYPE;
751 } TPI_Type;
752 
753 /* TPI Asynchronous Clock Prescaler Register Definitions */
754 #define TPI_ACPR_PRESCALER_Pos 0U
755 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
757 /* TPI Selected Pin Protocol Register Definitions */
758 #define TPI_SPPR_TXMODE_Pos 0U
759 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
761 /* TPI Formatter and Flush Status Register Definitions */
762 #define TPI_FFSR_FtNonStop_Pos 3U
763 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
765 #define TPI_FFSR_TCPresent_Pos 2U
766 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
768 #define TPI_FFSR_FtStopped_Pos 1U
769 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
771 #define TPI_FFSR_FlInProg_Pos 0U
772 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
774 /* TPI Formatter and Flush Control Register Definitions */
775 #define TPI_FFCR_TrigIn_Pos 8U
776 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
778 #define TPI_FFCR_FOnMan_Pos 6U
779 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
781 #define TPI_FFCR_EnFCont_Pos 1U
782 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
784 /* TPI TRIGGER Register Definitions */
785 #define TPI_TRIGGER_TRIGGER_Pos 0U
786 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
788 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
789 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
790 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
792 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
793 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
795 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
796 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
798 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
799 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
801 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
802 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
804 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
805 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
807 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
808 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
810 /* TPI Integration Test ATB Control Register 2 Register Definitions */
811 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U
812 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
814 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U
815 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
817 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U
818 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
820 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U
821 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
823 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
824 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
825 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
827 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
828 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
830 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
831 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
833 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
834 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
836 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
837 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
839 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
840 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
842 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
843 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
845 /* TPI Integration Test ATB Control Register 0 Definitions */
846 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U
847 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
849 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U
850 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
852 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U
853 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
855 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U
856 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
858 /* TPI Integration Mode Control Register Definitions */
859 #define TPI_ITCTRL_Mode_Pos 0U
860 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
862 /* TPI DEVID Register Definitions */
863 #define TPI_DEVID_NRZVALID_Pos 11U
864 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
866 #define TPI_DEVID_MANCVALID_Pos 10U
867 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
869 #define TPI_DEVID_PTINVALID_Pos 9U
870 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
872 #define TPI_DEVID_FIFOSZ_Pos 6U
873 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
875 #define TPI_DEVID_NrTraceInput_Pos 0U
876 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
878 /* TPI DEVTYPE Register Definitions */
879 #define TPI_DEVTYPE_SubType_Pos 4U
880 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
882 #define TPI_DEVTYPE_MajorType_Pos 0U
883 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
885  /* end of group CMSIS_TPI */
886 
887 
888 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
889 
899 typedef struct
900 {
901  __IM uint32_t TYPE;
902  __IOM uint32_t CTRL;
903  __IOM uint32_t RNR;
904  __IOM uint32_t RBAR;
905  __IOM uint32_t RLAR;
906  uint32_t RESERVED0[7U];
907  union {
908  __IOM uint32_t MAIR[2];
909  struct {
910  __IOM uint32_t MAIR0;
911  __IOM uint32_t MAIR1;
912  };
913  };
914 } MPU_Type;
915 
916 #define MPU_TYPE_RALIASES 1U
917 
918 /* MPU Type Register Definitions */
919 #define MPU_TYPE_IREGION_Pos 16U
920 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
922 #define MPU_TYPE_DREGION_Pos 8U
923 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
925 #define MPU_TYPE_SEPARATE_Pos 0U
926 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
928 /* MPU Control Register Definitions */
929 #define MPU_CTRL_PRIVDEFENA_Pos 2U
930 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
932 #define MPU_CTRL_HFNMIENA_Pos 1U
933 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
935 #define MPU_CTRL_ENABLE_Pos 0U
936 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
938 /* MPU Region Number Register Definitions */
939 #define MPU_RNR_REGION_Pos 0U
940 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
942 /* MPU Region Base Address Register Definitions */
943 #define MPU_RBAR_BASE_Pos 5U
944 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
946 #define MPU_RBAR_SH_Pos 3U
947 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
949 #define MPU_RBAR_AP_Pos 1U
950 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
952 #define MPU_RBAR_XN_Pos 0U
953 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
955 /* MPU Region Limit Address Register Definitions */
956 #define MPU_RLAR_LIMIT_Pos 5U
957 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
959 #define MPU_RLAR_AttrIndx_Pos 1U
960 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
962 #define MPU_RLAR_EN_Pos 0U
963 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
965 /* MPU Memory Attribute Indirection Register 0 Definitions */
966 #define MPU_MAIR0_Attr3_Pos 24U
967 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
969 #define MPU_MAIR0_Attr2_Pos 16U
970 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
972 #define MPU_MAIR0_Attr1_Pos 8U
973 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
975 #define MPU_MAIR0_Attr0_Pos 0U
976 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
978 /* MPU Memory Attribute Indirection Register 1 Definitions */
979 #define MPU_MAIR1_Attr7_Pos 24U
980 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
982 #define MPU_MAIR1_Attr6_Pos 16U
983 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
985 #define MPU_MAIR1_Attr5_Pos 8U
986 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
988 #define MPU_MAIR1_Attr4_Pos 0U
989 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
991 
992 #endif
993 
994 
995 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
996 
1006 typedef struct
1007 {
1008  __IOM uint32_t CTRL;
1009  __IM uint32_t TYPE;
1010 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1011  __IOM uint32_t RNR;
1012  __IOM uint32_t RBAR;
1013  __IOM uint32_t RLAR;
1014 #endif
1015 } SAU_Type;
1016 
1017 /* SAU Control Register Definitions */
1018 #define SAU_CTRL_ALLNS_Pos 1U
1019 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1021 #define SAU_CTRL_ENABLE_Pos 0U
1022 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1024 /* SAU Type Register Definitions */
1025 #define SAU_TYPE_SREGION_Pos 0U
1026 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1028 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1029 /* SAU Region Number Register Definitions */
1030 #define SAU_RNR_REGION_Pos 0U
1031 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1033 /* SAU Region Base Address Register Definitions */
1034 #define SAU_RBAR_BADDR_Pos 5U
1035 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1037 /* SAU Region Limit Address Register Definitions */
1038 #define SAU_RLAR_LADDR_Pos 5U
1039 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1041 #define SAU_RLAR_NSC_Pos 1U
1042 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1044 #define SAU_RLAR_ENABLE_Pos 0U
1045 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1047 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1048 
1050 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1051 
1052 
1063 typedef struct
1064 {
1065  __IOM uint32_t DHCSR;
1066  __OM uint32_t DCRSR;
1067  __IOM uint32_t DCRDR;
1068  __IOM uint32_t DEMCR;
1069  uint32_t RESERVED4[1U];
1070  __IOM uint32_t DAUTHCTRL;
1071  __IOM uint32_t DSCSR;
1072 } CoreDebug_Type;
1073 
1074 /* Debug Halting Control and Status Register Definitions */
1075 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1076 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1081 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1082 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1084 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1085 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1087 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1088 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1090 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1091 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1093 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1094 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1096 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1097 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1099 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1100 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1102 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1103 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1105 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1106 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1108 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1109 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1111 /* Debug Core Register Selector Register Definitions */
1112 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1113 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1115 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1116 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1118 /* Debug Exception and Monitor Control Register */
1119 #define CoreDebug_DEMCR_DWTENA_Pos 24U
1120 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)
1122 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1123 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1125 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1126 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1128 /* Debug Authentication Control Register Definitions */
1129 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1130 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1132 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1133 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1135 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1136 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1138 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1139 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1141 /* Debug Security Control and Status Register Definitions */
1142 #define CoreDebug_DSCSR_CDS_Pos 16U
1143 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1145 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1146 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1148 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1149 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1151 
1167 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1168 
1175 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1176 
1187 /* Memory mapping of Core Hardware */
1188  #define SCS_BASE (0xE000E000UL)
1189  #define DWT_BASE (0xE0001000UL)
1190  #define TPI_BASE (0xE0040000UL)
1191  #define CoreDebug_BASE (0xE000EDF0UL)
1192  #define SysTick_BASE (SCS_BASE + 0x0010UL)
1193  #define NVIC_BASE (SCS_BASE + 0x0100UL)
1194  #define SCB_BASE (SCS_BASE + 0x0D00UL)
1197  #define SCB ((SCB_Type *) SCB_BASE )
1198  #define SysTick ((SysTick_Type *) SysTick_BASE )
1199  #define NVIC ((NVIC_Type *) NVIC_BASE )
1200  #define DWT ((DWT_Type *) DWT_BASE )
1201  #define TPI ((TPI_Type *) TPI_BASE )
1202  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
1204  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1205  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1206  #define MPU ((MPU_Type *) MPU_BASE )
1207  #endif
1208 
1209  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1210  #define SAU_BASE (SCS_BASE + 0x0DD0UL)
1211  #define SAU ((SAU_Type *) SAU_BASE )
1212  #endif
1213 
1214 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1215  #define SCS_BASE_NS (0xE002E000UL)
1216  #define CoreDebug_BASE_NS (0xE002EDF0UL)
1217  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
1218  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
1219  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
1221  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
1222  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
1223  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
1224  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
1226  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1227  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
1228  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
1229  #endif
1230 
1231 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1232 
1236 /*******************************************************************************
1237  * Hardware Abstraction Layer
1238  Core Function Interface contains:
1239  - Core NVIC Functions
1240  - Core SysTick Functions
1241  - Core Register Access Functions
1242  ******************************************************************************/
1249 /* ########################## NVIC functions #################################### */
1257 #ifdef CMSIS_NVIC_VIRTUAL
1258  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1259  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1260  #endif
1261  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1262 #else
1263 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
1264 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
1265  #define NVIC_EnableIRQ __NVIC_EnableIRQ
1266  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1267  #define NVIC_DisableIRQ __NVIC_DisableIRQ
1268  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1269  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1270  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1271  #define NVIC_GetActive __NVIC_GetActive
1272  #define NVIC_SetPriority __NVIC_SetPriority
1273  #define NVIC_GetPriority __NVIC_GetPriority
1274  #define NVIC_SystemReset __NVIC_SystemReset
1275 #endif /* CMSIS_NVIC_VIRTUAL */
1276 
1277 #ifdef CMSIS_VECTAB_VIRTUAL
1278  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1279  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1280  #endif
1281  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1282 #else
1283  #define NVIC_SetVector __NVIC_SetVector
1284  #define NVIC_GetVector __NVIC_GetVector
1285 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1286 
1287 #define NVIC_USER_IRQ_OFFSET 16
1288 
1289 
1290 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1291 
1292 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1293 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1294 
1295 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1296 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1297 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1298 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1299 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
1300 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
1301 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
1302 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
1303 
1304 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
1305 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
1306 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1307 #else
1308 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
1309 #endif
1310 
1311 
1312 /* Interrupt Priorities are WORD accessible only under Armv6-M */
1313 /* The following MACROS handle generation of the register offset and byte masks */
1314 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1315 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1316 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1317 
1318 #define __NVIC_SetPriorityGrouping(X) (void)(X)
1319 #define __NVIC_GetPriorityGrouping() (0U)
1320 
1327 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1328 {
1329  if ((int32_t)(IRQn) >= 0)
1330  {
1331  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1332  }
1333 }
1334 
1335 
1344 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1345 {
1346  if ((int32_t)(IRQn) >= 0)
1347  {
1348  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1349  }
1350  else
1351  {
1352  return(0U);
1353  }
1354 }
1355 
1356 
1363 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1364 {
1365  if ((int32_t)(IRQn) >= 0)
1366  {
1367  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1368  __DSB();
1369  __ISB();
1370  }
1371 }
1372 
1373 
1382 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1383 {
1384  if ((int32_t)(IRQn) >= 0)
1385  {
1386  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1387  }
1388  else
1389  {
1390  return(0U);
1391  }
1392 }
1393 
1394 
1401 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1402 {
1403  if ((int32_t)(IRQn) >= 0)
1404  {
1405  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1406  }
1407 }
1408 
1409 
1416 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1417 {
1418  if ((int32_t)(IRQn) >= 0)
1419  {
1420  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1421  }
1422 }
1423 
1424 
1433 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1434 {
1435  if ((int32_t)(IRQn) >= 0)
1436  {
1437  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1438  }
1439  else
1440  {
1441  return(0U);
1442  }
1443 }
1444 
1445 
1446 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1447 
1455 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1456 {
1457  if ((int32_t)(IRQn) >= 0)
1458  {
1459  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1460  }
1461  else
1462  {
1463  return(0U);
1464  }
1465 }
1466 
1467 
1476 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1477 {
1478  if ((int32_t)(IRQn) >= 0)
1479  {
1480  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1481  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1482  }
1483  else
1484  {
1485  return(0U);
1486  }
1487 }
1488 
1489 
1498 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1499 {
1500  if ((int32_t)(IRQn) >= 0)
1501  {
1502  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1503  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1504  }
1505  else
1506  {
1507  return(0U);
1508  }
1509 }
1510 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1511 
1512 
1522 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1523 {
1524  if ((int32_t)(IRQn) >= 0)
1525  {
1526  NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1527  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1528  }
1529  else
1530  {
1531  SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1532  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1533  }
1534 }
1535 
1536 
1546 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1547 {
1548 
1549  if ((int32_t)(IRQn) >= 0)
1550  {
1551  return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1552  }
1553  else
1554  {
1555  return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1556  }
1557 }
1558 
1559 
1571 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1572 {
1573  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1574  uint32_t PreemptPriorityBits;
1575  uint32_t SubPriorityBits;
1576 
1577  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1578  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1579 
1580  return (
1581  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1582  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1583  );
1584 }
1585 
1586 
1598 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1599 {
1600  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1601  uint32_t PreemptPriorityBits;
1602  uint32_t SubPriorityBits;
1603 
1604  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1605  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1606 
1607  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1608  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1609 }
1610 
1611 
1622 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1623 {
1624 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1625  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1626 #else
1627  uint32_t *vectors = (uint32_t *)0x0U;
1628 #endif
1629  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1630 }
1631 
1632 
1641 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1642 {
1643 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1644  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1645 #else
1646  uint32_t *vectors = (uint32_t *)0x0U;
1647 #endif
1648  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1649 }
1650 
1651 
1656 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1657 {
1658  __DSB(); /* Ensure all outstanding memory accesses included
1659  buffered write are completed before reset */
1660  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1661  SCB_AIRCR_SYSRESETREQ_Msk);
1662  __DSB(); /* Ensure completion of memory access */
1663 
1664  for(;;) /* wait until reset */
1665  {
1666  __NOP();
1667  }
1668 }
1669 
1670 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1671 
1677 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1678 {
1679  if ((int32_t)(IRQn) >= 0)
1680  {
1681  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1682  }
1683 }
1684 
1685 
1694 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1695 {
1696  if ((int32_t)(IRQn) >= 0)
1697  {
1698  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1699  }
1700  else
1701  {
1702  return(0U);
1703  }
1704 }
1705 
1706 
1713 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1714 {
1715  if ((int32_t)(IRQn) >= 0)
1716  {
1717  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1718  }
1719 }
1720 
1721 
1730 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1731 {
1732  if ((int32_t)(IRQn) >= 0)
1733  {
1734  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1735  }
1736  else
1737  {
1738  return(0U);
1739  }
1740 }
1741 
1742 
1749 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1750 {
1751  if ((int32_t)(IRQn) >= 0)
1752  {
1753  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1754  }
1755 }
1756 
1757 
1764 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1765 {
1766  if ((int32_t)(IRQn) >= 0)
1767  {
1768  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1769  }
1770 }
1771 
1772 
1781 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1782 {
1783  if ((int32_t)(IRQn) >= 0)
1784  {
1785  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1786  }
1787  else
1788  {
1789  return(0U);
1790  }
1791 }
1792 
1793 
1803 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
1804 {
1805  if ((int32_t)(IRQn) >= 0)
1806  {
1807  NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1808  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1809  }
1810  else
1811  {
1812  SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1813  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1814  }
1815 }
1816 
1817 
1826 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
1827 {
1828 
1829  if ((int32_t)(IRQn) >= 0)
1830  {
1831  return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1832  }
1833  else
1834  {
1835  return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1836  }
1837 }
1838 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
1839 
1842 /* ########################## MPU functions #################################### */
1843 
1844 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1845 
1846 #include "mpu_armv8.h"
1847 
1848 #endif
1849 
1850 /* ########################## FPU functions #################################### */
1866 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1867 {
1868  return 0U; /* No FPU */
1869 }
1870 
1871 
1876 /* ########################## SAU functions #################################### */
1884 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1885 
1890 __STATIC_INLINE void TZ_SAU_Enable(void)
1891 {
1892  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
1893 }
1894 
1895 
1896 
1901 __STATIC_INLINE void TZ_SAU_Disable(void)
1902 {
1903  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
1904 }
1905 
1906 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1907 
1913 /* ################################## SysTick function ############################################ */
1921 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1922 
1934 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1935 {
1936  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1937  {
1938  return (1UL); /* Reload value impossible */
1939  }
1940 
1941  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1942  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1943  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1944  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1945  SysTick_CTRL_TICKINT_Msk |
1946  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1947  return (0UL); /* Function successful */
1948 }
1949 
1950 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1951 
1963 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
1964 {
1965  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1966  {
1967  return (1UL); /* Reload value impossible */
1968  }
1969 
1970  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1971  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1972  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
1973  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1974  SysTick_CTRL_TICKINT_Msk |
1975  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1976  return (0UL); /* Function successful */
1977 }
1978 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1979 
1980 #endif
1981 
1987 #ifdef __cplusplus
1988 }
1989 #endif
1990 
1991 #endif /* __CORE_CM23_H_DEPENDANT */
1992 
1993 #endif /* __CMSIS_GENERIC */
SCB
#define SCB
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:1197
__IOM
#define __IOM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:201
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2054
CONTROL_Type::@396::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:326
COMP2
#define COMP2
Definition: stm32h735xx.h:2592
APSR_Type::@393::N
uint32_t N
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:241
COMP1
#define COMP1
Definition: stm32h735xx.h:2591
APSR_Type::@393::V
uint32_t V
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:238
TPI_Type::ITATBCTR2
__IOM uint32_t ITATBCTR2
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:740
__OM
#define __OM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:200
xPSR_Type::@395::ISR
uint32_t ISR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:285
TPI_Type::ITFTTD0
__IM uint32_t ITFTTD0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:739
IRQn
IRQn
Definition: MIMXRT1052.h:78
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2106
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:571
cmsis_compiler.h
CMSIS compiler generic header file.
xPSR_Type::@395::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:286
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:331
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:480
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:944
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:274
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:933
APSR_Type::@393::Z
uint32_t Z
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:240
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:1315
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1052.h:91
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:1314
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2079
APSR_Type::@393::C
uint32_t C
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:239
xPSR_Type::@395::Z
uint32_t Z
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:291
__NOP
#define __NOP
No Operation.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:416
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2010
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1978
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:455
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:574
APSR_Type::@393::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:237
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1119
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1902
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1993
__STATIC_INLINE
#define __STATIC_INLINE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:63
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:581
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f407xx.h:66
CONTROL_Type::@396::nPRIV
uint32_t nPRIV
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:324
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:386
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2129
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:461
CONTROL_Type::@396::SPSEL
uint32_t SPSEL
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:325
__IM
#define __IM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:199
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1940
NVIC
#define NVIC
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:1199
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2145
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1639
TPI_Type::ITFTTD1
__IM uint32_t ITFTTD1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:743
NVIC_SetPriority
#define NVIC_SetPriority
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:1272
_IP_IDX
#define _IP_IDX(IRQn)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:1316
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1269
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:577
xPSR_Type::@395::N
uint32_t N
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:292
__NO_RETURN
#define __NO_RETURN
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:69
COMP12
#define COMP12
Definition: stm32h735xx.h:2590
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:421
SysTick
#define SysTick
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:1198
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:1287
IPSR_Type::@394::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:268
cmsis_version.h
CMSIS Core(M) Version definitions.
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2156
xPSR_Type::@395::C
uint32_t C
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:290
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2032
xPSR_Type::@395::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:288
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2199
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1959
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1052.h:266
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:979
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:313
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1921
xPSR_Type::@395::V
uint32_t V
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:289
xPSR_Type::@395::T
uint32_t T
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:287
IPSR_Type::@394::ISR
uint32_t ISR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:267

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:13:48