stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_RCC_EX_H
22 #define STM32H7xx_HAL_RCC_EX_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49 
50  uint32_t PLL2M;
53  uint32_t PLL2N;
58  uint32_t PLL2P;
62  uint32_t PLL2Q;
65  uint32_t PLL2R;
67  uint32_t PLL2RGE;
69  uint32_t PLL2VCOSEL;
72  uint32_t PLL2FRACN;
74 }RCC_PLL2InitTypeDef;
75 
79 typedef struct
80 {
81 
82  uint32_t PLL3M;
85  uint32_t PLL3N;
90  uint32_t PLL3P;
94  uint32_t PLL3Q;
97  uint32_t PLL3R;
99  uint32_t PLL3RGE;
101  uint32_t PLL3VCOSEL;
104  uint32_t PLL3FRACN;
106 }RCC_PLL3InitTypeDef;
107 
111 typedef struct
112 {
113  uint32_t PLL1_P_Frequency;
114  uint32_t PLL1_Q_Frequency;
115  uint32_t PLL1_R_Frequency;
116 }PLL1_ClocksTypeDef;
117 
121 typedef struct
122 {
123  uint32_t PLL2_P_Frequency;
124  uint32_t PLL2_Q_Frequency;
125  uint32_t PLL2_R_Frequency;
126 }PLL2_ClocksTypeDef;
127 
131 typedef struct
132 {
133  uint32_t PLL3_P_Frequency;
134  uint32_t PLL3_Q_Frequency;
135  uint32_t PLL3_R_Frequency;
136 }PLL3_ClocksTypeDef;
137 
138 
142 typedef struct
143 {
144  uint32_t PeriphClockSelection;
147  RCC_PLL2InitTypeDef PLL2;
150  RCC_PLL3InitTypeDef PLL3;
153  uint32_t FmcClockSelection;
156 #if defined(QUADSPI)
157  uint32_t QspiClockSelection;
159 #endif /* QUADSPI */
160 
161 #if defined(OCTOSPI1) || defined(OCTOSPI2)
162  uint32_t OspiClockSelection;
164 #endif /*(OCTOSPI1) || (OCTOSPI2)*/
165 
166 
167 #if defined(DSI)
168  uint32_t DsiClockSelection;
170 #endif /* DSI */
171 
172  uint32_t SdmmcClockSelection;
175  uint32_t CkperClockSelection;
178  uint32_t Sai1ClockSelection;
181 #if defined(SAI3)
182  uint32_t Sai23ClockSelection;
184 #endif /* SAI3 */
185 
186 #if defined(RCC_CDCCIP1R_SAI2ASEL)
187  uint32_t Sai2AClockSelection;
189 #endif /* RCC_CDCCIP1R_SAI2ASEL */
190 
191 #if defined(RCC_CDCCIP1R_SAI2BSEL)
192  uint32_t Sai2BClockSelection;
194 #endif /* RCC_CDCCIP1R_SAI2BSEL */
195 
196  uint32_t Spi123ClockSelection;
199  uint32_t Spi45ClockSelection;
202  uint32_t SpdifrxClockSelection;
205  uint32_t Dfsdm1ClockSelection;
208 #if defined(DFSDM2_BASE)
209  uint32_t Dfsdm2ClockSelection;
211 #endif /* DFSDM2_BASE */
212 
213 #if defined(FDCAN1) || defined(FDCAN2)
214  uint32_t FdcanClockSelection;
216 #endif /*FDCAN1 || FDCAN2*/
217 
218  uint32_t Swpmi1ClockSelection;
221  uint32_t Usart234578ClockSelection;
224  uint32_t Usart16ClockSelection;
227  uint32_t RngClockSelection;
230 #if defined(I2C5)
231  uint32_t I2c1235ClockSelection;
233 #else
234  uint32_t I2c123ClockSelection;
236 #endif /*I2C5*/
237 
238  uint32_t UsbClockSelection;
241  uint32_t CecClockSelection;
244  uint32_t Lptim1ClockSelection;
247  uint32_t Lpuart1ClockSelection;
250  uint32_t I2c4ClockSelection;
253  uint32_t Lptim2ClockSelection;
256  uint32_t Lptim345ClockSelection;
259  uint32_t AdcClockSelection;
261 #if defined(SAI4)
262  uint32_t Sai4AClockSelection;
265  uint32_t Sai4BClockSelection;
267 #endif /* SAI4 */
268 
269  uint32_t Spi6ClockSelection;
272  uint32_t RTCClockSelection;
275 #if defined(HRTIM1)
276  uint32_t Hrtim1ClockSelection;
278 #endif /* HRTIM1 */
279 
280  uint32_t TIMPresSelection;
282 }RCC_PeriphCLKInitTypeDef;
283 
285 #if defined(I2C5)
286 #define I2c123ClockSelection I2c1235ClockSelection
287 #else
288 #define I2c1235ClockSelection I2c123ClockSelection
289 #endif /*I2C5*/
290 
291 
295 typedef struct
296 {
297  uint32_t Prescaler;
300  uint32_t Source;
303  uint32_t Polarity;
306  uint32_t ReloadValue;
310  uint32_t ErrorLimitValue;
313  uint32_t HSI48CalibrationValue;
316 }RCC_CRSInitTypeDef;
317 
321 typedef struct
322 {
323  uint32_t ReloadValue;
326  uint32_t HSI48CalibrationValue;
329  uint32_t FreqErrorCapture;
333  uint32_t FreqErrorDirection;
338 }RCC_CRSSynchroInfoTypeDef;
339 
345 /* Exported constants --------------------------------------------------------*/
354 #if defined(UART9) && defined(USART10)
355 #define RCC_PERIPHCLK_USART16910 (0x00000001U)
356 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910
357 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910
358 #define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910
359 #define RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910
360 /*alias*/
361 #define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910
362 #else
363 #define RCC_PERIPHCLK_USART16 (0x00000001U)
364 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16
365 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16
366 /* alias */
367 #define RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16
368 #endif /* UART9 && USART10*/
369 #define RCC_PERIPHCLK_USART234578 (0x00000002U)
370 #define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578
371 #define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578
372 #define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578
373 #define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578
374 #define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
375 #define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
376 #define RCC_PERIPHCLK_LPUART1 (0x00000004U)
377 #if defined(I2C5)
378 #define RCC_PERIPHCLK_I2C1235 (0x00000008U)
379 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235
380 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235
381 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235
382 /* alias */
383 #define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235
384 #else
385 #define RCC_PERIPHCLK_I2C123 (0x00000008U)
386 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
387 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
388 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
389 #endif /*I2C5*/
390 #define RCC_PERIPHCLK_I2C4 (0x00000010U)
391 #if defined(I2C5)
392 #define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235
393 #endif /*I2C5*/
394 #define RCC_PERIPHCLK_LPTIM1 (0x00000020U)
395 #define RCC_PERIPHCLK_LPTIM2 (0x00000040U)
396 #define RCC_PERIPHCLK_LPTIM345 (0x00000080U)
397 #define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345
398 #if defined(LPTIM4)
399 #define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345
400 #endif /*LPTIM4*/
401 #if defined(LPTIM5)
402 #define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345
403 #endif /*LPTIM5*/
404 #define RCC_PERIPHCLK_SAI1 (0x00000100U)
405 #if defined(SAI3)
406 #define RCC_PERIPHCLK_SAI23 (0x00000200U)
407 #define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23
408 #define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23
409 #endif /* SAI3 */
410 #if defined(RCC_CDCCIP1R_SAI2ASEL_0)
411 #define RCC_PERIPHCLK_SAI2A (0x00000200U)
412 #endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
413 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
414 #define RCC_PERIPHCLK_SAI2B (0x00000400U)
415 #endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
416 #if defined(SAI4)
417 #define RCC_PERIPHCLK_SAI4A (0x00000400U)
418 #define RCC_PERIPHCLK_SAI4B (0x00000800U)
419 #endif /* SAI4 */
420 #define RCC_PERIPHCLK_SPI123 (0x00001000U)
421 #define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123
422 #define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123
423 #define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123
424 #define RCC_PERIPHCLK_SPI45 (0x00002000U)
425 #define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45
426 #define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45
427 #define RCC_PERIPHCLK_SPI6 (0x00004000U)
428 #define RCC_PERIPHCLK_FDCAN (0x00008000U)
429 #define RCC_PERIPHCLK_SDMMC (0x00010000U)
430 #define RCC_PERIPHCLK_RNG (0x00020000U)
431 #define RCC_PERIPHCLK_USB (0x00040000U)
432 #define RCC_PERIPHCLK_ADC (0x00080000U)
433 #define RCC_PERIPHCLK_SWPMI1 (0x00100000U)
434 #define RCC_PERIPHCLK_DFSDM1 (0x00200000U)
435 #if defined(DFSDM2_BASE)
436 #define RCC_PERIPHCLK_DFSDM2 (0x00000800U)
437 #endif /* DFSDM2 */
438 #define RCC_PERIPHCLK_RTC (0x00400000U)
439 #define RCC_PERIPHCLK_CEC (0x00800000U)
440 #define RCC_PERIPHCLK_FMC (0x01000000U)
441 #if defined(QUADSPI)
442 #define RCC_PERIPHCLK_QSPI (0x02000000U)
443 #endif /* QUADSPI */
444 #if defined(OCTOSPI1) || defined(OCTOSPI2)
445 #define RCC_PERIPHCLK_OSPI (0x02000000U)
446 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
447 #define RCC_PERIPHCLK_DSI (0x04000000U)
448 #define RCC_PERIPHCLK_SPDIFRX (0x08000000U)
449 #if defined(HRTIM1)
450 #define RCC_PERIPHCLK_HRTIM1 (0x10000000U)
451 #endif /* HRTIM1 */
452 #if defined(LTDC)
453 #define RCC_PERIPHCLK_LTDC (0x20000000U)
454 #endif /* LTDC */
455 #define RCC_PERIPHCLK_TIM (0x40000000U)
456 #define RCC_PERIPHCLK_CKPER (0x80000000U)
457 
466 #define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
467 #define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
468 #define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN
469 
477 #define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
478 #define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
479 #define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN
480 
488 #define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
489 #define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
490 #define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
491 #define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
501 #define RCC_PLL2VCOWIDE (0x00000000U)
502 #define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL
503 
511 #define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
512 #define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
513 #define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
514 #define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
524 #define RCC_PLL3VCOWIDE (0x00000000U)
525 #define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL
526 
534 #if defined(RCC_D2CCIP2R_USART16SEL)
535 #define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U)
536 /* alias */
537 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
538 #define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
539 #define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
540 #define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
541 #define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
542 #define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
543 
544 #elif defined(RCC_CDCCIP2R_USART16910SEL)
545 #define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U)
546 /* alias */
547 #define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
548 #define RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0
549 #define RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1
550 #define RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
551 #define RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2
552 #define RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
553 
554 /* Aliases */
555 #define RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
556 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
557 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
558 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
559 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
560 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
561 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
562 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
563 
564 #else /* RCC_D2CCIP2R_USART16910SEL */
565 #define RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U)
566 #define RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0
567 #define RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1
568 #define RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
569 #define RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2
570 #define RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
571 
572 /* Aliases */
573 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2
574 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2
575 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
576 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
577 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
578 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
579 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
580 #endif /* RCC_D2CCIP2R_USART16SEL */
581 
588 #define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
589 #define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
590 #define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
591 #define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
592 #define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
593 #define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
594 
601 #define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
602 #define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
603 #define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
604 #define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
605 #define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
606 #define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
607 
612 #if defined(UART9)
613 
616 #define RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
617 #define RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
618 #define RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
619 #define RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
620 #define RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
621 #define RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
622 
625 #endif /* UART9 */
626 
627 #if defined(USART10)
628 
631 #define RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
632 #define RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
633 #define RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
634 #define RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
635 #define RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
636 #define RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
637 
640 #endif /* USART10 */
641 
645 #if defined(RCC_D2CCIP2R_USART28SEL)
646 #define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U)
647 /* alias */
648 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
649 #define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
650 #define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
651 #define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
652 #define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
653 #define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
654 #else
655 #define RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U)
656 /* alias */
657 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
658 #define RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
659 #define RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0
660 #define RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1
661 #define RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
662 #define RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2
663 #define RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
664 #endif /* RCC_D2CCIP2R_USART28SEL */
665 
672 #define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
673 #define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
674 #define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
675 #define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
676 #define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
677 #define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
678 
686 #define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
687 #define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
688 #define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
689 #define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
690 #define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
691 #define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
692 
700 #define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
701 #define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
702 #define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
703 #define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
704 #define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
705 #define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
706 
714 #define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
715 #define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
716 #define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
717 #define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
718 #define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
719 #define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
720 
728 #define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
729 #define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
730 #define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
731 #define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
732 #define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
733 #define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
734 
742 #define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
743 #define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
744 #define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
745 #define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
746 #define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
747 #define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
748 
756 #if defined(RCC_D3CCIPR_LPUART1SEL)
757 #define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U)
758 /* alias */
759 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_D3PCLK1
760 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0
761 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1
762 #define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
763 #define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2
764 #define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
765 #else
766 #define RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U)
767 /* alias*/
768 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4
769 #define RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4
770 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0
771 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1
772 #define RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
773 #define RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2
774 #define RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
775 #endif /* RCC_D3CCIPR_LPUART1SEL */
776 
783 #if defined (RCC_D2CCIP2R_I2C123SEL)
784 #define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U)
785 #define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
786 #define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
787 #define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
788 /* aliases */
789 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
790 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
791 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
792 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
793 #elif defined(RCC_CDCCIP2R_I2C123SEL)
794 #define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U)
795 /* alias */
796 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1
797 #define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0
798 #define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1
799 #define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
800 /* aliases */
801 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
802 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
803 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
804 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
805 #elif defined(I2C5)
806 #define RCC_I2C1235CLKSOURCE_D2PCLK1 (0x00000000U)
807 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C1235SEL_0
808 #define RCC_I2C1235CLKSOURCE_HSI RCC_D2CCIP2R_I2C1235SEL_1
809 #define RCC_I2C1235CLKSOURCE_CSI (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
810 /* aliases */
811 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
812 #define RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
813 #define RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
814 #define RCC_I2C123CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
815 #endif /* RCC_D2CCIP2R_I2C123SEL */
816 
823 #if defined(I2C5)
824 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
825 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
826 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
827 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
828 #else
829 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
830 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
831 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
832 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
833 #endif /*I2C5*/
834 
842 #if defined(I2C5)
843 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
844 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
845 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
846 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
847 #else
848 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
849 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
850 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
851 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
852 #endif /*I2C5*/
853 
861 #if defined(I2C5)
862 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
863 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
864 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
865 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
866 #else
867 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
868 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
869 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
870 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
871 #endif /*I2C5*/
872 
880 #if defined(RCC_D3CCIPR_I2C4SEL)
881 #define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U)
882 #define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0
883 #define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1
884 #define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
885 #else
886 #define RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U)
887 /* alias */
888 #define RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4
889 #define RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0
890 #define RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1
891 #define RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
892 #endif /* RCC_D3CCIPR_I2C4SEL */
893 
897 #if defined(I2C5)
898 
901 #define RCC_I2C5CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
902 #define RCC_I2C5CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
903 #define RCC_I2C5CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
904 #define RCC_I2C5CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
905 
909 #endif /*I2C5*/
910 
914 #if defined(RCC_D2CCIP2R_RNGSEL)
915 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
916 #define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0
917 #define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1
918 #define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL
919 #else
920 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
921 #define RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0
922 #define RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1
923 #define RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL
924 #endif /* RCC_D2CCIP2R_RNGSEL */
925 
929 #if defined(HRTIM1)
930 
934 #define RCC_HRTIM1CLK_TIMCLK (0x00000000U)
935 #define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL
936 
940 #endif /*HRTIM1*/
941 
945 #if defined(RCC_D2CCIP2R_USBSEL)
946 #define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
947 #define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
948 #define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL
949 #else
950 #define RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0
951 #define RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1
952 #define RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL
953 #endif /* RCC_D2CCIP2R_USBSEL */
954 
962 #if defined(RCC_D2CCIP1R_SAI1SEL)
963 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U)
964 #define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0
965 #define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1
966 #define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
967 #define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2
968 #else
969 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U)
970 #define RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0
971 #define RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1
972 #define RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
973 #define RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2
974 #endif /* RCC_D2CCIP1R_SAI1SEL */
975 
979 #if defined(SAI3)
980 
983 #define RCC_SAI23CLKSOURCE_PLL (0x00000000U)
984 #define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
985 #define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
986 #define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
987 #define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2
988 
995 #define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
996 #define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
997 #define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
998 #define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
999 #define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
1000 
1008 #define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
1009 #define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
1010 #define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
1011 #define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
1012 #define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
1013 
1016 #endif /* SAI3 */
1017 
1018 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1019 
1022 #define RCC_SAI2ACLKSOURCE_PLL (0x00000000U)
1023 #define RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0
1024 #define RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1
1025 #define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
1026 #define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2
1027 #define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
1028 
1031 #endif /* RCC_CDCCIP1R_SAI2ASEL */
1032 
1033 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1034 
1037 #define RCC_SAI2BCLKSOURCE_PLL (0x00000000U)
1038 #define RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0
1039 #define RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1
1040 #define RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
1041 #define RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2
1042 #define RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
1043 
1046 #endif /* RCC_CDCCIP1R_SAI2BSEL */
1047 
1048 
1052 #if defined(RCC_D2CCIP1R_SPI123SEL)
1053 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U)
1054 #define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0
1055 #define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
1056 #define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
1057 #define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2
1058 #else
1059 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U)
1060 #define RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0
1061 #define RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1
1062 #define RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
1063 #define RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2
1064 #endif /* RCC_D2CCIP1R_SPI123SEL */
1065 
1072 #define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1073 #define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1074 #define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1075 #define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1076 #define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1077 
1085 #define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1086 #define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1087 #define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1088 #define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1089 #define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1090 
1098 #define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1099 #define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1100 #define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1101 #define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1102 #define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1103 
1111 #if defined(RCC_D2CCIP1R_SPI45SEL)
1112 #define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U)
1113 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
1114 #define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
1115 #define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
1116 #define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
1117 #define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
1118 #define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
1119 #else
1120 #define RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U)
1121 /* aliases */
1122 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
1123 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1
1124 #define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0
1125 #define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1
1126 #define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
1127 #define RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2
1128 #define RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
1129 #endif /* RCC_D2CCIP1R_SPI45SEL */
1130 
1137 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
1138 #define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
1139 #define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
1140 #define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
1141 #define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
1142 #define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
1143 
1151 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
1152 #define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
1153 #define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
1154 #define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
1155 #define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
1156 #define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
1157 
1165 #if defined(RCC_D3CCIPR_SPI6SEL)
1166 #define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U)
1167 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_D3PCLK1
1168 #define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0
1169 #define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1
1170 #define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
1171 #define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2
1172 #define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
1173 #else
1174 #define RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U)
1175 /* alias */
1176 #define RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
1177 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4
1178 #define RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0
1179 #define RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1
1180 #define RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
1181 #define RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2
1182 #define RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
1183 #define RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
1184 #endif /* RCC_D3CCIPR_SPI6SEL */
1185 
1191 #if defined(SAI4_Block_A)
1192 
1195 #define RCC_SAI4ACLKSOURCE_PLL (0x00000000U)
1196 #define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0
1197 #define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1
1198 #define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
1199 #define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2
1200 #if defined(RCC_VER_3_0)
1201 #define RCC_SAI4ACLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
1202 #endif /*RCC_VER_3_0*/
1203 
1207 #endif /* SAI4_Block_A */
1208 
1209 
1210 
1211 #if defined(SAI4_Block_B)
1212 
1215 #define RCC_SAI4BCLKSOURCE_PLL (0x00000000U)
1216 #define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0
1217 #define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1
1218 #define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
1219 #define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2
1220 #if defined(RCC_VER_3_0)
1221 #define RCC_SAI4BCLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
1222 #endif /* RCC_VER_3_0 */
1223 
1227 #endif /* SAI4_Block_B */
1228 
1229 
1233 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
1234 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U)
1235 /* alias */
1236 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_D2PCLK1
1237 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0
1238 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1
1239 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
1240 #define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2
1241 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
1242 #else
1243 #define RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U)
1244 /* alias */
1245 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
1246 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
1247 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0
1248 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1
1249 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
1250 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2
1251 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
1252 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
1253 
1261 #if defined(RCC_D3CCIPR_LPTIM2SEL)
1262 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U)
1263 /* alias */
1264 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_D3PCLK1
1265 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0
1266 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1
1267 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
1268 #define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2
1269 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
1270 #else
1271 #define RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U)
1272 /*alias*/
1273 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4
1274 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4
1275 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0
1276 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1
1277 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
1278 #define RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2
1279 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
1280 #endif /* RCC_D3CCIPR_LPTIM2SEL */
1281 
1288 #if defined(RCC_D3CCIPR_LPTIM345SEL)
1289 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U)
1290 /* alias*/
1291 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_D3PCLK1
1292 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
1293 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
1294 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
1295 #define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
1296 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
1297 #else
1298 #define RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U)
1299 /* alias */
1300 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4
1301 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4
1302 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0
1303 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1
1304 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
1305 #define RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2
1306 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
1307 #endif /* RCC_D3CCIPR_LPTIM345SEL */
1308 
1315 #define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1316 #define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1317 #define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1318 #define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1319 #define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1320 #define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1321 
1325 #if defined(LPTIM4)
1326 
1329 #define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1330 #define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1331 #define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1332 #define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1333 #define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1334 #define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1335 
1338 #endif /* LPTIM4 */
1339 
1340 #if defined(LPTIM5)
1341 
1344 #define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1345 #define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1346 #define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1347 #define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1348 #define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1349 #define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1350 
1354 #endif /* LPTIM5 */
1355 
1356 #if defined(QUADSPI)
1357 
1360 #define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U)
1361 #define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0
1362 #define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1
1363 #define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL
1364 
1368 #endif /* QUADSPI */
1369 
1370 
1371 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1372 
1376 #if defined(RCC_CDCCIPR_OCTOSPISEL)
1377 #define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U)
1378 /*aliases*/
1379 #define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK
1380 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK
1381 #define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0
1382 #define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1
1383 #define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL
1384 #else
1385 #define RCC_OSPICLKSOURCE_D1HCLK (0x00000000U)
1386 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_D1HCLK
1387 #define RCC_OSPICLKSOURCE_PLL RCC_D1CCIPR_OCTOSPISEL_0
1388 #define RCC_OSPICLKSOURCE_PLL2 RCC_D1CCIPR_OCTOSPISEL_1
1389 #define RCC_OSPICLKSOURCE_CLKP RCC_D1CCIPR_OCTOSPISEL
1390 #endif /* RCC_CDCCIPR_OCTOSPISEL */
1391 
1392 
1396 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
1397 
1398 #if defined(DSI)
1399 
1402 #define RCC_DSICLKSOURCE_PHY (0x00000000U)
1403 #define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL
1404 
1408 #endif /* DSI */
1409 
1413 #if defined(RCC_D1CCIPR_FMCSEL)
1414 #define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U)
1415 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_D1HCLK
1416 #define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0
1417 #define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1
1418 #define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL
1419 #else
1420 #define RCC_FMCCLKSOURCE_CDHCLK (0x00000000U)
1421 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK
1422 /*alias*/
1423 #define RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK
1424 #define RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0
1425 #define RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1
1426 #define RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL
1427 #endif /* RCC_D1CCIPR_FMCSEL */
1428 
1432 #if defined(FDCAN1) || defined(FDCAN2)
1433 
1436 #if defined(RCC_D2CCIP1R_FDCANSEL)
1437 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U)
1438 #define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0
1439 #define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1
1440 #else
1441 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U)
1442 #define RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0
1443 #define RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1
1444 #endif /* D3_SRAM_BASE */
1445 
1448 #endif /*FDCAN1 || FDCAN2*/
1449 
1450 
1454 #if defined(RCC_D1CCIPR_SDMMCSEL)
1455 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
1456 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL
1457 #else
1458 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
1459 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL
1460 #endif /* RCC_D1CCIPR_SDMMCSEL */
1461 
1469 #if defined(RCC_D3CCIPR_ADCSEL_0)
1470 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
1471 #define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0
1472 #define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1
1473 #else
1474 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
1475 #define RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0
1476 #define RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1
1477 #endif /* RCC_D3CCIPR_ADCSEL_0 */
1478 
1485 #if defined(RCC_D2CCIP1R_SWPSEL)
1486 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U)
1487 #define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL
1488 #else
1489 #define RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U)
1490 /* alias */
1491 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1
1492 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL
1493 #endif /* RCC_D2CCIP1R_SWPSEL */
1494 
1501 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
1502 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U)
1503 #define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL
1504 #else
1505 #define RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U)
1506 /* alias */
1507 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1
1508 #define RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL
1509 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
1510 
1514 #if defined(DFSDM2_BASE)
1515 
1518 #define RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U)
1519 /* alias */
1520 #define RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4
1521 #define RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL
1522 
1525 #endif /* DFSDM2 */
1526 
1530 #if defined(RCC_D2CCIP1R_SPDIFSEL_0)
1531 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
1532 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0
1533 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1
1534 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL
1535 #else
1536 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
1537 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0
1538 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1
1539 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL
1540 #endif /* RCC_D2CCIP1R_SPDIFSEL_0 */
1541 
1548 #if defined(RCC_D2CCIP2R_CECSEL_0)
1549 #define RCC_CECCLKSOURCE_LSE (0x00000000U)
1550 #define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0
1551 #define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1
1552 #else
1553 #define RCC_CECCLKSOURCE_LSE (0x00000000U)
1554 #define RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0
1555 #define RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1
1556 #endif /* RCC_D2CCIP2R_CECSEL_0 */
1557 
1565 #if defined(RCC_D1CCIPR_CKPERSEL_0)
1566 #define RCC_CLKPSOURCE_HSI (0x00000000U)
1567 #define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0
1568 #define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1
1569 #else
1570 #define RCC_CLKPSOURCE_HSI (0x00000000U)
1571 #define RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0
1572 #define RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1
1573 #endif /* RCC_D1CCIPR_CKPERSEL_0 */
1574 
1581 #define RCC_TIMPRES_DESACTIVATED (0x00000000U)
1582 #define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE
1583 
1588 #if defined(DUAL_CORE)
1589 
1593 #define RCC_BOOT_C1 RCC_GCR_BOOT_C1
1594 #define RCC_BOOT_C2 RCC_GCR_BOOT_C2
1595 
1599 #endif /*DUAL_CORE*/
1600 
1601 #if defined(DUAL_CORE)
1602 
1605 #define RCC_WWDG1 RCC_GCR_WW1RSC
1606 #define RCC_WWDG2 RCC_GCR_WW2RSC
1607 
1612 #else
1613 
1617 #define RCC_WWDG1 RCC_GCR_WW1RSC
1618 
1623 #endif /*DUAL_CORE*/
1624 
1628 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18
1636 #define RCC_CRS_NONE (0x00000000U)
1637 #define RCC_CRS_TIMEOUT (0x00000001U)
1638 #define RCC_CRS_SYNCOK (0x00000002U)
1639 #define RCC_CRS_SYNCWARN (0x00000004U)
1640 #define RCC_CRS_SYNCERR (0x00000008U)
1641 #define RCC_CRS_SYNCMISS (0x00000010U)
1642 #define RCC_CRS_TRIMOVF (0x00000020U)
1643 
1650 #define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U)
1651 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
1652 #define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1
1653 #define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)
1663 #define RCC_CRS_SYNC_DIV1 (0x00000000U)
1664 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
1665 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
1666 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
1667 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
1668 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
1669 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
1670 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV
1678 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U)
1679 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
1687 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU)
1696 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U)
1704 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U)
1714 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U)
1715 #define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR)
1723 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
1724 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
1725 #define RCC_CRS_IT_ERR CRS_CR_ERRIE
1726 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
1727 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
1728 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
1729 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE
1738 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
1739 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
1740 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF
1741 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
1742 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
1743 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
1744 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF
1756 /* Exported macro ------------------------------------------------------------*/
1757 
1767 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
1768 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
1769 
1786 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
1787 
1788 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
1789 
1795 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
1796 
1797 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
1798 
1831 #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
1832  do{ \
1833  MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
1834  WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
1835  ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
1836  } while(0)
1837 
1854 #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \
1855  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
1856 
1866 #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
1867  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
1868 
1869 
1880 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
1881  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
1882 
1889 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
1890 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
1891 
1897 #define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
1898 
1899 #define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
1900 
1917 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
1918 
1919 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
1920 
1953 #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
1954  do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \
1955  WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
1956  ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
1957  } while(0)
1958 
1959 
1960 
1977  #define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
1978 
1988 #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
1989  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
1990 
1991 
2002 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
2003  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
2004 
2016 #if defined(RCC_D2CCIP1R_SAI1SEL)
2017 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
2018  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
2019 #else
2020 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
2021  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
2022 #endif /* RCC_D2CCIP1R_SAI1SEL */
2023 
2032 #if defined(RCC_D2CCIP1R_SAI1SEL)
2033 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
2034 #else
2035 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
2036 #endif /* RCC_D2CCIP1R_SAI1SEL */
2037 
2049 #if defined(RCC_D2CCIP1R_SPDIFSEL)
2050 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
2051  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
2052 #else
2053 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
2054  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
2055 #endif /* RCC_D2CCIP1R_SPDIFSEL */
2056 
2061 #if defined(RCC_D2CCIP1R_SPDIFSEL)
2062 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
2063 #else
2064 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
2065 #endif /* RCC_D2CCIP1R_SPDIFSEL */
2066 
2067 #if defined(SAI3)
2068 
2080 #define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
2081  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
2082 
2091 #define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
2092 
2105 #define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG
2106 
2115 #define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE
2116 
2129 #define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG
2130 
2139 #define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE
2140 #endif /* SAI3 */
2141 
2142 #if defined(RCC_CDCCIP1R_SAI2ASEL)
2143 
2156 #define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\
2157  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
2158 
2168 #define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
2169 #endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */
2170 
2171 #if defined(RCC_CDCCIP1R_SAI2BSEL)
2172 
2185 #define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\
2186  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
2187 
2197 #define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
2198 #endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */
2199 
2200 
2201 #if defined(SAI4_Block_A)
2202 
2214 #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
2215  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
2216 
2225 #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
2226 #endif /* SAI4_Block_A */
2227 
2228 #if defined(SAI4_Block_B)
2229 
2241 #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
2242  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
2243 
2252 #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
2253 #endif /* SAI4_Block_B */
2254 
2266 #if defined(RCC_D2CCIP2R_I2C123SEL)
2267 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \
2268  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))
2269 #elif defined(RCC_CDCCIP2R_I2C123SEL)
2270 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \
2271  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))
2272 #else /* RCC_D2CCIP2R_I2C1235SEL */
2273 #define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \
2274  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))
2275 /* alias */
2276 #define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG
2277 #endif /* RCC_D2CCIP2R_I2C123SEL */
2278 
2288 #if defined(RCC_D2CCIP2R_I2C123SEL)
2289 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
2290 #elif defined(RCC_CDCCIP2R_I2C123SEL)
2291 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
2292 #else /* RCC_D2CCIP2R_I2C1235SEL */
2293 #define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))
2294 /* alias */
2295 #define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2296 #endif /* RCC_D2CCIP2R_I2C123SEL */
2297 
2307 #if defined(I2C5)
2308 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG
2309 #else
2310 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG
2311 #endif /*I2C5*/
2312 
2320 #if defined(I2C5)
2321 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2322 #else
2323 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2324 #endif /*I2C5*/
2325 
2335 #if defined(I2C5)
2336 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG
2337 #else
2338 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
2339 #endif /*I2C5*/
2340 
2348 #if defined(I2C5)
2349 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2350 #else
2351 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2352 #endif /*I2C5*/
2353 
2363 #if defined(I2C5)
2364 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG
2365 #else
2366 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
2367 #endif /*I2C5*/
2368 
2376 #if defined(I2C5)
2377 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2378 #else
2379 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2380 #endif /*I2C5*/
2381 
2391 #if defined(RCC_D3CCIPR_I2C4SEL)
2392 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
2393  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
2394 #else
2395 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
2396  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
2397 #endif /* RCC_D3CCIPR_I2C4SEL */
2398 
2406 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
2407 
2408 #if defined(I2C5)
2409 
2418 #define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG
2419 #endif /* I2C5 */
2420 
2421 #if defined(I2C5)
2422 
2429 #define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2430 #endif /* I2C5 */
2431 
2445 #if defined(RCC_D2CCIP2R_USART16SEL)
2446 #define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \
2447  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__))
2448 #elif defined(RCC_CDCCIP2R_USART16910SEL)
2449 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
2450  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
2451 /* alias */
2452 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
2453 #else /* RCC_D2CCIP2R_USART16910SEL */
2454 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
2455  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
2456 /* alias */
2457 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
2458 #endif /* RCC_D2CCIP2R_USART16SEL */
2459 
2471 #if defined(RCC_D2CCIP2R_USART16SEL)
2472 #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
2473 #elif defined(RCC_CDCCIP2R_USART16910SEL)
2474 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
2475 /* alias*/
2476 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
2477 #else /* RCC_D2CCIP2R_USART16910SEL */
2478 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))
2479 /* alias */
2480 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
2481 #endif /* RCC_D2CCIP2R_USART16SEL */
2482 
2494 #if defined(RCC_D2CCIP2R_USART28SEL)
2495 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
2496  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
2497 #else
2498 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
2499  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
2500 #endif /* RCC_D2CCIP2R_USART28SEL */
2501 
2511 #if defined(RCC_D2CCIP2R_USART28SEL)
2512 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
2513 #else
2514 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
2515 #endif /* RCC_D2CCIP2R_USART28SEL */
2516 
2528 #define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG
2529 
2539 #define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE
2540 
2552 #define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG
2553 
2563 #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2564 
2576 #define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG
2577 
2587 #define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2588 
2600 #define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG
2601 
2611 #define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2612 
2624 #define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG
2625 
2635 #define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2636 
2648 #define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG
2649 
2659 #define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE
2660 
2672 #define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG
2673 
2683 #define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2684 
2696 #define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG
2697 
2707 #define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2708 
2709 #if defined(UART9)
2710 
2721 #define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG
2722 
2732 #define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE
2733 #endif /* UART9 */
2734 
2735 #if defined(USART10)
2736 
2747 #define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG
2748 
2758 #define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE
2759 #endif /* USART10 */
2760 
2772 #if defined (RCC_D3CCIPR_LPUART1SEL)
2773 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
2774  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
2775 #else
2776 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
2777  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
2778 #endif /* RCC_D3CCIPR_LPUART1SEL */
2779 
2789 #if defined (RCC_D3CCIPR_LPUART1SEL)
2790 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
2791 #else
2792 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
2793 #endif /* RCC_D3CCIPR_LPUART1SEL */
2794 
2806 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
2807 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
2808  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
2809 #else
2810 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
2811  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
2812 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
2813 
2823 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
2824 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
2825 #else
2826 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
2827 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
2828 
2840 #if defined(RCC_D3CCIPR_LPTIM2SEL)
2841 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
2842  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
2843 #else
2844 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
2845  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
2846 #endif /* RCC_D3CCIPR_LPTIM2SEL */
2847 
2857 #if defined(RCC_D3CCIPR_LPTIM2SEL)
2858 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
2859 #else
2860 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
2861 #endif /* RCC_D3CCIPR_LPTIM2SEL */
2862 
2873 #if defined(RCC_D3CCIPR_LPTIM345SEL)
2874 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
2875  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
2876 #else
2877 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
2878  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__))
2879 #endif /* RCC_D3CCIPR_LPTIM345SEL */
2880 
2890 #if defined(RCC_D3CCIPR_LPTIM345SEL)
2891 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
2892 #else
2893 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
2894 #endif /* RCC_D3CCIPR_LPTIM345SEL */
2895 
2906 #define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG
2907 
2917 #define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
2918 
2919 #if defined(LPTIM4)
2920 
2930 #define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG
2931 
2932 
2942 #define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
2943 #endif /* LPTIM4 */
2944 
2945 #if defined(LPTIM5)
2946 
2956 #define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG
2957 
2958 
2968 #define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
2969 #endif /* LPTIM5 */
2970 
2971 #if defined(QUADSPI)
2972 
2980 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
2981  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
2982 
2983 
2991 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
2992 #endif /* QUADSPI */
2993 
2994 #if defined(OCTOSPI1) || defined(OCTOSPI2)
2995 
3003 #if defined(RCC_CDCCIPR_OCTOSPISEL)
3004 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
3005  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
3006 #else
3007 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
3008  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
3009 #endif /* RCC_CDCCIPR_OCTOSPISEL */
3010 
3018 #if defined(RCC_CDCCIPR_OCTOSPISEL)
3019 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
3020 #else
3021 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)))
3022 #endif /* RCC_CDCCIPR_OCTOSPISEL */
3023 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
3024 
3025 
3026 #if defined(DSI)
3027 
3033 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
3034  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
3035 
3036 
3042 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
3043 #endif /*DSI*/
3044 
3053 #if defined(RCC_D1CCIPR_FMCSEL)
3054 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
3055  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
3056 #else
3057 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
3058  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
3059 #endif /* RCC_D1CCIPR_FMCSEL */
3060 
3068 #if defined(RCC_D1CCIPR_FMCSEL)
3069 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
3070 #else
3071 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
3072 #endif /* RCC_D1CCIPR_FMCSEL */
3073 
3081 #if defined(RCC_D2CCIP2R_USBSEL)
3082 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
3083  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
3084 #else
3085 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
3086  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
3087 #endif /* RCC_D2CCIP2R_USBSEL */
3088 
3095 #if defined(RCC_D2CCIP2R_USBSEL)
3096 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
3097 #else
3098 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
3099 #endif /* RCC_D2CCIP2R_USBSEL */
3100 
3108 #if defined(RCC_D3CCIPR_ADCSEL)
3109 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
3110  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
3111 #else
3112 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
3113  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
3114 #endif /* RCC_D3CCIPR_ADCSEL */
3115 
3122 #if defined(RCC_D3CCIPR_ADCSEL)
3123 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
3124 #else
3125 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
3126 #endif /* RCC_D3CCIPR_ADCSEL */
3127 
3134 #if defined(RCC_D2CCIP1R_SWPSEL)
3135 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
3136  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
3137 #else
3138 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
3139  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
3140 #endif /* RCC_D2CCIP1R_SWPSEL */
3141 
3147 #if defined(RCC_D2CCIP1R_SWPSEL)
3148 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
3149 #else
3150 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
3151 #endif /* RCC_D2CCIP1R_SWPSEL */
3152 
3159 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3160 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
3161  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
3162 #else
3163 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
3164  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
3165 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3166 
3172 #if defined (RCC_D2CCIP1R_DFSDM1SEL)
3173 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
3174 #else
3175 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
3176 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3177 
3178 #if defined(DFSDM2_BASE)
3179 
3185 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
3186  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
3187 
3193 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
3194 #endif /* DFSDM2 */
3195 
3204 #if defined(RCC_D2CCIP2R_CECSEL)
3205 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
3206  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
3207 #else
3208 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
3209  MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
3210 #endif /* RCC_D2CCIP2R_CECSEL */
3211 
3218 #if defined(RCC_D2CCIP2R_CECSEL)
3219 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
3220 #else
3221 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
3222 #endif /* RCC_D2CCIP2R_CECSEL */
3223 
3231 #if defined(RCC_D1CCIPR_CKPERSEL)
3232 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
3233  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
3234 #else
3235 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
3236  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
3237 #endif /* RCC_D1CCIPR_CKPERSEL */
3238 
3245 #if defined(RCC_D1CCIPR_CKPERSEL)
3246 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
3247 #else
3248 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
3249 #endif /* RCC_D1CCIPR_CKPERSEL */
3250 
3251 #if defined(FDCAN1) || defined(FDCAN2)
3252 
3259 #if defined(RCC_D2CCIP1R_FDCANSEL)
3260 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
3261  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
3262 #else
3263 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
3264  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
3265 #endif /* RCC_D2CCIP1R_FDCANSEL */
3266 
3273 #if defined(RCC_D2CCIP1R_FDCANSEL)
3274 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
3275 #else
3276 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
3277 #endif /* RCC_D2CCIP1R_FDCANSEL */
3278 
3279 #endif /*FDCAN1 || FDCAN2*/
3280 
3293 #if defined(RCC_D2CCIP1R_SPI123SEL)
3294 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
3295  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
3296 #else
3297 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
3298  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
3299 #endif /* RCC_D2CCIP1R_SPI123SEL */
3300 
3309 #if defined(RCC_D2CCIP1R_SPI123SEL)
3310 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
3311 #else
3312 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
3313 #endif /* RCC_D2CCIP1R_SPI123SEL */
3314 
3327 #define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG
3328 
3337 #define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3338 
3351 #define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG
3352 
3361 #define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3362 
3375 #define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG
3376 
3385 #define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3386 
3400 #if defined(RCC_D2CCIP1R_SPI45SEL)
3401 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
3402  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
3403 #else
3404 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
3405  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
3406 #endif /* RCC_D2CCIP1R_SPI45SEL */
3407 
3417 #if defined(RCC_D2CCIP1R_SPI45SEL)
3418 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
3419 #else
3420 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
3421 #endif /* RCC_D2CCIP1R_SPI45SEL */
3422 
3436 #define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG
3437 
3447 #define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE
3448 
3462 #define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG
3463 
3473 #define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE
3474 
3493 #if defined(RCC_D3CCIPR_SPI6SEL)
3494 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
3495  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
3496 #else
3497 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
3498  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
3499 #endif /* RCC_D3CCIPR_SPI6SEL */
3500 
3511 #if defined(RCC_D3CCIPR_SPI6SEL)
3512 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
3513 #else
3514 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
3515 #endif /* RCC_D3CCIPR_SPI6SEL */
3516 
3523 #if defined(RCC_D1CCIPR_SDMMCSEL)
3524 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
3525  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
3526 #else
3527 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
3528  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
3529 #endif /* RCC_D1CCIPR_SDMMCSEL */
3530 
3533 #if defined(RCC_D1CCIPR_SDMMCSEL)
3534 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
3535 #else
3536 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
3537 #endif /* RCC_D1CCIPR_SDMMCSEL */
3538 
3548 #if defined(RCC_D2CCIP2R_RNGSEL)
3549 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
3550  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
3551 #else
3552 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
3553  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
3554 #endif /* RCC_D2CCIP2R_RNGSEL */
3555 
3563 #if defined(RCC_D2CCIP2R_RNGSEL)
3564 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
3565 #else
3566 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
3567 #endif /* RCC_D2CCIP2R_RNGSEL */
3568 
3569 #if defined(HRTIM1)
3570 
3576 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
3577  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
3578 
3584 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
3585 #endif /* HRTIM1 */
3586 
3597 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
3598  RCC->CFGR |= (__PRESC__); \
3599  }while(0)
3600 
3605 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
3606 
3611 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
3612 
3617 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
3618 
3623 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
3624 
3625 #if defined(DUAL_CORE)
3626 
3630 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
3631 
3636 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
3637 
3642 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
3643 
3648 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
3649 #endif /* DUAL_CORE */
3650 
3655 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
3656 
3657 
3662 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
3663 
3664 
3669 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
3670 
3675 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
3676 
3681 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
3682  do { \
3683  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
3684  __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
3685  } while(0)
3686 
3691 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
3692  do { \
3693  __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
3694  __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
3695  } while(0)
3696 
3701 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
3702 
3707 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
3708 
3709 #if defined(DUAL_CORE)
3710 
3714 #define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
3715 
3720 #define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
3721 #endif /* DUAL_CORE */
3722 
3726 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
3727 
3738 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
3739 
3750 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
3751 
3761 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
3762 
3774 /* CRS IT Error Mask */
3775 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
3776 
3777 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
3778  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
3779  { \
3780  WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
3781  } \
3782  else \
3783  { \
3784  WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
3785  } \
3786  } while(0)
3787 
3801 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
3802 
3818 /* CRS Flag Error Mask */
3819 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
3820 
3821 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
3822  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
3823  { \
3824  WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
3825  } \
3826  else \
3827  { \
3828  WRITE_REG(CRS->ICR, (__FLAG__)); \
3829  } \
3830  } while(0)
3831 
3840 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
3841 
3846 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
3847 
3853 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
3854 
3859 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
3860 
3871 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
3872 
3873 
3884 /* Exported functions --------------------------------------------------------*/
3892 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
3893 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
3894 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
3895 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
3896 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
3897 uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
3898 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
3899 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
3900 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
3908 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
3909 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
3910 void HAL_RCCEx_EnableLSECSS(void);
3911 void HAL_RCCEx_DisableLSECSS(void);
3912 void HAL_RCCEx_EnableLSECSS_IT(void);
3913 void HAL_RCCEx_LSECSS_IRQHandler(void);
3914 void HAL_RCCEx_LSECSS_Callback(void);
3915 #if defined(DUAL_CORE)
3916 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
3917 #endif /*DUAL_CORE*/
3918 #if defined(RCC_GCR_WW1RSC)
3919 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
3920 #endif /*RCC_GCR_WW1RSC*/
3921 
3930 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
3931 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
3932 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
3933 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
3934 void HAL_RCCEx_CRS_IRQHandler(void);
3935 void HAL_RCCEx_CRS_SyncOkCallback(void);
3936 void HAL_RCCEx_CRS_SyncWarnCallback(void);
3937 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
3938 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
3939 
3948  /* Private macros ------------------------------------------------------------*/
3956 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
3957  ((VALUE) == RCC_PLL2_DIVQ) || \
3958  ((VALUE) == RCC_PLL2_DIVR))
3959 
3960 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
3961  ((VALUE) == RCC_PLL3_DIVQ) || \
3962  ((VALUE) == RCC_PLL3_DIVR))
3963 
3964 #if defined(RCC_D2CCIP2R_USART16SEL)
3965 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
3966  ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \
3967  ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \
3968  ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \
3969  ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \
3970  ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
3971 #else
3972 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
3973  ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
3974  ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \
3975  ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \
3976  ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \
3977  ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \
3978  ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
3979 /* alias*/
3980 #define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE
3981 #endif /* RCC_D2CCIP2R_USART16SEL */
3982 
3983 #if defined(RCC_D2CCIP2R_USART28SEL)
3984 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
3985  ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \
3986  ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \
3987  ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \
3988  ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \
3989  ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
3990 #else
3991 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
3992  ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
3993  ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \
3994  ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \
3995  ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \
3996  ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \
3997  ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
3998 #endif /* RCC_D2CCIP2R_USART28SEL */
3999 
4000 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
4001  ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \
4002  ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \
4003  ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \
4004  ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
4005  ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
4006 
4007 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
4008  ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \
4009  ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \
4010  ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \
4011  ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
4012  ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
4013 
4014 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
4015  ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \
4016  ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \
4017  ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \
4018  ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
4019  ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
4020 
4021 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
4022  ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \
4023  ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \
4024  ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \
4025  ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
4026  ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
4027 
4028 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
4029  ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \
4030  ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \
4031  ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \
4032  ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
4033  ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
4034 
4035 #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
4036  ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \
4037  ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \
4038  ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \
4039  ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
4040  ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
4041 
4042 #define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
4043  ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \
4044  ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \
4045  ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \
4046  ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
4047  ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
4048 
4049 #define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
4050  ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \
4051  ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \
4052  ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \
4053  ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
4054  ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
4055 
4056 #if defined(UART9)
4057 #define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
4058  ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \
4059  ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \
4060  ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \
4061  ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \
4062  ((SOURCE) == RCC_UART9CLKSOURCE_HSI))
4063 #endif
4064 
4065 #if defined(USART10)
4066 #define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
4067  ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \
4068  ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \
4069  ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \
4070  ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \
4071  ((SOURCE) == RCC_USART10CLKSOURCE_HSI))
4072 #endif
4073 
4074 #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
4075  ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \
4076  ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \
4077  ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \
4078  ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \
4079  ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
4080 
4081 #if defined(I2C5)
4082 #define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \
4083  ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \
4084  ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \
4085  ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI))
4086 
4087 #define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */
4088 #else
4089 #define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \
4090  ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \
4091  ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
4092  ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
4093 #endif /*I2C5*/
4094 
4095 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \
4096  ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
4097  ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
4098  ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
4099 
4100 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \
4101  ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
4102  ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
4103  ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
4104 
4105 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \
4106  ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
4107  ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
4108  ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
4109 
4110 #define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \
4111  ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \
4112  ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
4113  ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
4114 
4115 #if defined(I2C5)
4116 #define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \
4117  ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \
4118  ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \
4119  ((SOURCE) == RCC_I2C5CLKSOURCE_CSI))
4120 #endif /*I2C5*/
4121 
4122 #define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
4123  ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \
4124  ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \
4125  ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
4126 
4127 #if defined(HRTIM1)
4128 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
4129  ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
4130 #endif
4131 
4132 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
4133  ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
4134  ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
4135 
4136 #define IS_RCC_SAI1CLK(__SOURCE__) \
4137  (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
4138  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
4139  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
4140  ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
4141  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
4142 
4143 #if defined(SAI3)
4144 #define IS_RCC_SAI23CLK(__SOURCE__) \
4145  (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \
4146  ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
4147  ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
4148  ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
4149  ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
4150 
4151 #define IS_RCC_SAI2CLK(__SOURCE__) \
4152  (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
4153  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
4154  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
4155  ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
4156  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
4157 
4158 
4159 #define IS_RCC_SAI3CLK(__SOURCE__) \
4160  (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \
4161  ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
4162  ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
4163  ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
4164  ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
4165 #endif
4166 
4167 #if defined(RCC_CDCCIP1R_SAI2ASEL)
4168 #define IS_RCC_SAI2ACLK(__SOURCE__) \
4169  (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \
4170  ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
4171  ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
4172  ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
4173  ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
4174  ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))
4175 #endif
4176 
4177 #if defined(RCC_CDCCIP1R_SAI2BSEL)
4178 #define IS_RCC_SAI2BCLK(__SOURCE__) \
4179  (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \
4180  ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
4181  ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
4182  ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
4183  ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
4184  ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))
4185 #endif
4186 
4187 #define IS_RCC_SPI123CLK(__SOURCE__) \
4188  (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \
4189  ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
4190  ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
4191  ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
4192  ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
4193 
4194 #define IS_RCC_SPI1CLK(__SOURCE__) \
4195  (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \
4196  ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
4197  ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
4198  ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
4199  ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
4200 
4201 #define IS_RCC_SPI2CLK(__SOURCE__) \
4202  (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \
4203  ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
4204  ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
4205  ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
4206  ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
4207 
4208 #define IS_RCC_SPI3CLK(__SOURCE__) \
4209  (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \
4210  ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
4211  ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
4212  ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
4213  ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
4214 
4215 #define IS_RCC_SPI45CLK(__SOURCE__) \
4216  (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \
4217  ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \
4218  ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \
4219  ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \
4220  ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \
4221  ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
4222 
4223 #define IS_RCC_SPI4CLK(__SOURCE__) \
4224  (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \
4225  ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \
4226  ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \
4227  ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \
4228  ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \
4229  ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
4230 
4231 #define IS_RCC_SPI5CLK(__SOURCE__) \
4232  (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
4233  ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \
4234  ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \
4235  ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \
4236  ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \
4237  ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
4238 
4239 #if defined(RCC_D3CCIPR_SPI6SEL)
4240 #define IS_RCC_SPI6CLK(__SOURCE__) \
4241  (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
4242  ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \
4243  ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \
4244  ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
4245  ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
4246  ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
4247 #else
4248 #define IS_RCC_SPI6CLK(__SOURCE__) \
4249  (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
4250  ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \
4251  ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \
4252  ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
4253  ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
4254  ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \
4255  ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
4256 #endif /* RCC_D3CCIPR_SPI6SEL */
4257 
4258 #if defined(SAI4)
4259 #define IS_RCC_SAI4ACLK(__SOURCE__) \
4260  (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \
4261  ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
4262  ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
4263  ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
4264  ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
4265 
4266 #define IS_RCC_SAI4BCLK(__SOURCE__) \
4267  (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \
4268  ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
4269  ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
4270  ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
4271  ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
4272 #endif /*SAI4*/
4273 
4274 #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
4275 #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
4276 #define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4277 #define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4278 #define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4279 
4280 #define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
4281 #define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
4282 #define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4283 #define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4284 #define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4285 
4286 #define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \
4287  ((VALUE) == RCC_PLL2VCIRANGE_1) || \
4288  ((VALUE) == RCC_PLL2VCIRANGE_2) || \
4289  ((VALUE) == RCC_PLL2VCIRANGE_3))
4290 
4291 #define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \
4292  ((VALUE) == RCC_PLL3VCIRANGE_1) || \
4293  ((VALUE) == RCC_PLL3VCIRANGE_2) || \
4294  ((VALUE) == RCC_PLL3VCIRANGE_3))
4295 
4296 #define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \
4297  ((VALUE) == RCC_PLL2VCOMEDIUM))
4298 
4299 #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \
4300  ((VALUE) == RCC_PLL3VCOMEDIUM))
4301 
4302 #define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
4303 
4304 #define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
4305  ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \
4306  ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \
4307  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \
4308  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
4309  ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
4310 
4311 #define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
4312  ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \
4313  ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \
4314  ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \
4315  ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \
4316  ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
4317 
4318 #define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
4319  ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \
4320  ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \
4321  ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \
4322  ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \
4323  ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
4324 
4325 #define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \
4326  ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \
4327  ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \
4328  ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \
4329  ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \
4330  ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
4331 
4332 #if defined(LPTIM4)
4333 #define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
4334  ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \
4335  ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \
4336  ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \
4337  ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \
4338  ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
4339 #endif /* LPTIM4*/
4340 
4341 #if defined(LPTIM5)
4342 #define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
4343  ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \
4344  ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \
4345  ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \
4346  ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \
4347  ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
4348 #endif /*LPTIM5*/
4349 
4350 #if defined(QUADSPI)
4351 #define IS_RCC_QSPICLK(__SOURCE__) \
4352  (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \
4353  ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \
4354  ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \
4355  ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
4356 #endif /*QUADSPI*/
4357 
4358 #if defined(OCTOSPI1) || defined(OCTOSPI1)
4359 #define IS_RCC_OSPICLK(__SOURCE__) \
4360  (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \
4361  ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \
4362  ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \
4363  ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))
4364 #endif /*OCTOSPI1 || OCTOSPI1*/
4365 
4366 #if defined(DSI)
4367 #define IS_RCC_DSICLK(__SOURCE__) \
4368  (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \
4369  ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
4370 #endif /*DSI*/
4371 
4372 #define IS_RCC_FMCCLK(__SOURCE__) \
4373  (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \
4374  ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \
4375  ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \
4376  ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
4377 
4378 #if defined(FDCAN1) || defined(FDCAN2)
4379 #define IS_RCC_FDCANCLK(__SOURCE__) \
4380  (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
4381  ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
4382  ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
4383 #endif /*FDCAN1 || FDCAN2*/
4384 
4385 #define IS_RCC_SDMMC(__SOURCE__) \
4386  (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \
4387  ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
4388 
4389 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
4390  ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
4391  ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
4392 
4393 #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
4394  ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
4395 
4396 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
4397  ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
4398 
4399 #if defined(DFSDM2_BASE)
4400 #define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
4401  ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))
4402 #endif /*DFSDM2*/
4403 
4404 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \
4405  ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
4406  ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
4407  ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
4408 
4409 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
4410  ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
4411  ((SOURCE) == RCC_CECCLKSOURCE_CSI))
4412 
4413 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \
4414  ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
4415  ((SOURCE) == RCC_CLKPSOURCE_HSE))
4416 #define IS_RCC_TIMPRES(VALUE) \
4417  (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
4418  ((VALUE) == RCC_TIMPRES_ACTIVATED))
4419 
4420 #if defined(DUAL_CORE)
4421 #define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \
4422  ((CORE) == RCC_BOOT_C2))
4423 #endif /*DUAL_CORE*/
4424 
4425 #if defined(DUAL_CORE)
4426 #define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \
4427  ((WWDG) == RCC_WWDG2))
4428 #else
4429 #define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
4430 
4431 #endif /*DUAL_CORE*/
4432 
4433 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
4434  ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
4435  ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
4436  ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
4437 
4438 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
4439  ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
4440  ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
4441  ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
4442 
4443 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
4444  ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
4445 
4446 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
4447 
4448 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
4449 
4450 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
4451 
4452 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
4453  ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
4454 
4470 #ifdef __cplusplus
4471 }
4472 #endif
4473 
4474 #endif /* STM32H7xx_HAL_RCC_EX_H */
4475 
4476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_RCCEx_EnableLSECSS
void HAL_RCCEx_EnableLSECSS(void)
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
HAL_RCCEx_CRS_ErrorCallback
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
RCC_PLL3InitTypeDef
PLL3 Clock structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:79
I2c1235ClockSelection
#define I2c1235ClockSelection
Definition: stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:288
RCC_CRSInitTypeDef
RCC_CRS Init structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:295
HAL_RCCEx_GetD3PCLK1Freq
uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
HAL_RCCEx_WakeUpStopCLKConfig
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
HAL_RCCEx_CRS_SyncOkCallback
void HAL_RCCEx_CRS_SyncOkCallback(void)
HAL_RCCEx_GetPLL1ClockFreq
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
HAL_RCCEx_CRSWaitSynchronization
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
HAL_RCCEx_CRS_SyncWarnCallback
void HAL_RCCEx_CRS_SyncWarnCallback(void)
HAL_RCCEx_CRSSoftwareSynchronizationGenerate
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
HAL_RCCEx_CRSGetSynchronizationInfo
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
HAL_RCCEx_CRSConfig
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:321
PLL2_ClocksTypeDef
RCC PLL2 Clocks structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:121
HAL_RCCEx_EnableLSECSS_IT
void HAL_RCCEx_EnableLSECSS_IT(void)
HAL_RCCEx_GetPLL3ClockFreq
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
HAL_RCCEx_KerWakeUpStopCLKConfig
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
PLL1_ClocksTypeDef
RCC PLL1 Clocks structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:111
HAL_RCCEx_LSECSS_Callback
void HAL_RCCEx_LSECSS_Callback(void)
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
PLL3_ClocksTypeDef
RCC PLL3 Clocks structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:131
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
RCC_PLL2InitTypeDef
PLL2 Clock structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:47
HAL_RCCEx_GetD1PCLK1Freq
uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
HAL_RCCEx_CRS_IRQHandler
void HAL_RCCEx_CRS_IRQHandler(void)
HAL_RCCEx_GetD1SysClockFreq
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:126
HAL_RCCEx_GetPLL2ClockFreq
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
HAL_RCCEx_LSECSS_IRQHandler
void HAL_RCCEx_LSECSS_IRQHandler(void)
HAL_RCCEx_CRS_ExpectedSyncCallback
void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
HAL_RCCEx_DisableLSECSS
void HAL_RCCEx_DisableLSECSS(void)
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:55