PLL3 Clock structure definition. More...
#include <stm32h7xx_hal_rcc_ex.h>
Public Attributes | |
uint32_t | PLL3FRACN |
uint32_t | PLL3M |
uint32_t | PLL3N |
uint32_t | PLL3P |
uint32_t | PLL3Q |
uint32_t | PLL3R |
uint32_t | PLL3RGE |
uint32_t | PLL3VCOSEL |
PLL3 Clock structure definition.
Definition at line 79 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
uint32_t RCC_PLL3InitTypeDef::PLL3FRACN |
PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191
Definition at line 104 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
uint32_t RCC_PLL3InitTypeDef::PLL3M |
PLL3M: Division factor for PLL3 VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63
Definition at line 82 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
uint32_t RCC_PLL3InitTypeDef::PLL3N |
PLL3N: Multiplication factor for PLL3 VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512 or between Min_Data = 8 and Max_Data = 420(*) (*) : For stm32h7a3xx and stm32h7b3xx family lines.
Definition at line 85 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
uint32_t RCC_PLL3InitTypeDef::PLL3P |
PLL3P: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed
Definition at line 90 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
uint32_t RCC_PLL3InitTypeDef::PLL3Q |
PLL3Q: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128
Definition at line 94 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
uint32_t RCC_PLL3InitTypeDef::PLL3R |
PLL3R: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128
Definition at line 97 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
uint32_t RCC_PLL3InitTypeDef::PLL3RGE |
PLL3RGE: PLL3 clock Input range This parameter must be a value of RCC PLL3 VCI Range
Definition at line 99 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
uint32_t RCC_PLL3InitTypeDef::PLL3VCOSEL |
PLL3VCOSEL: PLL3 clock Output range This parameter must be a value of RCC PLL3 VCO Range
Definition at line 101 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.