|
| #define | __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) |
| | Macro to configure the ADC clock. More...
|
| |
| #define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) |
| | macro to configure the CEC clock (CECCLK). More...
|
| |
| #define | __HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) |
| | Macro to configure the CLKP : Oscillator clock for peripheral. More...
|
| |
| #define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) |
| | Enable or disable the automatic hardware adjustment of TRIM bits. More...
|
| |
| #define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) |
| | Enable the automatic hardware adjustment of TRIM bits. More...
|
| |
| #define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) |
| |
| #define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) |
| |
| #define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) |
| | Disable the specified CRS interrupts. More...
|
| |
| #define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) |
| | Enable the specified CRS interrupts. More...
|
| |
| #define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) |
| | Disable the oscillator clock for frequency error counter. More...
|
| |
| #define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) |
| | Enable the oscillator clock for frequency error counter. More...
|
| |
| #define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) |
| | Check whether the specified CRS flag is set or not. More...
|
| |
| #define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) |
| | Check whether the CRS interrupt has occurred or not. More...
|
| |
| #define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) |
| | Macro to calculate reload value to be set in CRS register according to target and sync frequencies. More...
|
| |
| #define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) |
| | Macro to configure the DFSDM1 clock. More...
|
| |
| #define | __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) |
| | macro to configure the FMC clock source. More...
|
| |
| #define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) |
| | Macro to get the ADC clock source. More...
|
| |
| #define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) |
| | macro to get the CEC clock source. More...
|
| |
| #define | __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) |
| | Macro to get the Oscillator clock for peripheral source. More...
|
| |
| #define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) |
| | Macro to get the DFSDM1 clock source. More...
|
| |
| #define | __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) |
| | macro to get the FMC clock source. More...
|
| |
| #define | __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) |
| | macro to get the I2C1/2/3/5* clock source. More...
|
| |
| #define | __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE |
| |
| #define | __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| | macro to get the I2C1 clock source. More...
|
| |
| #define | __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| | macro to get the I2C2 clock source. More...
|
| |
| #define | __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| | macro to get the I2C3 clock source. More...
|
| |
| #define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) |
| | macro to get the I2C4 clock source. More...
|
| |
| #define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) |
| | macro to get the LPTIM1 clock source. More...
|
| |
| #define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) |
| | macro to get the LPTIM2 clock source. More...
|
| |
| #define | __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) |
| | macro to get the LPTIM3/4/5 clock source. More...
|
| |
| #define | __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE |
| | macro to get the LPTIM3 clock source. More...
|
| |
| #define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) |
| | macro to get the LPUART1 clock source. More...
|
| |
| #define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) |
| | macro to get the RNG clock source. More...
|
| |
| #define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) |
| | Macro to get the SAI1 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) |
| | Macro to get the SDMMC clock. More...
|
| |
| #define | __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) |
| | Macro to get the SPDIFRX clock source. More...
|
| |
| #define | __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) |
| | Macro to get the SPI1/2/3 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| | Macro to get the SPI1 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| | Macro to get the SPI2 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| | Macro to get the SPI3 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) |
| | Macro to get the SPI4/5 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
| | Macro to get the SPI4 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
| | Macro to get the SPI5 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) |
| | Macro to get the SPI6 clock source. More...
|
| |
| #define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) |
| | Macro to get the SWPMI1 clock source. More...
|
| |
| #define | __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| | macro to get the UART4 clock source. More...
|
| |
| #define | __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| | macro to get the UART5 clock source. More...
|
| |
| #define | __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| | macro to get the UART7 clock source. More...
|
| |
| #define | __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| | macro to get the UART8 clock source. More...
|
| |
| #define | __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) |
| | macro to get the USART1/6/9* /10* clock source. More...
|
| |
| #define | __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE |
| |
| #define | __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE |
| | macro to get the USART1 clock source. More...
|
| |
| #define | __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) |
| | macro to get the USART2/3/4/5/7/8 clock source. More...
|
| |
| #define | __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| | macro to get the USART2 clock source. More...
|
| |
| #define | __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| | macro to get the USART3 clock source. More...
|
| |
| #define | __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE |
| | macro to get the USART6 clock source. More...
|
| |
| #define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) |
| | Macro to get the USB clock source. More...
|
| |
| #define | __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) |
| | macro to configure the I2C1/2/3/5* clock (I2C123CLK). More...
|
| |
| #define | __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG |
| |
| #define | __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG |
| | macro to configure the I2C1 clock (I2C1CLK). More...
|
| |
| #define | __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG |
| | macro to configure the I2C2 clock (I2C2CLK). More...
|
| |
| #define | __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG |
| | macro to configure the I2C3 clock (I2C3CLK). More...
|
| |
| #define | __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) |
| | macro to configure the I2C4 clock (I2C4CLK). More...
|
| |
| #define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) |
| | macro to configure the LPTIM1 clock source. More...
|
| |
| #define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) |
| | macro to configure the LPTIM2 clock source. More...
|
| |
| #define | __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) |
| | macro to configure the LPTIM3/4/5 clock source. More...
|
| |
| #define | __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG |
| | macro to configure the LPTIM3 clock source. More...
|
| |
| #define | __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) |
| | macro to configure the LPUART1 clock (LPUART1CLK). More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) |
| | Clear the RCC LSE CSS EXTI flag. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
| | Disable the RCC LSE CSS Event Line. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
| | Disable the RCC LSE CSS Extended Interrupt Falling Trigger. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
| | Disable the RCC LSE CSS Extended Interrupt Line. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
| | Disable the RCC LSE CSS Extended Interrupt Rising Trigger. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() |
| | Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
| | Enable the RCC LSE CSS Event Line. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
| | Enable the RCC LSE CSS Extended Interrupt Falling Trigger. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
| | Enable the RCC LSE CSS Extended Interrupt Line. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
| | Enable the RCC LSE CSS Extended Interrupt Rising Trigger. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() |
| | Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) |
| | Generate a Software interrupt on the RCC LSE CSS EXTI line. More...
|
| |
| #define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) |
| | Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. More...
|
| |
| #define | __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) |
| | Macro to configures the PLL2 multiplication and division factors. More...
|
| |
| #define | __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) |
| |
| #define | __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) |
| | Macros to enable or disable PLL2. More...
|
| |
| #define | __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) |
| | Macro to select the PLL2 reference frequency range. More...
|
| |
| #define | __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) |
| | Macro to select the PLL2 reference frequency range. More...
|
| |
| #define | __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
| |
| #define | __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
| | Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) More...
|
| |
| #define | __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) |
| | Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor. More...
|
| |
| #define | __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
| |
| #define | __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
| | Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO. More...
|
| |
| #define | __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) |
| | Macro to configures the PLL3 multiplication and division factors. More...
|
| |
| #define | __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) |
| |
| #define | __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) |
| | Macros to enable or disable the main PLL3. More...
|
| |
| #define | __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) |
| | Macro to select the PLL3 reference frequency range. More...
|
| |
| #define | __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) |
| | Macro to select the PLL3 reference frequency range. More...
|
| |
| #define | __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
| |
| #define | __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
| | Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) More...
|
| |
| #define | __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) |
| | Macro to configures PLL3 clock Fractional Part of The Multiplication Factor. More...
|
| |
| #define | __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
| |
| #define | __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
| | Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO. More...
|
| |
| #define | __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) |
| | macro to configure the RNG clock (RNGCLK). More...
|
| |
| #define | __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) |
| | Macro to Configure the SAI1 clock source. More...
|
| |
| #define | __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) |
| | Macro to configure the SDMMC clock. More...
|
| |
| #define | __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) |
| | Macro to Configure the SPDIFRX clock source. More...
|
| |
| #define | __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) |
| | Macro to Configure the SPI1/2/3 clock source. More...
|
| |
| #define | __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG |
| | Macro to Configure the SPI1 clock source. More...
|
| |
| #define | __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG |
| | Macro to Configure the SPI2 clock source. More...
|
| |
| #define | __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG |
| | Macro to Configure the SPI3 clock source. More...
|
| |
| #define | __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) |
| | Macro to Configure the SPI4/5 clock source. More...
|
| |
| #define | __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG |
| | Macro to Configure the SPI4 clock source. More...
|
| |
| #define | __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG |
| | Macro to Configure the SPI5 clock source. More...
|
| |
| #define | __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) |
| | Macro to Configure the SPI6 clock source. More...
|
| |
| #define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) |
| | Macro to configure the SWPMI1 clock. More...
|
| |
| #define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__) |
| | Macro to configure the Timers clocks prescalers. More...
|
| |
| #define | __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG |
| | macro to configure the UART4 clock (UART4CLK). More...
|
| |
| #define | __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG |
| | macro to configure the UART5 clock (UART5CLK). More...
|
| |
| #define | __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG |
| | macro to configure the UART5 clock (UART7CLK). More...
|
| |
| #define | __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG |
| | macro to configure the UART8 clock (UART8CLK). More...
|
| |
| #define | __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) |
| | macro to configure the USART1/6/9* /10* clock (USART16CLK). More...
|
| |
| #define | __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG |
| |
| #define | __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG |
| | macro to configure the USART1 clock (USART1CLK). More...
|
| |
| #define | __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) |
| | macro to configure the USART234578 clock (USART234578CLK). More...
|
| |
| #define | __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG |
| | macro to configure the USART2 clock (USART2CLK). More...
|
| |
| #define | __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG |
| | macro to configure the USART3 clock (USART3CLK). More...
|
| |
| #define | __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG |
| | macro to configure the USART6 clock (USART6CLK). More...
|
| |
| #define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) |
| | Macro to configure the USB clock (USBCLK). More...
|
| |
| #define | I2c1235ClockSelection I2c123ClockSelection |
| |
| #define | IS_RCC_ADCCLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_CECCLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_CLKPSOURCE(SOURCE) |
| |
| #define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) |
| |
| #define | IS_RCC_CRS_FREQERRORDIR(__DIR__) |
| |
| #define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) |
| |
| #define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) |
| |
| #define | IS_RCC_CRS_SYNC_DIV(__DIV__) |
| |
| #define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) |
| |
| #define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) |
| |
| #define | IS_RCC_DFSDM1CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_FMCCLK(__SOURCE__) |
| |
| #define | IS_RCC_I2C123CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_I2C1CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_I2C2CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_I2C3CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_I2C4CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_LPTIM1CLK(SOURCE) |
| |
| #define | IS_RCC_LPTIM2CLK(SOURCE) |
| |
| #define | IS_RCC_LPTIM345CLK(SOURCE) |
| |
| #define | IS_RCC_LPTIM3CLK(SOURCE) |
| |
| #define | IS_RCC_LPUART1CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) |
| |
| #define | IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) |
| |
| #define | IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) |
| |
| #define | IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| |
| #define | IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| |
| #define | IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| |
| #define | IS_RCC_PLL2RGE_VALUE(VALUE) |
| |
| #define | IS_RCC_PLL2VCO_VALUE(VALUE) |
| |
| #define | IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) |
| |
| #define | IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) |
| |
| #define | IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) |
| |
| #define | IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| |
| #define | IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| |
| #define | IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| |
| #define | IS_RCC_PLL3RGE_VALUE(VALUE) |
| |
| #define | IS_RCC_PLL3VCO_VALUE(VALUE) |
| |
| #define | IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U) |
| |
| #define | IS_RCC_RNGCLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_SAI1CLK(__SOURCE__) |
| |
| #define | IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) |
| |
| #define | IS_RCC_SDMMC(__SOURCE__) |
| |
| #define | IS_RCC_SPDIFRXCLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_SPI123CLK(__SOURCE__) |
| |
| #define | IS_RCC_SPI1CLK(__SOURCE__) |
| |
| #define | IS_RCC_SPI2CLK(__SOURCE__) |
| |
| #define | IS_RCC_SPI3CLK(__SOURCE__) |
| |
| #define | IS_RCC_SPI45CLK(__SOURCE__) |
| |
| #define | IS_RCC_SPI4CLK(__SOURCE__) |
| |
| #define | IS_RCC_SPI5CLK(__SOURCE__) |
| |
| #define | IS_RCC_SPI6CLK(__SOURCE__) |
| |
| #define | IS_RCC_SWPMI1CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_TIMPRES(VALUE) |
| |
| #define | IS_RCC_UART4CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_UART5CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_UART7CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_UART8CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE |
| |
| #define | IS_RCC_USART16CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_USART1CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_USART234578CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_USART2CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_USART3CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_USART6CLKSOURCE(SOURCE) |
| |
| #define | IS_RCC_USBCLKSOURCE(SOURCE) |
| |
| #define | RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1 |
| |
| #define | RCC_ADCCLKSOURCE_PLL2 (0x00000000U) |
| |
| #define | RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0 |
| |
| #define | RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1 |
| |
| #define | RCC_CECCLKSOURCE_LSE (0x00000000U) |
| |
| #define | RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0 |
| |
| #define | RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0 |
| |
| #define | RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1 |
| |
| #define | RCC_CLKPSOURCE_HSI (0x00000000U) |
| |
| #define | RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) |
| |
| #define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF |
| |
| #define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
| | Clear the CRS specified FLAG. More...
|
| |
| #define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF |
| |
| #define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR |
| |
| #define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS |
| |
| #define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF |
| |
| #define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF |
| |
| #define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF |
| |
| #define | RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) |
| |
| #define | RCC_CRS_FREQERRORDIR_UP (0x00000000U) |
| |
| #define | RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) |
| |
| #define | RCC_CRS_IT_ERR CRS_CR_ERRIE |
| |
| #define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
| | Clear the CRS interrupt pending bits. More...
|
| |
| #define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE |
| |
| #define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE |
| |
| #define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE |
| |
| #define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE |
| |
| #define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE |
| |
| #define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE |
| |
| #define | RCC_CRS_NONE (0x00000000U) |
| |
| #define | RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) |
| |
| #define | RCC_CRS_SYNC_DIV1 (0x00000000U) |
| |
| #define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV |
| |
| #define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 |
| |
| #define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 |
| |
| #define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) |
| |
| #define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 |
| |
| #define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) |
| |
| #define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) |
| |
| #define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL |
| |
| #define | RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) |
| |
| #define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 |
| |
| #define | RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) |
| |
| #define | RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 |
| |
| #define | RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) |
| |
| #define | RCC_CRS_SYNCERR (0x00000008U) |
| |
| #define | RCC_CRS_SYNCMISS (0x00000010U) |
| |
| #define | RCC_CRS_SYNCOK (0x00000002U) |
| |
| #define | RCC_CRS_SYNCWARN (0x00000004U) |
| |
| #define | RCC_CRS_TIMEOUT (0x00000001U) |
| |
| #define | RCC_CRS_TRIMOVF (0x00000020U) |
| |
| #define | RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U) |
| |
| #define | RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1 |
| |
| #define | RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL |
| |
| #define | RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 |
| |
| #define | RCC_FMCCLKSOURCE_CDHCLK (0x00000000U) |
| |
| #define | RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL |
| |
| #define | RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK |
| |
| #define | RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK |
| |
| #define | RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0 |
| |
| #define | RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1 |
| |
| #define | RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI |
| |
| #define | RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 |
| |
| #define | RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI |
| |
| #define | RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 |
| |
| #define | RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI |
| |
| #define | RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 |
| |
| #define | RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI |
| |
| #define | RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 |
| |
| #define | RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI |
| |
| #define | RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 |
| |
| #define | RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI |
| |
| #define | RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 |
| |
| #define | RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) |
| |
| #define | RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4 |
| |
| #define | RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1 |
| |
| #define | RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0 |
| |
| #define | RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U) |
| |
| #define | RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U) |
| |
| #define | RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) |
| |
| #define | RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 |
| |
| #define | RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) |
| |
| #define | RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2 |
| |
| #define | RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 |
| |
| #define | RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0 |
| |
| #define | RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1 |
| |
| #define | RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) |
| |
| #define | RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4 |
| |
| #define | RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) |
| |
| #define | RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2 |
| |
| #define | RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4 |
| |
| #define | RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0 |
| |
| #define | RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1 |
| |
| #define | RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U) |
| |
| #define | RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) |
| |
| #define | RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4 |
| |
| #define | RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) |
| |
| #define | RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2 |
| |
| #define | RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4 |
| |
| #define | RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0 |
| |
| #define | RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1 |
| |
| #define | RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U) |
| |
| #define | RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP |
| |
| #define | RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 |
| |
| #define | RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE |
| |
| #define | RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI |
| |
| #define | RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 |
| |
| #define | RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 |
| |
| #define | RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2 |
| |
| #define | RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4 |
| |
| #define | RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) |
| |
| #define | RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0) |
| |
| #define | RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4 |
| |
| #define | RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0 |
| |
| #define | RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1 |
| |
| #define | RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U) |
| |
| #define | RCC_PERIPHCLK_ADC (0x00080000U) |
| |
| #define | RCC_PERIPHCLK_CEC (0x00800000U) |
| |
| #define | RCC_PERIPHCLK_CKPER (0x80000000U) |
| |
| #define | RCC_PERIPHCLK_DFSDM1 (0x00200000U) |
| |
| #define | RCC_PERIPHCLK_DSI (0x04000000U) |
| |
| #define | RCC_PERIPHCLK_FDCAN (0x00008000U) |
| |
| #define | RCC_PERIPHCLK_FMC (0x01000000U) |
| |
| #define | RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123 |
| |
| #define | RCC_PERIPHCLK_I2C123 (0x00000008U) |
| |
| #define | RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123 |
| |
| #define | RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123 |
| |
| #define | RCC_PERIPHCLK_I2C4 (0x00000010U) |
| |
| #define | RCC_PERIPHCLK_LPTIM1 (0x00000020U) |
| |
| #define | RCC_PERIPHCLK_LPTIM2 (0x00000040U) |
| |
| #define | RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345 |
| |
| #define | RCC_PERIPHCLK_LPTIM345 (0x00000080U) |
| |
| #define | RCC_PERIPHCLK_LPUART1 (0x00000004U) |
| |
| #define | RCC_PERIPHCLK_RNG (0x00020000U) |
| |
| #define | RCC_PERIPHCLK_RTC (0x00400000U) |
| |
| #define | RCC_PERIPHCLK_SAI1 (0x00000100U) |
| |
| #define | RCC_PERIPHCLK_SDMMC (0x00010000U) |
| |
| #define | RCC_PERIPHCLK_SPDIFRX (0x08000000U) |
| |
| #define | RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123 |
| |
| #define | RCC_PERIPHCLK_SPI123 (0x00001000U) |
| |
| #define | RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123 |
| |
| #define | RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123 |
| |
| #define | RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45 |
| |
| #define | RCC_PERIPHCLK_SPI45 (0x00002000U) |
| |
| #define | RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45 |
| |
| #define | RCC_PERIPHCLK_SPI6 (0x00004000U) |
| |
| #define | RCC_PERIPHCLK_SWPMI1 (0x00100000U) |
| |
| #define | RCC_PERIPHCLK_TIM (0x40000000U) |
| |
| #define | RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578 |
| |
| #define | RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578 |
| |
| #define | RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578 |
| |
| #define | RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578 |
| |
| #define | RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16 |
| |
| #define | RCC_PERIPHCLK_USART16 (0x00000001U) |
| |
| #define | RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16 |
| |
| #define | RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578 |
| |
| #define | RCC_PERIPHCLK_USART234578 (0x00000002U) |
| |
| #define | RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578 |
| |
| #define | RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16 |
| |
| #define | RCC_PERIPHCLK_USB (0x00040000U) |
| |
| #define | RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN |
| |
| #define | RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN |
| |
| #define | RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN |
| |
| #define | RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 |
| |
| #define | RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 |
| |
| #define | RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 |
| |
| #define | RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 |
| |
| #define | RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL |
| |
| #define | RCC_PLL2VCOWIDE (0x00000000U) |
| |
| #define | RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN |
| |
| #define | RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN |
| |
| #define | RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN |
| |
| #define | RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 |
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| #define | RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 |
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| #define | RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 |
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| #define | RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 |
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| #define | RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL |
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| #define | RCC_PLL3VCOWIDE (0x00000000U) |
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| #define | RCC_RNGCLKSOURCE_HSI48 (0x00000000U) |
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| #define | RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1 |
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| #define | RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL |
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| #define | RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0 |
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| #define | RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2 |
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| #define | RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) |
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| #define | RCC_SAI1CLKSOURCE_PLL (0x00000000U) |
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| #define | RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0 |
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| #define | RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1 |
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| #define | RCC_SDMMCCLKSOURCE_PLL (0x00000000U) |
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| #define | RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL |
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| #define | RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL |
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| #define | RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) |
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| #define | RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0 |
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| #define | RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1 |
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| #define | RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2 |
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| #define | RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) |
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| #define | RCC_SPI123CLKSOURCE_PLL (0x00000000U) |
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| #define | RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0 |
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| #define | RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1 |
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| #define | RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP |
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| #define | RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN |
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| #define | RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL |
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| #define | RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 |
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| #define | RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 |
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| #define | RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP |
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| #define | RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN |
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| #define | RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL |
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| #define | RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 |
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| #define | RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 |
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| #define | RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP |
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| #define | RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN |
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| #define | RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL |
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| #define | RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 |
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| #define | RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 |
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| #define | RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U) |
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| #define | RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2 |
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| #define | RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ |
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| #define | RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) |
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| #define | RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) |
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| #define | RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 |
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| #define | RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0 |
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| #define | RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1 |
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| #define | RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI |
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| #define | RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 |
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| #define | RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE |
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| #define | RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI |
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| #define | RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 |
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| #define | RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 |
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| #define | RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI |
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| #define | RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 |
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| #define | RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE |
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| #define | RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI |
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| #define | RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 |
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| #define | RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 |
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| #define | RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2 |
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| #define | RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ |
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| #define | RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) |
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| #define | RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) |
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| #define | RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4 |
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| #define | RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) |
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| #define | RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0 |
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| #define | RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1 |
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| #define | RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U) |
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| #define | RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U) |
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| #define | RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1 |
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| #define | RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL |
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| #define | RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE |
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| #define | RCC_TIMPRES_DESACTIVATED (0x00000000U) |
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| #define | RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI |
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| #define | RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 |
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| #define | RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI |
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| #define | RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE |
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| #define | RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 |
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| #define | RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 |
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| #define | RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI |
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| #define | RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 |
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| #define | RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI |
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| #define | RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE |
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| #define | RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 |
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| #define | RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 |
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| #define | RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI |
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| #define | RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 |
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| #define | RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI |
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| #define | RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE |
| |
| #define | RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 |
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| #define | RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 |
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| #define | RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI |
| |
| #define | RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 |
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| #define | RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI |
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| #define | RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE |
| |
| #define | RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 |
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| #define | RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 |
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| #define | RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2 |
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| #define | RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U) |
| |
| #define | RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) |
| |
| #define | RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) |
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| #define | RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0 |
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| #define | RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1 |
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| #define | RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI |
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| #define | RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 |
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| #define | RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI |
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| #define | RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE |
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| #define | RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 |
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| #define | RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 |
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| #define | RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 |
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| #define | RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI |
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| #define | RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 |
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| #define | RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI |
| |
| #define | RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE |
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| #define | RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 |
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| #define | RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 |
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| #define | RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U) |
| |
| #define | RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2 |
| |
| #define | RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 |
| |
| #define | RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) |
| |
| #define | RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) |
| |
| #define | RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 |
| |
| #define | RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0 |
| |
| #define | RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1 |
| |
| #define | RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI |
| |
| #define | RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 |
| |
| #define | RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI |
| |
| #define | RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE |
| |
| #define | RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 |
| |
| #define | RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 |
| |
| #define | RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI |
| |
| #define | RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 |
| |
| #define | RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI |
| |
| #define | RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE |
| |
| #define | RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 |
| |
| #define | RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 |
| |
| #define | RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI |
| |
| #define | RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 |
| |
| #define | RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI |
| |
| #define | RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE |
| |
| #define | RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 |
| |
| #define | RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 |
| |
| #define | RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL |
| |
| #define | RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0 |
| |
| #define | RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1 |
| |
| #define | RCC_WWDG1 RCC_GCR_WW1RSC |
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