Macros
Collaboration diagram for SPI6 Clock Source:

Macros

#define RCC_SPI6CLKSOURCE_CSI   RCC_SRDCCIPR_SPI6SEL_2
 
#define RCC_SPI6CLKSOURCE_CSI   RCC_SRDCCIPR_SPI6SEL_2
 
#define RCC_SPI6CLKSOURCE_D3PCLK1   RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
 
#define RCC_SPI6CLKSOURCE_D3PCLK1   RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
 
#define RCC_SPI6CLKSOURCE_HSE   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
 
#define RCC_SPI6CLKSOURCE_HSE   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
 
#define RCC_SPI6CLKSOURCE_HSI   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
 
#define RCC_SPI6CLKSOURCE_HSI   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
 
#define RCC_SPI6CLKSOURCE_PCLK4   RCC_SPI6CLKSOURCE_SRDPCLK4
 
#define RCC_SPI6CLKSOURCE_PCLK4   RCC_SPI6CLKSOURCE_SRDPCLK4
 
#define RCC_SPI6CLKSOURCE_PIN   (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
 
#define RCC_SPI6CLKSOURCE_PIN   (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
 
#define RCC_SPI6CLKSOURCE_PLL2   RCC_SRDCCIPR_SPI6SEL_0
 
#define RCC_SPI6CLKSOURCE_PLL2   RCC_SRDCCIPR_SPI6SEL_0
 
#define RCC_SPI6CLKSOURCE_PLL3   RCC_SRDCCIPR_SPI6SEL_1
 
#define RCC_SPI6CLKSOURCE_PLL3   RCC_SRDCCIPR_SPI6SEL_1
 
#define RCC_SPI6CLKSOURCE_SRDPCLK4   (0x00000000U)
 
#define RCC_SPI6CLKSOURCE_SRDPCLK4   (0x00000000U)
 

Detailed Description

Macro Definition Documentation

◆ RCC_SPI6CLKSOURCE_CSI [1/2]

#define RCC_SPI6CLKSOURCE_CSI   RCC_SRDCCIPR_SPI6SEL_2

◆ RCC_SPI6CLKSOURCE_CSI [2/2]

#define RCC_SPI6CLKSOURCE_CSI   RCC_SRDCCIPR_SPI6SEL_2

◆ RCC_SPI6CLKSOURCE_D3PCLK1 [1/2]

#define RCC_SPI6CLKSOURCE_D3PCLK1   RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

◆ RCC_SPI6CLKSOURCE_D3PCLK1 [2/2]

#define RCC_SPI6CLKSOURCE_D3PCLK1   RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

◆ RCC_SPI6CLKSOURCE_HSE [1/2]

#define RCC_SPI6CLKSOURCE_HSE   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

◆ RCC_SPI6CLKSOURCE_HSE [2/2]

#define RCC_SPI6CLKSOURCE_HSE   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

◆ RCC_SPI6CLKSOURCE_HSI [1/2]

#define RCC_SPI6CLKSOURCE_HSI   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

◆ RCC_SPI6CLKSOURCE_HSI [2/2]

#define RCC_SPI6CLKSOURCE_HSI   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

◆ RCC_SPI6CLKSOURCE_PCLK4 [1/2]

#define RCC_SPI6CLKSOURCE_PCLK4   RCC_SPI6CLKSOURCE_SRDPCLK4

◆ RCC_SPI6CLKSOURCE_PCLK4 [2/2]

#define RCC_SPI6CLKSOURCE_PCLK4   RCC_SPI6CLKSOURCE_SRDPCLK4

◆ RCC_SPI6CLKSOURCE_PIN [1/2]

#define RCC_SPI6CLKSOURCE_PIN   (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

◆ RCC_SPI6CLKSOURCE_PIN [2/2]

#define RCC_SPI6CLKSOURCE_PIN   (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

◆ RCC_SPI6CLKSOURCE_PLL2 [1/2]

#define RCC_SPI6CLKSOURCE_PLL2   RCC_SRDCCIPR_SPI6SEL_0

◆ RCC_SPI6CLKSOURCE_PLL2 [2/2]

#define RCC_SPI6CLKSOURCE_PLL2   RCC_SRDCCIPR_SPI6SEL_0

◆ RCC_SPI6CLKSOURCE_PLL3 [1/2]

#define RCC_SPI6CLKSOURCE_PLL3   RCC_SRDCCIPR_SPI6SEL_1

◆ RCC_SPI6CLKSOURCE_PLL3 [2/2]

#define RCC_SPI6CLKSOURCE_PLL3   RCC_SRDCCIPR_SPI6SEL_1

◆ RCC_SPI6CLKSOURCE_SRDPCLK4 [1/2]

#define RCC_SPI6CLKSOURCE_SRDPCLK4   (0x00000000U)

◆ RCC_SPI6CLKSOURCE_SRDPCLK4 [2/2]

#define RCC_SPI6CLKSOURCE_SRDPCLK4   (0x00000000U)


picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:08