CMSIS Cortex-M23 Core Peripheral Access Layer Header File. More...

#include <stdint.h>
#include "cmsis_version.h"
#include "cmsis_compiler.h"

Include dependency graph for stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h:

Classes
union	APSR_Type
	Union type to access the Application Program Status Register (APSR). More...

union	CONTROL_Type
	Union type to access the Control Registers (CONTROL). More...

struct	CoreDebug_Type
	Structure type to access the Core Debug Register (CoreDebug). More...

struct	DWT_Type
	Structure type to access the Data Watchpoint and Trace Register (DWT). More...

union	IPSR_Type
	Union type to access the Interrupt Program Status Register (IPSR). More...

struct	NVIC_Type
	Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...

struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...

struct	SysTick_Type
	Structure type to access the System Timer (SysTick). More...

struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...

union	xPSR_Type
	Union type to access the Special-Purpose Program Status Registers (xPSR). More...

Macros
#define	__CORE_CM23_H_GENERIC


#define	__CM23_CMSIS_VERSION

#define	__CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)

#define	__CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)

#define	__CORE_CM23_H_DEPENDANT

#define	__CORTEX_M (23U)

#define	__FPU_USED 0U

#define	__I volatile const

#define	__IM volatile const /! Defines 'read only' structure member permissions /

#define	__IO volatile

#define	__IOM volatile /! Defines 'read / write' structure member permissions /

#define	__NVIC_GetPriorityGrouping() (0U)

#define	__NVIC_SetPriorityGrouping(X) (void)(X)

#define	__O volatile

#define	__OM volatile /! Defines 'write only' structure member permissions /

#define	_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value. More...

#define	_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )

#define	_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range. More...

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_C_Pos 29U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_N_Pos 31U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_V_Pos 28U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_Z_Pos 30U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)

#define	CoreDebug_DEMCR_DWTENA_Pos 24U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	DWT ((DWT_Type *) DWT_BASE )

#define	DWT_BASE (0xE0001000UL)

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)

#define	DWT_FUNCTION_ACTION_Pos 4U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

#define	DWT_FUNCTION_ID_Pos 27U

#define	DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/)

#define	DWT_FUNCTION_MATCH_Pos 0U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

#define	EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

#define	EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

#define	EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

#define	EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

#define	EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

#define	EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

#define	EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */

#define	FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	IPSR_ISR_Pos 0U

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_USER_IRQ_OFFSET 16

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCS_BASE (0xE000E000UL)

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	TPI ((TPI_Type *) TPI_BASE )

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_BASE (0xE0040000UL)

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	xPSR_ISR_Pos 0U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_N_Pos 31U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_Z_Pos 30U