stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h
Go to the documentation of this file.
1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_SC000_H_GENERIC
32 #define __CORE_SC000_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 /* CMSIS SC000 definitions */
66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
69  __SC000_CMSIS_VERSION_SUB )
71 #define __CORTEX_SC (000U)
76 #define __FPU_USED 0U
77 
78 #if defined ( __CC_ARM )
79  #if defined __TARGET_FPU_VFP
80  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81  #endif
82 
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84  #if defined __ARM_PCS_VFP
85  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86  #endif
87 
88 #elif defined ( __GNUC__ )
89  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91  #endif
92 
93 #elif defined ( __ICCARM__ )
94  #if defined __ARMVFP__
95  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96  #endif
97 
98 #elif defined ( __TI_ARM__ )
99  #if defined __TI_VFP_SUPPORT__
100  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101  #endif
102 
103 #elif defined ( __TASKING__ )
104  #if defined __FPU_VFP__
105  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #endif
107 
108 #elif defined ( __CSMC__ )
109  #if ( __CSMC__ & 0x400U)
110  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111  #endif
112 
113 #endif
114 
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116 
117 
118 #ifdef __cplusplus
119 }
120 #endif
121 
122 #endif /* __CORE_SC000_H_GENERIC */
123 
124 #ifndef __CMSIS_GENERIC
125 
126 #ifndef __CORE_SC000_H_DEPENDANT
127 #define __CORE_SC000_H_DEPENDANT
128 
129 #ifdef __cplusplus
130  extern "C" {
131 #endif
132 
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135  #ifndef __SC000_REV
136  #define __SC000_REV 0x0000U
137  #warning "__SC000_REV not defined in device header file; using default!"
138  #endif
139 
140  #ifndef __MPU_PRESENT
141  #define __MPU_PRESENT 0U
142  #warning "__MPU_PRESENT not defined in device header file; using default!"
143  #endif
144 
145  #ifndef __NVIC_PRIO_BITS
146  #define __NVIC_PRIO_BITS 2U
147  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
148  #endif
149 
150  #ifndef __Vendor_SysTickConfig
151  #define __Vendor_SysTickConfig 0U
152  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
153  #endif
154 #endif
155 
156 /* IO definitions (access restrictions to peripheral registers) */
164 #ifdef __cplusplus
165  #define __I volatile
166 #else
167  #define __I volatile const
168 #endif
169 #define __O volatile
170 #define __IO volatile
172 /* following defines should be used for structure members */
173 #define __IM volatile const
174 #define __OM volatile
175 #define __IOM volatile
177 
181 /*******************************************************************************
182  * Register Abstraction
183  Core Register contain:
184  - Core Register
185  - Core NVIC Register
186  - Core SCB Register
187  - Core SysTick Register
188  - Core MPU Register
189  ******************************************************************************/
190 
205 typedef union
206 {
207  struct
208  {
209  uint32_t _reserved0:28;
210  uint32_t V:1;
211  uint32_t C:1;
212  uint32_t Z:1;
213  uint32_t N:1;
214  } b;
215  uint32_t w;
216 } APSR_Type;
217 
218 /* APSR Register Definitions */
219 #define APSR_N_Pos 31U
220 #define APSR_N_Msk (1UL << APSR_N_Pos)
222 #define APSR_Z_Pos 30U
223 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
225 #define APSR_C_Pos 29U
226 #define APSR_C_Msk (1UL << APSR_C_Pos)
228 #define APSR_V_Pos 28U
229 #define APSR_V_Msk (1UL << APSR_V_Pos)
235 typedef union
236 {
237  struct
238  {
239  uint32_t ISR:9;
240  uint32_t _reserved0:23;
241  } b;
242  uint32_t w;
243 } IPSR_Type;
244 
245 /* IPSR Register Definitions */
246 #define IPSR_ISR_Pos 0U
247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
253 typedef union
254 {
255  struct
256  {
257  uint32_t ISR:9;
258  uint32_t _reserved0:15;
259  uint32_t T:1;
260  uint32_t _reserved1:3;
261  uint32_t V:1;
262  uint32_t C:1;
263  uint32_t Z:1;
264  uint32_t N:1;
265  } b;
266  uint32_t w;
267 } xPSR_Type;
268 
269 /* xPSR Register Definitions */
270 #define xPSR_N_Pos 31U
271 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
273 #define xPSR_Z_Pos 30U
274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
276 #define xPSR_C_Pos 29U
277 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
279 #define xPSR_V_Pos 28U
280 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
282 #define xPSR_T_Pos 24U
283 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
285 #define xPSR_ISR_Pos 0U
286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
292 typedef union
293 {
294  struct
295  {
296  uint32_t _reserved0:1;
297  uint32_t SPSEL:1;
298  uint32_t _reserved1:30;
299  } b;
300  uint32_t w;
301 } CONTROL_Type;
302 
303 /* CONTROL Register Definitions */
304 #define CONTROL_SPSEL_Pos 1U
305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
307 
320 typedef struct
321 {
322  __IOM uint32_t ISER[1U];
323  uint32_t RESERVED0[31U];
324  __IOM uint32_t ICER[1U];
325  uint32_t RSERVED1[31U];
326  __IOM uint32_t ISPR[1U];
327  uint32_t RESERVED2[31U];
328  __IOM uint32_t ICPR[1U];
329  uint32_t RESERVED3[31U];
330  uint32_t RESERVED4[64U];
331  __IOM uint32_t IP[8U];
332 } NVIC_Type;
333 
347 typedef struct
348 {
349  __IM uint32_t CPUID;
350  __IOM uint32_t ICSR;
351  __IOM uint32_t VTOR;
352  __IOM uint32_t AIRCR;
353  __IOM uint32_t SCR;
354  __IOM uint32_t CCR;
355  uint32_t RESERVED0[1U];
356  __IOM uint32_t SHP[2U];
357  __IOM uint32_t SHCSR;
358  uint32_t RESERVED1[154U];
359  __IOM uint32_t SFCR;
360 } SCB_Type;
361 
362 /* SCB CPUID Register Definitions */
363 #define SCB_CPUID_IMPLEMENTER_Pos 24U
364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
366 #define SCB_CPUID_VARIANT_Pos 20U
367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
369 #define SCB_CPUID_ARCHITECTURE_Pos 16U
370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
372 #define SCB_CPUID_PARTNO_Pos 4U
373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
375 #define SCB_CPUID_REVISION_Pos 0U
376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
378 /* SCB Interrupt Control State Register Definitions */
379 #define SCB_ICSR_NMIPENDSET_Pos 31U
380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
382 #define SCB_ICSR_PENDSVSET_Pos 28U
383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
385 #define SCB_ICSR_PENDSVCLR_Pos 27U
386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
388 #define SCB_ICSR_PENDSTSET_Pos 26U
389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
391 #define SCB_ICSR_PENDSTCLR_Pos 25U
392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
394 #define SCB_ICSR_ISRPREEMPT_Pos 23U
395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
397 #define SCB_ICSR_ISRPENDING_Pos 22U
398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
400 #define SCB_ICSR_VECTPENDING_Pos 12U
401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
403 #define SCB_ICSR_VECTACTIVE_Pos 0U
404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
406 /* SCB Interrupt Control State Register Definitions */
407 #define SCB_VTOR_TBLOFF_Pos 7U
408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
410 /* SCB Application Interrupt and Reset Control Register Definitions */
411 #define SCB_AIRCR_VECTKEY_Pos 16U
412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
417 #define SCB_AIRCR_ENDIANESS_Pos 15U
418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
426 /* SCB System Control Register Definitions */
427 #define SCB_SCR_SEVONPEND_Pos 4U
428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
430 #define SCB_SCR_SLEEPDEEP_Pos 2U
431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
433 #define SCB_SCR_SLEEPONEXIT_Pos 1U
434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
436 /* SCB Configuration Control Register Definitions */
437 #define SCB_CCR_STKALIGN_Pos 9U
438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
440 #define SCB_CCR_UNALIGN_TRP_Pos 3U
441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
443 /* SCB System Handler Control and State Register Definitions */
444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
447 
460 typedef struct
461 {
462  uint32_t RESERVED0[2U];
463  __IOM uint32_t ACTLR;
464 } SCnSCB_Type;
465 
466 /* Auxiliary Control Register Definitions */
467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
470 
483 typedef struct
484 {
485  __IOM uint32_t CTRL;
486  __IOM uint32_t LOAD;
487  __IOM uint32_t VAL;
488  __IM uint32_t CALIB;
489 } SysTick_Type;
490 
491 /* SysTick Control / Status Register Definitions */
492 #define SysTick_CTRL_COUNTFLAG_Pos 16U
493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
495 #define SysTick_CTRL_CLKSOURCE_Pos 2U
496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
498 #define SysTick_CTRL_TICKINT_Pos 1U
499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
501 #define SysTick_CTRL_ENABLE_Pos 0U
502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
504 /* SysTick Reload Register Definitions */
505 #define SysTick_LOAD_RELOAD_Pos 0U
506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
508 /* SysTick Current Register Definitions */
509 #define SysTick_VAL_CURRENT_Pos 0U
510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
512 /* SysTick Calibration Register Definitions */
513 #define SysTick_CALIB_NOREF_Pos 31U
514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
516 #define SysTick_CALIB_SKEW_Pos 30U
517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
519 #define SysTick_CALIB_TENMS_Pos 0U
520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
522 
524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
525 
535 typedef struct
536 {
537  __IM uint32_t TYPE;
538  __IOM uint32_t CTRL;
539  __IOM uint32_t RNR;
540  __IOM uint32_t RBAR;
541  __IOM uint32_t RASR;
542 } MPU_Type;
543 
544 /* MPU Type Register Definitions */
545 #define MPU_TYPE_IREGION_Pos 16U
546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
548 #define MPU_TYPE_DREGION_Pos 8U
549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
551 #define MPU_TYPE_SEPARATE_Pos 0U
552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
554 /* MPU Control Register Definitions */
555 #define MPU_CTRL_PRIVDEFENA_Pos 2U
556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
558 #define MPU_CTRL_HFNMIENA_Pos 1U
559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
561 #define MPU_CTRL_ENABLE_Pos 0U
562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
564 /* MPU Region Number Register Definitions */
565 #define MPU_RNR_REGION_Pos 0U
566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
568 /* MPU Region Base Address Register Definitions */
569 #define MPU_RBAR_ADDR_Pos 8U
570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
572 #define MPU_RBAR_VALID_Pos 4U
573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
575 #define MPU_RBAR_REGION_Pos 0U
576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
578 /* MPU Region Attribute and Size Register Definitions */
579 #define MPU_RASR_ATTRS_Pos 16U
580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
582 #define MPU_RASR_XN_Pos 28U
583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
585 #define MPU_RASR_AP_Pos 24U
586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
588 #define MPU_RASR_TEX_Pos 19U
589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
591 #define MPU_RASR_S_Pos 18U
592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
594 #define MPU_RASR_C_Pos 17U
595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
597 #define MPU_RASR_B_Pos 16U
598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
600 #define MPU_RASR_SRD_Pos 8U
601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
603 #define MPU_RASR_SIZE_Pos 1U
604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
606 #define MPU_RASR_ENABLE_Pos 0U
607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
609 
610 #endif
611 
612 
620 
636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
637 
644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
645 
656 /* Memory mapping of Core Hardware */
657 #define SCS_BASE (0xE000E000UL)
658 #define SysTick_BASE (SCS_BASE + 0x0010UL)
659 #define NVIC_BASE (SCS_BASE + 0x0100UL)
660 #define SCB_BASE (SCS_BASE + 0x0D00UL)
662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
663 #define SCB ((SCB_Type *) SCB_BASE )
664 #define SysTick ((SysTick_Type *) SysTick_BASE )
665 #define NVIC ((NVIC_Type *) NVIC_BASE )
667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
668  #define MPU_BASE (SCS_BASE + 0x0D90UL)
669  #define MPU ((MPU_Type *) MPU_BASE )
670 #endif
671 
676 /*******************************************************************************
677  * Hardware Abstraction Layer
678  Core Function Interface contains:
679  - Core NVIC Functions
680  - Core SysTick Functions
681  - Core Register Access Functions
682  ******************************************************************************/
689 /* ########################## NVIC functions #################################### */
697 #ifdef CMSIS_NVIC_VIRTUAL
698  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
699  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
700  #endif
701  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
702 #else
703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
705  #define NVIC_EnableIRQ __NVIC_EnableIRQ
706  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
707  #define NVIC_DisableIRQ __NVIC_DisableIRQ
708  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
709  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
710  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
712  #define NVIC_SetPriority __NVIC_SetPriority
713  #define NVIC_GetPriority __NVIC_GetPriority
714  #define NVIC_SystemReset __NVIC_SystemReset
715 #endif /* CMSIS_NVIC_VIRTUAL */
716 
717 #ifdef CMSIS_VECTAB_VIRTUAL
718  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
719  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
720  #endif
721  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
722 #else
723  #define NVIC_SetVector __NVIC_SetVector
724  #define NVIC_GetVector __NVIC_GetVector
725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
726 
727 #define NVIC_USER_IRQ_OFFSET 16
728 
729 
730 /* The following EXC_RETURN values are saved the LR on exception entry */
731 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
732 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
733 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
734 
735 
736 /* Interrupt Priorities are WORD accessible only under Armv6-M */
737 /* The following MACROS handle generation of the register offset and byte masks */
738 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
739 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
740 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
741 
742 
749 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
750 {
751  if ((int32_t)(IRQn) >= 0)
752  {
753  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
754  }
755 }
756 
757 
766 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
767 {
768  if ((int32_t)(IRQn) >= 0)
769  {
770  return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
771  }
772  else
773  {
774  return(0U);
775  }
776 }
777 
778 
785 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
786 {
787  if ((int32_t)(IRQn) >= 0)
788  {
789  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
790  __DSB();
791  __ISB();
792  }
793 }
794 
795 
804 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
805 {
806  if ((int32_t)(IRQn) >= 0)
807  {
808  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
809  }
810  else
811  {
812  return(0U);
813  }
814 }
815 
816 
823 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
824 {
825  if ((int32_t)(IRQn) >= 0)
826  {
827  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
828  }
829 }
830 
831 
838 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
839 {
840  if ((int32_t)(IRQn) >= 0)
841  {
842  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
843  }
844 }
845 
846 
856 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
857 {
858  if ((int32_t)(IRQn) >= 0)
859  {
860  NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
861  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
862  }
863  else
864  {
865  SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
866  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
867  }
868 }
869 
870 
880 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
881 {
882 
883  if ((int32_t)(IRQn) >= 0)
884  {
885  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
886  }
887  else
888  {
889  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
890  }
891 }
892 
893 
903 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
904 {
905  uint32_t *vectors = (uint32_t *)SCB->VTOR;
906  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
907 }
908 
909 
918 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
919 {
920  uint32_t *vectors = (uint32_t *)SCB->VTOR;
921  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
922 }
923 
924 
929 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
930 {
931  __DSB(); /* Ensure all outstanding memory accesses included
932  buffered write are completed before reset */
933  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
934  SCB_AIRCR_SYSRESETREQ_Msk);
935  __DSB(); /* Ensure completion of memory access */
936 
937  for(;;) /* wait until reset */
938  {
939  __NOP();
940  }
941 }
942 
946 /* ########################## FPU functions #################################### */
962 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
963 {
964  return 0U; /* No FPU */
965 }
966 
967 
972 /* ################################## SysTick function ############################################ */
980 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
981 
993 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
994 {
995  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
996  {
997  return (1UL); /* Reload value impossible */
998  }
999 
1000  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1001  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1002  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1003  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1004  SysTick_CTRL_TICKINT_Msk |
1005  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1006  return (0UL); /* Function successful */
1007 }
1008 
1009 #endif
1010 
1016 #ifdef __cplusplus
1017 }
1018 #endif
1019 
1020 #endif /* __CORE_SC000_H_DEPENDANT */
1021 
1022 #endif /* __CMSIS_GENERIC */
SCB
#define SCB
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:663
__IM
#define __IM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:173
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2054
CONTROL_Type::@420::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:298
APSR_Type::@417::V
uint32_t V
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:210
IRQn
IRQn
Definition: MIMXRT1052.h:78
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:496
cmsis_compiler.h
CMSIS compiler generic header file.
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:331
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:421
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:944
IPSR_Type::@418::ISR
uint32_t ISR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:239
xPSR_Type::@419::N
uint32_t N
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:264
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:274
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:933
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:739
APSR_Type::@417::C
uint32_t C
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:211
__IOM
#define __IOM
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:175
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1052.h:91
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:738
__NOP
#define __NOP
No Operation.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:416
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1978
xPSR_Type::@419::V
uint32_t V
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:261
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:455
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:499
xPSR_Type::@419::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:258
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1902
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1993
__STATIC_INLINE
#define __STATIC_INLINE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:63
CONTROL_Type::@420::SPSEL
uint32_t SPSEL
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:297
CONTROL_Type::@420::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:296
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:506
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f407xx.h:66
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:386
xPSR_Type::@419::Z
uint32_t Z
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:263
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2129
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:411
xPSR_Type::@419::C
uint32_t C
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:262
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1940
NVIC
#define NVIC
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:665
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2145
NVIC_SetPriority
#define NVIC_SetPriority
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:712
APSR_Type::@417::Z
uint32_t Z
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:212
_IP_IDX
#define _IP_IDX(IRQn)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:740
xPSR_Type::@419::_reserved1
uint32_t _reserved1
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:260
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:502
__NO_RETURN
#define __NO_RETURN
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:69
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:421
APSR_Type::@417::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:209
SCB_Type::SFCR
__IOM uint32_t SFCR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:359
SysTick
#define SysTick
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:664
APSR_Type::@417::N
uint32_t N
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:213
IPSR_Type::@418::_reserved0
uint32_t _reserved0
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:240
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:727
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:921
cmsis_version.h
CMSIS Core(M) Version definitions.
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2156
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2032
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:2199
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1959
xPSR_Type::@419::ISR
uint32_t ISR
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:257
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1052.h:266
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:979
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:313
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1921
xPSR_Type::@419::T
uint32_t T
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc000.h:259

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:13:48