Public Attributes | List of all members

Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...

#include <core_cm3.h>

Public Attributes

__I uint32_t CID0
 
__I uint32_t CID1
 
__I uint32_t CID2
 
__I uint32_t CID3
 
__IO uint32_t IMCR
 
__IO uint32_t IRR
 
__I uint32_t IRR
 
__IO uint32_t IWR
 
__O uint32_t IWR
 
__IO uint32_t LAR
 
__O uint32_t LAR
 
__IO uint32_t LSR
 
__I uint32_t LSR
 
__I uint32_t PID0
 
__I uint32_t PID1
 
__I uint32_t PID2
 
__I uint32_t PID3
 
__I uint32_t PID4
 
__I uint32_t PID5
 
__I uint32_t PID6
 
__I uint32_t PID7
 
union {
   __O uint16_t   u16
 
   __O uint32_t   u32
 
   __O uint8_t   u8
 
PORT [32]
 
union {
   __O uint16_t   u16
 
   __O uint32_t   u32
 
   __O uint8_t   u8
 
PORT [32]
 
union {
   __O uint16_t   u16
 
   __O uint32_t   u32
 
   __O uint8_t   u8
 
PORT [32]
 
union {
   __O uint16_t   u16
 
   __O uint32_t   u32
 
   __O uint8_t   u8
 
PORT [32]
 
union {
   __O uint16_t   u16
 
   __O uint32_t   u32
 
   __O uint8_t   u8
 
PORT [32]
 
uint32_t RESERVED0 [864]
 
uint32_t RESERVED1 [15]
 
uint32_t RESERVED2 [15]
 
uint32_t RESERVED3 [29]
 
uint32_t RESERVED4 [43]
 
uint32_t RESERVED5 [6]
 
__IO uint32_t TCR
 
__IO uint32_t TER
 
__IO uint32_t TPR
 

Detailed Description

Structure type to access the Instrumentation Trace Macrocell Register (ITM).

Definition at line 660 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

Member Data Documentation

__I uint32_t ITM_Type::CID0

Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

Offset: ITM Component Identification Register #0

Definition at line 690 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::CID1

Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

Offset: ITM Component Identification Register #1

Definition at line 691 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::CID2

Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

Offset: ITM Component Identification Register #2

Definition at line 692 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::CID3

Offset: 0xFFC (R/ ) ITM Component Identification Register #3

Offset: ITM Component Identification Register #3

Definition at line 693 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t ITM_Type::IMCR

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

Offset: ITM Integration Mode Control Register

Definition at line 677 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t ITM_Type::IRR

Offset: ITM Integration Read Register

Definition at line 428 of file breezy/breezystm32/lib/CMSIS/CM3/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::IRR

Offset: 0xEFC (R/ ) ITM Integration Read Register

Definition at line 676 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t ITM_Type::IWR

Offset: ITM Integration Write Register

Definition at line 427 of file breezy/breezystm32/lib/CMSIS/CM3/CoreSupport/core_cm3.h.

__O uint32_t ITM_Type::IWR

Offset: 0xEF8 ( /W) ITM Integration Write Register

Definition at line 675 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t ITM_Type::LAR

Offset: ITM Lock Access Register

Definition at line 431 of file breezy/breezystm32/lib/CMSIS/CM3/CoreSupport/core_cm3.h.

__O uint32_t ITM_Type::LAR

Offset: 0xFB0 ( /W) ITM Lock Access Register

Definition at line 679 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t ITM_Type::LSR

Offset: ITM Lock Status Register

Definition at line 432 of file breezy/breezystm32/lib/CMSIS/CM3/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::LSR

Offset: 0xFB4 (R/ ) ITM Lock Status Register

Definition at line 680 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::PID0

Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

Offset: ITM Peripheral Identification Register #0

Definition at line 686 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::PID1

Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

Offset: ITM Peripheral Identification Register #1

Definition at line 687 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::PID2

Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

Offset: ITM Peripheral Identification Register #2

Definition at line 688 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::PID3

Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

Offset: ITM Peripheral Identification Register #3

Definition at line 689 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::PID4

Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

Offset: ITM Peripheral Identification Register #4

Definition at line 682 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::PID5

Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

Offset: ITM Peripheral Identification Register #5

Definition at line 683 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::PID6

Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

Offset: ITM Peripheral Identification Register #6

Definition at line 684 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t ITM_Type::PID7

Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

Offset: ITM Peripheral Identification Register #7

Definition at line 685 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__O { ... } ITM_Type::PORT[32]

Offset: 0x00 ITM Stimulus Port Registers

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

uint32_t ITM_Type::RESERVED0
uint32_t ITM_Type::RESERVED1
uint32_t ITM_Type::RESERVED2
uint32_t ITM_Type::RESERVED3
uint32_t ITM_Type::RESERVED4
uint32_t ITM_Type::RESERVED5
__IO uint32_t ITM_Type::TCR

Offset: 0xE80 (R/W) ITM Trace Control Register

Offset: ITM Trace Control Register

Definition at line 673 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t ITM_Type::TER

Offset: 0xE00 (R/W) ITM Trace Enable Register

Offset: ITM Trace Enable Register

Definition at line 669 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t ITM_Type::TPR

Offset: 0xE40 (R/W) ITM Trace Privilege Register

Offset: ITM Trace Privilege Register

Definition at line 671 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__O uint16_t ITM_Type::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

Offset: ITM Stimulus Port 16-bit

Definition at line 665 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__O uint32_t ITM_Type::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

Offset: ITM Stimulus Port 32-bit

Definition at line 666 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__O uint8_t ITM_Type::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

Offset: ITM Stimulus Port 8-bit

Definition at line 664 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.


The documentation for this struct was generated from the following files:


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Mon Jan 13 2020 19:50:06