Classes | Macros
Instrumentation Trace Macrocell (ITM)

Type definitions for the Instrumentation Trace Macrocell (ITM) More...

Collaboration diagram for Instrumentation Trace Macrocell (ITM):

Classes

struct  ITM_Type
 Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
 

Macros

#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)
 
#define ITM_IMCR_INTEGRATION_Pos   0
 
#define ITM_IMCR_INTEGRATION_Pos   0
 
#define ITM_IMCR_INTEGRATION_Pos   0
 
#define ITM_IMCR_INTEGRATION_Pos   0
 
#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)
 
#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)
 
#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)
 
#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)
 
#define ITM_IRR_ATREADYM_Pos   0
 
#define ITM_IRR_ATREADYM_Pos   0
 
#define ITM_IRR_ATREADYM_Pos   0
 
#define ITM_IRR_ATREADYM_Pos   0
 
#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)
 
#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)
 
#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)
 
#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)
 
#define ITM_IWR_ATVALIDM_Pos   0
 
#define ITM_IWR_ATVALIDM_Pos   0
 
#define ITM_IWR_ATVALIDM_Pos   0
 
#define ITM_IWR_ATVALIDM_Pos   0
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Access_Pos   1
 
#define ITM_LSR_Access_Pos   1
 
#define ITM_LSR_Access_Pos   1
 
#define ITM_LSR_Access_Pos   1
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2
 
#define ITM_LSR_ByteAcc_Pos   2
 
#define ITM_LSR_ByteAcc_Pos   2
 
#define ITM_LSR_ByteAcc_Pos   2
 
#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)
 
#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)
 
#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)
 
#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)
 
#define ITM_LSR_Present_Pos   0
 
#define ITM_LSR_Present_Pos   0
 
#define ITM_LSR_Present_Pos   0
 
#define ITM_LSR_Present_Pos   0
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_BUSY_Pos   23
 
#define ITM_TCR_BUSY_Pos   23
 
#define ITM_TCR_BUSY_Pos   23
 
#define ITM_TCR_BUSY_Pos   23
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3
 
#define ITM_TCR_DWTENA_Pos   3
 
#define ITM_TCR_DWTENA_Pos   3
 
#define ITM_TCR_DWTENA_Pos   3
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10
 
#define ITM_TCR_GTSFREQ_Pos   10
 
#define ITM_TCR_GTSFREQ_Pos   10
 
#define ITM_TCR_GTSFREQ_Pos   10
 
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
 
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
 
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
 
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0
 
#define ITM_TCR_ITMENA_Pos   0
 
#define ITM_TCR_ITMENA_Pos   0
 
#define ITM_TCR_ITMENA_Pos   0
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_SWOENA_Pos   4
 
#define ITM_TCR_SWOENA_Pos   4
 
#define ITM_TCR_SWOENA_Pos   4
 
#define ITM_TCR_SWOENA_Pos   4
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2
 
#define ITM_TCR_SYNCENA_Pos   2
 
#define ITM_TCR_SYNCENA_Pos   2
 
#define ITM_TCR_SYNCENA_Pos   2
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16
 
#define ITM_TCR_TraceBusID_Pos   16
 
#define ITM_TCR_TraceBusID_Pos   16
 
#define ITM_TCR_TraceBusID_Pos   16
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1
 
#define ITM_TCR_TSENA_Pos   1
 
#define ITM_TCR_TSENA_Pos   1
 
#define ITM_TCR_TSENA_Pos   1
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8
 
#define ITM_TCR_TSPrescale_Pos   8
 
#define ITM_TCR_TSPrescale_Pos   8
 
#define ITM_TCR_TSPrescale_Pos   8
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
 
#define ITM_TPR_PRIVMASK_Pos   0
 
#define ITM_TPR_PRIVMASK_Pos   0
 
#define ITM_TPR_PRIVMASK_Pos   0
 
#define ITM_TPR_PRIVMASK_Pos   0
 

Detailed Description

Type definitions for the Instrumentation Trace Macrocell (ITM)

Macro Definition Documentation

#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)

ITM IMCR: INTEGRATION Mask

Definition at line 718 of file core_sc300.h.

#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)

ITM IMCR: INTEGRATION Mask

Definition at line 738 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)

ITM IMCR: INTEGRATION Mask

Definition at line 778 of file core_cm4.h.

#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)

ITM IMCR: INTEGRATION Mask

Definition at line 959 of file core_cm7.h.

#define ITM_IMCR_INTEGRATION_Pos   0

ITM IMCR: INTEGRATION Position

Definition at line 717 of file core_sc300.h.

#define ITM_IMCR_INTEGRATION_Pos   0

ITM IMCR: INTEGRATION Position

Definition at line 737 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_IMCR_INTEGRATION_Pos   0

ITM IMCR: INTEGRATION Position

Definition at line 777 of file core_cm4.h.

#define ITM_IMCR_INTEGRATION_Pos   0

ITM IMCR: INTEGRATION Position

Definition at line 958 of file core_cm7.h.

#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)

ITM IRR: ATREADYM Mask

Definition at line 714 of file core_sc300.h.

#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)

ITM IRR: ATREADYM Mask

Definition at line 734 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)

ITM IRR: ATREADYM Mask

Definition at line 774 of file core_cm4.h.

#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)

ITM IRR: ATREADYM Mask

Definition at line 955 of file core_cm7.h.

#define ITM_IRR_ATREADYM_Pos   0

ITM IRR: ATREADYM Position

Definition at line 713 of file core_sc300.h.

#define ITM_IRR_ATREADYM_Pos   0

ITM IRR: ATREADYM Position

Definition at line 733 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_IRR_ATREADYM_Pos   0

ITM IRR: ATREADYM Position

Definition at line 773 of file core_cm4.h.

#define ITM_IRR_ATREADYM_Pos   0

ITM IRR: ATREADYM Position

Definition at line 954 of file core_cm7.h.

#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)

ITM IWR: ATVALIDM Mask

Definition at line 710 of file core_sc300.h.

#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)

ITM IWR: ATVALIDM Mask

Definition at line 730 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)

ITM IWR: ATVALIDM Mask

Definition at line 770 of file core_cm4.h.

#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)

ITM IWR: ATVALIDM Mask

Definition at line 951 of file core_cm7.h.

#define ITM_IWR_ATVALIDM_Pos   0

ITM IWR: ATVALIDM Position

Definition at line 709 of file core_sc300.h.

#define ITM_IWR_ATVALIDM_Pos   0

ITM IWR: ATVALIDM Position

Definition at line 729 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_IWR_ATVALIDM_Pos   0

ITM IWR: ATVALIDM Position

Definition at line 769 of file core_cm4.h.

#define ITM_IWR_ATVALIDM_Pos   0

ITM IWR: ATVALIDM Position

Definition at line 950 of file core_cm7.h.

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 725 of file core_sc300.h.

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 745 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 785 of file core_cm4.h.

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 966 of file core_cm7.h.

#define ITM_LSR_Access_Pos   1

ITM LSR: Access Position

Definition at line 724 of file core_sc300.h.

#define ITM_LSR_Access_Pos   1

ITM LSR: Access Position

Definition at line 744 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_LSR_Access_Pos   1

ITM LSR: Access Position

Definition at line 784 of file core_cm4.h.

#define ITM_LSR_Access_Pos   1

ITM LSR: Access Position

Definition at line 965 of file core_cm7.h.

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 722 of file core_sc300.h.

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 742 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 782 of file core_cm4.h.

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 963 of file core_cm7.h.

#define ITM_LSR_ByteAcc_Pos   2

ITM LSR: ByteAcc Position

Definition at line 721 of file core_sc300.h.

#define ITM_LSR_ByteAcc_Pos   2

ITM LSR: ByteAcc Position

Definition at line 741 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_LSR_ByteAcc_Pos   2

ITM LSR: ByteAcc Position

Definition at line 781 of file core_cm4.h.

#define ITM_LSR_ByteAcc_Pos   2

ITM LSR: ByteAcc Position

Definition at line 962 of file core_cm7.h.

#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)

ITM LSR: Present Mask

Definition at line 728 of file core_sc300.h.

#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)

ITM LSR: Present Mask

Definition at line 748 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)

ITM LSR: Present Mask

Definition at line 788 of file core_cm4.h.

#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)

ITM LSR: Present Mask

Definition at line 969 of file core_cm7.h.

#define ITM_LSR_Present_Pos   0

ITM LSR: Present Position

Definition at line 727 of file core_sc300.h.

#define ITM_LSR_Present_Pos   0

ITM LSR: Present Position

Definition at line 747 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_LSR_Present_Pos   0

ITM LSR: Present Position

Definition at line 787 of file core_cm4.h.

#define ITM_LSR_Present_Pos   0

ITM LSR: Present Position

Definition at line 968 of file core_cm7.h.

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 682 of file core_sc300.h.

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 702 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 742 of file core_cm4.h.

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 923 of file core_cm7.h.

#define ITM_TCR_BUSY_Pos   23

ITM TCR: BUSY Position

Definition at line 681 of file core_sc300.h.

#define ITM_TCR_BUSY_Pos   23

ITM TCR: BUSY Position

Definition at line 701 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_BUSY_Pos   23

ITM TCR: BUSY Position

Definition at line 741 of file core_cm4.h.

#define ITM_TCR_BUSY_Pos   23

ITM TCR: BUSY Position

Definition at line 922 of file core_cm7.h.

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 697 of file core_sc300.h.

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 717 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 757 of file core_cm4.h.

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 938 of file core_cm7.h.

#define ITM_TCR_DWTENA_Pos   3

ITM TCR: DWTENA Position

Definition at line 696 of file core_sc300.h.

#define ITM_TCR_DWTENA_Pos   3

ITM TCR: DWTENA Position

Definition at line 716 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_DWTENA_Pos   3

ITM TCR: DWTENA Position

Definition at line 756 of file core_cm4.h.

#define ITM_TCR_DWTENA_Pos   3

ITM TCR: DWTENA Position

Definition at line 937 of file core_cm7.h.

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 688 of file core_sc300.h.

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 708 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 748 of file core_cm4.h.

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 929 of file core_cm7.h.

#define ITM_TCR_GTSFREQ_Pos   10

ITM TCR: Global timestamp frequency Position

Definition at line 687 of file core_sc300.h.

#define ITM_TCR_GTSFREQ_Pos   10

ITM TCR: Global timestamp frequency Position

Definition at line 707 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_GTSFREQ_Pos   10

ITM TCR: Global timestamp frequency Position

Definition at line 747 of file core_cm4.h.

#define ITM_TCR_GTSFREQ_Pos   10

ITM TCR: Global timestamp frequency Position

Definition at line 928 of file core_cm7.h.

#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)

ITM TCR: ITM Enable bit Mask

Definition at line 706 of file core_sc300.h.

#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)

ITM TCR: ITM Enable bit Mask

Definition at line 726 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)

ITM TCR: ITM Enable bit Mask

Definition at line 766 of file core_cm4.h.

#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)

ITM TCR: ITM Enable bit Mask

Definition at line 947 of file core_cm7.h.

#define ITM_TCR_ITMENA_Pos   0

ITM TCR: ITM Enable bit Position

Definition at line 705 of file core_sc300.h.

#define ITM_TCR_ITMENA_Pos   0

ITM TCR: ITM Enable bit Position

Definition at line 725 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_ITMENA_Pos   0

ITM TCR: ITM Enable bit Position

Definition at line 765 of file core_cm4.h.

#define ITM_TCR_ITMENA_Pos   0

ITM TCR: ITM Enable bit Position

Definition at line 946 of file core_cm7.h.

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 694 of file core_sc300.h.

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 714 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 754 of file core_cm4.h.

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 935 of file core_cm7.h.

#define ITM_TCR_SWOENA_Pos   4

ITM TCR: SWOENA Position

Definition at line 693 of file core_sc300.h.

#define ITM_TCR_SWOENA_Pos   4

ITM TCR: SWOENA Position

Definition at line 713 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_SWOENA_Pos   4

ITM TCR: SWOENA Position

Definition at line 753 of file core_cm4.h.

#define ITM_TCR_SWOENA_Pos   4

ITM TCR: SWOENA Position

Definition at line 934 of file core_cm7.h.

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 700 of file core_sc300.h.

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 720 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 760 of file core_cm4.h.

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 941 of file core_cm7.h.

#define ITM_TCR_SYNCENA_Pos   2

ITM TCR: SYNCENA Position

Definition at line 699 of file core_sc300.h.

#define ITM_TCR_SYNCENA_Pos   2

ITM TCR: SYNCENA Position

Definition at line 719 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_SYNCENA_Pos   2

ITM TCR: SYNCENA Position

Definition at line 759 of file core_cm4.h.

#define ITM_TCR_SYNCENA_Pos   2

ITM TCR: SYNCENA Position

Definition at line 940 of file core_cm7.h.

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 685 of file core_sc300.h.

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 705 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 745 of file core_cm4.h.

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 926 of file core_cm7.h.

#define ITM_TCR_TraceBusID_Pos   16

ITM TCR: ATBID Position

Definition at line 684 of file core_sc300.h.

#define ITM_TCR_TraceBusID_Pos   16

ITM TCR: ATBID Position

Definition at line 704 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_TraceBusID_Pos   16

ITM TCR: ATBID Position

Definition at line 744 of file core_cm4.h.

#define ITM_TCR_TraceBusID_Pos   16

ITM TCR: ATBID Position

Definition at line 925 of file core_cm7.h.

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 703 of file core_sc300.h.

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 723 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 763 of file core_cm4.h.

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 944 of file core_cm7.h.

#define ITM_TCR_TSENA_Pos   1

ITM TCR: TSENA Position

Definition at line 702 of file core_sc300.h.

#define ITM_TCR_TSENA_Pos   1

ITM TCR: TSENA Position

Definition at line 722 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_TSENA_Pos   1

ITM TCR: TSENA Position

Definition at line 762 of file core_cm4.h.

#define ITM_TCR_TSENA_Pos   1

ITM TCR: TSENA Position

Definition at line 943 of file core_cm7.h.

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 691 of file core_sc300.h.

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 711 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 751 of file core_cm4.h.

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 932 of file core_cm7.h.

#define ITM_TCR_TSPrescale_Pos   8

ITM TCR: TSPrescale Position

Definition at line 690 of file core_sc300.h.

#define ITM_TCR_TSPrescale_Pos   8

ITM TCR: TSPrescale Position

Definition at line 710 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TCR_TSPrescale_Pos   8

ITM TCR: TSPrescale Position

Definition at line 750 of file core_cm4.h.

#define ITM_TCR_TSPrescale_Pos   8

ITM TCR: TSPrescale Position

Definition at line 931 of file core_cm7.h.

#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)

ITM TPR: PRIVMASK Mask

Definition at line 678 of file core_sc300.h.

#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)

ITM TPR: PRIVMASK Mask

Definition at line 698 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)

ITM TPR: PRIVMASK Mask

Definition at line 738 of file core_cm4.h.

#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)

ITM TPR: PRIVMASK Mask

Definition at line 919 of file core_cm7.h.

#define ITM_TPR_PRIVMASK_Pos   0

ITM TPR: PRIVMASK Position

Definition at line 677 of file core_sc300.h.

#define ITM_TPR_PRIVMASK_Pos   0

ITM TPR: PRIVMASK Position

Definition at line 697 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

#define ITM_TPR_PRIVMASK_Pos   0

ITM TPR: PRIVMASK Position

Definition at line 737 of file core_cm4.h.

#define ITM_TPR_PRIVMASK_Pos   0

ITM TPR: PRIVMASK Position

Definition at line 918 of file core_cm7.h.



rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Fri Jul 24 2020 03:20:12