core_cm7.h
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1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_CM7_H_GENERIC
43 #define __CORE_CM7_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
63 /*******************************************************************************
64  * CMSIS definitions
65  ******************************************************************************/
70 /* CMSIS CM7 definitions */
71 #define __CM7_CMSIS_VERSION_MAIN (0x04)
72 #define __CM7_CMSIS_VERSION_SUB (0x00)
73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
74  __CM7_CMSIS_VERSION_SUB )
76 #define __CORTEX_M (0x07)
79 #if defined ( __CC_ARM )
80  #define __ASM __asm
81  #define __INLINE __inline
82  #define __STATIC_INLINE static __inline
83 
84 #elif defined ( __GNUC__ )
85  #define __ASM __asm
86  #define __INLINE inline
87  #define __STATIC_INLINE static inline
88 
89 #elif defined ( __ICCARM__ )
90  #define __ASM __asm
91  #define __INLINE inline
92  #define __STATIC_INLINE static inline
93 
94 #elif defined ( __TMS470__ )
95  #define __ASM __asm
96  #define __STATIC_INLINE static inline
97 
98 #elif defined ( __TASKING__ )
99  #define __ASM __asm
100  #define __INLINE inline
101  #define __STATIC_INLINE static inline
102 
103 #elif defined ( __CSMC__ )
104  #define __packed
105  #define __ASM _asm
106  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107  #define __STATIC_INLINE static inline
108 
109 #endif
110 
114 #if defined ( __CC_ARM )
115  #if defined __TARGET_FPU_VFP
116  #if (__FPU_PRESENT == 1)
117  #define __FPU_USED 1
118  #else
119  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
120  #define __FPU_USED 0
121  #endif
122  #else
123  #define __FPU_USED 0
124  #endif
125 
126 #elif defined ( __GNUC__ )
127  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
128  #if (__FPU_PRESENT == 1)
129  #define __FPU_USED 1
130  #else
131  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132  #define __FPU_USED 0
133  #endif
134  #else
135  #define __FPU_USED 0
136  #endif
137 
138 #elif defined ( __ICCARM__ )
139  #if defined __ARMVFP__
140  #if (__FPU_PRESENT == 1)
141  #define __FPU_USED 1
142  #else
143  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #define __FPU_USED 0
145  #endif
146  #else
147  #define __FPU_USED 0
148  #endif
149 
150 #elif defined ( __TMS470__ )
151  #if defined __TI_VFP_SUPPORT__
152  #if (__FPU_PRESENT == 1)
153  #define __FPU_USED 1
154  #else
155  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156  #define __FPU_USED 0
157  #endif
158  #else
159  #define __FPU_USED 0
160  #endif
161 
162 #elif defined ( __TASKING__ )
163  #if defined __FPU_VFP__
164  #if (__FPU_PRESENT == 1)
165  #define __FPU_USED 1
166  #else
167  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
168  #define __FPU_USED 0
169  #endif
170  #else
171  #define __FPU_USED 0
172  #endif
173 
174 #elif defined ( __CSMC__ ) /* Cosmic */
175  #if ( __CSMC__ & 0x400) // FPU present for parser
176  #if (__FPU_PRESENT == 1)
177  #define __FPU_USED 1
178  #else
179  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
180  #define __FPU_USED 0
181  #endif
182  #else
183  #define __FPU_USED 0
184  #endif
185 #endif
186 
187 #include <stdint.h> /* standard types definitions */
188 #include <core_cmInstr.h> /* Core Instruction Access */
189 #include <core_cmFunc.h> /* Core Function Access */
190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
191 
192 #ifdef __cplusplus
193 }
194 #endif
195 
196 #endif /* __CORE_CM7_H_GENERIC */
197 
198 #ifndef __CMSIS_GENERIC
199 
200 #ifndef __CORE_CM7_H_DEPENDANT
201 #define __CORE_CM7_H_DEPENDANT
202 
203 #ifdef __cplusplus
204  extern "C" {
205 #endif
206 
207 /* check device defines and use defaults */
208 #if defined __CHECK_DEVICE_DEFINES
209  #ifndef __CM7_REV
210  #define __CM7_REV 0x0000
211  #warning "__CM7_REV not defined in device header file; using default!"
212  #endif
213 
214  #ifndef __FPU_PRESENT
215  #define __FPU_PRESENT 0
216  #warning "__FPU_PRESENT not defined in device header file; using default!"
217  #endif
218 
219  #ifndef __MPU_PRESENT
220  #define __MPU_PRESENT 0
221  #warning "__MPU_PRESENT not defined in device header file; using default!"
222  #endif
223 
224  #ifndef __ICACHE_PRESENT
225  #define __ICACHE_PRESENT 0
226  #warning "__ICACHE_PRESENT not defined in device header file; using default!"
227  #endif
228 
229  #ifndef __DCACHE_PRESENT
230  #define __DCACHE_PRESENT 0
231  #warning "__DCACHE_PRESENT not defined in device header file; using default!"
232  #endif
233 
234  #ifndef __DTCM_PRESENT
235  #define __DTCM_PRESENT 0
236  #warning "__DTCM_PRESENT not defined in device header file; using default!"
237  #endif
238 
239  #ifndef __NVIC_PRIO_BITS
240  #define __NVIC_PRIO_BITS 3
241  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
242  #endif
243 
244  #ifndef __Vendor_SysTickConfig
245  #define __Vendor_SysTickConfig 0
246  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
247  #endif
248 #endif
249 
250 /* IO definitions (access restrictions to peripheral registers) */
258 #ifdef __cplusplus
259  #define __I volatile
260 #else
261  #define __I volatile const
262 #endif
263 #define __O volatile
264 #define __IO volatile
266 
270 /*******************************************************************************
271  * Register Abstraction
272  Core Register contain:
273  - Core Register
274  - Core NVIC Register
275  - Core SCB Register
276  - Core SysTick Register
277  - Core Debug Register
278  - Core MPU Register
279  - Core FPU Register
280  ******************************************************************************/
281 
293 typedef union
294 {
295  struct
296  {
297 #if (__CORTEX_M != 0x07)
298  uint32_t _reserved0:27;
299 #else
300  uint32_t _reserved0:16;
301  uint32_t GE:4;
302  uint32_t _reserved1:7;
303 #endif
304  uint32_t Q:1;
305  uint32_t V:1;
306  uint32_t C:1;
307  uint32_t Z:1;
308  uint32_t N:1;
309  } b;
310  uint32_t w;
311 } APSR_Type;
312 
313 
316 typedef union
317 {
318  struct
319  {
320  uint32_t ISR:9;
321  uint32_t _reserved0:23;
322  } b;
323  uint32_t w;
324 } IPSR_Type;
325 
326 
329 typedef union
330 {
331  struct
332  {
333  uint32_t ISR:9;
334 #if (__CORTEX_M != 0x07)
335  uint32_t _reserved0:15;
336 #else
337  uint32_t _reserved0:7;
338  uint32_t GE:4;
339  uint32_t _reserved1:4;
340 #endif
341  uint32_t T:1;
342  uint32_t IT:2;
343  uint32_t Q:1;
344  uint32_t V:1;
345  uint32_t C:1;
346  uint32_t Z:1;
347  uint32_t N:1;
348  } b;
349  uint32_t w;
350 } xPSR_Type;
351 
352 
355 typedef union
356 {
357  struct
358  {
359  uint32_t nPRIV:1;
360  uint32_t SPSEL:1;
361  uint32_t FPCA:1;
362  uint32_t _reserved0:29;
363  } b;
364  uint32_t w;
365 } CONTROL_Type;
366 
378 typedef struct
379 {
380  __IO uint32_t ISER[8];
381  uint32_t RESERVED0[24];
382  __IO uint32_t ICER[8];
383  uint32_t RSERVED1[24];
384  __IO uint32_t ISPR[8];
385  uint32_t RESERVED2[24];
386  __IO uint32_t ICPR[8];
387  uint32_t RESERVED3[24];
388  __IO uint32_t IABR[8];
389  uint32_t RESERVED4[56];
390  __IO uint8_t IP[240];
391  uint32_t RESERVED5[644];
392  __O uint32_t STIR;
393 } NVIC_Type;
394 
395 /* Software Triggered Interrupt Register Definitions */
396 #define NVIC_STIR_INTID_Pos 0
397 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
399 
410 typedef struct
411 {
412  __I uint32_t CPUID;
413  __IO uint32_t ICSR;
414  __IO uint32_t VTOR;
415  __IO uint32_t AIRCR;
416  __IO uint32_t SCR;
417  __IO uint32_t CCR;
418  __IO uint8_t SHPR[12];
419  __IO uint32_t SHCSR;
420  __IO uint32_t CFSR;
421  __IO uint32_t HFSR;
422  __IO uint32_t DFSR;
423  __IO uint32_t MMFAR;
424  __IO uint32_t BFAR;
425  __IO uint32_t AFSR;
426  __I uint32_t ID_PFR[2];
427  __I uint32_t ID_DFR;
428  __I uint32_t ID_AFR;
429  __I uint32_t ID_MFR[4];
430  __I uint32_t ID_ISAR[5];
431  uint32_t RESERVED0[1];
432  __I uint32_t CLIDR;
433  __I uint32_t CTR;
434  __I uint32_t CCSIDR;
435  __IO uint32_t CSSELR;
436  __IO uint32_t CPACR;
437  uint32_t RESERVED3[93];
438  __O uint32_t STIR;
439  uint32_t RESERVED4[15];
440  __I uint32_t MVFR0;
441  __I uint32_t MVFR1;
442  __I uint32_t MVFR2;
443  uint32_t RESERVED5[1];
444  __O uint32_t ICIALLU;
445  uint32_t RESERVED6[1];
446  __O uint32_t ICIMVAU;
447  __O uint32_t DCIMVAU;
448  __O uint32_t DCISW;
449  __O uint32_t DCCMVAU;
450  __O uint32_t DCCMVAC;
451  __O uint32_t DCCSW;
452  __O uint32_t DCCIMVAC;
453  __O uint32_t DCCISW;
454  uint32_t RESERVED7[6];
455  __IO uint32_t ITCMCR;
456  __IO uint32_t DTCMCR;
457  __IO uint32_t AHBPCR;
458  __IO uint32_t CACR;
459  __IO uint32_t AHBSCR;
460  uint32_t RESERVED8[1];
461  __IO uint32_t ABFSR;
462 } SCB_Type;
463 
464 /* SCB CPUID Register Definitions */
465 #define SCB_CPUID_IMPLEMENTER_Pos 24
466 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
468 #define SCB_CPUID_VARIANT_Pos 20
469 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
471 #define SCB_CPUID_ARCHITECTURE_Pos 16
472 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
474 #define SCB_CPUID_PARTNO_Pos 4
475 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
477 #define SCB_CPUID_REVISION_Pos 0
478 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
480 /* SCB Interrupt Control State Register Definitions */
481 #define SCB_ICSR_NMIPENDSET_Pos 31
482 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
484 #define SCB_ICSR_PENDSVSET_Pos 28
485 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
487 #define SCB_ICSR_PENDSVCLR_Pos 27
488 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
490 #define SCB_ICSR_PENDSTSET_Pos 26
491 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
493 #define SCB_ICSR_PENDSTCLR_Pos 25
494 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
496 #define SCB_ICSR_ISRPREEMPT_Pos 23
497 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
499 #define SCB_ICSR_ISRPENDING_Pos 22
500 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
502 #define SCB_ICSR_VECTPENDING_Pos 12
503 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
505 #define SCB_ICSR_RETTOBASE_Pos 11
506 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
508 #define SCB_ICSR_VECTACTIVE_Pos 0
509 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
511 /* SCB Vector Table Offset Register Definitions */
512 #define SCB_VTOR_TBLOFF_Pos 7
513 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
515 /* SCB Application Interrupt and Reset Control Register Definitions */
516 #define SCB_AIRCR_VECTKEY_Pos 16
517 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
519 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
520 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
522 #define SCB_AIRCR_ENDIANESS_Pos 15
523 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
525 #define SCB_AIRCR_PRIGROUP_Pos 8
526 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
528 #define SCB_AIRCR_SYSRESETREQ_Pos 2
529 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
531 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
532 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
534 #define SCB_AIRCR_VECTRESET_Pos 0
535 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
537 /* SCB System Control Register Definitions */
538 #define SCB_SCR_SEVONPEND_Pos 4
539 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
541 #define SCB_SCR_SLEEPDEEP_Pos 2
542 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
544 #define SCB_SCR_SLEEPONEXIT_Pos 1
545 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
547 /* SCB Configuration Control Register Definitions */
548 #define SCB_CCR_BP_Pos 18
549 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
551 #define SCB_CCR_IC_Pos 17
552 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
554 #define SCB_CCR_DC_Pos 16
555 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
557 #define SCB_CCR_STKALIGN_Pos 9
558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
560 #define SCB_CCR_BFHFNMIGN_Pos 8
561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
563 #define SCB_CCR_DIV_0_TRP_Pos 4
564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
566 #define SCB_CCR_UNALIGN_TRP_Pos 3
567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
569 #define SCB_CCR_USERSETMPEND_Pos 1
570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
572 #define SCB_CCR_NONBASETHRDENA_Pos 0
573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
575 /* SCB System Handler Control and State Register Definitions */
576 #define SCB_SHCSR_USGFAULTENA_Pos 18
577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
579 #define SCB_SHCSR_BUSFAULTENA_Pos 17
580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
582 #define SCB_SHCSR_MEMFAULTENA_Pos 16
583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
585 #define SCB_SHCSR_SVCALLPENDED_Pos 15
586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14
589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13
592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12
595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
597 #define SCB_SHCSR_SYSTICKACT_Pos 11
598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
600 #define SCB_SHCSR_PENDSVACT_Pos 10
601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
603 #define SCB_SHCSR_MONITORACT_Pos 8
604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
606 #define SCB_SHCSR_SVCALLACT_Pos 7
607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
609 #define SCB_SHCSR_USGFAULTACT_Pos 3
610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
612 #define SCB_SHCSR_BUSFAULTACT_Pos 1
613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
615 #define SCB_SHCSR_MEMFAULTACT_Pos 0
616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
618 /* SCB Configurable Fault Status Registers Definitions */
619 #define SCB_CFSR_USGFAULTSR_Pos 16
620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
622 #define SCB_CFSR_BUSFAULTSR_Pos 8
623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
625 #define SCB_CFSR_MEMFAULTSR_Pos 0
626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
628 /* SCB Hard Fault Status Registers Definitions */
629 #define SCB_HFSR_DEBUGEVT_Pos 31
630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
632 #define SCB_HFSR_FORCED_Pos 30
633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
635 #define SCB_HFSR_VECTTBL_Pos 1
636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
638 /* SCB Debug Fault Status Register Definitions */
639 #define SCB_DFSR_EXTERNAL_Pos 4
640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
642 #define SCB_DFSR_VCATCH_Pos 3
643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
645 #define SCB_DFSR_DWTTRAP_Pos 2
646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
648 #define SCB_DFSR_BKPT_Pos 1
649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
651 #define SCB_DFSR_HALTED_Pos 0
652 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)
654 /* Cache Level ID register */
655 #define SCB_CLIDR_LOUU_Pos 27
656 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
658 #define SCB_CLIDR_LOC_Pos 24
659 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos)
661 /* Cache Type register */
662 #define SCB_CTR_FORMAT_Pos 29
663 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
665 #define SCB_CTR_CWG_Pos 24
666 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
668 #define SCB_CTR_ERG_Pos 20
669 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
671 #define SCB_CTR_DMINLINE_Pos 16
672 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
674 #define SCB_CTR_IMINLINE_Pos 0
675 #define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos)
677 /* Cache Size ID Register */
678 #define SCB_CCSIDR_WT_Pos 31
679 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos)
681 #define SCB_CCSIDR_WB_Pos 30
682 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos)
684 #define SCB_CCSIDR_RA_Pos 29
685 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos)
687 #define SCB_CCSIDR_WA_Pos 28
688 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos)
690 #define SCB_CCSIDR_NUMSETS_Pos 13
691 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
693 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3
694 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
696 #define SCB_CCSIDR_LINESIZE_Pos 0
697 #define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos)
699 /* Cache Size Selection Register */
700 #define SCB_CSSELR_LEVEL_Pos 0
701 #define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos)
703 #define SCB_CSSELR_IND_Pos 0
704 #define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos)
706 /* SCB Software Triggered Interrupt Register */
707 #define SCB_STIR_INTID_Pos 0
708 #define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos)
710 /* Instruction Tightly-Coupled Memory Control Register*/
711 #define SCB_ITCMCR_SZ_Pos 3
712 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
714 #define SCB_ITCMCR_RETEN_Pos 2
715 #define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos)
717 #define SCB_ITCMCR_RMW_Pos 1
718 #define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos)
720 #define SCB_ITCMCR_EN_Pos 0
721 #define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos)
723 /* Data Tightly-Coupled Memory Control Registers */
724 #define SCB_DTCMCR_SZ_Pos 3
725 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
727 #define SCB_DTCMCR_RETEN_Pos 2
728 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
730 #define SCB_DTCMCR_RMW_Pos 1
731 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
733 #define SCB_DTCMCR_EN_Pos 0
734 #define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos)
736 /* AHBP Control Register */
737 #define SCB_AHBPCR_SZ_Pos 1
738 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
740 #define SCB_AHBPCR_EN_Pos 0
741 #define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos)
743 /* L1 Cache Control Register */
744 #define SCB_CACR_FORCEWT_Pos 2
745 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
747 #define SCB_CACR_ECCEN_Pos 1
748 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
750 #define SCB_CACR_SIWT_Pos 0
751 #define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos)
753 /* AHBS control register */
754 #define SCB_AHBSCR_INITCOUNT_Pos 11
755 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
757 #define SCB_AHBSCR_TPRI_Pos 2
758 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
760 #define SCB_AHBSCR_CTL_Pos 0
761 #define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos)
763 /* Auxiliary Bus Fault Status Register */
764 #define SCB_ABFSR_AXIMTYPE_Pos 8
765 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
767 #define SCB_ABFSR_EPPB_Pos 4
768 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
770 #define SCB_ABFSR_AXIM_Pos 3
771 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
773 #define SCB_ABFSR_AHBP_Pos 2
774 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
776 #define SCB_ABFSR_DTCM_Pos 1
777 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
779 #define SCB_ABFSR_ITCM_Pos 0
780 #define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos)
782 
793 typedef struct
794 {
795  uint32_t RESERVED0[1];
796  __I uint32_t ICTR;
797  __IO uint32_t ACTLR;
798 } SCnSCB_Type;
799 
800 /* Interrupt Controller Type Register Definitions */
801 #define SCnSCB_ICTR_INTLINESNUM_Pos 0
802 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
804 /* Auxiliary Control Register Definitions */
805 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12
806 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)
808 #define SCnSCB_ACTLR_DISRAMODE_Pos 11
809 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)
811 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10
812 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)
814 #define SCnSCB_ACTLR_DISFOLD_Pos 2
815 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
817 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0
818 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
820 
831 typedef struct
832 {
833  __IO uint32_t CTRL;
834  __IO uint32_t LOAD;
835  __IO uint32_t VAL;
836  __I uint32_t CALIB;
837 } SysTick_Type;
838 
839 /* SysTick Control / Status Register Definitions */
840 #define SysTick_CTRL_COUNTFLAG_Pos 16
841 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
843 #define SysTick_CTRL_CLKSOURCE_Pos 2
844 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
846 #define SysTick_CTRL_TICKINT_Pos 1
847 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
849 #define SysTick_CTRL_ENABLE_Pos 0
850 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
852 /* SysTick Reload Register Definitions */
853 #define SysTick_LOAD_RELOAD_Pos 0
854 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
856 /* SysTick Current Register Definitions */
857 #define SysTick_VAL_CURRENT_Pos 0
858 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
860 /* SysTick Calibration Register Definitions */
861 #define SysTick_CALIB_NOREF_Pos 31
862 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
864 #define SysTick_CALIB_SKEW_Pos 30
865 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
867 #define SysTick_CALIB_TENMS_Pos 0
868 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
870 
881 typedef struct
882 {
883  __O union
884  {
885  __O uint8_t u8;
886  __O uint16_t u16;
887  __O uint32_t u32;
888  } PORT [32];
889  uint32_t RESERVED0[864];
890  __IO uint32_t TER;
891  uint32_t RESERVED1[15];
892  __IO uint32_t TPR;
893  uint32_t RESERVED2[15];
894  __IO uint32_t TCR;
895  uint32_t RESERVED3[29];
896  __O uint32_t IWR;
897  __I uint32_t IRR;
898  __IO uint32_t IMCR;
899  uint32_t RESERVED4[43];
900  __O uint32_t LAR;
901  __I uint32_t LSR;
902  uint32_t RESERVED5[6];
903  __I uint32_t PID4;
904  __I uint32_t PID5;
905  __I uint32_t PID6;
906  __I uint32_t PID7;
907  __I uint32_t PID0;
908  __I uint32_t PID1;
909  __I uint32_t PID2;
910  __I uint32_t PID3;
911  __I uint32_t CID0;
912  __I uint32_t CID1;
913  __I uint32_t CID2;
914  __I uint32_t CID3;
915 } ITM_Type;
916 
917 /* ITM Trace Privilege Register Definitions */
918 #define ITM_TPR_PRIVMASK_Pos 0
919 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos)
921 /* ITM Trace Control Register Definitions */
922 #define ITM_TCR_BUSY_Pos 23
923 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
925 #define ITM_TCR_TraceBusID_Pos 16
926 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
928 #define ITM_TCR_GTSFREQ_Pos 10
929 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
931 #define ITM_TCR_TSPrescale_Pos 8
932 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
934 #define ITM_TCR_SWOENA_Pos 4
935 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
937 #define ITM_TCR_DWTENA_Pos 3
938 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
940 #define ITM_TCR_SYNCENA_Pos 2
941 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
943 #define ITM_TCR_TSENA_Pos 1
944 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
946 #define ITM_TCR_ITMENA_Pos 0
947 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos)
949 /* ITM Integration Write Register Definitions */
950 #define ITM_IWR_ATVALIDM_Pos 0
951 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos)
953 /* ITM Integration Read Register Definitions */
954 #define ITM_IRR_ATREADYM_Pos 0
955 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos)
957 /* ITM Integration Mode Control Register Definitions */
958 #define ITM_IMCR_INTEGRATION_Pos 0
959 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos)
961 /* ITM Lock Status Register Definitions */
962 #define ITM_LSR_ByteAcc_Pos 2
963 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
965 #define ITM_LSR_Access_Pos 1
966 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
968 #define ITM_LSR_Present_Pos 0
969 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos)
971  /* end of group CMSIS_ITM */
972 
973 
982 typedef struct
983 {
984  __IO uint32_t CTRL;
985  __IO uint32_t CYCCNT;
986  __IO uint32_t CPICNT;
987  __IO uint32_t EXCCNT;
988  __IO uint32_t SLEEPCNT;
989  __IO uint32_t LSUCNT;
990  __IO uint32_t FOLDCNT;
991  __I uint32_t PCSR;
992  __IO uint32_t COMP0;
993  __IO uint32_t MASK0;
994  __IO uint32_t FUNCTION0;
995  uint32_t RESERVED0[1];
996  __IO uint32_t COMP1;
997  __IO uint32_t MASK1;
998  __IO uint32_t FUNCTION1;
999  uint32_t RESERVED1[1];
1000  __IO uint32_t COMP2;
1001  __IO uint32_t MASK2;
1002  __IO uint32_t FUNCTION2;
1003  uint32_t RESERVED2[1];
1004  __IO uint32_t COMP3;
1005  __IO uint32_t MASK3;
1006  __IO uint32_t FUNCTION3;
1007  uint32_t RESERVED3[981];
1008  __O uint32_t LAR;
1009  __I uint32_t LSR;
1010 } DWT_Type;
1011 
1012 /* DWT Control Register Definitions */
1013 #define DWT_CTRL_NUMCOMP_Pos 28
1014 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1016 #define DWT_CTRL_NOTRCPKT_Pos 27
1017 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1019 #define DWT_CTRL_NOEXTTRIG_Pos 26
1020 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1022 #define DWT_CTRL_NOCYCCNT_Pos 25
1023 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1025 #define DWT_CTRL_NOPRFCNT_Pos 24
1026 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1028 #define DWT_CTRL_CYCEVTENA_Pos 22
1029 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1031 #define DWT_CTRL_FOLDEVTENA_Pos 21
1032 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1034 #define DWT_CTRL_LSUEVTENA_Pos 20
1035 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1037 #define DWT_CTRL_SLEEPEVTENA_Pos 19
1038 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1040 #define DWT_CTRL_EXCEVTENA_Pos 18
1041 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1043 #define DWT_CTRL_CPIEVTENA_Pos 17
1044 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1046 #define DWT_CTRL_EXCTRCENA_Pos 16
1047 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1049 #define DWT_CTRL_PCSAMPLENA_Pos 12
1050 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1052 #define DWT_CTRL_SYNCTAP_Pos 10
1053 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1055 #define DWT_CTRL_CYCTAP_Pos 9
1056 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1058 #define DWT_CTRL_POSTINIT_Pos 5
1059 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1061 #define DWT_CTRL_POSTPRESET_Pos 1
1062 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1064 #define DWT_CTRL_CYCCNTENA_Pos 0
1065 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
1067 /* DWT CPI Count Register Definitions */
1068 #define DWT_CPICNT_CPICNT_Pos 0
1069 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos)
1071 /* DWT Exception Overhead Count Register Definitions */
1072 #define DWT_EXCCNT_EXCCNT_Pos 0
1073 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
1075 /* DWT Sleep Count Register Definitions */
1076 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0
1077 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
1079 /* DWT LSU Count Register Definitions */
1080 #define DWT_LSUCNT_LSUCNT_Pos 0
1081 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
1083 /* DWT Folded-instruction Count Register Definitions */
1084 #define DWT_FOLDCNT_FOLDCNT_Pos 0
1085 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
1087 /* DWT Comparator Mask Register Definitions */
1088 #define DWT_MASK_MASK_Pos 0
1089 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos)
1091 /* DWT Comparator Function Register Definitions */
1092 #define DWT_FUNCTION_MATCHED_Pos 24
1093 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1095 #define DWT_FUNCTION_DATAVADDR1_Pos 16
1096 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1098 #define DWT_FUNCTION_DATAVADDR0_Pos 12
1099 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1101 #define DWT_FUNCTION_DATAVSIZE_Pos 10
1102 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1104 #define DWT_FUNCTION_LNK1ENA_Pos 9
1105 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1107 #define DWT_FUNCTION_DATAVMATCH_Pos 8
1108 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1110 #define DWT_FUNCTION_CYCMATCH_Pos 7
1111 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1113 #define DWT_FUNCTION_EMITRANGE_Pos 5
1114 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1116 #define DWT_FUNCTION_FUNCTION_Pos 0
1117 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
1119  /* end of group CMSIS_DWT */
1120 
1121 
1130 typedef struct
1131 {
1132  __IO uint32_t SSPSR;
1133  __IO uint32_t CSPSR;
1134  uint32_t RESERVED0[2];
1135  __IO uint32_t ACPR;
1136  uint32_t RESERVED1[55];
1137  __IO uint32_t SPPR;
1138  uint32_t RESERVED2[131];
1139  __I uint32_t FFSR;
1140  __IO uint32_t FFCR;
1141  __I uint32_t FSCR;
1142  uint32_t RESERVED3[759];
1143  __I uint32_t TRIGGER;
1144  __I uint32_t FIFO0;
1145  __I uint32_t ITATBCTR2;
1146  uint32_t RESERVED4[1];
1147  __I uint32_t ITATBCTR0;
1148  __I uint32_t FIFO1;
1149  __IO uint32_t ITCTRL;
1150  uint32_t RESERVED5[39];
1151  __IO uint32_t CLAIMSET;
1152  __IO uint32_t CLAIMCLR;
1153  uint32_t RESERVED7[8];
1154  __I uint32_t DEVID;
1155  __I uint32_t DEVTYPE;
1156 } TPI_Type;
1157 
1158 /* TPI Asynchronous Clock Prescaler Register Definitions */
1159 #define TPI_ACPR_PRESCALER_Pos 0
1160 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
1162 /* TPI Selected Pin Protocol Register Definitions */
1163 #define TPI_SPPR_TXMODE_Pos 0
1164 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
1166 /* TPI Formatter and Flush Status Register Definitions */
1167 #define TPI_FFSR_FtNonStop_Pos 3
1168 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1170 #define TPI_FFSR_TCPresent_Pos 2
1171 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1173 #define TPI_FFSR_FtStopped_Pos 1
1174 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1176 #define TPI_FFSR_FlInProg_Pos 0
1177 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
1179 /* TPI Formatter and Flush Control Register Definitions */
1180 #define TPI_FFCR_TrigIn_Pos 8
1181 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1183 #define TPI_FFCR_EnFCont_Pos 1
1184 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1186 /* TPI TRIGGER Register Definitions */
1187 #define TPI_TRIGGER_TRIGGER_Pos 0
1188 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
1190 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1191 #define TPI_FIFO0_ITM_ATVALID_Pos 29
1192 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1194 #define TPI_FIFO0_ITM_bytecount_Pos 27
1195 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1197 #define TPI_FIFO0_ETM_ATVALID_Pos 26
1198 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1200 #define TPI_FIFO0_ETM_bytecount_Pos 24
1201 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1203 #define TPI_FIFO0_ETM2_Pos 16
1204 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1206 #define TPI_FIFO0_ETM1_Pos 8
1207 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1209 #define TPI_FIFO0_ETM0_Pos 0
1210 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
1212 /* TPI ITATBCTR2 Register Definitions */
1213 #define TPI_ITATBCTR2_ATREADY_Pos 0
1214 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
1216 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1217 #define TPI_FIFO1_ITM_ATVALID_Pos 29
1218 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1220 #define TPI_FIFO1_ITM_bytecount_Pos 27
1221 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1223 #define TPI_FIFO1_ETM_ATVALID_Pos 26
1224 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1226 #define TPI_FIFO1_ETM_bytecount_Pos 24
1227 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1229 #define TPI_FIFO1_ITM2_Pos 16
1230 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1232 #define TPI_FIFO1_ITM1_Pos 8
1233 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1235 #define TPI_FIFO1_ITM0_Pos 0
1236 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
1238 /* TPI ITATBCTR0 Register Definitions */
1239 #define TPI_ITATBCTR0_ATREADY_Pos 0
1240 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
1242 /* TPI Integration Mode Control Register Definitions */
1243 #define TPI_ITCTRL_Mode_Pos 0
1244 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
1246 /* TPI DEVID Register Definitions */
1247 #define TPI_DEVID_NRZVALID_Pos 11
1248 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1250 #define TPI_DEVID_MANCVALID_Pos 10
1251 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1253 #define TPI_DEVID_PTINVALID_Pos 9
1254 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1256 #define TPI_DEVID_MinBufSz_Pos 6
1257 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1259 #define TPI_DEVID_AsynClkIn_Pos 5
1260 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1262 #define TPI_DEVID_NrTraceInput_Pos 0
1263 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
1265 /* TPI DEVTYPE Register Definitions */
1266 #define TPI_DEVTYPE_SubType_Pos 0
1267 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
1269 #define TPI_DEVTYPE_MajorType_Pos 4
1270 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1272  /* end of group CMSIS_TPI */
1273 
1274 
1275 #if (__MPU_PRESENT == 1)
1276 
1284 typedef struct
1285 {
1286  __I uint32_t TYPE;
1287  __IO uint32_t CTRL;
1288  __IO uint32_t RNR;
1289  __IO uint32_t RBAR;
1290  __IO uint32_t RASR;
1291  __IO uint32_t RBAR_A1;
1292  __IO uint32_t RASR_A1;
1293  __IO uint32_t RBAR_A2;
1294  __IO uint32_t RASR_A2;
1295  __IO uint32_t RBAR_A3;
1296  __IO uint32_t RASR_A3;
1297 } MPU_Type;
1298 
1299 /* MPU Type Register */
1300 #define MPU_TYPE_IREGION_Pos 16
1301 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1303 #define MPU_TYPE_DREGION_Pos 8
1304 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1306 #define MPU_TYPE_SEPARATE_Pos 0
1307 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
1309 /* MPU Control Register */
1310 #define MPU_CTRL_PRIVDEFENA_Pos 2
1311 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1313 #define MPU_CTRL_HFNMIENA_Pos 1
1314 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1316 #define MPU_CTRL_ENABLE_Pos 0
1317 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
1319 /* MPU Region Number Register */
1320 #define MPU_RNR_REGION_Pos 0
1321 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
1323 /* MPU Region Base Address Register */
1324 #define MPU_RBAR_ADDR_Pos 5
1325 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1327 #define MPU_RBAR_VALID_Pos 4
1328 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1330 #define MPU_RBAR_REGION_Pos 0
1331 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
1333 /* MPU Region Attribute and Size Register */
1334 #define MPU_RASR_ATTRS_Pos 16
1335 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1337 #define MPU_RASR_XN_Pos 28
1338 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1340 #define MPU_RASR_AP_Pos 24
1341 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1343 #define MPU_RASR_TEX_Pos 19
1344 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1346 #define MPU_RASR_S_Pos 18
1347 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1349 #define MPU_RASR_C_Pos 17
1350 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1352 #define MPU_RASR_B_Pos 16
1353 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1355 #define MPU_RASR_SRD_Pos 8
1356 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1358 #define MPU_RASR_SIZE_Pos 1
1359 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1361 #define MPU_RASR_ENABLE_Pos 0
1362 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
1364 
1365 #endif
1366 
1367 
1368 #if (__FPU_PRESENT == 1)
1369 
1377 typedef struct
1378 {
1379  uint32_t RESERVED0[1];
1380  __IO uint32_t FPCCR;
1381  __IO uint32_t FPCAR;
1382  __IO uint32_t FPDSCR;
1383  __I uint32_t MVFR0;
1384  __I uint32_t MVFR1;
1385  __I uint32_t MVFR2;
1386 } FPU_Type;
1387 
1388 /* Floating-Point Context Control Register */
1389 #define FPU_FPCCR_ASPEN_Pos 31
1390 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1392 #define FPU_FPCCR_LSPEN_Pos 30
1393 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1395 #define FPU_FPCCR_MONRDY_Pos 8
1396 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1398 #define FPU_FPCCR_BFRDY_Pos 6
1399 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1401 #define FPU_FPCCR_MMRDY_Pos 5
1402 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1404 #define FPU_FPCCR_HFRDY_Pos 4
1405 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1407 #define FPU_FPCCR_THREAD_Pos 3
1408 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1410 #define FPU_FPCCR_USER_Pos 1
1411 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1413 #define FPU_FPCCR_LSPACT_Pos 0
1414 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos)
1416 /* Floating-Point Context Address Register */
1417 #define FPU_FPCAR_ADDRESS_Pos 3
1418 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1420 /* Floating-Point Default Status Control Register */
1421 #define FPU_FPDSCR_AHP_Pos 26
1422 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1424 #define FPU_FPDSCR_DN_Pos 25
1425 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1427 #define FPU_FPDSCR_FZ_Pos 24
1428 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1430 #define FPU_FPDSCR_RMode_Pos 22
1431 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1433 /* Media and FP Feature Register 0 */
1434 #define FPU_MVFR0_FP_rounding_modes_Pos 28
1435 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1437 #define FPU_MVFR0_Short_vectors_Pos 24
1438 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1440 #define FPU_MVFR0_Square_root_Pos 20
1441 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1443 #define FPU_MVFR0_Divide_Pos 16
1444 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1446 #define FPU_MVFR0_FP_excep_trapping_Pos 12
1447 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1449 #define FPU_MVFR0_Double_precision_Pos 8
1450 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1452 #define FPU_MVFR0_Single_precision_Pos 4
1453 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1455 #define FPU_MVFR0_A_SIMD_registers_Pos 0
1456 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)
1458 /* Media and FP Feature Register 1 */
1459 #define FPU_MVFR1_FP_fused_MAC_Pos 28
1460 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1462 #define FPU_MVFR1_FP_HPFP_Pos 24
1463 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1465 #define FPU_MVFR1_D_NaN_mode_Pos 4
1466 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1468 #define FPU_MVFR1_FtZ_mode_Pos 0
1469 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos)
1471 /* Media and FP Feature Register 2 */
1472 
1474 #endif
1475 
1476 
1485 typedef struct
1486 {
1487  __IO uint32_t DHCSR;
1488  __O uint32_t DCRSR;
1489  __IO uint32_t DCRDR;
1490  __IO uint32_t DEMCR;
1491 } CoreDebug_Type;
1492 
1493 /* Debug Halting Control and Status Register */
1494 #define CoreDebug_DHCSR_DBGKEY_Pos 16
1495 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1497 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25
1498 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1500 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
1501 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1503 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19
1504 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1506 #define CoreDebug_DHCSR_S_SLEEP_Pos 18
1507 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1509 #define CoreDebug_DHCSR_S_HALT_Pos 17
1510 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1512 #define CoreDebug_DHCSR_S_REGRDY_Pos 16
1513 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1515 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
1516 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1518 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3
1519 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1521 #define CoreDebug_DHCSR_C_STEP_Pos 2
1522 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1524 #define CoreDebug_DHCSR_C_HALT_Pos 1
1525 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1527 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0
1528 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
1530 /* Debug Core Register Selector Register */
1531 #define CoreDebug_DCRSR_REGWnR_Pos 16
1532 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1534 #define CoreDebug_DCRSR_REGSEL_Pos 0
1535 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
1537 /* Debug Exception and Monitor Control Register */
1538 #define CoreDebug_DEMCR_TRCENA_Pos 24
1539 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1541 #define CoreDebug_DEMCR_MON_REQ_Pos 19
1542 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1544 #define CoreDebug_DEMCR_MON_STEP_Pos 18
1545 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1547 #define CoreDebug_DEMCR_MON_PEND_Pos 17
1548 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1550 #define CoreDebug_DEMCR_MON_EN_Pos 16
1551 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1553 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10
1554 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1556 #define CoreDebug_DEMCR_VC_INTERR_Pos 9
1557 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1559 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8
1560 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1562 #define CoreDebug_DEMCR_VC_STATERR_Pos 7
1563 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1565 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6
1566 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1568 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5
1569 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1571 #define CoreDebug_DEMCR_VC_MMERR_Pos 4
1572 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1574 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0
1575 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
1577 
1586 /* Memory mapping of Cortex-M4 Hardware */
1587 #define SCS_BASE (0xE000E000UL)
1588 #define ITM_BASE (0xE0000000UL)
1589 #define DWT_BASE (0xE0001000UL)
1590 #define TPI_BASE (0xE0040000UL)
1591 #define CoreDebug_BASE (0xE000EDF0UL)
1592 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1593 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1594 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1596 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1597 #define SCB ((SCB_Type *) SCB_BASE )
1598 #define SysTick ((SysTick_Type *) SysTick_BASE )
1599 #define NVIC ((NVIC_Type *) NVIC_BASE )
1600 #define ITM ((ITM_Type *) ITM_BASE )
1601 #define DWT ((DWT_Type *) DWT_BASE )
1602 #define TPI ((TPI_Type *) TPI_BASE )
1603 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1605 #if (__MPU_PRESENT == 1)
1606  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1607  #define MPU ((MPU_Type *) MPU_BASE )
1608 #endif
1609 
1610 #if (__FPU_PRESENT == 1)
1611  #define FPU_BASE (SCS_BASE + 0x0F30UL)
1612  #define FPU ((FPU_Type *) FPU_BASE )
1613 #endif
1614 
1619 /*******************************************************************************
1620  * Hardware Abstraction Layer
1621  Core Function Interface contains:
1622  - Core NVIC Functions
1623  - Core SysTick Functions
1624  - Core Debug Functions
1625  - Core Register Access Functions
1626  ******************************************************************************/
1632 /* ########################## NVIC functions #################################### */
1649 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1650 {
1651  uint32_t reg_value;
1652  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1653 
1654  reg_value = SCB->AIRCR; /* read old register configuration */
1655  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1656  reg_value = (reg_value |
1657  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1658  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1659  SCB->AIRCR = reg_value;
1660 }
1661 
1662 
1669 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1670 {
1671  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1672 }
1673 
1674 
1681 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1682 {
1683 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
1684  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
1685 }
1686 
1687 
1694 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1695 {
1696  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1697 }
1698 
1699 
1710 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1711 {
1712  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1713 }
1714 
1715 
1722 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1723 {
1724  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1725 }
1726 
1727 
1734 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1735 {
1736  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1737 }
1738 
1739 
1749 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1750 {
1751  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1752 }
1753 
1754 
1764 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1765 {
1766  if(IRQn < 0) {
1767  SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1768  else {
1769  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1770 }
1771 
1772 
1784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1785 {
1786 
1787  if(IRQn < 0) {
1788  return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1789  else {
1790  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1791 }
1792 
1793 
1806 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1807 {
1808  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1809  uint32_t PreemptPriorityBits;
1810  uint32_t SubPriorityBits;
1811 
1812  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1813  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1814 
1815  return (
1816  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1817  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1818  );
1819 }
1820 
1821 
1834 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1835 {
1836  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1837  uint32_t PreemptPriorityBits;
1838  uint32_t SubPriorityBits;
1839 
1840  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1841  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1842 
1843  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1844  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1845 }
1846 
1847 
1852 __STATIC_INLINE void NVIC_SystemReset(void)
1853 {
1854  __DSB(); /* Ensure all outstanding memory accesses included
1855  buffered write are completed before reset */
1856  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1857  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1858  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1859  __DSB(); /* Ensure completion of memory access */
1860  while(1); /* wait until reset */
1861 }
1862 
1866 /* ########################## Cache functions #################################### */
1873 /* Cache Size ID Register Macros */
1874 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
1875 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
1876 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )
1877 
1878 
1883 __STATIC_INLINE void SCB_EnableICache(void)
1884 {
1885  #if (__ICACHE_PRESENT == 1)
1886  __DSB();
1887  __ISB();
1888  SCB->ICIALLU = 0; // invalidate I-Cache
1889  SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache
1890  __DSB();
1891  __ISB();
1892  #endif
1893 }
1894 
1895 
1900 __STATIC_INLINE void SCB_DisableICache(void)
1901 {
1902  #if (__ICACHE_PRESENT == 1)
1903  __DSB();
1904  __ISB();
1905  SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache
1906  SCB->ICIALLU = 0; // invalidate I-Cache
1907  __DSB();
1908  __ISB();
1909  #endif
1910 }
1911 
1912 
1917 __STATIC_INLINE void SCB_InvalidateICache(void)
1918 {
1919  #if (__ICACHE_PRESENT == 1)
1920  __DSB();
1921  __ISB();
1922  SCB->ICIALLU = 0;
1923  __DSB();
1924  __ISB();
1925  #endif
1926 }
1927 
1928 
1933 __STATIC_INLINE void SCB_EnableDCache(void)
1934 {
1935  #if (__DCACHE_PRESENT == 1)
1936  uint32_t ccsidr, sshift, wshift, sw;
1937  uint32_t sets, ways;
1938 
1939  ccsidr = SCB->CCSIDR;
1940  sets = CCSIDR_SETS(ccsidr);
1941  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
1942  ways = CCSIDR_WAYS(ccsidr);
1943  wshift = __CLZ(ways) & 0x1f;
1944 
1945  __DSB();
1946 
1947  do { // invalidate D-Cache
1948  int32_t tmpways = ways;
1949  do {
1950  sw = ((tmpways << wshift) | (sets << sshift));
1951  SCB->DCISW = sw;
1952  } while(tmpways--);
1953  } while(sets--);
1954  __DSB();
1955 
1956  SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache
1957 
1958  __DSB();
1959  __ISB();
1960  #endif
1961 }
1962 
1963 
1968 __STATIC_INLINE void SCB_DisableDCache(void)
1969 {
1970  #if (__DCACHE_PRESENT == 1)
1971  uint32_t ccsidr, sshift, wshift, sw;
1972  uint32_t sets, ways;
1973 
1974  ccsidr = SCB->CCSIDR;
1975  sets = CCSIDR_SETS(ccsidr);
1976  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
1977  ways = CCSIDR_WAYS(ccsidr);
1978  wshift = __CLZ(ways) & 0x1f;
1979 
1980  __DSB();
1981 
1982  SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache
1983 
1984  do { // clean & invalidate D-Cache
1985  int32_t tmpways = ways;
1986  do {
1987  sw = ((tmpways << wshift) | (sets << sshift));
1988  SCB->DCCISW = sw;
1989  } while(tmpways--);
1990  } while(sets--);
1991 
1992 
1993  __DSB();
1994  __ISB();
1995  #endif
1996 }
1997 
1998 
2003 __STATIC_INLINE void SCB_InvalidateDCache(void)
2004 {
2005  #if (__DCACHE_PRESENT == 1)
2006  uint32_t ccsidr, sshift, wshift, sw;
2007  uint32_t sets, ways;
2008 
2009  ccsidr = SCB->CCSIDR;
2010  sets = CCSIDR_SETS(ccsidr);
2011  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
2012  ways = CCSIDR_WAYS(ccsidr);
2013  wshift = __CLZ(ways) & 0x1f;
2014 
2015  __DSB();
2016 
2017  do { // invalidate D-Cache
2018  int32_t tmpways = ways;
2019  do {
2020  sw = ((tmpways << wshift) | (sets << sshift));
2021  SCB->DCISW = sw;
2022  } while(tmpways--);
2023  } while(sets--);
2024 
2025  __DSB();
2026  __ISB();
2027  #endif
2028 }
2029 
2030 
2035 __STATIC_INLINE void SCB_CleanDCache(void)
2036 {
2037  #if (__DCACHE_PRESENT == 1)
2038  uint32_t ccsidr, sshift, wshift, sw;
2039  uint32_t sets, ways;
2040 
2041  ccsidr = SCB->CCSIDR;
2042  sets = CCSIDR_SETS(ccsidr);
2043  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
2044  ways = CCSIDR_WAYS(ccsidr);
2045  wshift = __CLZ(ways) & 0x1f;
2046 
2047  __DSB();
2048 
2049  do { // clean D-Cache
2050  int32_t tmpways = ways;
2051  do {
2052  sw = ((tmpways << wshift) | (sets << sshift));
2053  SCB->DCCSW = sw;
2054  } while(tmpways--);
2055  } while(sets--);
2056 
2057  __DSB();
2058  __ISB();
2059  #endif
2060 }
2061 
2062 
2067 __STATIC_INLINE void SCB_CleanInvalidateDCache(void)
2068 {
2069  #if (__DCACHE_PRESENT == 1)
2070  uint32_t ccsidr, sshift, wshift, sw;
2071  uint32_t sets, ways;
2072 
2073  ccsidr = SCB->CCSIDR;
2074  sets = CCSIDR_SETS(ccsidr);
2075  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
2076  ways = CCSIDR_WAYS(ccsidr);
2077  wshift = __CLZ(ways) & 0x1f;
2078 
2079  __DSB();
2080 
2081  do { // clean & invalidate D-Cache
2082  int32_t tmpways = ways;
2083  do {
2084  sw = ((tmpways << wshift) | (sets << sshift));
2085  SCB->DCCISW = sw;
2086  } while(tmpways--);
2087  } while(sets--);
2088 
2089  __DSB();
2090  __ISB();
2091  #endif
2092 }
2093 
2094 
2099 /* ################################## SysTick function ############################################ */
2106 #if (__Vendor_SysTickConfig == 0)
2107 
2123 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2124 {
2125  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
2126 
2127  SysTick->LOAD = ticks - 1; /* set reload register */
2128  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
2129  SysTick->VAL = 0; /* Load the SysTick Counter Value */
2132  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2133  return (0); /* Function successful */
2134 }
2135 
2136 #endif
2137 
2142 /* ##################################### Debug In/Output function ########################################### */
2149 extern volatile int32_t ITM_RxBuffer;
2150 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5
2163 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2164 {
2165  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
2166  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
2167  {
2168  while (ITM->PORT[0].u32 == 0);
2169  ITM->PORT[0].u8 = (uint8_t) ch;
2170  }
2171  return (ch);
2172 }
2173 
2174 
2182 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
2183  int32_t ch = -1; /* no character available */
2184 
2185  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
2186  ch = ITM_RxBuffer;
2187  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2188  }
2189 
2190  return (ch);
2191 }
2192 
2193 
2201 __STATIC_INLINE int32_t ITM_CheckChar (void) {
2202 
2203  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
2204  return (0); /* no character available */
2205  } else {
2206  return (1); /* character available */
2207  }
2208 }
2209 
2215 #ifdef __cplusplus
2216 }
2217 #endif
2218 
2219 #endif /* __CORE_CM7_H_DEPENDANT */
2220 
2221 #endif /* __CMSIS_GENERIC */
__O uint32_t DCCIMVAC
Definition: core_cm7.h:452
__O uint32_t DCISW
Definition: core_cm7.h:448
CMSIS Cortex-M Core Function Access Header File.
__STATIC_INLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: core_cm7.h:1917
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
__STATIC_INLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: core_cm7.h:1968
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm7.h:516
__IO uint32_t ABFSR
Definition: core_cm7.h:461
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:309
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
__IO uint32_t CACR
Definition: core_cm7.h:458
#define SCB_CCR_IC_Msk
Definition: core_cm7.h:552
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm7.h:844
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:334
#define ITM
Definition: core_cm7.h:1600
Structure type to access the Data Watchpoint and Trace Register (DWT).
CMSIS Cortex-M Core Instruction Access Header File.
__I uint32_t MVFR2
Definition: core_cm7.h:442
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:186
#define __IO
Definition: core_cm7.h:264
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
#define ITM_RXBUFFER_EMPTY
Definition: core_cm7.h:2150
__O uint32_t DCCISW
Definition: core_cm7.h:453
__I uint32_t ID_DFR
Definition: core_cm7.h:427
#define __O
Definition: core_cm7.h:263
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:611
__O uint32_t DCIMVAU
Definition: core_cm7.h:447
__STATIC_INLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: core_cm7.h:1933
__IO uint32_t CSSELR
Definition: core_cm7.h:435
__IO uint32_t ITCMCR
Definition: core_cm7.h:455
__STATIC_INLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: core_cm7.h:1900
volatile int32_t ITM_RxBuffer
__IO uint32_t AHBSCR
Definition: core_cm7.h:459
__I uint32_t MVFR0
Definition: core_cm7.h:440
__STATIC_INLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: core_cm7.h:1883
__I uint32_t ID_AFR
Definition: core_cm7.h:428
__O uint32_t ICIALLU
Definition: core_cm7.h:444
__STATIC_INLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: core_cm7.h:2003
__O uint32_t DCCMVAU
Definition: core_cm7.h:449
__O uint32_t STIR
Definition: core_cm7.h:438
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm7.h:847
#define SCB
Definition: core_cm7.h:1597
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:556
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:439
Structure type to access the Core Debug Register (CoreDebug).
CMSIS Cortex-M SIMD Header File.
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:647
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:224
__I uint32_t CLIDR
Definition: core_cm7.h:432
__I uint32_t CTR
Definition: core_cm7.h:433
__I uint32_t MVFR1
Definition: core_cm7.h:441
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:544
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm7.h:517
#define CCSIDR_WAYS(x)
Definition: core_cm7.h:1874
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:572
__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: core_cm7.h:2067
#define SysTick
Definition: core_cm7.h:1598
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm7.h:526
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:685
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:286
Structure type to access the Trace Port Interface Register (TPI).
#define NVIC
Definition: core_cm7.h:1599
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm7.h:854
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode Priority.
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:584
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:596
__I uint32_t LSR
Definition: core_cm7.h:1009
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:247
__IO uint32_t AHBPCR
Definition: core_cm7.h:457
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:260
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:633
__O uint32_t ICIMVAU
Definition: core_cm7.h:446
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm7.h:850
__STATIC_INLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: core_cm7.h:2035
#define SCB_CCR_DC_Msk
Definition: core_cm7.h:555
#define CCSIDR_LSSHIFT(x)
Definition: core_cm7.h:1876
uint16_t u16
Definition: stm32f4xx.h:691
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
__I uint32_t CCSIDR
Definition: core_cm7.h:434
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
__O uint32_t DCCMVAC
Definition: core_cm7.h:450
#define CCSIDR_SETS(x)
Definition: core_cm7.h:1875
#define __NVIC_PRIO_BITS
Definition: stm32f4xx.h:178
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
uint32_t u32
Definition: stm32f4xx.h:690
#define ITM_TCR_ITMENA_Msk
Definition: core_cm7.h:947
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm7.h:529
__IO uint32_t DTCMCR
Definition: core_cm7.h:456
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
__O uint32_t DCCSW
Definition: core_cm7.h:451
uint8_t u8
Definition: stm32f4xx.h:692
#define __I
Definition: core_cm7.h:261
__O uint32_t LAR
Definition: core_cm7.h:1008
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm7.h:525


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:18