38 #if defined ( __ICCARM__ ) 39 #pragma system_include 42 #ifndef __CORE_CM3_H_GENERIC 43 #define __CORE_CM3_H_GENERIC 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) 72 #define __CM3_CMSIS_VERSION_SUB (0x00) 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ 74 __CM3_CMSIS_VERSION_SUB ) 76 #define __CORTEX_M (0x03) 79 #if defined ( __CC_ARM ) 81 #define __INLINE __inline 82 #define __STATIC_INLINE static __inline 84 #elif defined ( __GNUC__ ) 86 #define __INLINE inline 87 #define __STATIC_INLINE static inline 89 #elif defined ( __ICCARM__ ) 91 #define __INLINE inline 92 #define __STATIC_INLINE static inline 94 #elif defined ( __TMS470__ ) 96 #define __STATIC_INLINE static inline 98 #elif defined ( __TASKING__ ) 100 #define __INLINE inline 101 #define __STATIC_INLINE static inline 103 #elif defined ( __CSMC__ ) 106 #define __INLINE inline 107 #define __STATIC_INLINE static inline 116 #if defined ( __CC_ARM ) 117 #if defined __TARGET_FPU_VFP 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 121 #elif defined ( __GNUC__ ) 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 126 #elif defined ( __ICCARM__ ) 127 #if defined __ARMVFP__ 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 131 #elif defined ( __TMS470__ ) 132 #if defined __TI__VFP_SUPPORT____ 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 136 #elif defined ( __TASKING__ ) 137 #if defined __FPU_VFP__ 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 141 #elif defined ( __CSMC__ ) 142 #if ( __CSMC__ & 0x400) // FPU present for parser 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 157 #ifndef __CMSIS_GENERIC 159 #ifndef __CORE_CM3_H_DEPENDANT 160 #define __CORE_CM3_H_DEPENDANT 167 #if defined __CHECK_DEVICE_DEFINES 169 #define __CM3_REV 0x0200 170 #warning "__CM3_REV not defined in device header file; using default!" 173 #ifndef __MPU_PRESENT 174 #define __MPU_PRESENT 0 175 #warning "__MPU_PRESENT not defined in device header file; using default!" 178 #ifndef __NVIC_PRIO_BITS 179 #define __NVIC_PRIO_BITS 4 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 183 #ifndef __Vendor_SysTickConfig 184 #define __Vendor_SysTickConfig 0 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 200 #define __I volatile const 203 #define __IO volatile 235 #if (__CORTEX_M != 0x04) 236 uint32_t _reserved0:27;
238 uint32_t _reserved0:16;
240 uint32_t _reserved1:7;
259 uint32_t _reserved0:23;
272 #if (__CORTEX_M != 0x04) 273 uint32_t _reserved0:15;
275 uint32_t _reserved0:7;
277 uint32_t _reserved1:4;
300 uint32_t _reserved0:29;
318 __IO uint32_t ISER[8];
319 uint32_t RESERVED0[24];
320 __IO uint32_t ICER[8];
321 uint32_t RSERVED1[24];
322 __IO uint32_t ISPR[8];
323 uint32_t RESERVED2[24];
324 __IO uint32_t ICPR[8];
325 uint32_t RESERVED3[24];
327 uint32_t RESERVED4[56];
329 uint32_t RESERVED5[644];
334 #define NVIC_STIR_INTID_Pos 0 335 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) 369 uint32_t RESERVED0[5];
374 #define SCB_CPUID_IMPLEMENTER_Pos 24 375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) 377 #define SCB_CPUID_VARIANT_Pos 20 378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) 380 #define SCB_CPUID_ARCHITECTURE_Pos 16 381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) 383 #define SCB_CPUID_PARTNO_Pos 4 384 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) 386 #define SCB_CPUID_REVISION_Pos 0 387 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) 390 #define SCB_ICSR_NMIPENDSET_Pos 31 391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) 393 #define SCB_ICSR_PENDSVSET_Pos 28 394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) 396 #define SCB_ICSR_PENDSVCLR_Pos 27 397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) 399 #define SCB_ICSR_PENDSTSET_Pos 26 400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) 402 #define SCB_ICSR_PENDSTCLR_Pos 25 403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) 405 #define SCB_ICSR_ISRPREEMPT_Pos 23 406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) 408 #define SCB_ICSR_ISRPENDING_Pos 22 409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) 411 #define SCB_ICSR_VECTPENDING_Pos 12 412 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) 414 #define SCB_ICSR_RETTOBASE_Pos 11 415 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) 417 #define SCB_ICSR_VECTACTIVE_Pos 0 418 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) 421 #if (__CM3_REV < 0x0201) 422 #define SCB_VTOR_TBLBASE_Pos 29 423 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) 425 #define SCB_VTOR_TBLOFF_Pos 7 426 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) 428 #define SCB_VTOR_TBLOFF_Pos 7 429 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) 433 #define SCB_AIRCR_VECTKEY_Pos 16 434 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) 436 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 437 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) 439 #define SCB_AIRCR_ENDIANESS_Pos 15 440 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) 442 #define SCB_AIRCR_PRIGROUP_Pos 8 443 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) 445 #define SCB_AIRCR_SYSRESETREQ_Pos 2 446 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) 448 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 449 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) 451 #define SCB_AIRCR_VECTRESET_Pos 0 452 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) 455 #define SCB_SCR_SEVONPEND_Pos 4 456 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) 458 #define SCB_SCR_SLEEPDEEP_Pos 2 459 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) 461 #define SCB_SCR_SLEEPONEXIT_Pos 1 462 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) 465 #define SCB_CCR_STKALIGN_Pos 9 466 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) 468 #define SCB_CCR_BFHFNMIGN_Pos 8 469 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) 471 #define SCB_CCR_DIV_0_TRP_Pos 4 472 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) 474 #define SCB_CCR_UNALIGN_TRP_Pos 3 475 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) 477 #define SCB_CCR_USERSETMPEND_Pos 1 478 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) 480 #define SCB_CCR_NONBASETHRDENA_Pos 0 481 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) 484 #define SCB_SHCSR_USGFAULTENA_Pos 18 485 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) 487 #define SCB_SHCSR_BUSFAULTENA_Pos 17 488 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) 490 #define SCB_SHCSR_MEMFAULTENA_Pos 16 491 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) 493 #define SCB_SHCSR_SVCALLPENDED_Pos 15 494 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) 496 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 497 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) 499 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 500 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) 502 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 503 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) 505 #define SCB_SHCSR_SYSTICKACT_Pos 11 506 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) 508 #define SCB_SHCSR_PENDSVACT_Pos 10 509 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) 511 #define SCB_SHCSR_MONITORACT_Pos 8 512 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) 514 #define SCB_SHCSR_SVCALLACT_Pos 7 515 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) 517 #define SCB_SHCSR_USGFAULTACT_Pos 3 518 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) 520 #define SCB_SHCSR_BUSFAULTACT_Pos 1 521 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) 523 #define SCB_SHCSR_MEMFAULTACT_Pos 0 524 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) 527 #define SCB_CFSR_USGFAULTSR_Pos 16 528 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) 530 #define SCB_CFSR_BUSFAULTSR_Pos 8 531 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) 533 #define SCB_CFSR_MEMFAULTSR_Pos 0 534 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) 537 #define SCB_HFSR_DEBUGEVT_Pos 31 538 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) 540 #define SCB_HFSR_FORCED_Pos 30 541 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) 543 #define SCB_HFSR_VECTTBL_Pos 1 544 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) 547 #define SCB_DFSR_EXTERNAL_Pos 4 548 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) 550 #define SCB_DFSR_VCATCH_Pos 3 551 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) 553 #define SCB_DFSR_DWTTRAP_Pos 2 554 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) 556 #define SCB_DFSR_BKPT_Pos 1 557 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) 559 #define SCB_DFSR_HALTED_Pos 0 560 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) 575 uint32_t RESERVED0[1];
577 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) 580 uint32_t RESERVED1[1];
585 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 586 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) 590 #define SCnSCB_ACTLR_DISFOLD_Pos 2 591 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) 593 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 594 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) 596 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 597 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) 619 #define SysTick_CTRL_COUNTFLAG_Pos 16 620 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) 622 #define SysTick_CTRL_CLKSOURCE_Pos 2 623 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) 625 #define SysTick_CTRL_TICKINT_Pos 1 626 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) 628 #define SysTick_CTRL_ENABLE_Pos 0 629 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) 632 #define SysTick_LOAD_RELOAD_Pos 0 633 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) 636 #define SysTick_VAL_CURRENT_Pos 0 637 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) 640 #define SysTick_CALIB_NOREF_Pos 31 641 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) 643 #define SysTick_CALIB_SKEW_Pos 30 644 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) 646 #define SysTick_CALIB_TENMS_Pos 0 647 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) 668 uint32_t RESERVED0[864];
670 uint32_t RESERVED1[15];
672 uint32_t RESERVED2[15];
674 uint32_t RESERVED3[29];
678 uint32_t RESERVED4[43];
681 uint32_t RESERVED5[6];
697 #define ITM_TPR_PRIVMASK_Pos 0 698 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) 701 #define ITM_TCR_BUSY_Pos 23 702 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) 704 #define ITM_TCR_TraceBusID_Pos 16 705 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) 707 #define ITM_TCR_GTSFREQ_Pos 10 708 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) 710 #define ITM_TCR_TSPrescale_Pos 8 711 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) 713 #define ITM_TCR_SWOENA_Pos 4 714 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) 716 #define ITM_TCR_DWTENA_Pos 3 717 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) 719 #define ITM_TCR_SYNCENA_Pos 2 720 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) 722 #define ITM_TCR_TSENA_Pos 1 723 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) 725 #define ITM_TCR_ITMENA_Pos 0 726 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) 729 #define ITM_IWR_ATVALIDM_Pos 0 730 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) 733 #define ITM_IRR_ATREADYM_Pos 0 734 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) 737 #define ITM_IMCR_INTEGRATION_Pos 0 738 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) 741 #define ITM_LSR_ByteAcc_Pos 2 742 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) 744 #define ITM_LSR_Access_Pos 1 745 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) 747 #define ITM_LSR_Present_Pos 0 748 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) 774 uint32_t RESERVED0[1];
778 uint32_t RESERVED1[1];
782 uint32_t RESERVED2[1];
789 #define DWT_CTRL_NUMCOMP_Pos 28 790 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) 792 #define DWT_CTRL_NOTRCPKT_Pos 27 793 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) 795 #define DWT_CTRL_NOEXTTRIG_Pos 26 796 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) 798 #define DWT_CTRL_NOCYCCNT_Pos 25 799 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) 801 #define DWT_CTRL_NOPRFCNT_Pos 24 802 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) 804 #define DWT_CTRL_CYCEVTENA_Pos 22 805 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) 807 #define DWT_CTRL_FOLDEVTENA_Pos 21 808 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) 810 #define DWT_CTRL_LSUEVTENA_Pos 20 811 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) 813 #define DWT_CTRL_SLEEPEVTENA_Pos 19 814 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) 816 #define DWT_CTRL_EXCEVTENA_Pos 18 817 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) 819 #define DWT_CTRL_CPIEVTENA_Pos 17 820 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) 822 #define DWT_CTRL_EXCTRCENA_Pos 16 823 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) 825 #define DWT_CTRL_PCSAMPLENA_Pos 12 826 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) 828 #define DWT_CTRL_SYNCTAP_Pos 10 829 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) 831 #define DWT_CTRL_CYCTAP_Pos 9 832 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) 834 #define DWT_CTRL_POSTINIT_Pos 5 835 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) 837 #define DWT_CTRL_POSTPRESET_Pos 1 838 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) 840 #define DWT_CTRL_CYCCNTENA_Pos 0 841 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) 844 #define DWT_CPICNT_CPICNT_Pos 0 845 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) 848 #define DWT_EXCCNT_EXCCNT_Pos 0 849 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) 852 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 853 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) 856 #define DWT_LSUCNT_LSUCNT_Pos 0 857 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) 860 #define DWT_FOLDCNT_FOLDCNT_Pos 0 861 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) 864 #define DWT_MASK_MASK_Pos 0 865 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) 868 #define DWT_FUNCTION_MATCHED_Pos 24 869 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) 871 #define DWT_FUNCTION_DATAVADDR1_Pos 16 872 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) 874 #define DWT_FUNCTION_DATAVADDR0_Pos 12 875 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) 877 #define DWT_FUNCTION_DATAVSIZE_Pos 10 878 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) 880 #define DWT_FUNCTION_LNK1ENA_Pos 9 881 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) 883 #define DWT_FUNCTION_DATAVMATCH_Pos 8 884 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) 886 #define DWT_FUNCTION_CYCMATCH_Pos 7 887 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) 889 #define DWT_FUNCTION_EMITRANGE_Pos 5 890 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) 892 #define DWT_FUNCTION_FUNCTION_Pos 0 893 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) 910 uint32_t RESERVED0[2];
912 uint32_t RESERVED1[55];
914 uint32_t RESERVED2[131];
918 uint32_t RESERVED3[759];
922 uint32_t RESERVED4[1];
926 uint32_t RESERVED5[39];
929 uint32_t RESERVED7[8];
935 #define TPI_ACPR_PRESCALER_Pos 0 936 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) 939 #define TPI_SPPR_TXMODE_Pos 0 940 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) 943 #define TPI_FFSR_FtNonStop_Pos 3 944 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) 946 #define TPI_FFSR_TCPresent_Pos 2 947 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) 949 #define TPI_FFSR_FtStopped_Pos 1 950 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) 952 #define TPI_FFSR_FlInProg_Pos 0 953 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) 956 #define TPI_FFCR_TrigIn_Pos 8 957 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) 959 #define TPI_FFCR_EnFCont_Pos 1 960 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) 963 #define TPI_TRIGGER_TRIGGER_Pos 0 964 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) 967 #define TPI_FIFO0_ITM_ATVALID_Pos 29 968 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) 970 #define TPI_FIFO0_ITM_bytecount_Pos 27 971 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) 973 #define TPI_FIFO0_ETM_ATVALID_Pos 26 974 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) 976 #define TPI_FIFO0_ETM_bytecount_Pos 24 977 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) 979 #define TPI_FIFO0_ETM2_Pos 16 980 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) 982 #define TPI_FIFO0_ETM1_Pos 8 983 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) 985 #define TPI_FIFO0_ETM0_Pos 0 986 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) 989 #define TPI_ITATBCTR2_ATREADY_Pos 0 990 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) 993 #define TPI_FIFO1_ITM_ATVALID_Pos 29 994 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) 996 #define TPI_FIFO1_ITM_bytecount_Pos 27 997 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) 999 #define TPI_FIFO1_ETM_ATVALID_Pos 26 1000 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) 1002 #define TPI_FIFO1_ETM_bytecount_Pos 24 1003 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) 1005 #define TPI_FIFO1_ITM2_Pos 16 1006 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) 1008 #define TPI_FIFO1_ITM1_Pos 8 1009 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) 1011 #define TPI_FIFO1_ITM0_Pos 0 1012 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) 1015 #define TPI_ITATBCTR0_ATREADY_Pos 0 1016 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) 1019 #define TPI_ITCTRL_Mode_Pos 0 1020 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) 1023 #define TPI_DEVID_NRZVALID_Pos 11 1024 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) 1026 #define TPI_DEVID_MANCVALID_Pos 10 1027 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) 1029 #define TPI_DEVID_PTINVALID_Pos 9 1030 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) 1032 #define TPI_DEVID_MinBufSz_Pos 6 1033 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) 1035 #define TPI_DEVID_AsynClkIn_Pos 5 1036 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) 1038 #define TPI_DEVID_NrTraceInput_Pos 0 1039 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) 1042 #define TPI_DEVTYPE_SubType_Pos 0 1043 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) 1045 #define TPI_DEVTYPE_MajorType_Pos 4 1046 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) 1051 #if (__MPU_PRESENT == 1) 1067 __IO uint32_t RBAR_A1;
1068 __IO uint32_t RASR_A1;
1069 __IO uint32_t RBAR_A2;
1070 __IO uint32_t RASR_A2;
1071 __IO uint32_t RBAR_A3;
1072 __IO uint32_t RASR_A3;
1076 #define MPU_TYPE_IREGION_Pos 16 1077 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) 1079 #define MPU_TYPE_DREGION_Pos 8 1080 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) 1082 #define MPU_TYPE_SEPARATE_Pos 0 1083 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) 1086 #define MPU_CTRL_PRIVDEFENA_Pos 2 1087 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) 1089 #define MPU_CTRL_HFNMIENA_Pos 1 1090 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) 1092 #define MPU_CTRL_ENABLE_Pos 0 1093 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) 1096 #define MPU_RNR_REGION_Pos 0 1097 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) 1100 #define MPU_RBAR_ADDR_Pos 5 1101 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) 1103 #define MPU_RBAR_VALID_Pos 4 1104 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) 1106 #define MPU_RBAR_REGION_Pos 0 1107 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) 1110 #define MPU_RASR_ATTRS_Pos 16 1111 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) 1113 #define MPU_RASR_XN_Pos 28 1114 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) 1116 #define MPU_RASR_AP_Pos 24 1117 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) 1119 #define MPU_RASR_TEX_Pos 19 1120 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) 1122 #define MPU_RASR_S_Pos 18 1123 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) 1125 #define MPU_RASR_C_Pos 17 1126 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) 1128 #define MPU_RASR_B_Pos 16 1129 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) 1131 #define MPU_RASR_SRD_Pos 8 1132 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) 1134 #define MPU_RASR_SIZE_Pos 1 1135 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) 1137 #define MPU_RASR_ENABLE_Pos 0 1138 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) 1161 #define CoreDebug_DHCSR_DBGKEY_Pos 16 1162 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) 1164 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 1165 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) 1167 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 1168 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) 1170 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 1171 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) 1173 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 1174 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) 1176 #define CoreDebug_DHCSR_S_HALT_Pos 17 1177 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) 1179 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 1180 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) 1182 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 1183 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) 1185 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 1186 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) 1188 #define CoreDebug_DHCSR_C_STEP_Pos 2 1189 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) 1191 #define CoreDebug_DHCSR_C_HALT_Pos 1 1192 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) 1194 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 1195 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) 1198 #define CoreDebug_DCRSR_REGWnR_Pos 16 1199 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) 1201 #define CoreDebug_DCRSR_REGSEL_Pos 0 1202 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) 1205 #define CoreDebug_DEMCR_TRCENA_Pos 24 1206 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) 1208 #define CoreDebug_DEMCR_MON_REQ_Pos 19 1209 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) 1211 #define CoreDebug_DEMCR_MON_STEP_Pos 18 1212 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) 1214 #define CoreDebug_DEMCR_MON_PEND_Pos 17 1215 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) 1217 #define CoreDebug_DEMCR_MON_EN_Pos 16 1218 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) 1220 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 1221 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) 1223 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 1224 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) 1226 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 1227 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) 1229 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 1230 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) 1232 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 1233 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) 1235 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 1236 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) 1238 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 1239 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) 1241 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 1242 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) 1254 #define SCS_BASE (0xE000E000UL) 1255 #define ITM_BASE (0xE0000000UL) 1256 #define DWT_BASE (0xE0001000UL) 1257 #define TPI_BASE (0xE0040000UL) 1258 #define CoreDebug_BASE (0xE000EDF0UL) 1259 #define SysTick_BASE (SCS_BASE + 0x0010UL) 1260 #define NVIC_BASE (SCS_BASE + 0x0100UL) 1261 #define SCB_BASE (SCS_BASE + 0x0D00UL) 1263 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) 1264 #define SCB ((SCB_Type *) SCB_BASE ) 1265 #define SysTick ((SysTick_Type *) SysTick_BASE ) 1266 #define NVIC ((NVIC_Type *) NVIC_BASE ) 1267 #define ITM ((ITM_Type *) ITM_BASE ) 1268 #define DWT ((DWT_Type *) DWT_BASE ) 1269 #define TPI ((TPI_Type *) TPI_BASE ) 1270 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) 1272 #if (__MPU_PRESENT == 1) 1273 #define MPU_BASE (SCS_BASE + 0x0D90UL) 1274 #define MPU ((MPU_Type *) MPU_BASE ) 1314 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);
1316 reg_value =
SCB->AIRCR;
1318 reg_value = (reg_value |
1320 (PriorityGroupTmp << 8));
1321 SCB->AIRCR = reg_value;
1345 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(
IRQn) & 0x1F));
1357 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(
IRQn) & 0x1F));
1373 return((uint32_t) ((
NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
1385 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(
IRQn) & 0x1F));
1397 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(
IRQn) & 0x1F));
1412 return((uint32_t)((
NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
1467 __STATIC_INLINE uint32_t
NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1469 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);
1470 uint32_t PreemptPriorityBits;
1471 uint32_t SubPriorityBits;
1477 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1478 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1495 __STATIC_INLINE
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1497 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);
1498 uint32_t PreemptPriorityBits;
1499 uint32_t SubPriorityBits;
1504 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1505 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1535 #if (__Vendor_SysTickConfig == 0) 1579 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 1592 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 1595 (
ITM->TER & (1UL << 0) ) )
1597 while (
ITM->PORT[0].u32 == 0);
1598 ITM->PORT[0].u8 = (uint8_t) ch;
CMSIS Cortex-M Core Function Access Header File.
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
#define SCB_AIRCR_VECTKEY_Pos
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
#define SysTick_CTRL_CLKSOURCE_Msk
Structure type to access the System Control Block (SCB).
Structure type to access the Data Watchpoint and Trace Register (DWT).
CMSIS Cortex-M Core Instruction Access Header File.
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
#define ITM_RXBUFFER_EMPTY
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
volatile int32_t ITM_RxBuffer
#define SysTick_CTRL_TICKINT_Msk
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Structure type to access the System Timer (SysTick).
Structure type to access the Core Debug Register (CoreDebug).
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Union type to access the Application Program Status Register (APSR).
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
#define SCB_AIRCR_VECTKEY_Msk
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
#define SCB_AIRCR_PRIGROUP_Msk
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Union type to access the Control Registers (CONTROL).
Structure type to access the Trace Port Interface Register (TPI).
#define SysTick_LOAD_RELOAD_Msk
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode Priority.
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Union type to access the Interrupt Program Status Register (IPSR).
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Union type to access the Special-Purpose Program Status Registers (xPSR).
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
#define SysTick_CTRL_ENABLE_Msk
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
#define ITM_TCR_ITMENA_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
#define SCB_AIRCR_PRIGROUP_Pos