airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h
Go to the documentation of this file.
1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_CM3_H_GENERIC
43 #define __CORE_CM3_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
63 /*******************************************************************************
64  * CMSIS definitions
65  ******************************************************************************/
70 /* CMSIS CM3 definitions */
71 #define __CM3_CMSIS_VERSION_MAIN (0x04)
72 #define __CM3_CMSIS_VERSION_SUB (0x00)
73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
74  __CM3_CMSIS_VERSION_SUB )
76 #define __CORTEX_M (0x03)
79 #if defined ( __CC_ARM )
80  #define __ASM __asm
81  #define __INLINE __inline
82  #define __STATIC_INLINE static __inline
83 
84 #elif defined ( __GNUC__ )
85  #define __ASM __asm
86  #define __INLINE inline
87  #define __STATIC_INLINE static inline
88 
89 #elif defined ( __ICCARM__ )
90  #define __ASM __asm
91  #define __INLINE inline
92  #define __STATIC_INLINE static inline
93 
94 #elif defined ( __TMS470__ )
95  #define __ASM __asm
96  #define __STATIC_INLINE static inline
97 
98 #elif defined ( __TASKING__ )
99  #define __ASM __asm
100  #define __INLINE inline
101  #define __STATIC_INLINE static inline
102 
103 #elif defined ( __CSMC__ )
104  #define __packed
105  #define __ASM _asm
106  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107  #define __STATIC_INLINE static inline
108 
109 #endif
110 
114 #define __FPU_USED 0
115 
116 #if defined ( __CC_ARM )
117  #if defined __TARGET_FPU_VFP
118  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119  #endif
120 
121 #elif defined ( __GNUC__ )
122  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124  #endif
125 
126 #elif defined ( __ICCARM__ )
127  #if defined __ARMVFP__
128  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined ( __TMS470__ )
132  #if defined __TI__VFP_SUPPORT____
133  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __TASKING__ )
137  #if defined __FPU_VFP__
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __CSMC__ ) /* Cosmic */
142  #if ( __CSMC__ & 0x400) // FPU present for parser
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 #endif
146 
147 #include <stdint.h> /* standard types definitions */
148 #include <core_cmInstr.h> /* Core Instruction Access */
149 #include <core_cmFunc.h> /* Core Function Access */
150 
151 #ifdef __cplusplus
152 }
153 #endif
154 
155 #endif /* __CORE_CM3_H_GENERIC */
156 
157 #ifndef __CMSIS_GENERIC
158 
159 #ifndef __CORE_CM3_H_DEPENDANT
160 #define __CORE_CM3_H_DEPENDANT
161 
162 #ifdef __cplusplus
163  extern "C" {
164 #endif
165 
166 /* check device defines and use defaults */
167 #if defined __CHECK_DEVICE_DEFINES
168  #ifndef __CM3_REV
169  #define __CM3_REV 0x0200
170  #warning "__CM3_REV not defined in device header file; using default!"
171  #endif
172 
173  #ifndef __MPU_PRESENT
174  #define __MPU_PRESENT 0
175  #warning "__MPU_PRESENT not defined in device header file; using default!"
176  #endif
177 
178  #ifndef __NVIC_PRIO_BITS
179  #define __NVIC_PRIO_BITS 4
180  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
181  #endif
182 
183  #ifndef __Vendor_SysTickConfig
184  #define __Vendor_SysTickConfig 0
185  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
186  #endif
187 #endif
188 
189 /* IO definitions (access restrictions to peripheral registers) */
197 #ifdef __cplusplus
198  #define __I volatile
199 #else
200  #define __I volatile const
201 #endif
202 #define __O volatile
203 #define __IO volatile
205 
209 /*******************************************************************************
210  * Register Abstraction
211  Core Register contain:
212  - Core Register
213  - Core NVIC Register
214  - Core SCB Register
215  - Core SysTick Register
216  - Core Debug Register
217  - Core MPU Register
218  ******************************************************************************/
219 
231 typedef union
232 {
233  struct
234  {
235 #if (__CORTEX_M != 0x04)
236  uint32_t _reserved0:27;
237 #else
238  uint32_t _reserved0:16;
239  uint32_t GE:4;
240  uint32_t _reserved1:7;
241 #endif
242  uint32_t Q:1;
243  uint32_t V:1;
244  uint32_t C:1;
245  uint32_t Z:1;
246  uint32_t N:1;
247  } b;
248  uint32_t w;
249 } APSR_Type;
250 
251 
254 typedef union
255 {
256  struct
257  {
258  uint32_t ISR:9;
259  uint32_t _reserved0:23;
260  } b;
261  uint32_t w;
262 } IPSR_Type;
263 
264 
267 typedef union
268 {
269  struct
270  {
271  uint32_t ISR:9;
272 #if (__CORTEX_M != 0x04)
273  uint32_t _reserved0:15;
274 #else
275  uint32_t _reserved0:7;
276  uint32_t GE:4;
277  uint32_t _reserved1:4;
278 #endif
279  uint32_t T:1;
280  uint32_t IT:2;
281  uint32_t Q:1;
282  uint32_t V:1;
283  uint32_t C:1;
284  uint32_t Z:1;
285  uint32_t N:1;
286  } b;
287  uint32_t w;
288 } xPSR_Type;
289 
290 
293 typedef union
294 {
295  struct
296  {
297  uint32_t nPRIV:1;
298  uint32_t SPSEL:1;
299  uint32_t FPCA:1;
300  uint32_t _reserved0:29;
301  } b;
302  uint32_t w;
303 } CONTROL_Type;
304 
316 typedef struct
317 {
318  __IO uint32_t ISER[8];
319  uint32_t RESERVED0[24];
320  __IO uint32_t ICER[8];
321  uint32_t RSERVED1[24];
322  __IO uint32_t ISPR[8];
323  uint32_t RESERVED2[24];
324  __IO uint32_t ICPR[8];
325  uint32_t RESERVED3[24];
326  __IO uint32_t IABR[8];
327  uint32_t RESERVED4[56];
328  __IO uint8_t IP[240];
329  uint32_t RESERVED5[644];
330  __O uint32_t STIR;
331 } NVIC_Type;
332 
333 /* Software Triggered Interrupt Register Definitions */
334 #define NVIC_STIR_INTID_Pos 0
335 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
337 
348 typedef struct
349 {
350  __I uint32_t CPUID;
351  __IO uint32_t ICSR;
352  __IO uint32_t VTOR;
353  __IO uint32_t AIRCR;
354  __IO uint32_t SCR;
355  __IO uint32_t CCR;
356  __IO uint8_t SHP[12];
357  __IO uint32_t SHCSR;
358  __IO uint32_t CFSR;
359  __IO uint32_t HFSR;
360  __IO uint32_t DFSR;
361  __IO uint32_t MMFAR;
362  __IO uint32_t BFAR;
363  __IO uint32_t AFSR;
364  __I uint32_t PFR[2];
365  __I uint32_t DFR;
366  __I uint32_t ADR;
367  __I uint32_t MMFR[4];
368  __I uint32_t ISAR[5];
369  uint32_t RESERVED0[5];
370  __IO uint32_t CPACR;
371 } SCB_Type;
372 
373 /* SCB CPUID Register Definitions */
374 #define SCB_CPUID_IMPLEMENTER_Pos 24
375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
377 #define SCB_CPUID_VARIANT_Pos 20
378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
380 #define SCB_CPUID_ARCHITECTURE_Pos 16
381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
383 #define SCB_CPUID_PARTNO_Pos 4
384 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
386 #define SCB_CPUID_REVISION_Pos 0
387 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
389 /* SCB Interrupt Control State Register Definitions */
390 #define SCB_ICSR_NMIPENDSET_Pos 31
391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
393 #define SCB_ICSR_PENDSVSET_Pos 28
394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
396 #define SCB_ICSR_PENDSVCLR_Pos 27
397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
399 #define SCB_ICSR_PENDSTSET_Pos 26
400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
402 #define SCB_ICSR_PENDSTCLR_Pos 25
403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
405 #define SCB_ICSR_ISRPREEMPT_Pos 23
406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
408 #define SCB_ICSR_ISRPENDING_Pos 22
409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
411 #define SCB_ICSR_VECTPENDING_Pos 12
412 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
414 #define SCB_ICSR_RETTOBASE_Pos 11
415 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
417 #define SCB_ICSR_VECTACTIVE_Pos 0
418 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
420 /* SCB Vector Table Offset Register Definitions */
421 #if (__CM3_REV < 0x0201) /* core r2p1 */
422 #define SCB_VTOR_TBLBASE_Pos 29
423 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
425 #define SCB_VTOR_TBLOFF_Pos 7
426 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
427 #else
428 #define SCB_VTOR_TBLOFF_Pos 7
429 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
430 #endif
431 
432 /* SCB Application Interrupt and Reset Control Register Definitions */
433 #define SCB_AIRCR_VECTKEY_Pos 16
434 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
436 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
437 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
439 #define SCB_AIRCR_ENDIANESS_Pos 15
440 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
442 #define SCB_AIRCR_PRIGROUP_Pos 8
443 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
445 #define SCB_AIRCR_SYSRESETREQ_Pos 2
446 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
448 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
449 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
451 #define SCB_AIRCR_VECTRESET_Pos 0
452 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
454 /* SCB System Control Register Definitions */
455 #define SCB_SCR_SEVONPEND_Pos 4
456 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
458 #define SCB_SCR_SLEEPDEEP_Pos 2
459 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
461 #define SCB_SCR_SLEEPONEXIT_Pos 1
462 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
464 /* SCB Configuration Control Register Definitions */
465 #define SCB_CCR_STKALIGN_Pos 9
466 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
468 #define SCB_CCR_BFHFNMIGN_Pos 8
469 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
471 #define SCB_CCR_DIV_0_TRP_Pos 4
472 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
474 #define SCB_CCR_UNALIGN_TRP_Pos 3
475 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
477 #define SCB_CCR_USERSETMPEND_Pos 1
478 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
480 #define SCB_CCR_NONBASETHRDENA_Pos 0
481 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
483 /* SCB System Handler Control and State Register Definitions */
484 #define SCB_SHCSR_USGFAULTENA_Pos 18
485 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
487 #define SCB_SHCSR_BUSFAULTENA_Pos 17
488 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
490 #define SCB_SHCSR_MEMFAULTENA_Pos 16
491 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
493 #define SCB_SHCSR_SVCALLPENDED_Pos 15
494 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
496 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14
497 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
499 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13
500 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
502 #define SCB_SHCSR_USGFAULTPENDED_Pos 12
503 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
505 #define SCB_SHCSR_SYSTICKACT_Pos 11
506 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
508 #define SCB_SHCSR_PENDSVACT_Pos 10
509 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
511 #define SCB_SHCSR_MONITORACT_Pos 8
512 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
514 #define SCB_SHCSR_SVCALLACT_Pos 7
515 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
517 #define SCB_SHCSR_USGFAULTACT_Pos 3
518 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
520 #define SCB_SHCSR_BUSFAULTACT_Pos 1
521 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
523 #define SCB_SHCSR_MEMFAULTACT_Pos 0
524 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
526 /* SCB Configurable Fault Status Registers Definitions */
527 #define SCB_CFSR_USGFAULTSR_Pos 16
528 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
530 #define SCB_CFSR_BUSFAULTSR_Pos 8
531 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
533 #define SCB_CFSR_MEMFAULTSR_Pos 0
534 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
536 /* SCB Hard Fault Status Registers Definitions */
537 #define SCB_HFSR_DEBUGEVT_Pos 31
538 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
540 #define SCB_HFSR_FORCED_Pos 30
541 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
543 #define SCB_HFSR_VECTTBL_Pos 1
544 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
546 /* SCB Debug Fault Status Register Definitions */
547 #define SCB_DFSR_EXTERNAL_Pos 4
548 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
550 #define SCB_DFSR_VCATCH_Pos 3
551 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
553 #define SCB_DFSR_DWTTRAP_Pos 2
554 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
556 #define SCB_DFSR_BKPT_Pos 1
557 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
559 #define SCB_DFSR_HALTED_Pos 0
560 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)
562 
573 typedef struct
574 {
575  uint32_t RESERVED0[1];
576  __I uint32_t ICTR;
577 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
578  __IO uint32_t ACTLR;
579 #else
580  uint32_t RESERVED1[1];
581 #endif
582 } SCnSCB_Type;
583 
584 /* Interrupt Controller Type Register Definitions */
585 #define SCnSCB_ICTR_INTLINESNUM_Pos 0
586 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
588 /* Auxiliary Control Register Definitions */
589 
590 #define SCnSCB_ACTLR_DISFOLD_Pos 2
591 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
593 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1
594 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
596 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0
597 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
599 
610 typedef struct
611 {
612  __IO uint32_t CTRL;
613  __IO uint32_t LOAD;
614  __IO uint32_t VAL;
615  __I uint32_t CALIB;
616 } SysTick_Type;
617 
618 /* SysTick Control / Status Register Definitions */
619 #define SysTick_CTRL_COUNTFLAG_Pos 16
620 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
622 #define SysTick_CTRL_CLKSOURCE_Pos 2
623 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
625 #define SysTick_CTRL_TICKINT_Pos 1
626 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
628 #define SysTick_CTRL_ENABLE_Pos 0
629 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
631 /* SysTick Reload Register Definitions */
632 #define SysTick_LOAD_RELOAD_Pos 0
633 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
635 /* SysTick Current Register Definitions */
636 #define SysTick_VAL_CURRENT_Pos 0
637 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
639 /* SysTick Calibration Register Definitions */
640 #define SysTick_CALIB_NOREF_Pos 31
641 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
643 #define SysTick_CALIB_SKEW_Pos 30
644 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
646 #define SysTick_CALIB_TENMS_Pos 0
647 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
649 
660 typedef struct
661 {
662  __O union
663  {
664  __O uint8_t u8;
665  __O uint16_t u16;
666  __O uint32_t u32;
667  } PORT [32];
668  uint32_t RESERVED0[864];
669  __IO uint32_t TER;
670  uint32_t RESERVED1[15];
671  __IO uint32_t TPR;
672  uint32_t RESERVED2[15];
673  __IO uint32_t TCR;
674  uint32_t RESERVED3[29];
675  __O uint32_t IWR;
676  __I uint32_t IRR;
677  __IO uint32_t IMCR;
678  uint32_t RESERVED4[43];
679  __O uint32_t LAR;
680  __I uint32_t LSR;
681  uint32_t RESERVED5[6];
682  __I uint32_t PID4;
683  __I uint32_t PID5;
684  __I uint32_t PID6;
685  __I uint32_t PID7;
686  __I uint32_t PID0;
687  __I uint32_t PID1;
688  __I uint32_t PID2;
689  __I uint32_t PID3;
690  __I uint32_t CID0;
691  __I uint32_t CID1;
692  __I uint32_t CID2;
693  __I uint32_t CID3;
694 } ITM_Type;
695 
696 /* ITM Trace Privilege Register Definitions */
697 #define ITM_TPR_PRIVMASK_Pos 0
698 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos)
700 /* ITM Trace Control Register Definitions */
701 #define ITM_TCR_BUSY_Pos 23
702 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
704 #define ITM_TCR_TraceBusID_Pos 16
705 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
707 #define ITM_TCR_GTSFREQ_Pos 10
708 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
710 #define ITM_TCR_TSPrescale_Pos 8
711 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
713 #define ITM_TCR_SWOENA_Pos 4
714 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
716 #define ITM_TCR_DWTENA_Pos 3
717 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
719 #define ITM_TCR_SYNCENA_Pos 2
720 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
722 #define ITM_TCR_TSENA_Pos 1
723 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
725 #define ITM_TCR_ITMENA_Pos 0
726 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos)
728 /* ITM Integration Write Register Definitions */
729 #define ITM_IWR_ATVALIDM_Pos 0
730 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos)
732 /* ITM Integration Read Register Definitions */
733 #define ITM_IRR_ATREADYM_Pos 0
734 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos)
736 /* ITM Integration Mode Control Register Definitions */
737 #define ITM_IMCR_INTEGRATION_Pos 0
738 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos)
740 /* ITM Lock Status Register Definitions */
741 #define ITM_LSR_ByteAcc_Pos 2
742 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
744 #define ITM_LSR_Access_Pos 1
745 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
747 #define ITM_LSR_Present_Pos 0
748 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos)
750  /* end of group CMSIS_ITM */
751 
752 
761 typedef struct
762 {
763  __IO uint32_t CTRL;
764  __IO uint32_t CYCCNT;
765  __IO uint32_t CPICNT;
766  __IO uint32_t EXCCNT;
767  __IO uint32_t SLEEPCNT;
768  __IO uint32_t LSUCNT;
769  __IO uint32_t FOLDCNT;
770  __I uint32_t PCSR;
771  __IO uint32_t COMP0;
772  __IO uint32_t MASK0;
773  __IO uint32_t FUNCTION0;
774  uint32_t RESERVED0[1];
775  __IO uint32_t COMP1;
776  __IO uint32_t MASK1;
777  __IO uint32_t FUNCTION1;
778  uint32_t RESERVED1[1];
779  __IO uint32_t COMP2;
780  __IO uint32_t MASK2;
781  __IO uint32_t FUNCTION2;
782  uint32_t RESERVED2[1];
783  __IO uint32_t COMP3;
784  __IO uint32_t MASK3;
785  __IO uint32_t FUNCTION3;
786 } DWT_Type;
787 
788 /* DWT Control Register Definitions */
789 #define DWT_CTRL_NUMCOMP_Pos 28
790 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
792 #define DWT_CTRL_NOTRCPKT_Pos 27
793 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
795 #define DWT_CTRL_NOEXTTRIG_Pos 26
796 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
798 #define DWT_CTRL_NOCYCCNT_Pos 25
799 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
801 #define DWT_CTRL_NOPRFCNT_Pos 24
802 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
804 #define DWT_CTRL_CYCEVTENA_Pos 22
805 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
807 #define DWT_CTRL_FOLDEVTENA_Pos 21
808 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
810 #define DWT_CTRL_LSUEVTENA_Pos 20
811 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
813 #define DWT_CTRL_SLEEPEVTENA_Pos 19
814 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
816 #define DWT_CTRL_EXCEVTENA_Pos 18
817 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
819 #define DWT_CTRL_CPIEVTENA_Pos 17
820 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
822 #define DWT_CTRL_EXCTRCENA_Pos 16
823 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
825 #define DWT_CTRL_PCSAMPLENA_Pos 12
826 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
828 #define DWT_CTRL_SYNCTAP_Pos 10
829 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
831 #define DWT_CTRL_CYCTAP_Pos 9
832 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
834 #define DWT_CTRL_POSTINIT_Pos 5
835 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
837 #define DWT_CTRL_POSTPRESET_Pos 1
838 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
840 #define DWT_CTRL_CYCCNTENA_Pos 0
841 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
843 /* DWT CPI Count Register Definitions */
844 #define DWT_CPICNT_CPICNT_Pos 0
845 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos)
847 /* DWT Exception Overhead Count Register Definitions */
848 #define DWT_EXCCNT_EXCCNT_Pos 0
849 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
851 /* DWT Sleep Count Register Definitions */
852 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0
853 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
855 /* DWT LSU Count Register Definitions */
856 #define DWT_LSUCNT_LSUCNT_Pos 0
857 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
859 /* DWT Folded-instruction Count Register Definitions */
860 #define DWT_FOLDCNT_FOLDCNT_Pos 0
861 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
863 /* DWT Comparator Mask Register Definitions */
864 #define DWT_MASK_MASK_Pos 0
865 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos)
867 /* DWT Comparator Function Register Definitions */
868 #define DWT_FUNCTION_MATCHED_Pos 24
869 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
871 #define DWT_FUNCTION_DATAVADDR1_Pos 16
872 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
874 #define DWT_FUNCTION_DATAVADDR0_Pos 12
875 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
877 #define DWT_FUNCTION_DATAVSIZE_Pos 10
878 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
880 #define DWT_FUNCTION_LNK1ENA_Pos 9
881 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
883 #define DWT_FUNCTION_DATAVMATCH_Pos 8
884 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
886 #define DWT_FUNCTION_CYCMATCH_Pos 7
887 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
889 #define DWT_FUNCTION_EMITRANGE_Pos 5
890 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
892 #define DWT_FUNCTION_FUNCTION_Pos 0
893 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
895  /* end of group CMSIS_DWT */
896 
897 
906 typedef struct
907 {
908  __IO uint32_t SSPSR;
909  __IO uint32_t CSPSR;
910  uint32_t RESERVED0[2];
911  __IO uint32_t ACPR;
912  uint32_t RESERVED1[55];
913  __IO uint32_t SPPR;
914  uint32_t RESERVED2[131];
915  __I uint32_t FFSR;
916  __IO uint32_t FFCR;
917  __I uint32_t FSCR;
918  uint32_t RESERVED3[759];
919  __I uint32_t TRIGGER;
920  __I uint32_t FIFO0;
921  __I uint32_t ITATBCTR2;
922  uint32_t RESERVED4[1];
923  __I uint32_t ITATBCTR0;
924  __I uint32_t FIFO1;
925  __IO uint32_t ITCTRL;
926  uint32_t RESERVED5[39];
927  __IO uint32_t CLAIMSET;
928  __IO uint32_t CLAIMCLR;
929  uint32_t RESERVED7[8];
930  __I uint32_t DEVID;
931  __I uint32_t DEVTYPE;
932 } TPI_Type;
933 
934 /* TPI Asynchronous Clock Prescaler Register Definitions */
935 #define TPI_ACPR_PRESCALER_Pos 0
936 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
938 /* TPI Selected Pin Protocol Register Definitions */
939 #define TPI_SPPR_TXMODE_Pos 0
940 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
942 /* TPI Formatter and Flush Status Register Definitions */
943 #define TPI_FFSR_FtNonStop_Pos 3
944 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
946 #define TPI_FFSR_TCPresent_Pos 2
947 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
949 #define TPI_FFSR_FtStopped_Pos 1
950 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
952 #define TPI_FFSR_FlInProg_Pos 0
953 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
955 /* TPI Formatter and Flush Control Register Definitions */
956 #define TPI_FFCR_TrigIn_Pos 8
957 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
959 #define TPI_FFCR_EnFCont_Pos 1
960 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
962 /* TPI TRIGGER Register Definitions */
963 #define TPI_TRIGGER_TRIGGER_Pos 0
964 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
966 /* TPI Integration ETM Data Register Definitions (FIFO0) */
967 #define TPI_FIFO0_ITM_ATVALID_Pos 29
968 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
970 #define TPI_FIFO0_ITM_bytecount_Pos 27
971 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
973 #define TPI_FIFO0_ETM_ATVALID_Pos 26
974 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
976 #define TPI_FIFO0_ETM_bytecount_Pos 24
977 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
979 #define TPI_FIFO0_ETM2_Pos 16
980 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
982 #define TPI_FIFO0_ETM1_Pos 8
983 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
985 #define TPI_FIFO0_ETM0_Pos 0
986 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
988 /* TPI ITATBCTR2 Register Definitions */
989 #define TPI_ITATBCTR2_ATREADY_Pos 0
990 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
992 /* TPI Integration ITM Data Register Definitions (FIFO1) */
993 #define TPI_FIFO1_ITM_ATVALID_Pos 29
994 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
996 #define TPI_FIFO1_ITM_bytecount_Pos 27
997 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
999 #define TPI_FIFO1_ETM_ATVALID_Pos 26
1000 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1002 #define TPI_FIFO1_ETM_bytecount_Pos 24
1003 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1005 #define TPI_FIFO1_ITM2_Pos 16
1006 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1008 #define TPI_FIFO1_ITM1_Pos 8
1009 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1011 #define TPI_FIFO1_ITM0_Pos 0
1012 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
1014 /* TPI ITATBCTR0 Register Definitions */
1015 #define TPI_ITATBCTR0_ATREADY_Pos 0
1016 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
1018 /* TPI Integration Mode Control Register Definitions */
1019 #define TPI_ITCTRL_Mode_Pos 0
1020 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
1022 /* TPI DEVID Register Definitions */
1023 #define TPI_DEVID_NRZVALID_Pos 11
1024 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1026 #define TPI_DEVID_MANCVALID_Pos 10
1027 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1029 #define TPI_DEVID_PTINVALID_Pos 9
1030 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1032 #define TPI_DEVID_MinBufSz_Pos 6
1033 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1035 #define TPI_DEVID_AsynClkIn_Pos 5
1036 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1038 #define TPI_DEVID_NrTraceInput_Pos 0
1039 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
1041 /* TPI DEVTYPE Register Definitions */
1042 #define TPI_DEVTYPE_SubType_Pos 0
1043 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
1045 #define TPI_DEVTYPE_MajorType_Pos 4
1046 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1048  /* end of group CMSIS_TPI */
1049 
1050 
1051 #if (__MPU_PRESENT == 1)
1052 
1060 typedef struct
1061 {
1062  __I uint32_t TYPE;
1063  __IO uint32_t CTRL;
1064  __IO uint32_t RNR;
1065  __IO uint32_t RBAR;
1066  __IO uint32_t RASR;
1067  __IO uint32_t RBAR_A1;
1068  __IO uint32_t RASR_A1;
1069  __IO uint32_t RBAR_A2;
1070  __IO uint32_t RASR_A2;
1071  __IO uint32_t RBAR_A3;
1072  __IO uint32_t RASR_A3;
1073 } MPU_Type;
1074 
1075 /* MPU Type Register */
1076 #define MPU_TYPE_IREGION_Pos 16
1077 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1079 #define MPU_TYPE_DREGION_Pos 8
1080 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1082 #define MPU_TYPE_SEPARATE_Pos 0
1083 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
1085 /* MPU Control Register */
1086 #define MPU_CTRL_PRIVDEFENA_Pos 2
1087 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1089 #define MPU_CTRL_HFNMIENA_Pos 1
1090 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1092 #define MPU_CTRL_ENABLE_Pos 0
1093 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
1095 /* MPU Region Number Register */
1096 #define MPU_RNR_REGION_Pos 0
1097 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
1099 /* MPU Region Base Address Register */
1100 #define MPU_RBAR_ADDR_Pos 5
1101 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1103 #define MPU_RBAR_VALID_Pos 4
1104 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1106 #define MPU_RBAR_REGION_Pos 0
1107 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
1109 /* MPU Region Attribute and Size Register */
1110 #define MPU_RASR_ATTRS_Pos 16
1111 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1113 #define MPU_RASR_XN_Pos 28
1114 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1116 #define MPU_RASR_AP_Pos 24
1117 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1119 #define MPU_RASR_TEX_Pos 19
1120 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1122 #define MPU_RASR_S_Pos 18
1123 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1125 #define MPU_RASR_C_Pos 17
1126 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1128 #define MPU_RASR_B_Pos 16
1129 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1131 #define MPU_RASR_SRD_Pos 8
1132 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1134 #define MPU_RASR_SIZE_Pos 1
1135 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1137 #define MPU_RASR_ENABLE_Pos 0
1138 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
1140 
1141 #endif
1142 
1143 
1152 typedef struct
1153 {
1154  __IO uint32_t DHCSR;
1155  __O uint32_t DCRSR;
1156  __IO uint32_t DCRDR;
1157  __IO uint32_t DEMCR;
1158 } CoreDebug_Type;
1159 
1160 /* Debug Halting Control and Status Register */
1161 #define CoreDebug_DHCSR_DBGKEY_Pos 16
1162 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1164 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25
1165 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1167 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
1168 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1170 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19
1171 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1173 #define CoreDebug_DHCSR_S_SLEEP_Pos 18
1174 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1176 #define CoreDebug_DHCSR_S_HALT_Pos 17
1177 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1179 #define CoreDebug_DHCSR_S_REGRDY_Pos 16
1180 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1182 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
1183 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1185 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3
1186 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1188 #define CoreDebug_DHCSR_C_STEP_Pos 2
1189 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1191 #define CoreDebug_DHCSR_C_HALT_Pos 1
1192 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1194 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0
1195 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
1197 /* Debug Core Register Selector Register */
1198 #define CoreDebug_DCRSR_REGWnR_Pos 16
1199 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1201 #define CoreDebug_DCRSR_REGSEL_Pos 0
1202 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
1204 /* Debug Exception and Monitor Control Register */
1205 #define CoreDebug_DEMCR_TRCENA_Pos 24
1206 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1208 #define CoreDebug_DEMCR_MON_REQ_Pos 19
1209 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1211 #define CoreDebug_DEMCR_MON_STEP_Pos 18
1212 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1214 #define CoreDebug_DEMCR_MON_PEND_Pos 17
1215 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1217 #define CoreDebug_DEMCR_MON_EN_Pos 16
1218 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1220 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10
1221 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1223 #define CoreDebug_DEMCR_VC_INTERR_Pos 9
1224 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1226 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8
1227 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1229 #define CoreDebug_DEMCR_VC_STATERR_Pos 7
1230 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1232 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6
1233 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1235 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5
1236 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1238 #define CoreDebug_DEMCR_VC_MMERR_Pos 4
1239 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1241 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0
1242 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
1244 
1253 /* Memory mapping of Cortex-M3 Hardware */
1254 #define SCS_BASE (0xE000E000UL)
1255 #define ITM_BASE (0xE0000000UL)
1256 #define DWT_BASE (0xE0001000UL)
1257 #define TPI_BASE (0xE0040000UL)
1258 #define CoreDebug_BASE (0xE000EDF0UL)
1259 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1260 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1261 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1263 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1264 #define SCB ((SCB_Type *) SCB_BASE )
1265 #define SysTick ((SysTick_Type *) SysTick_BASE )
1266 #define NVIC ((NVIC_Type *) NVIC_BASE )
1267 #define ITM ((ITM_Type *) ITM_BASE )
1268 #define DWT ((DWT_Type *) DWT_BASE )
1269 #define TPI ((TPI_Type *) TPI_BASE )
1270 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1272 #if (__MPU_PRESENT == 1)
1273  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1274  #define MPU ((MPU_Type *) MPU_BASE )
1275 #endif
1276 
1281 /*******************************************************************************
1282  * Hardware Abstraction Layer
1283  Core Function Interface contains:
1284  - Core NVIC Functions
1285  - Core SysTick Functions
1286  - Core Debug Functions
1287  - Core Register Access Functions
1288  ******************************************************************************/
1294 /* ########################## NVIC functions #################################### */
1311 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1312 {
1313  uint32_t reg_value;
1314  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1315 
1316  reg_value = SCB->AIRCR; /* read old register configuration */
1317  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1318  reg_value = (reg_value |
1319  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1320  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1321  SCB->AIRCR = reg_value;
1322 }
1323 
1324 
1331 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1332 {
1333  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1334 }
1335 
1336 
1343 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1344 {
1345  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1346 }
1347 
1348 
1355 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1356 {
1357  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1358 }
1359 
1360 
1371 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1372 {
1373  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1374 }
1375 
1376 
1383 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1384 {
1385  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1386 }
1387 
1388 
1395 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1396 {
1397  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1398 }
1399 
1400 
1410 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1411 {
1412  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1413 }
1414 
1415 
1425 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1426 {
1427  if(IRQn < 0) {
1428  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1429  else {
1430  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1431 }
1432 
1433 
1445 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1446 {
1447 
1448  if(IRQn < 0) {
1449  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1450  else {
1451  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1452 }
1453 
1454 
1467 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1468 {
1469  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1470  uint32_t PreemptPriorityBits;
1471  uint32_t SubPriorityBits;
1472 
1473  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1474  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1475 
1476  return (
1477  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1478  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1479  );
1480 }
1481 
1482 
1495 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1496 {
1497  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1498  uint32_t PreemptPriorityBits;
1499  uint32_t SubPriorityBits;
1500 
1501  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1502  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1503 
1504  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1505  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1506 }
1507 
1508 
1513 __STATIC_INLINE void NVIC_SystemReset(void)
1514 {
1515  __DSB(); /* Ensure all outstanding memory accesses included
1516  buffered write are completed before reset */
1517  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1518  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1519  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1520  __DSB(); /* Ensure completion of memory access */
1521  while(1); /* wait until reset */
1522 }
1523 
1528 /* ################################## SysTick function ############################################ */
1535 #if (__Vendor_SysTickConfig == 0)
1536 
1552 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1553 {
1554  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1555 
1556  SysTick->LOAD = ticks - 1; /* set reload register */
1557  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1558  SysTick->VAL = 0; /* Load the SysTick Counter Value */
1561  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1562  return (0); /* Function successful */
1563 }
1564 
1565 #endif
1566 
1571 /* ##################################### Debug In/Output function ########################################### */
1578 extern volatile int32_t ITM_RxBuffer;
1579 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5
1592 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1593 {
1594  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1595  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1596  {
1597  while (ITM->PORT[0].u32 == 0);
1598  ITM->PORT[0].u8 = (uint8_t) ch;
1599  }
1600  return (ch);
1601 }
1602 
1603 
1611 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1612  int32_t ch = -1; /* no character available */
1613 
1614  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1615  ch = ITM_RxBuffer;
1616  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1617  }
1618 
1619  return (ch);
1620 }
1621 
1622 
1630 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1631 
1632  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1633  return (0); /* no character available */
1634  } else {
1635  return (1); /* character available */
1636  }
1637 }
1638 
1644 #ifdef __cplusplus
1645 }
1646 #endif
1647 
1648 #endif /* __CORE_CM3_H_DEPENDANT */
1649 
1650 #endif /* __CMSIS_GENERIC */
CMSIS Cortex-M Core Function Access Header File.
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:309
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:334
Structure type to access the Data Watchpoint and Trace Register (DWT).
CMSIS Cortex-M Core Instruction Access Header File.
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:186
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:611
volatile int32_t ITM_RxBuffer
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:556
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:439
Structure type to access the Core Debug Register (CoreDebug).
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:647
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:224
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:544
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:572
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:685
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:286
Structure type to access the Trace Port Interface Register (TPI).
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode Priority.
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:584
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:596
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:247
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:260
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:633
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
#define __NVIC_PRIO_BITS
Definition: stm32f4xx.h:178
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Structure type to access the Instrumentation Trace Macrocell Register (ITM).


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:18