Modules
Defines and Type Definitions

Type definitions and defines for Cortex-M processor based devices. More...

Collaboration diagram for Defines and Type Definitions:

Modules

 Status and Control Registers
 Core Register type definitions.
 
 Nested Vectored Interrupt Controller (NVIC)
 Type definitions for the NVIC Registers.
 
 System Control Block (SCB)
 Type definitions for the System Control Block Registers.
 
 System Tick Timer (SysTick)
 Type definitions for the System Timer Registers.
 
 Core Debug Registers (CoreDebug)
 Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file.
 
 Core Definitions
 Definitions for base addresses, unions, and structures.
 
 System Controls not in SCB (SCnSCB)
 Type definitions for the System Control and ID Register not in the SCB.
 
 Instrumentation Trace Macrocell (ITM)
 Type definitions for the Instrumentation Trace Macrocell (ITM)
 
 Data Watchpoint and Trace (DWT)
 Type definitions for the Data Watchpoint and Trace (DWT)
 
 Trace Port Interface (TPI)
 Type definitions for the Trace Port Interface (TPI)
 

Detailed Description

Type definitions and defines for Cortex-M processor based devices.



rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Fri Jul 24 2020 03:20:12