breezy/breezystm32/lib/CMSIS/CM3/CoreSupport/core_cm3.h
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1 /**************************************************************************/
24 #ifndef __CM3_CORE_H__
25 #define __CM3_CORE_H__
26 
62 /*lint -save */
63 /*lint -e10 */
64 /*lint -e530 */
65 /*lint -e550 */
66 /*lint -e754 */
67 /*lint -e750 */
68 /*lint -e528 */
69 /*lint -e751 */
70 
71 
80 #ifdef __cplusplus
81  extern "C" {
82 #endif
83 
84 #define __CM3_CMSIS_VERSION_MAIN (0x01)
85 #define __CM3_CMSIS_VERSION_SUB (0x30)
86 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
88 #define __CORTEX_M (0x03)
90 #include <stdint.h> /* Include standard types */
91 
92 #if defined (__ICCARM__)
93  #include <intrinsics.h> /* IAR Intrinsics */
94 #endif
95 
96 
97 #ifndef __NVIC_PRIO_BITS
98  #define __NVIC_PRIO_BITS 4
99 #endif
100 
101 
102 
103 
110 #ifdef __cplusplus
111  #define __I volatile
112 #else
113  #define __I volatile const
114 #endif
115 #define __O volatile
116 #define __IO volatile
120 /*******************************************************************************
121  * Register Abstraction
122  ******************************************************************************/
123 
132 typedef struct
133 {
134  __IO uint32_t ISER[8];
135  uint32_t RESERVED0[24];
136  __IO uint32_t ICER[8];
137  uint32_t RSERVED1[24];
138  __IO uint32_t ISPR[8];
139  uint32_t RESERVED2[24];
140  __IO uint32_t ICPR[8];
141  uint32_t RESERVED3[24];
142  __IO uint32_t IABR[8];
143  uint32_t RESERVED4[56];
144  __IO uint8_t IP[240];
145  uint32_t RESERVED5[644];
146  __O uint32_t STIR;
147 } NVIC_Type; /* end of group CMSIS_CM3_NVIC */
149 
150 
155 typedef struct
156 {
157  __I uint32_t CPUID;
158  __IO uint32_t ICSR;
159  __IO uint32_t VTOR;
160  __IO uint32_t AIRCR;
161  __IO uint32_t SCR;
162  __IO uint32_t CCR;
163  __IO uint8_t SHP[12];
164  __IO uint32_t SHCSR;
165  __IO uint32_t CFSR;
166  __IO uint32_t HFSR;
167  __IO uint32_t DFSR;
168  __IO uint32_t MMFAR;
169  __IO uint32_t BFAR;
170  __IO uint32_t AFSR;
171  __I uint32_t PFR[2];
172  __I uint32_t DFR;
173  __I uint32_t ADR;
174  __I uint32_t MMFR[4];
175  __I uint32_t ISAR[5];
176 } SCB_Type;
177 
178 /* SCB CPUID Register Definitions */
179 #define SCB_CPUID_IMPLEMENTER_Pos 24
180 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)
182 #define SCB_CPUID_VARIANT_Pos 20
183 #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos)
185 #define SCB_CPUID_PARTNO_Pos 4
186 #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos)
188 #define SCB_CPUID_REVISION_Pos 0
189 #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos)
191 /* SCB Interrupt Control State Register Definitions */
192 #define SCB_ICSR_NMIPENDSET_Pos 31
193 #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos)
195 #define SCB_ICSR_PENDSVSET_Pos 28
196 #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos)
198 #define SCB_ICSR_PENDSVCLR_Pos 27
199 #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos)
201 #define SCB_ICSR_PENDSTSET_Pos 26
202 #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos)
204 #define SCB_ICSR_PENDSTCLR_Pos 25
205 #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos)
207 #define SCB_ICSR_ISRPREEMPT_Pos 23
208 #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos)
210 #define SCB_ICSR_ISRPENDING_Pos 22
211 #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos)
213 #define SCB_ICSR_VECTPENDING_Pos 12
214 #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos)
216 #define SCB_ICSR_RETTOBASE_Pos 11
217 #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos)
219 #define SCB_ICSR_VECTACTIVE_Pos 0
220 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)
222 /* SCB Interrupt Control State Register Definitions */
223 #define SCB_VTOR_TBLBASE_Pos 29
224 #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos)
226 #define SCB_VTOR_TBLOFF_Pos 7
227 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)
229 /* SCB Application Interrupt and Reset Control Register Definitions */
230 #define SCB_AIRCR_VECTKEY_Pos 16
231 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)
233 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
234 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)
236 #define SCB_AIRCR_ENDIANESS_Pos 15
237 #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos)
239 #define SCB_AIRCR_PRIGROUP_Pos 8
240 #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos)
242 #define SCB_AIRCR_SYSRESETREQ_Pos 2
243 #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos)
245 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
246 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)
248  /* SCB Configuration Control Register Definitions */
249 #define SCB_AIRCR_VECTRESET_Pos 0
250 #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos)
252 /* SCB System Control Register Definitions */
253 #define SCB_SCR_SEVONPEND_Pos 4
254 #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos)
256 #define SCB_SCR_SLEEPDEEP_Pos 2
257 #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos)
259 #define SCB_SCR_SLEEPONEXIT_Pos 1
260 #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos)
262 /* SCB Configuration Control Register Definitions */
263 #define SCB_CCR_STKALIGN_Pos 9
264 #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos)
266 #define SCB_CCR_BFHFNMIGN_Pos 8
267 #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos)
269 #define SCB_CCR_DIV_0_TRP_Pos 4
270 #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos)
272 #define SCB_CCR_UNALIGN_TRP_Pos 3
273 #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos)
275 #define SCB_CCR_USERSETMPEND_Pos 1
276 #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos)
278 #define SCB_CCR_NONBASETHRDENA_Pos 0
279 #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos)
281  /* SCB Configuration Control Register Definitions */
282 /* SCB System Handler Control and State Register Definitions */
283 #define SCB_SHCSR_USGFAULTENA_Pos 18
284 #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos)
286 #define SCB_SHCSR_BUSFAULTENA_Pos 17
287 #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos)
289 #define SCB_SHCSR_MEMFAULTENA_Pos 16
290 #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos)
292 #define SCB_SHCSR_SVCALLPENDED_Pos 15
293 #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos)
295 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14
296 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)
298 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13
299 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)
301 #define SCB_SHCSR_USGFAULTPENDED_Pos 12
302 #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)
304 #define SCB_SHCSR_SYSTICKACT_Pos 11
305 #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos)
307 #define SCB_SHCSR_PENDSVACT_Pos 10
308 #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos)
310 #define SCB_SHCSR_MONITORACT_Pos 8
311 #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos)
313 #define SCB_SHCSR_SVCALLACT_Pos 7
314 #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos)
316 #define SCB_SHCSR_USGFAULTACT_Pos 3
317 #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos)
319 #define SCB_SHCSR_BUSFAULTACT_Pos 1
320 #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos)
322 #define SCB_SHCSR_MEMFAULTACT_Pos 0
323 #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos)
325 /* SCB Configurable Fault Status Registers Definitions */
326 #define SCB_CFSR_USGFAULTSR_Pos 16
327 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)
329 #define SCB_CFSR_BUSFAULTSR_Pos 8
330 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)
332 #define SCB_CFSR_MEMFAULTSR_Pos 0
333 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)
335 /* SCB Hard Fault Status Registers Definitions */
336 #define SCB_HFSR_DEBUGEVT_Pos 31
337 #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos)
339 #define SCB_HFSR_FORCED_Pos 30
340 #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos)
342 #define SCB_HFSR_VECTTBL_Pos 1
343 #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos)
345 /* SCB Debug Fault Status Register Definitions */
346 #define SCB_DFSR_EXTERNAL_Pos 4
347 #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos)
349 #define SCB_DFSR_VCATCH_Pos 3
350 #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos)
352 #define SCB_DFSR_DWTTRAP_Pos 2
353 #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos)
355 #define SCB_DFSR_BKPT_Pos 1
356 #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos)
358 #define SCB_DFSR_HALTED_Pos 0
359 #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos)
360  /* end of group CMSIS_CM3_SCB */
361 
362 
367 typedef struct
368 {
369  __IO uint32_t CTRL;
370  __IO uint32_t LOAD;
371  __IO uint32_t VAL;
372  __I uint32_t CALIB;
373 } SysTick_Type;
374 
375 /* SysTick Control / Status Register Definitions */
376 #define SysTick_CTRL_COUNTFLAG_Pos 16
377 #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos)
379 #define SysTick_CTRL_CLKSOURCE_Pos 2
380 #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos)
382 #define SysTick_CTRL_TICKINT_Pos 1
383 #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos)
385 #define SysTick_CTRL_ENABLE_Pos 0
386 #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos)
388 /* SysTick Reload Register Definitions */
389 #define SysTick_LOAD_RELOAD_Pos 0
390 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)
392 /* SysTick Current Register Definitions */
393 #define SysTick_VAL_CURRENT_Pos 0
394 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)
396 /* SysTick Calibration Register Definitions */
397 #define SysTick_CALIB_NOREF_Pos 31
398 #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos)
400 #define SysTick_CALIB_SKEW_Pos 30
401 #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos)
403 #define SysTick_CALIB_TENMS_Pos 0
404 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)
405  /* end of group CMSIS_CM3_SysTick */
406 
407 
412 typedef struct
413 {
414  __O union
415  {
416  __O uint8_t u8;
417  __O uint16_t u16;
418  __O uint32_t u32;
419  } PORT [32];
420  uint32_t RESERVED0[864];
421  __IO uint32_t TER;
422  uint32_t RESERVED1[15];
423  __IO uint32_t TPR;
424  uint32_t RESERVED2[15];
425  __IO uint32_t TCR;
426  uint32_t RESERVED3[29];
427  __IO uint32_t IWR;
428  __IO uint32_t IRR;
429  __IO uint32_t IMCR;
430  uint32_t RESERVED4[43];
431  __IO uint32_t LAR;
432  __IO uint32_t LSR;
433  uint32_t RESERVED5[6];
434  __I uint32_t PID4;
435  __I uint32_t PID5;
436  __I uint32_t PID6;
437  __I uint32_t PID7;
438  __I uint32_t PID0;
439  __I uint32_t PID1;
440  __I uint32_t PID2;
441  __I uint32_t PID3;
442  __I uint32_t CID0;
443  __I uint32_t CID1;
444  __I uint32_t CID2;
445  __I uint32_t CID3;
446 } ITM_Type;
447 
448 /* ITM Trace Privilege Register Definitions */
449 #define ITM_TPR_PRIVMASK_Pos 0
450 #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos)
452 /* ITM Trace Control Register Definitions */
453 #define ITM_TCR_BUSY_Pos 23
454 #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos)
456 #define ITM_TCR_ATBID_Pos 16
457 #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos)
459 #define ITM_TCR_TSPrescale_Pos 8
460 #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos)
462 #define ITM_TCR_SWOENA_Pos 4
463 #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos)
465 #define ITM_TCR_DWTENA_Pos 3
466 #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos)
468 #define ITM_TCR_SYNCENA_Pos 2
469 #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos)
471 #define ITM_TCR_TSENA_Pos 1
472 #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos)
474 #define ITM_TCR_ITMENA_Pos 0
475 #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos)
477 /* ITM Integration Write Register Definitions */
478 #define ITM_IWR_ATVALIDM_Pos 0
479 #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos)
481 /* ITM Integration Read Register Definitions */
482 #define ITM_IRR_ATREADYM_Pos 0
483 #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos)
485 /* ITM Integration Mode Control Register Definitions */
486 #define ITM_IMCR_INTEGRATION_Pos 0
487 #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos)
489 /* ITM Lock Status Register Definitions */
490 #define ITM_LSR_ByteAcc_Pos 2
491 #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos)
493 #define ITM_LSR_Access_Pos 1
494 #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos)
496 #define ITM_LSR_Present_Pos 0
497 #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos)
498  /* end of group CMSIS_CM3_ITM */
499 
500 
505 typedef struct
506 {
507  uint32_t RESERVED0;
508  __I uint32_t ICTR;
509 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
510  __IO uint32_t ACTLR;
511 #else
512  uint32_t RESERVED1;
513 #endif
515 
516 /* Interrupt Controller Type Register Definitions */
517 #define InterruptType_ICTR_INTLINESNUM_Pos 0
518 #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos)
520 /* Auxiliary Control Register Definitions */
521 #define InterruptType_ACTLR_DISFOLD_Pos 2
522 #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos)
524 #define InterruptType_ACTLR_DISDEFWBUF_Pos 1
525 #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)
527 #define InterruptType_ACTLR_DISMCYCINT_Pos 0
528 #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)
529  /* end of group CMSIS_CM3_InterruptType */
530 
531 
532 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
533 
537 typedef struct
538 {
539  __I uint32_t TYPE;
540  __IO uint32_t CTRL;
541  __IO uint32_t RNR;
542  __IO uint32_t RBAR;
543  __IO uint32_t RASR;
544  __IO uint32_t RBAR_A1;
545  __IO uint32_t RASR_A1;
546  __IO uint32_t RBAR_A2;
547  __IO uint32_t RASR_A2;
548  __IO uint32_t RBAR_A3;
549  __IO uint32_t RASR_A3;
550 } MPU_Type;
551 
552 /* MPU Type Register */
553 #define MPU_TYPE_IREGION_Pos 16
554 #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos)
556 #define MPU_TYPE_DREGION_Pos 8
557 #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos)
559 #define MPU_TYPE_SEPARATE_Pos 0
560 #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos)
562 /* MPU Control Register */
563 #define MPU_CTRL_PRIVDEFENA_Pos 2
564 #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos)
566 #define MPU_CTRL_HFNMIENA_Pos 1
567 #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos)
569 #define MPU_CTRL_ENABLE_Pos 0
570 #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos)
572 /* MPU Region Number Register */
573 #define MPU_RNR_REGION_Pos 0
574 #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos)
576 /* MPU Region Base Address Register */
577 #define MPU_RBAR_ADDR_Pos 5
578 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)
580 #define MPU_RBAR_VALID_Pos 4
581 #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos)
583 #define MPU_RBAR_REGION_Pos 0
584 #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos)
586 /* MPU Region Attribute and Size Register */
587 #define MPU_RASR_XN_Pos 28
588 #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos)
590 #define MPU_RASR_AP_Pos 24
591 #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos)
593 #define MPU_RASR_TEX_Pos 19
594 #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos)
596 #define MPU_RASR_S_Pos 18
597 #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos)
599 #define MPU_RASR_C_Pos 17
600 #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos)
602 #define MPU_RASR_B_Pos 16
603 #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos)
605 #define MPU_RASR_SRD_Pos 8
606 #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos)
608 #define MPU_RASR_SIZE_Pos 1
609 #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos)
611 #define MPU_RASR_ENA_Pos 0
612 #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos)
614  /* end of group CMSIS_CM3_MPU */
615 #endif
616 
617 
622 typedef struct
623 {
624  __IO uint32_t DHCSR;
625  __O uint32_t DCRSR;
626  __IO uint32_t DCRDR;
627  __IO uint32_t DEMCR;
629 
630 /* Debug Halting Control and Status Register */
631 #define CoreDebug_DHCSR_DBGKEY_Pos 16
632 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)
634 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25
635 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)
637 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
638 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
640 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19
641 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)
643 #define CoreDebug_DHCSR_S_SLEEP_Pos 18
644 #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)
646 #define CoreDebug_DHCSR_S_HALT_Pos 17
647 #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos)
649 #define CoreDebug_DHCSR_S_REGRDY_Pos 16
650 #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)
652 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
653 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
655 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3
656 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)
658 #define CoreDebug_DHCSR_C_STEP_Pos 2
659 #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos)
661 #define CoreDebug_DHCSR_C_HALT_Pos 1
662 #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos)
664 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0
665 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)
667 /* Debug Core Register Selector Register */
668 #define CoreDebug_DCRSR_REGWnR_Pos 16
669 #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos)
671 #define CoreDebug_DCRSR_REGSEL_Pos 0
672 #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)
674 /* Debug Exception and Monitor Control Register */
675 #define CoreDebug_DEMCR_TRCENA_Pos 24
676 #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos)
678 #define CoreDebug_DEMCR_MON_REQ_Pos 19
679 #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos)
681 #define CoreDebug_DEMCR_MON_STEP_Pos 18
682 #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos)
684 #define CoreDebug_DEMCR_MON_PEND_Pos 17
685 #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos)
687 #define CoreDebug_DEMCR_MON_EN_Pos 16
688 #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos)
690 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10
691 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)
693 #define CoreDebug_DEMCR_VC_INTERR_Pos 9
694 #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)
696 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8
697 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)
699 #define CoreDebug_DEMCR_VC_STATERR_Pos 7
700 #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)
702 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6
703 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)
705 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5
706 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)
708 #define CoreDebug_DEMCR_VC_MMERR_Pos 4
709 #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)
711 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0
712 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)
713  /* end of group CMSIS_CM3_CoreDebug */
714 
715 
716 /* Memory mapping of Cortex-M3 Hardware */
717 #define SCS_BASE (0xE000E000)
718 #define ITM_BASE (0xE0000000)
719 #define CoreDebug_BASE (0xE000EDF0)
720 #define SysTick_BASE (SCS_BASE + 0x0010)
721 #define NVIC_BASE (SCS_BASE + 0x0100)
722 #define SCB_BASE (SCS_BASE + 0x0D00)
724 #define InterruptType ((InterruptType_Type *) SCS_BASE)
725 #define SCB ((SCB_Type *) SCB_BASE)
726 #define SysTick ((SysTick_Type *) SysTick_BASE)
727 #define NVIC ((NVIC_Type *) NVIC_BASE)
728 #define ITM ((ITM_Type *) ITM_BASE)
729 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
731 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
732  #define MPU_BASE (SCS_BASE + 0x0D90)
733  #define MPU ((MPU_Type*) MPU_BASE)
734 #endif
735  /* end of group CMSIS_CM3_core_register */
737 
738 
739 /*******************************************************************************
740  * Hardware Abstraction Layer
741  ******************************************************************************/
742 
743 #if defined ( __CC_ARM )
744  #define __ASM __asm
745  #define __INLINE __inline
747 #elif defined ( __ICCARM__ )
748  #define __ASM __asm
749  #define __INLINE inline
751 #elif defined ( __GNUC__ )
752  #define __ASM __asm
753  #define __INLINE inline
755 #elif defined ( __TASKING__ )
756  #define __ASM __asm
757  #define __INLINE inline
759 #endif
760 
761 
762 /* ################### Compiler specific Intrinsics ########################### */
763 
764 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
765 /* ARM armcc specific functions */
766 
767 #define __enable_fault_irq __enable_fiq
768 #define __disable_fault_irq __disable_fiq
769 
770 #define __NOP __nop
771 #define __WFI __wfi
772 #define __WFE __wfe
773 #define __SEV __sev
774 #define __ISB() __isb(0)
775 #define __DSB() __dsb(0)
776 #define __DMB() __dmb(0)
777 #define __REV __rev
778 #define __RBIT __rbit
779 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
780 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
781 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
782 #define __STREXB(value, ptr) __strex(value, ptr)
783 #define __STREXH(value, ptr) __strex(value, ptr)
784 #define __STREXW(value, ptr) __strex(value, ptr)
785 
786 
787 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
788 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
789 /* intrinsic void __enable_irq(); */
790 /* intrinsic void __disable_irq(); */
791 
792 
800 extern uint32_t __get_PSP(void);
801 
810 extern void __set_PSP(uint32_t topOfProcStack);
811 
820 extern uint32_t __get_MSP(void);
821 
830 extern void __set_MSP(uint32_t topOfMainStack);
831 
840 extern uint32_t __REV16(uint16_t value);
841 
850 extern int32_t __REVSH(int16_t value);
851 
852 
853 #if (__ARMCC_VERSION < 400000)
854 
860 extern void __CLREX(void);
861 
869 extern uint32_t __get_BASEPRI(void);
870 
878 extern void __set_BASEPRI(uint32_t basePri);
879 
887 extern uint32_t __get_PRIMASK(void);
888 
896 extern void __set_PRIMASK(uint32_t priMask);
897 
905 extern uint32_t __get_FAULTMASK(void);
906 
914 extern void __set_FAULTMASK(uint32_t faultMask);
915 
923 extern uint32_t __get_CONTROL(void);
924 
932 extern void __set_CONTROL(uint32_t control);
933 
934 #else /* (__ARMCC_VERSION >= 400000) */
935 
941 #define __CLREX __clrex
942 
950 static __INLINE uint32_t __get_BASEPRI(void)
951 {
952  register uint32_t __regBasePri __ASM("basepri");
953  return(__regBasePri);
954 }
955 
963 static __INLINE void __set_BASEPRI(uint32_t basePri)
964 {
965  register uint32_t __regBasePri __ASM("basepri");
966  __regBasePri = (basePri & 0xff);
967 }
968 
976 static __INLINE uint32_t __get_PRIMASK(void)
977 {
978  register uint32_t __regPriMask __ASM("primask");
979  return(__regPriMask);
980 }
981 
989 static __INLINE void __set_PRIMASK(uint32_t priMask)
990 {
991  register uint32_t __regPriMask __ASM("primask");
992  __regPriMask = (priMask);
993 }
994 
1002 static __INLINE uint32_t __get_FAULTMASK(void)
1003 {
1004  register uint32_t __regFaultMask __ASM("faultmask");
1005  return(__regFaultMask);
1006 }
1007 
1015 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
1016 {
1017  register uint32_t __regFaultMask __ASM("faultmask");
1018  __regFaultMask = (faultMask & 1);
1019 }
1020 
1028 static __INLINE uint32_t __get_CONTROL(void)
1029 {
1030  register uint32_t __regControl __ASM("control");
1031  return(__regControl);
1032 }
1033 
1041 static __INLINE void __set_CONTROL(uint32_t control)
1042 {
1043  register uint32_t __regControl __ASM("control");
1044  __regControl = control;
1045 }
1046 
1047 #endif /* __ARMCC_VERSION */
1048 
1049 
1050 
1051 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
1052 /* IAR iccarm specific functions */
1053 
1054 #define __enable_irq __enable_interrupt
1055 #define __disable_irq __disable_interrupt
1057 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
1058 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
1059 
1060 #define __NOP __no_operation
1061 static __INLINE void __WFI() { __ASM ("wfi"); }
1062 static __INLINE void __WFE() { __ASM ("wfe"); }
1063 static __INLINE void __SEV() { __ASM ("sev"); }
1064 static __INLINE void __CLREX() { __ASM ("clrex"); }
1065 
1066 /* intrinsic void __ISB(void) */
1067 /* intrinsic void __DSB(void) */
1068 /* intrinsic void __DMB(void) */
1069 /* intrinsic void __set_PRIMASK(); */
1070 /* intrinsic void __get_PRIMASK(); */
1071 /* intrinsic void __set_FAULTMASK(); */
1072 /* intrinsic void __get_FAULTMASK(); */
1073 /* intrinsic uint32_t __REV(uint32_t value); */
1074 /* intrinsic uint32_t __REVSH(uint32_t value); */
1075 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
1076 /* intrinsic unsigned long __LDREX(unsigned long *); */
1077 
1078 
1086 extern uint32_t __get_PSP(void);
1087 
1096 extern void __set_PSP(uint32_t topOfProcStack);
1097 
1106 extern uint32_t __get_MSP(void);
1107 
1116 extern void __set_MSP(uint32_t topOfMainStack);
1117 
1126 extern uint32_t __REV16(uint16_t value);
1127 
1136 extern uint32_t __RBIT(uint32_t value);
1137 
1146 extern uint8_t __LDREXB(uint8_t *addr);
1147 
1156 extern uint16_t __LDREXH(uint16_t *addr);
1157 
1166 extern uint32_t __LDREXW(uint32_t *addr);
1167 
1177 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
1178 
1188 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
1189 
1199 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
1200 
1201 
1202 
1203 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
1204 /* GNU gcc specific functions */
1205 
1206 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
1207 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
1208 
1209 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
1210 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
1211 
1212 static __INLINE void __NOP() { __ASM volatile ("nop"); }
1213 static __INLINE void __WFI() { __ASM volatile ("wfi"); }
1214 static __INLINE void __WFE() { __ASM volatile ("wfe"); }
1215 static __INLINE void __SEV() { __ASM volatile ("sev"); }
1216 static __INLINE void __ISB() { __ASM volatile ("isb"); }
1217 static __INLINE void __DSB() { __ASM volatile ("dsb"); }
1218 static __INLINE void __DMB() { __ASM volatile ("dmb"); }
1219 static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
1220 
1221 
1229 extern uint32_t __get_PSP(void);
1230 
1239 extern void __set_PSP(uint32_t topOfProcStack);
1240 
1249 extern uint32_t __get_MSP(void);
1250 
1259 extern void __set_MSP(uint32_t topOfMainStack);
1260 
1268 extern uint32_t __get_BASEPRI(void);
1269 
1277 extern void __set_BASEPRI(uint32_t basePri);
1278 
1286 extern uint32_t __get_PRIMASK(void);
1287 
1295 extern void __set_PRIMASK(uint32_t priMask);
1296 
1304 extern uint32_t __get_FAULTMASK(void);
1305 
1313 extern void __set_FAULTMASK(uint32_t faultMask);
1314 
1322 extern uint32_t __get_CONTROL(void);
1323 
1331 extern void __set_CONTROL(uint32_t control);
1332 
1341 extern uint32_t __REV(uint32_t value);
1342 
1351 extern uint32_t __REV16(uint16_t value);
1352 
1361 extern int32_t __REVSH(int16_t value);
1362 
1371 extern uint32_t __RBIT(uint32_t value);
1372 
1381 extern uint8_t __LDREXB(uint8_t *addr);
1382 
1391 extern uint16_t __LDREXH(uint16_t *addr);
1392 
1401 extern uint32_t __LDREXW(uint32_t *addr);
1402 
1412 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
1413 
1423 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
1424 
1434 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
1435 
1436 
1437 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
1438 /* TASKING carm specific functions */
1439 
1440 /*
1441  * The CMSIS functions have been implemented as intrinsics in the compiler.
1442  * Please use "carm -?i" to get an up to date list of all instrinsics,
1443  * Including the CMSIS ones.
1444  */
1445 
1446 #endif
1447 
1448 
1456 
1457 /* ########################## NVIC functions #################################### */
1458 
1470 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1471 {
1472  uint32_t reg_value;
1473  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1474 
1475  reg_value = SCB->AIRCR; /* read old register configuration */
1476  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1477  reg_value = (reg_value |
1478  (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1479  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1480  SCB->AIRCR = reg_value;
1481 }
1482 
1491 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
1492 {
1493  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1494 }
1495 
1504 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1505 {
1506  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1507 }
1508 
1517 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1518 {
1519  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1520 }
1521 
1531 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1532 {
1533  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1534 }
1535 
1544 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1545 {
1546  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1547 }
1548 
1557 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1558 {
1559  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1560 }
1561 
1571 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1572 {
1573  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1574 }
1575 
1588 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1589 {
1590  if(IRQn < 0) {
1591  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
1592  else {
1593  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1594 }
1595 
1611 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1612 {
1613 
1614  if(IRQn < 0) {
1615  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
1616  else {
1617  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1618 }
1619 
1620 
1636 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1637 {
1638  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1639  uint32_t PreemptPriorityBits;
1640  uint32_t SubPriorityBits;
1641 
1642  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1643  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1644 
1645  return (
1646  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1647  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1648  );
1649 }
1650 
1651 
1667 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1668 {
1669  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1670  uint32_t PreemptPriorityBits;
1671  uint32_t SubPriorityBits;
1672 
1673  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1674  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1675 
1676  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1677  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1678 }
1679 
1680 
1681 
1682 /* ################################## SysTick function ############################################ */
1683 
1684 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
1685 
1696 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
1697 {
1698  if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1699 
1700  SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1701  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
1702  SysTick->VAL = 0; /* Load the SysTick Counter Value */
1705  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1706  return (0); /* Function successful */
1707 }
1708 
1709 #endif
1710 
1711 
1712 
1713 
1714 /* ################################## Reset function ############################################ */
1715 
1721 static __INLINE void NVIC_SystemReset(void)
1722 {
1723  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1724  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1725  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1726  __DSB(); /* Ensure completion of memory access */
1727  while(1); /* wait until reset */
1728 }
1729  /* end of group CMSIS_CM3_Core_FunctionInterface */
1731 
1732 
1733 
1734 /* ##################################### Debug In/Output function ########################################### */
1735 
1743 
1744 extern volatile int ITM_RxBuffer;
1745 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5
1758 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
1759 {
1760  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
1761  (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1762  (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
1763  {
1764  while (ITM->PORT[0].u32 == 0);
1765  ITM->PORT[0].u8 = (uint8_t) ch;
1766  }
1767  return (ch);
1768 }
1769 
1770 
1780 static __INLINE int ITM_ReceiveChar (void) {
1781  int ch = -1; /* no character available */
1782 
1783  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1784  ch = ITM_RxBuffer;
1785  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1786  }
1787 
1788  return (ch);
1789 }
1790 
1791 
1800 static __INLINE int ITM_CheckChar (void) {
1801 
1802  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1803  return (0); /* no character available */
1804  } else {
1805  return (1); /* character available */
1806  }
1807 }
1808  /* end of group CMSIS_CM3_core_DebugInterface */
1810 
1811 
1812 #ifdef __cplusplus
1813 }
1814 #endif
1815  /* end of group CMSIS_CM3_core_definitions */
1817 
1818 #endif /* __CM3_CORE_H__ */
1819 
1820 /*lint -restore */
static __INLINE int ITM_ReceiveChar(void)
Inputs a character via variable ITM_RxBuffer.
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Read the interrupt pending bit for a device specific interrupt source.
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:309
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:334
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:186
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
Initialize and start the SysTick counter and its interrupt.
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set the pending bit for an external interrupt.
volatile int ITM_RxBuffer
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear the pending bit for an external interrupt.
static __INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode the priority of an interrupt.
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt in NVIC Interrupt Controller.
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:439
Structure type to access the Core Debug Register (CoreDebug).
static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get the Priority Grouping from NVIC Interrupt Controller.
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Read the priority for an interrupt.
static volatile uint8_t addr
Definition: drv_i2c.c:95
static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Read the active bit for an external interrupt.
static __INLINE void NVIC_SystemReset(void)
Initiate a system reset request.
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set the priority for an interrupt.
static __INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode the priority for an interrupt.
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable the interrupt line for external interrupt specified.
uint16_t u16
Definition: stm32f4xx.h:691
static __INLINE int ITM_CheckChar(void)
Check if a character via variable ITM_RxBuffer is available.
uint32_t u32
Definition: stm32f4xx.h:690
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set the Priority Grouping in NVIC Interrupt Controller.
uint8_t u8
Definition: stm32f4xx.h:692


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:18