core_sc300.h
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1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_SC300_H_GENERIC
43 #define __CORE_SC300_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
63 /*******************************************************************************
64  * CMSIS definitions
65  ******************************************************************************/
70 /* CMSIS SC300 definitions */
71 #define __SC300_CMSIS_VERSION_MAIN (0x04)
72 #define __SC300_CMSIS_VERSION_SUB (0x00)
73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
74  __SC300_CMSIS_VERSION_SUB )
76 #define __CORTEX_SC (300)
79 #if defined ( __CC_ARM )
80  #define __ASM __asm
81  #define __INLINE __inline
82  #define __STATIC_INLINE static __inline
83 
84 #elif defined ( __GNUC__ )
85  #define __ASM __asm
86  #define __INLINE inline
87  #define __STATIC_INLINE static inline
88 
89 #elif defined ( __ICCARM__ )
90  #define __ASM __asm
91  #define __INLINE inline
92  #define __STATIC_INLINE static inline
93 
94 #elif defined ( __TMS470__ )
95  #define __ASM __asm
96  #define __STATIC_INLINE static inline
97 
98 #elif defined ( __TASKING__ )
99  #define __ASM __asm
100  #define __INLINE inline
101  #define __STATIC_INLINE static inline
102 
103 #elif defined ( __CSMC__ )
104  #define __packed
105  #define __ASM _asm
106  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107  #define __STATIC_INLINE static inline
108 
109 #endif
110 
114 #define __FPU_USED 0
115 
116 #if defined ( __CC_ARM )
117  #if defined __TARGET_FPU_VFP
118  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119  #endif
120 
121 #elif defined ( __GNUC__ )
122  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124  #endif
125 
126 #elif defined ( __ICCARM__ )
127  #if defined __ARMVFP__
128  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined ( __TMS470__ )
132  #if defined __TI__VFP_SUPPORT____
133  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __TASKING__ )
137  #if defined __FPU_VFP__
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __CSMC__ ) /* Cosmic */
142  #if ( __CSMC__ & 0x400) // FPU present for parser
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 #endif
146 
147 #include <stdint.h> /* standard types definitions */
148 #include <core_cmInstr.h> /* Core Instruction Access */
149 #include <core_cmFunc.h> /* Core Function Access */
150 
151 #ifdef __cplusplus
152 }
153 #endif
154 
155 #endif /* __CORE_SC300_H_GENERIC */
156 
157 #ifndef __CMSIS_GENERIC
158 
159 #ifndef __CORE_SC300_H_DEPENDANT
160 #define __CORE_SC300_H_DEPENDANT
161 
162 #ifdef __cplusplus
163  extern "C" {
164 #endif
165 
166 /* check device defines and use defaults */
167 #if defined __CHECK_DEVICE_DEFINES
168  #ifndef __SC300_REV
169  #define __SC300_REV 0x0000
170  #warning "__SC300_REV not defined in device header file; using default!"
171  #endif
172 
173  #ifndef __MPU_PRESENT
174  #define __MPU_PRESENT 0
175  #warning "__MPU_PRESENT not defined in device header file; using default!"
176  #endif
177 
178  #ifndef __NVIC_PRIO_BITS
179  #define __NVIC_PRIO_BITS 4
180  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
181  #endif
182 
183  #ifndef __Vendor_SysTickConfig
184  #define __Vendor_SysTickConfig 0
185  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
186  #endif
187 #endif
188 
189 /* IO definitions (access restrictions to peripheral registers) */
197 #ifdef __cplusplus
198  #define __I volatile
199 #else
200  #define __I volatile const
201 #endif
202 #define __O volatile
203 #define __IO volatile
205 
209 /*******************************************************************************
210  * Register Abstraction
211  Core Register contain:
212  - Core Register
213  - Core NVIC Register
214  - Core SCB Register
215  - Core SysTick Register
216  - Core Debug Register
217  - Core MPU Register
218  ******************************************************************************/
219 
231 typedef union
232 {
233  struct
234  {
235 #if (__CORTEX_M != 0x04)
236  uint32_t _reserved0:27;
237 #else
238  uint32_t _reserved0:16;
239  uint32_t GE:4;
240  uint32_t _reserved1:7;
241 #endif
242  uint32_t Q:1;
243  uint32_t V:1;
244  uint32_t C:1;
245  uint32_t Z:1;
246  uint32_t N:1;
247  } b;
248  uint32_t w;
249 } APSR_Type;
250 
251 
254 typedef union
255 {
256  struct
257  {
258  uint32_t ISR:9;
259  uint32_t _reserved0:23;
260  } b;
261  uint32_t w;
262 } IPSR_Type;
263 
264 
267 typedef union
268 {
269  struct
270  {
271  uint32_t ISR:9;
272 #if (__CORTEX_M != 0x04)
273  uint32_t _reserved0:15;
274 #else
275  uint32_t _reserved0:7;
276  uint32_t GE:4;
277  uint32_t _reserved1:4;
278 #endif
279  uint32_t T:1;
280  uint32_t IT:2;
281  uint32_t Q:1;
282  uint32_t V:1;
283  uint32_t C:1;
284  uint32_t Z:1;
285  uint32_t N:1;
286  } b;
287  uint32_t w;
288 } xPSR_Type;
289 
290 
293 typedef union
294 {
295  struct
296  {
297  uint32_t nPRIV:1;
298  uint32_t SPSEL:1;
299  uint32_t FPCA:1;
300  uint32_t _reserved0:29;
301  } b;
302  uint32_t w;
303 } CONTROL_Type;
304 
316 typedef struct
317 {
318  __IO uint32_t ISER[8];
319  uint32_t RESERVED0[24];
320  __IO uint32_t ICER[8];
321  uint32_t RSERVED1[24];
322  __IO uint32_t ISPR[8];
323  uint32_t RESERVED2[24];
324  __IO uint32_t ICPR[8];
325  uint32_t RESERVED3[24];
326  __IO uint32_t IABR[8];
327  uint32_t RESERVED4[56];
328  __IO uint8_t IP[240];
329  uint32_t RESERVED5[644];
330  __O uint32_t STIR;
331 } NVIC_Type;
332 
333 /* Software Triggered Interrupt Register Definitions */
334 #define NVIC_STIR_INTID_Pos 0
335 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
337 
348 typedef struct
349 {
350  __I uint32_t CPUID;
351  __IO uint32_t ICSR;
352  __IO uint32_t VTOR;
353  __IO uint32_t AIRCR;
354  __IO uint32_t SCR;
355  __IO uint32_t CCR;
356  __IO uint8_t SHP[12];
357  __IO uint32_t SHCSR;
358  __IO uint32_t CFSR;
359  __IO uint32_t HFSR;
360  __IO uint32_t DFSR;
361  __IO uint32_t MMFAR;
362  __IO uint32_t BFAR;
363  __IO uint32_t AFSR;
364  __I uint32_t PFR[2];
365  __I uint32_t DFR;
366  __I uint32_t ADR;
367  __I uint32_t MMFR[4];
368  __I uint32_t ISAR[5];
369  uint32_t RESERVED0[5];
370  __IO uint32_t CPACR;
371 } SCB_Type;
372 
373 /* SCB CPUID Register Definitions */
374 #define SCB_CPUID_IMPLEMENTER_Pos 24
375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
377 #define SCB_CPUID_VARIANT_Pos 20
378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
380 #define SCB_CPUID_ARCHITECTURE_Pos 16
381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
383 #define SCB_CPUID_PARTNO_Pos 4
384 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
386 #define SCB_CPUID_REVISION_Pos 0
387 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
389 /* SCB Interrupt Control State Register Definitions */
390 #define SCB_ICSR_NMIPENDSET_Pos 31
391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
393 #define SCB_ICSR_PENDSVSET_Pos 28
394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
396 #define SCB_ICSR_PENDSVCLR_Pos 27
397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
399 #define SCB_ICSR_PENDSTSET_Pos 26
400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
402 #define SCB_ICSR_PENDSTCLR_Pos 25
403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
405 #define SCB_ICSR_ISRPREEMPT_Pos 23
406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
408 #define SCB_ICSR_ISRPENDING_Pos 22
409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
411 #define SCB_ICSR_VECTPENDING_Pos 12
412 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
414 #define SCB_ICSR_RETTOBASE_Pos 11
415 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
417 #define SCB_ICSR_VECTACTIVE_Pos 0
418 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
420 /* SCB Vector Table Offset Register Definitions */
421 #define SCB_VTOR_TBLBASE_Pos 29
422 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
424 #define SCB_VTOR_TBLOFF_Pos 7
425 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
427 /* SCB Application Interrupt and Reset Control Register Definitions */
428 #define SCB_AIRCR_VECTKEY_Pos 16
429 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
431 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
432 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
434 #define SCB_AIRCR_ENDIANESS_Pos 15
435 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
437 #define SCB_AIRCR_PRIGROUP_Pos 8
438 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
440 #define SCB_AIRCR_SYSRESETREQ_Pos 2
441 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
443 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
444 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
446 #define SCB_AIRCR_VECTRESET_Pos 0
447 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
449 /* SCB System Control Register Definitions */
450 #define SCB_SCR_SEVONPEND_Pos 4
451 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
453 #define SCB_SCR_SLEEPDEEP_Pos 2
454 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
456 #define SCB_SCR_SLEEPONEXIT_Pos 1
457 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
459 /* SCB Configuration Control Register Definitions */
460 #define SCB_CCR_STKALIGN_Pos 9
461 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
463 #define SCB_CCR_BFHFNMIGN_Pos 8
464 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
466 #define SCB_CCR_DIV_0_TRP_Pos 4
467 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
469 #define SCB_CCR_UNALIGN_TRP_Pos 3
470 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
472 #define SCB_CCR_USERSETMPEND_Pos 1
473 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
475 #define SCB_CCR_NONBASETHRDENA_Pos 0
476 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
478 /* SCB System Handler Control and State Register Definitions */
479 #define SCB_SHCSR_USGFAULTENA_Pos 18
480 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
482 #define SCB_SHCSR_BUSFAULTENA_Pos 17
483 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
485 #define SCB_SHCSR_MEMFAULTENA_Pos 16
486 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
488 #define SCB_SHCSR_SVCALLPENDED_Pos 15
489 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
491 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14
492 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
494 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13
495 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
497 #define SCB_SHCSR_USGFAULTPENDED_Pos 12
498 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
500 #define SCB_SHCSR_SYSTICKACT_Pos 11
501 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
503 #define SCB_SHCSR_PENDSVACT_Pos 10
504 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
506 #define SCB_SHCSR_MONITORACT_Pos 8
507 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
509 #define SCB_SHCSR_SVCALLACT_Pos 7
510 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
512 #define SCB_SHCSR_USGFAULTACT_Pos 3
513 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
515 #define SCB_SHCSR_BUSFAULTACT_Pos 1
516 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
518 #define SCB_SHCSR_MEMFAULTACT_Pos 0
519 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
521 /* SCB Configurable Fault Status Registers Definitions */
522 #define SCB_CFSR_USGFAULTSR_Pos 16
523 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
525 #define SCB_CFSR_BUSFAULTSR_Pos 8
526 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
528 #define SCB_CFSR_MEMFAULTSR_Pos 0
529 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
531 /* SCB Hard Fault Status Registers Definitions */
532 #define SCB_HFSR_DEBUGEVT_Pos 31
533 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
535 #define SCB_HFSR_FORCED_Pos 30
536 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
538 #define SCB_HFSR_VECTTBL_Pos 1
539 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
541 /* SCB Debug Fault Status Register Definitions */
542 #define SCB_DFSR_EXTERNAL_Pos 4
543 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
545 #define SCB_DFSR_VCATCH_Pos 3
546 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
548 #define SCB_DFSR_DWTTRAP_Pos 2
549 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
551 #define SCB_DFSR_BKPT_Pos 1
552 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
554 #define SCB_DFSR_HALTED_Pos 0
555 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)
557 
568 typedef struct
569 {
570  uint32_t RESERVED0[1];
571  __I uint32_t ICTR;
572  uint32_t RESERVED1[1];
573 } SCnSCB_Type;
574 
575 /* Interrupt Controller Type Register Definitions */
576 #define SCnSCB_ICTR_INTLINESNUM_Pos 0
577 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
579 
590 typedef struct
591 {
592  __IO uint32_t CTRL;
593  __IO uint32_t LOAD;
594  __IO uint32_t VAL;
595  __I uint32_t CALIB;
596 } SysTick_Type;
597 
598 /* SysTick Control / Status Register Definitions */
599 #define SysTick_CTRL_COUNTFLAG_Pos 16
600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
602 #define SysTick_CTRL_CLKSOURCE_Pos 2
603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
605 #define SysTick_CTRL_TICKINT_Pos 1
606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
608 #define SysTick_CTRL_ENABLE_Pos 0
609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
611 /* SysTick Reload Register Definitions */
612 #define SysTick_LOAD_RELOAD_Pos 0
613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
615 /* SysTick Current Register Definitions */
616 #define SysTick_VAL_CURRENT_Pos 0
617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
619 /* SysTick Calibration Register Definitions */
620 #define SysTick_CALIB_NOREF_Pos 31
621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
623 #define SysTick_CALIB_SKEW_Pos 30
624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
626 #define SysTick_CALIB_TENMS_Pos 0
627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
629 
640 typedef struct
641 {
642  __O union
643  {
644  __O uint8_t u8;
645  __O uint16_t u16;
646  __O uint32_t u32;
647  } PORT [32];
648  uint32_t RESERVED0[864];
649  __IO uint32_t TER;
650  uint32_t RESERVED1[15];
651  __IO uint32_t TPR;
652  uint32_t RESERVED2[15];
653  __IO uint32_t TCR;
654  uint32_t RESERVED3[29];
655  __O uint32_t IWR;
656  __I uint32_t IRR;
657  __IO uint32_t IMCR;
658  uint32_t RESERVED4[43];
659  __O uint32_t LAR;
660  __I uint32_t LSR;
661  uint32_t RESERVED5[6];
662  __I uint32_t PID4;
663  __I uint32_t PID5;
664  __I uint32_t PID6;
665  __I uint32_t PID7;
666  __I uint32_t PID0;
667  __I uint32_t PID1;
668  __I uint32_t PID2;
669  __I uint32_t PID3;
670  __I uint32_t CID0;
671  __I uint32_t CID1;
672  __I uint32_t CID2;
673  __I uint32_t CID3;
674 } ITM_Type;
675 
676 /* ITM Trace Privilege Register Definitions */
677 #define ITM_TPR_PRIVMASK_Pos 0
678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos)
680 /* ITM Trace Control Register Definitions */
681 #define ITM_TCR_BUSY_Pos 23
682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
684 #define ITM_TCR_TraceBusID_Pos 16
685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
687 #define ITM_TCR_GTSFREQ_Pos 10
688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
690 #define ITM_TCR_TSPrescale_Pos 8
691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
693 #define ITM_TCR_SWOENA_Pos 4
694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
696 #define ITM_TCR_DWTENA_Pos 3
697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
699 #define ITM_TCR_SYNCENA_Pos 2
700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
702 #define ITM_TCR_TSENA_Pos 1
703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
705 #define ITM_TCR_ITMENA_Pos 0
706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos)
708 /* ITM Integration Write Register Definitions */
709 #define ITM_IWR_ATVALIDM_Pos 0
710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos)
712 /* ITM Integration Read Register Definitions */
713 #define ITM_IRR_ATREADYM_Pos 0
714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos)
716 /* ITM Integration Mode Control Register Definitions */
717 #define ITM_IMCR_INTEGRATION_Pos 0
718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos)
720 /* ITM Lock Status Register Definitions */
721 #define ITM_LSR_ByteAcc_Pos 2
722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
724 #define ITM_LSR_Access_Pos 1
725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
727 #define ITM_LSR_Present_Pos 0
728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos)
730  /* end of group CMSIS_ITM */
731 
732 
741 typedef struct
742 {
743  __IO uint32_t CTRL;
744  __IO uint32_t CYCCNT;
745  __IO uint32_t CPICNT;
746  __IO uint32_t EXCCNT;
747  __IO uint32_t SLEEPCNT;
748  __IO uint32_t LSUCNT;
749  __IO uint32_t FOLDCNT;
750  __I uint32_t PCSR;
751  __IO uint32_t COMP0;
752  __IO uint32_t MASK0;
753  __IO uint32_t FUNCTION0;
754  uint32_t RESERVED0[1];
755  __IO uint32_t COMP1;
756  __IO uint32_t MASK1;
757  __IO uint32_t FUNCTION1;
758  uint32_t RESERVED1[1];
759  __IO uint32_t COMP2;
760  __IO uint32_t MASK2;
761  __IO uint32_t FUNCTION2;
762  uint32_t RESERVED2[1];
763  __IO uint32_t COMP3;
764  __IO uint32_t MASK3;
765  __IO uint32_t FUNCTION3;
766 } DWT_Type;
767 
768 /* DWT Control Register Definitions */
769 #define DWT_CTRL_NUMCOMP_Pos 28
770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
772 #define DWT_CTRL_NOTRCPKT_Pos 27
773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
775 #define DWT_CTRL_NOEXTTRIG_Pos 26
776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
778 #define DWT_CTRL_NOCYCCNT_Pos 25
779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
781 #define DWT_CTRL_NOPRFCNT_Pos 24
782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
784 #define DWT_CTRL_CYCEVTENA_Pos 22
785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
787 #define DWT_CTRL_FOLDEVTENA_Pos 21
788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
790 #define DWT_CTRL_LSUEVTENA_Pos 20
791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
793 #define DWT_CTRL_SLEEPEVTENA_Pos 19
794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
796 #define DWT_CTRL_EXCEVTENA_Pos 18
797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
799 #define DWT_CTRL_CPIEVTENA_Pos 17
800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
802 #define DWT_CTRL_EXCTRCENA_Pos 16
803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
805 #define DWT_CTRL_PCSAMPLENA_Pos 12
806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
808 #define DWT_CTRL_SYNCTAP_Pos 10
809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
811 #define DWT_CTRL_CYCTAP_Pos 9
812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
814 #define DWT_CTRL_POSTINIT_Pos 5
815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
817 #define DWT_CTRL_POSTPRESET_Pos 1
818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
820 #define DWT_CTRL_CYCCNTENA_Pos 0
821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
823 /* DWT CPI Count Register Definitions */
824 #define DWT_CPICNT_CPICNT_Pos 0
825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos)
827 /* DWT Exception Overhead Count Register Definitions */
828 #define DWT_EXCCNT_EXCCNT_Pos 0
829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
831 /* DWT Sleep Count Register Definitions */
832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0
833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
835 /* DWT LSU Count Register Definitions */
836 #define DWT_LSUCNT_LSUCNT_Pos 0
837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
839 /* DWT Folded-instruction Count Register Definitions */
840 #define DWT_FOLDCNT_FOLDCNT_Pos 0
841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
843 /* DWT Comparator Mask Register Definitions */
844 #define DWT_MASK_MASK_Pos 0
845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos)
847 /* DWT Comparator Function Register Definitions */
848 #define DWT_FUNCTION_MATCHED_Pos 24
849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
851 #define DWT_FUNCTION_DATAVADDR1_Pos 16
852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
854 #define DWT_FUNCTION_DATAVADDR0_Pos 12
855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
857 #define DWT_FUNCTION_DATAVSIZE_Pos 10
858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
860 #define DWT_FUNCTION_LNK1ENA_Pos 9
861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
863 #define DWT_FUNCTION_DATAVMATCH_Pos 8
864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
866 #define DWT_FUNCTION_CYCMATCH_Pos 7
867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
869 #define DWT_FUNCTION_EMITRANGE_Pos 5
870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
872 #define DWT_FUNCTION_FUNCTION_Pos 0
873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
875  /* end of group CMSIS_DWT */
876 
877 
886 typedef struct
887 {
888  __IO uint32_t SSPSR;
889  __IO uint32_t CSPSR;
890  uint32_t RESERVED0[2];
891  __IO uint32_t ACPR;
892  uint32_t RESERVED1[55];
893  __IO uint32_t SPPR;
894  uint32_t RESERVED2[131];
895  __I uint32_t FFSR;
896  __IO uint32_t FFCR;
897  __I uint32_t FSCR;
898  uint32_t RESERVED3[759];
899  __I uint32_t TRIGGER;
900  __I uint32_t FIFO0;
901  __I uint32_t ITATBCTR2;
902  uint32_t RESERVED4[1];
903  __I uint32_t ITATBCTR0;
904  __I uint32_t FIFO1;
905  __IO uint32_t ITCTRL;
906  uint32_t RESERVED5[39];
907  __IO uint32_t CLAIMSET;
908  __IO uint32_t CLAIMCLR;
909  uint32_t RESERVED7[8];
910  __I uint32_t DEVID;
911  __I uint32_t DEVTYPE;
912 } TPI_Type;
913 
914 /* TPI Asynchronous Clock Prescaler Register Definitions */
915 #define TPI_ACPR_PRESCALER_Pos 0
916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
918 /* TPI Selected Pin Protocol Register Definitions */
919 #define TPI_SPPR_TXMODE_Pos 0
920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
922 /* TPI Formatter and Flush Status Register Definitions */
923 #define TPI_FFSR_FtNonStop_Pos 3
924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
926 #define TPI_FFSR_TCPresent_Pos 2
927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
929 #define TPI_FFSR_FtStopped_Pos 1
930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
932 #define TPI_FFSR_FlInProg_Pos 0
933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
935 /* TPI Formatter and Flush Control Register Definitions */
936 #define TPI_FFCR_TrigIn_Pos 8
937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
939 #define TPI_FFCR_EnFCont_Pos 1
940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
942 /* TPI TRIGGER Register Definitions */
943 #define TPI_TRIGGER_TRIGGER_Pos 0
944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
946 /* TPI Integration ETM Data Register Definitions (FIFO0) */
947 #define TPI_FIFO0_ITM_ATVALID_Pos 29
948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
950 #define TPI_FIFO0_ITM_bytecount_Pos 27
951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
953 #define TPI_FIFO0_ETM_ATVALID_Pos 26
954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
956 #define TPI_FIFO0_ETM_bytecount_Pos 24
957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
959 #define TPI_FIFO0_ETM2_Pos 16
960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
962 #define TPI_FIFO0_ETM1_Pos 8
963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
965 #define TPI_FIFO0_ETM0_Pos 0
966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
968 /* TPI ITATBCTR2 Register Definitions */
969 #define TPI_ITATBCTR2_ATREADY_Pos 0
970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
972 /* TPI Integration ITM Data Register Definitions (FIFO1) */
973 #define TPI_FIFO1_ITM_ATVALID_Pos 29
974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
976 #define TPI_FIFO1_ITM_bytecount_Pos 27
977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
979 #define TPI_FIFO1_ETM_ATVALID_Pos 26
980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
982 #define TPI_FIFO1_ETM_bytecount_Pos 24
983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
985 #define TPI_FIFO1_ITM2_Pos 16
986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
988 #define TPI_FIFO1_ITM1_Pos 8
989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
991 #define TPI_FIFO1_ITM0_Pos 0
992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
994 /* TPI ITATBCTR0 Register Definitions */
995 #define TPI_ITATBCTR0_ATREADY_Pos 0
996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
998 /* TPI Integration Mode Control Register Definitions */
999 #define TPI_ITCTRL_Mode_Pos 0
1000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
1002 /* TPI DEVID Register Definitions */
1003 #define TPI_DEVID_NRZVALID_Pos 11
1004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1006 #define TPI_DEVID_MANCVALID_Pos 10
1007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1009 #define TPI_DEVID_PTINVALID_Pos 9
1010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1012 #define TPI_DEVID_MinBufSz_Pos 6
1013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1015 #define TPI_DEVID_AsynClkIn_Pos 5
1016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1018 #define TPI_DEVID_NrTraceInput_Pos 0
1019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
1021 /* TPI DEVTYPE Register Definitions */
1022 #define TPI_DEVTYPE_SubType_Pos 0
1023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
1025 #define TPI_DEVTYPE_MajorType_Pos 4
1026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1028  /* end of group CMSIS_TPI */
1029 
1030 
1031 #if (__MPU_PRESENT == 1)
1032 
1040 typedef struct
1041 {
1042  __I uint32_t TYPE;
1043  __IO uint32_t CTRL;
1044  __IO uint32_t RNR;
1045  __IO uint32_t RBAR;
1046  __IO uint32_t RASR;
1047  __IO uint32_t RBAR_A1;
1048  __IO uint32_t RASR_A1;
1049  __IO uint32_t RBAR_A2;
1050  __IO uint32_t RASR_A2;
1051  __IO uint32_t RBAR_A3;
1052  __IO uint32_t RASR_A3;
1053 } MPU_Type;
1054 
1055 /* MPU Type Register */
1056 #define MPU_TYPE_IREGION_Pos 16
1057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1059 #define MPU_TYPE_DREGION_Pos 8
1060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1062 #define MPU_TYPE_SEPARATE_Pos 0
1063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
1065 /* MPU Control Register */
1066 #define MPU_CTRL_PRIVDEFENA_Pos 2
1067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1069 #define MPU_CTRL_HFNMIENA_Pos 1
1070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1072 #define MPU_CTRL_ENABLE_Pos 0
1073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
1075 /* MPU Region Number Register */
1076 #define MPU_RNR_REGION_Pos 0
1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
1079 /* MPU Region Base Address Register */
1080 #define MPU_RBAR_ADDR_Pos 5
1081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1083 #define MPU_RBAR_VALID_Pos 4
1084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1086 #define MPU_RBAR_REGION_Pos 0
1087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
1089 /* MPU Region Attribute and Size Register */
1090 #define MPU_RASR_ATTRS_Pos 16
1091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1093 #define MPU_RASR_XN_Pos 28
1094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1096 #define MPU_RASR_AP_Pos 24
1097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1099 #define MPU_RASR_TEX_Pos 19
1100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1102 #define MPU_RASR_S_Pos 18
1103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1105 #define MPU_RASR_C_Pos 17
1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1108 #define MPU_RASR_B_Pos 16
1109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1111 #define MPU_RASR_SRD_Pos 8
1112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1114 #define MPU_RASR_SIZE_Pos 1
1115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1117 #define MPU_RASR_ENABLE_Pos 0
1118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
1120 
1121 #endif
1122 
1123 
1132 typedef struct
1133 {
1134  __IO uint32_t DHCSR;
1135  __O uint32_t DCRSR;
1136  __IO uint32_t DCRDR;
1137  __IO uint32_t DEMCR;
1138 } CoreDebug_Type;
1139 
1140 /* Debug Halting Control and Status Register */
1141 #define CoreDebug_DHCSR_DBGKEY_Pos 16
1142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25
1145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
1148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19
1151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18
1154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1156 #define CoreDebug_DHCSR_S_HALT_Pos 17
1157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16
1160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
1163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3
1166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1168 #define CoreDebug_DHCSR_C_STEP_Pos 2
1169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1171 #define CoreDebug_DHCSR_C_HALT_Pos 1
1172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0
1175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
1177 /* Debug Core Register Selector Register */
1178 #define CoreDebug_DCRSR_REGWnR_Pos 16
1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1181 #define CoreDebug_DCRSR_REGSEL_Pos 0
1182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
1184 /* Debug Exception and Monitor Control Register */
1185 #define CoreDebug_DEMCR_TRCENA_Pos 24
1186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1188 #define CoreDebug_DEMCR_MON_REQ_Pos 19
1189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1191 #define CoreDebug_DEMCR_MON_STEP_Pos 18
1192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1194 #define CoreDebug_DEMCR_MON_PEND_Pos 17
1195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1197 #define CoreDebug_DEMCR_MON_EN_Pos 16
1198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10
1201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9
1204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8
1207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7
1210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6
1213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5
1216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4
1219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0
1222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
1224 
1233 /* Memory mapping of Cortex-M3 Hardware */
1234 #define SCS_BASE (0xE000E000UL)
1235 #define ITM_BASE (0xE0000000UL)
1236 #define DWT_BASE (0xE0001000UL)
1237 #define TPI_BASE (0xE0040000UL)
1238 #define CoreDebug_BASE (0xE000EDF0UL)
1239 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1240 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1241 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1244 #define SCB ((SCB_Type *) SCB_BASE )
1245 #define SysTick ((SysTick_Type *) SysTick_BASE )
1246 #define NVIC ((NVIC_Type *) NVIC_BASE )
1247 #define ITM ((ITM_Type *) ITM_BASE )
1248 #define DWT ((DWT_Type *) DWT_BASE )
1249 #define TPI ((TPI_Type *) TPI_BASE )
1250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1252 #if (__MPU_PRESENT == 1)
1253  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1254  #define MPU ((MPU_Type *) MPU_BASE )
1255 #endif
1256 
1261 /*******************************************************************************
1262  * Hardware Abstraction Layer
1263  Core Function Interface contains:
1264  - Core NVIC Functions
1265  - Core SysTick Functions
1266  - Core Debug Functions
1267  - Core Register Access Functions
1268  ******************************************************************************/
1274 /* ########################## NVIC functions #################################### */
1291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1292 {
1293  uint32_t reg_value;
1294  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1295 
1296  reg_value = SCB->AIRCR; /* read old register configuration */
1297  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1298  reg_value = (reg_value |
1299  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1300  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1301  SCB->AIRCR = reg_value;
1302 }
1303 
1304 
1311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1312 {
1313  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1314 }
1315 
1316 
1323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1324 {
1325  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1326 }
1327 
1328 
1335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1336 {
1337  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1338 }
1339 
1340 
1351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1352 {
1353  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1354 }
1355 
1356 
1363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1364 {
1365  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1366 }
1367 
1368 
1375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1376 {
1377  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1378 }
1379 
1380 
1390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1391 {
1392  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1393 }
1394 
1395 
1405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1406 {
1407  if(IRQn < 0) {
1408  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1409  else {
1410  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1411 }
1412 
1413 
1425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1426 {
1427 
1428  if(IRQn < 0) {
1429  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1430  else {
1431  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1432 }
1433 
1434 
1447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1448 {
1449  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1450  uint32_t PreemptPriorityBits;
1451  uint32_t SubPriorityBits;
1452 
1453  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1454  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1455 
1456  return (
1457  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1458  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1459  );
1460 }
1461 
1462 
1475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1476 {
1477  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1478  uint32_t PreemptPriorityBits;
1479  uint32_t SubPriorityBits;
1480 
1481  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1482  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1483 
1484  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1485  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1486 }
1487 
1488 
1493 __STATIC_INLINE void NVIC_SystemReset(void)
1494 {
1495  __DSB(); /* Ensure all outstanding memory accesses included
1496  buffered write are completed before reset */
1497  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1498  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1499  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1500  __DSB(); /* Ensure completion of memory access */
1501  while(1); /* wait until reset */
1502 }
1503 
1508 /* ################################## SysTick function ############################################ */
1515 #if (__Vendor_SysTickConfig == 0)
1516 
1532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1533 {
1534  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1535 
1536  SysTick->LOAD = ticks - 1; /* set reload register */
1537  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1538  SysTick->VAL = 0; /* Load the SysTick Counter Value */
1541  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1542  return (0); /* Function successful */
1543 }
1544 
1545 #endif
1546 
1551 /* ##################################### Debug In/Output function ########################################### */
1558 extern volatile int32_t ITM_RxBuffer;
1559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5
1572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1573 {
1574  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1575  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1576  {
1577  while (ITM->PORT[0].u32 == 0);
1578  ITM->PORT[0].u8 = (uint8_t) ch;
1579  }
1580  return (ch);
1581 }
1582 
1583 
1591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1592  int32_t ch = -1; /* no character available */
1593 
1594  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1595  ch = ITM_RxBuffer;
1596  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1597  }
1598 
1599  return (ch);
1600 }
1601 
1602 
1610 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1611 
1612  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1613  return (0); /* no character available */
1614  } else {
1615  return (1); /* character available */
1616  }
1617 }
1618 
1624 #ifdef __cplusplus
1625 }
1626 #endif
1627 
1628 #endif /* __CORE_SC300_H_DEPENDANT */
1629 
1630 #endif /* __CMSIS_GENERIC */
CMSIS Cortex-M Core Function Access Header File.
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_sc300.h:428
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:309
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_sc300.h:603
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:334
#define ITM
Definition: core_sc300.h:1247
Structure type to access the Data Watchpoint and Trace Register (DWT).
CMSIS Cortex-M Core Instruction Access Header File.
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:186
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
#define ITM_RXBUFFER_EMPTY
Definition: core_sc300.h:1559
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:611
#define __IO
Definition: core_sc300.h:203
volatile int32_t ITM_RxBuffer
#define SysTick_CTRL_TICKINT_Msk
Definition: core_sc300.h:606
#define SCB
Definition: core_sc300.h:1244
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:556
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:439
Structure type to access the Core Debug Register (CoreDebug).
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:647
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:224
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:544
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_sc300.h:429
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:572
#define SysTick
Definition: core_sc300.h:1245
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_sc300.h:438
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:685
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:286
Structure type to access the Trace Port Interface Register (TPI).
#define NVIC
Definition: core_sc300.h:1246
#define SysTick_LOAD_RELOAD_Msk
Definition: core_sc300.h:613
#define __O
Definition: core_sc300.h:202
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode Priority.
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:584
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:596
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:247
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:260
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:633
#define SysTick_CTRL_ENABLE_Msk
Definition: core_sc300.h:609
uint16_t u16
Definition: stm32f4xx.h:691
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
#define __NVIC_PRIO_BITS
Definition: stm32f4xx.h:178
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
uint32_t u32
Definition: stm32f4xx.h:690
#define ITM_TCR_ITMENA_Msk
Definition: core_sc300.h:706
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_sc300.h:441
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
uint8_t u8
Definition: stm32f4xx.h:692
#define __I
Definition: core_sc300.h:200
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_sc300.h:437


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:18