stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_RCC_H
22 #define STM32H7xx_HAL_RCC_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
40 
48 typedef struct
49 {
50  uint32_t PLLState;
53  uint32_t PLLSource;
56  uint32_t PLLM;
59  uint32_t PLLN;
64  uint32_t PLLP;
68  uint32_t PLLQ;
71  uint32_t PLLR;
73  uint32_t PLLRGE;
75  uint32_t PLLVCOSEL;
78  uint32_t PLLFRACN;
81 }RCC_PLLInitTypeDef;
82 
86 typedef struct
87 {
88  uint32_t OscillatorType;
91  uint32_t HSEState;
94  uint32_t LSEState;
97  uint32_t HSIState;
100  uint32_t HSICalibrationValue;
104  uint32_t LSIState;
107  uint32_t HSI48State;
110  uint32_t CSIState;
113  uint32_t CSICalibrationValue;
117  RCC_PLLInitTypeDef PLL;
119 }RCC_OscInitTypeDef;
120 
124 typedef struct
125 {
126  uint32_t ClockType;
129  uint32_t SYSCLKSource;
132  uint32_t SYSCLKDivider;
135  uint32_t AHBCLKDivider;
138  uint32_t APB3CLKDivider;
141  uint32_t APB1CLKDivider;
143  uint32_t APB2CLKDivider;
145  uint32_t APB4CLKDivider;
147 }RCC_ClkInitTypeDef;
148 
153 /* Exported constants --------------------------------------------------------*/
154 
162 #define RCC_OSCILLATORTYPE_NONE (0x00000000U)
163 #define RCC_OSCILLATORTYPE_HSE (0x00000001U)
164 #define RCC_OSCILLATORTYPE_HSI (0x00000002U)
165 #define RCC_OSCILLATORTYPE_LSE (0x00000004U)
166 #define RCC_OSCILLATORTYPE_LSI (0x00000008U)
167 #define RCC_OSCILLATORTYPE_CSI (0x00000010U)
168 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
169 
177 #define RCC_HSE_OFF (0x00000000U)
178 #define RCC_HSE_ON RCC_CR_HSEON
179 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
180 #if defined(RCC_CR_HSEEXT)
181 #define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
182 #endif /* RCC_CR_HSEEXT */
183 
191 #define RCC_LSE_OFF (0x00000000U)
192 #define RCC_LSE_ON RCC_BDCR_LSEON
193 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
194 #if defined(RCC_BDCR_LSEEXT)
195 #define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
196 #endif /* RCC_BDCR_LSEEXT */
197 
205 #define RCC_HSI_OFF (0x00000000U)
206 #define RCC_HSI_ON RCC_CR_HSION
208 #define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION)
209 #define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION)
210 #define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION)
211 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION)
214 #define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value for STM32H7 rev.V and above. (0x20 value for rev.Y handled within __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST macro ) */
215 
222 #define RCC_HSI48_OFF ((uint8_t)0x00)
223 #define RCC_HSI48_ON ((uint8_t)0x01)
224 
232 #define RCC_LSI_OFF (0x00000000U)
233 #define RCC_LSI_ON RCC_CSR_LSION
234 
242 #define RCC_CSI_OFF (0x00000000U)
243 #define RCC_CSI_ON RCC_CR_CSION
244 
245 #define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value for STM32H7 rev.V and above. (0x10 value for rev.Y handled within __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macro ) */
246 
253 #define RCC_PLL_NONE (0x00000000U)
254 #define RCC_PLL_OFF (0x00000001U)
255 #define RCC_PLL_ON (0x00000002U)
256 
265 #define RCC_PLLSOURCE_HSI (0x00000000U)
266 #define RCC_PLLSOURCE_CSI (0x00000001U)
267 #define RCC_PLLSOURCE_HSE (0x00000002U)
268 #define RCC_PLLSOURCE_NONE (0x00000003U)
269 
276 #define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN
277 #define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN
278 #define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN
279 
289 #define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
290 #define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
291 #define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
292 #define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3
303 #define RCC_PLL1VCOWIDE (0x00000000U)
304 #define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL
305 
314 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U)
315 #define RCC_CLOCKTYPE_HCLK (0x00000002U)
316 #define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)
317 #define RCC_CLOCKTYPE_PCLK1 (0x00000008U)
318 #define RCC_CLOCKTYPE_PCLK2 (0x00000010U)
319 #define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)
320 
328 #define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI
329 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
330 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
331 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1
332 
340 #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI
341 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
342 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
343 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1
351 #if defined(RCC_D1CFGR_D1CPRE_DIV1)
352 #define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1
353 #define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2
354 #define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4
355 #define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8
356 #define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16
357 #define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64
358 #define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128
359 #define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256
360 #define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512
361 #else
362 #define RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1
363 #define RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2
364 #define RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4
365 #define RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8
366 #define RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16
367 #define RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64
368 #define RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128
369 #define RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256
370 #define RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512
371 #endif
372 
380 #if defined(RCC_D1CFGR_HPRE_DIV1)
381 #define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1
382 #define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2
383 #define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4
384 #define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8
385 #define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16
386 #define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64
387 #define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128
388 #define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256
389 #define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512
390 #else
391 #define RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1
392 #define RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2
393 #define RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4
394 #define RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8
395 #define RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16
396 #define RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64
397 #define RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128
398 #define RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256
399 #define RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512
400 #endif
401 
408 #if defined (RCC_D1CFGR_D1PPRE_DIV1)
409 #define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1
410 #define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2
411 #define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4
412 #define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8
413 #define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16
414 #else
415 #define RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1
416 #define RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2
417 #define RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4
418 #define RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8
419 #define RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16
420 #endif
421 
428 #if defined (RCC_D2CFGR_D2PPRE1_DIV1)
429 #define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1
430 #define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2
431 #define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4
432 #define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8
433 #define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16
434 #else
435 #define RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1
436 #define RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2
437 #define RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4
438 #define RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8
439 #define RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16
440 #endif
441 
449 #if defined (RCC_D2CFGR_D2PPRE2_DIV1)
450 #define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1
451 #define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2
452 #define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4
453 #define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8
454 #define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16
455 #else
456 #define RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1
457 #define RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2
458 #define RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4
459 #define RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8
460 #define RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16
461 #endif
462 
469 #if defined(RCC_D3CFGR_D3PPRE_DIV1)
470 #define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1
471 #define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2
472 #define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4
473 #define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8
474 #define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16
475 #else
476 #define RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1
477 #define RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2
478 #define RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4
479 #define RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8
480 #define RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16
481 #endif
482 
489 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U)
490 #define RCC_RTCCLKSOURCE_LSE (0x00000100U)
491 #define RCC_RTCCLKSOURCE_LSI (0x00000200U)
492 #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)
493 #define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)
494 #define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)
495 #define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)
496 #define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)
497 #define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)
498 #define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)
499 #define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)
500 #define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)
501 #define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)
502 #define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)
503 #define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)
504 #define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)
505 #define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)
506 #define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)
507 #define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)
508 #define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)
509 #define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)
510 #define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)
511 #define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)
512 #define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)
513 #define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)
514 #define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)
515 #define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)
516 #define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)
517 #define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)
518 #define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)
519 #define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)
520 #define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)
521 #define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)
522 #define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)
523 #define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)
524 #define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)
525 #define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)
526 #define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)
527 #define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)
528 #define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)
529 #define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)
530 #define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)
531 #define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)
532 #define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)
533 #define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)
534 #define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)
535 #define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)
536 #define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)
537 #define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)
538 #define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)
539 #define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)
540 #define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)
541 #define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)
542 #define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)
543 #define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)
544 #define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)
545 #define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)
546 #define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)
547 #define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)
548 #define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)
549 #define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)
550 #define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)
551 #define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)
552 #define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)
553 #define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)
554 
555 
564 #define RCC_MCO1 (0x00000000U)
565 #define RCC_MCO2 (0x00000001U)
566 
574 #define RCC_MCO1SOURCE_HSI (0x00000000U)
575 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
576 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
577 #define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
578 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2
579 
587 #define RCC_MCO2SOURCE_SYSCLK (0x00000000U)
588 #define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0
589 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
590 #define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
591 #define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2
592 #define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
593 
601 #define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0
602 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1
603 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
604 #define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2
605 #define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
606 #define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
607 #define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
608 #define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3
609 #define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
610 #define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
611 #define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
612 #define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
613 #define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
614 #define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
615 #define RCC_MCODIV_15 RCC_CFGR_MCO1PRE
616 
617 
625 #define RCC_IT_LSIRDY (0x00000001U)
626 #define RCC_IT_LSERDY (0x00000002U)
627 #define RCC_IT_HSIRDY (0x00000004U)
628 #define RCC_IT_HSERDY (0x00000008U)
629 #define RCC_IT_CSIRDY (0x00000010U)
630 #define RCC_IT_HSI48RDY (0x00000020U)
631 #define RCC_IT_PLLRDY (0x00000040U)
632 #define RCC_IT_PLL2RDY (0x00000080U)
633 #define RCC_IT_PLL3RDY (0x00000100U)
634 #define RCC_IT_LSECSS (0x00000200U)
635 #define RCC_IT_CSS (0x00000400U)
636 
650 /* Flags in the CR register */
651 #define RCC_FLAG_HSIRDY ((uint8_t)0x22)
652 #define RCC_FLAG_HSIDIV ((uint8_t)0x25)
653 #define RCC_FLAG_CSIRDY ((uint8_t)0x28)
654 #define RCC_FLAG_HSI48RDY ((uint8_t)0x2D)
655 #if defined(RCC_CR_D1CKRDY)
656 #define RCC_FLAG_D1CKRDY ((uint8_t)0x2E)
657 #else
658 #define RCC_FLAG_CPUCKRDY ((uint8_t)0x2E)
659 #define RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */
660 #endif /* RCC_CR_D1CKRDY */
661 #if defined(RCC_CR_D2CKRDY)
662 #define RCC_FLAG_D2CKRDY ((uint8_t)0x2F)
663 #else
664 #define RCC_FLAG_CDCKRDY ((uint8_t)0x2F)
665 #define RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */
666 #endif /* RCC_CR_D2CKRDY */
667 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
668 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
669 #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
670 #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
671 /* Flags in the BDCR register */
672 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
673 
674 /* Flags in the CSR register */
675 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
676 
677 /* Flags in the RSR register */
678 #if defined(RCC_RSR_CPURSTF)
679 #define RCC_FLAG_CPURST ((uint8_t)0x91)
680 #endif /* RCC_RSR_CPURSTF */
681 
682 #if defined(RCC_RSR_D1RSTF)
683 #define RCC_FLAG_D1RST ((uint8_t)0x93)
684 #else
685 #define RCC_FLAG_CDRST ((uint8_t)0x93)
686 #endif /* RCC_RSR_D1RSTF */
687 #if defined(RCC_RSR_D2RSTF)
688 #define RCC_FLAG_D2RST ((uint8_t)0x94)
689 #endif /* RCC_RSR_D2RSTF */
690 #define RCC_FLAG_BORRST ((uint8_t)0x95)
691 #define RCC_FLAG_PINRST ((uint8_t)0x96)
692 #define RCC_FLAG_PORRST ((uint8_t)0x97)
693 #define RCC_FLAG_SFTRST ((uint8_t)0x98)
694 #define RCC_FLAG_IWDG1RST ((uint8_t)0x9A)
695 #define RCC_FLAG_WWDG1RST ((uint8_t)0x9C)
696 #define RCC_FLAG_LPWR1RST ((uint8_t)0x9E)
697 #define RCC_FLAG_LPWR2RST ((uint8_t)0x9F)
698 
699 #if defined(DUAL_CORE)
700 #define RCC_FLAG_C1RST (RCC_FLAG_CPURST)
701 #define RCC_FLAG_C2RST ((uint8_t)0x92)
702 #define RCC_FLAG_SFTR1ST (RCC_FLAG_SFTRST)
703 #define RCC_FLAG_SFTR2ST ((uint8_t)0x99)
704 #define RCC_FLAG_WWDG2RST ((uint8_t)0x9D)
705 #define RCC_FLAG_IWDG2RST ((uint8_t)0x9B)
706 #endif /*DUAL_CORE*/
707 
708 
716 #define RCC_LSEDRIVE_LOW (0x00000000U)
717 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
718 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
719 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
727 #define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)
728 #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK
729 
737 #define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)
738 #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK
739 
740 
745 #if defined(RCC_VER_X)
746 #define HAL_RCC_REV_Y_HSITRIM_Pos (12U)
747 #define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U)
748 #define HAL_RCC_REV_Y_CSITRIM_Pos (26U)
749 #define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U)
750 #endif /* RCC_VER_X */
751 
756 /* Exported macros -----------------------------------------------------------*/
757 
767 #define __HAL_RCC_MDMA_CLK_ENABLE() do { \
768  __IO uint32_t tmpreg; \
769  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
770  /* Delay after an RCC peripheral clock enabling */ \
771  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
772  UNUSED(tmpreg); \
773  } while(0)
774 
775 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
776  __IO uint32_t tmpreg; \
777  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
778  /* Delay after an RCC peripheral clock enabling */ \
779  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
780  UNUSED(tmpreg); \
781  } while(0)
782 
783 #if defined(JPEG)
784 #define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \
785  __IO uint32_t tmpreg; \
786  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
787  /* Delay after an RCC peripheral clock enabling */ \
788  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
789  UNUSED(tmpreg); \
790  } while(0)
791 #endif /* JPEG */
792 
793 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
794  __IO uint32_t tmpreg; \
795  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
796  /* Delay after an RCC peripheral clock enabling */ \
797  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
798  UNUSED(tmpreg); \
799  } while(0)
800 
801 #if defined(QUADSPI)
802 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
803  __IO uint32_t tmpreg; \
804  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
805  /* Delay after an RCC peripheral clock enabling */ \
806  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
807  UNUSED(tmpreg); \
808  } while(0)
809 #endif /* QUADSPI */
810 #if defined(OCTOSPI1)
811 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
812  __IO uint32_t tmpreg; \
813  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
814  /* Delay after an RCC peripheral clock enabling */ \
815  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
816  UNUSED(tmpreg); \
817  } while(0)
818 #endif /* OCTOSPI1 */
819 #if defined(OCTOSPI2)
820 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
821  __IO uint32_t tmpreg; \
822  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
823  /* Delay after an RCC peripheral clock enabling */ \
824  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
825  UNUSED(tmpreg); \
826  } while(0)
827 #endif /* OCTOSPI2 */
828 #if defined(OCTOSPIM)
829 #define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \
830  __IO uint32_t tmpreg; \
831  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
832  /* Delay after an RCC peripheral clock enabling */ \
833  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
834  UNUSED(tmpreg); \
835  } while(0)
836 #endif /* OCTOSPIM */
837 #if defined(OTFDEC1)
838 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \
839  __IO uint32_t tmpreg; \
840  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
841  /* Delay after an RCC peripheral clock enabling */ \
842  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
843  UNUSED(tmpreg); \
844  } while(0)
845 #endif /* OTFDEC1 */
846 #if defined(OTFDEC2)
847 #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \
848  __IO uint32_t tmpreg; \
849  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
850  /* Delay after an RCC peripheral clock enabling */ \
851  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
852  UNUSED(tmpreg); \
853  } while(0)
854 #endif /* OTFDEC2 */
855 #if defined(GFXMMU)
856 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \
857  __IO uint32_t tmpreg; \
858  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
859  /* Delay after an RCC peripheral clock enabling */ \
860  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
861  UNUSED(tmpreg); \
862  } while(0)
863 #endif /* GFXMMU */
864 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
865  __IO uint32_t tmpreg; \
866  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
867  /* Delay after an RCC peripheral clock enabling */ \
868  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
869  UNUSED(tmpreg); \
870  } while(0)
871 
872 
873 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
874 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
875 #if defined(JPEG)
876 #define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
877 #endif /* JPEG */
878 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
879 
880 #if defined(QUADSPI)
881 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
882 #endif /* QUADSPI */
883 #if defined(OCTOSPI1)
884 #define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
885 #endif /* OCTOSPII */
886 #if defined(OCTOSPI2)
887 #define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
888 #endif /* OCTOSPI2 */
889 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
890 #if defined(OCTOSPIM)
891 #define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
892 #endif /* OCTOSPIM */
893 #if defined(OTFDEC1)
894 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
895 #endif /* OTOFDEC1 */
896 #if defined(OTFDEC2)
897 #define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
898 #endif /* OTOFDEC2 */
899 #if defined(GFXMMU)
900 #define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
901 #endif /* GFXMMU */
902 
909 #define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)
910 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)
911 #if defined(JPEG)
912 #define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
913 #endif /* JPEG */
914 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)
915 #if defined (QUADSPI)
916 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U)
917 #endif /* QUADSPI */
918 #if defined(OCTOSPI1)
919 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U)
920 #endif /* OCTOSPII */
921 #if defined(OCTOSPI2)
922 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U)
923 #endif /* OCTOSPI2 */
924 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
925 #if defined(OCTOSPIM)
926 #define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
927 #endif /* OCTOSPIM */
928 #if defined(OTFDEC1)
929 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
930 #endif /* OTOFDEC1 */
931 #if defined(OTFDEC2)
932 #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
933 #endif /* OTOFDEC2 */
934 #if defined(GFXMMU)
935 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
936 #endif /* GFXMMU */
937 
938 #define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)
939 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)
940 #if defined(JPEG)
941 #define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
942 #endif /* JPEG */
943 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)
944 #if defined (QUADSPI)
945 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U)
946 #endif /* QUADSPI */
947 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
948 #if defined(OCTOSPI1)
949 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
950 #endif
951 #if defined(OCTOSPI2)
952 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
953 #endif
954 #if defined(OCTOSPIM)
955 #define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
956 #endif
957 #if defined(OTFDEC1)
958 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
959 #endif
960 #if defined(OTFDEC2)
961 #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
962 #endif
963 #if defined(GFXMMU)
964 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
965 #endif
966 
972 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
973  __IO uint32_t tmpreg; \
974  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
975  /* Delay after an RCC peripheral clock enabling */ \
976  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
977  UNUSED(tmpreg); \
978  } while(0)
979 
980 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
981  __IO uint32_t tmpreg; \
982  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
983  /* Delay after an RCC peripheral clock enabling */ \
984  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
985  UNUSED(tmpreg); \
986  } while(0)
987 
988 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \
989  __IO uint32_t tmpreg; \
990  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
991  /* Delay after an RCC peripheral clock enabling */ \
992  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
993  UNUSED(tmpreg); \
994  } while(0)
995 
996 #if defined(DUAL_CORE)
997 #define __HAL_RCC_ART_CLK_ENABLE() do { \
998  __IO uint32_t tmpreg; \
999  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
1000  /* Delay after an RCC peripheral clock enabling */ \
1001  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
1002  UNUSED(tmpreg); \
1003  } while(0)
1004 #endif /*DUAL_CORE*/
1005 
1006 #if defined(RCC_AHB1ENR_CRCEN)
1007 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
1008  __IO uint32_t tmpreg; \
1009  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1010  /* Delay after an RCC peripheral clock enabling */ \
1011  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1012  UNUSED(tmpreg); \
1013  } while(0)
1014 #endif
1015 
1016 #if defined(ETH)
1017 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \
1018  __IO uint32_t tmpreg; \
1019  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
1020  /* Delay after an RCC peripheral clock enabling */ \
1021  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
1022  UNUSED(tmpreg); \
1023  } while(0)
1024 
1025 #define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \
1026  __IO uint32_t tmpreg; \
1027  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
1028  /* Delay after an RCC peripheral clock enabling */ \
1029  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
1030  UNUSED(tmpreg); \
1031  } while(0)
1032 
1033 #define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \
1034  __IO uint32_t tmpreg; \
1035  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
1036  /* Delay after an RCC peripheral clock enabling */ \
1037  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
1038  UNUSED(tmpreg); \
1039  } while(0)
1040 #endif
1041 
1042 #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \
1043  __IO uint32_t tmpreg; \
1044  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
1045  /* Delay after an RCC peripheral clock enabling */ \
1046  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
1047  UNUSED(tmpreg); \
1048  } while(0)
1049 
1050 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
1051  __IO uint32_t tmpreg; \
1052  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
1053  /* Delay after an RCC peripheral clock enabling */ \
1054  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
1055  UNUSED(tmpreg); \
1056  } while(0)
1057 
1058 #if defined(USB2_OTG_FS)
1059 #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \
1060  __IO uint32_t tmpreg; \
1061  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
1062  /* Delay after an RCC peripheral clock enabling */ \
1063  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
1064  UNUSED(tmpreg); \
1065  } while(0)
1066 
1067 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
1068  __IO uint32_t tmpreg; \
1069  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
1070  /* Delay after an RCC peripheral clock enabling */ \
1071  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
1072  UNUSED(tmpreg); \
1073  } while(0)
1074 #endif
1075 
1076 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
1077 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
1078 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
1079 #if defined(DUAL_CORE)
1080 #define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
1081 #endif /*DUAL_CORE*/
1082 #if defined(RCC_AHB1ENR_CRCEN)
1083 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
1084 #endif
1085 #if defined(ETH)
1086 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
1087 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
1088 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
1089 #endif
1090 #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
1091 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
1092 #if defined(USB2_OTG_FS)
1093 #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
1094 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
1095 #endif /* USB2_OTG_FS */
1096 
1103 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)
1104 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)
1105 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)
1106 #if defined(DUAL_CORE)
1107 #define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U)
1108 #endif /*DUAL_CORE*/
1109 #if defined(RCC_AHB1ENR_CRCEN)
1110 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U)
1111 #endif
1112 #if defined(ETH)
1113 #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U)
1114 #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U)
1115 #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U)
1116 #endif
1117 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)
1118 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
1119 #if defined(USB2_OTG_FS)
1120 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U)
1121 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)
1122 #endif /* USB2_OTG_FS */
1123 
1124 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)
1125 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)
1126 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)
1127 #if defined(DUAL_CORE)
1128 #define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U)
1129 #endif /*DUAL_CORE*/
1130 #if defined(RCC_AHB1ENR_CRCEN)
1131 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U)
1132 #endif
1133 #if defined(ETH)
1134 #define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U)
1135 #define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U)
1136 #define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U)
1137 #endif
1138 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)
1139 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
1140 #if defined(USB2_OTG_FS)
1141 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U)
1142 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)
1143 #endif /* USB2_OTG_FS */
1144 
1151 #if defined(DCMI) && defined(PSSI)
1152 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \
1153  __IO uint32_t tmpreg; \
1154  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
1155  /* Delay after an RCC peripheral clock enabling */ \
1156  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
1157  UNUSED(tmpreg); \
1158  } while(0)
1159 
1160 #define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/
1161 #else
1162 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
1163  __IO uint32_t tmpreg; \
1164  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1165  /* Delay after an RCC peripheral clock enabling */ \
1166  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1167  UNUSED(tmpreg); \
1168  } while(0)
1169 #endif /* DCMI && PSSI */
1170 
1171 #if defined(CRYP)
1172 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
1173  __IO uint32_t tmpreg; \
1174  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1175  /* Delay after an RCC peripheral clock enabling */ \
1176  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1177  UNUSED(tmpreg); \
1178  } while(0)
1179 #endif /* CRYP */
1180 
1181 #if defined(HASH)
1182 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
1183  __IO uint32_t tmpreg; \
1184  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1185  /* Delay after an RCC peripheral clock enabling */ \
1186  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1187  UNUSED(tmpreg); \
1188  } while(0)
1189 #endif /* HASH */
1190 
1191 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
1192  __IO uint32_t tmpreg; \
1193  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1194  /* Delay after an RCC peripheral clock enabling */ \
1195  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1196  UNUSED(tmpreg); \
1197  } while(0)
1198 
1199 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
1200  __IO uint32_t tmpreg; \
1201  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
1202  /* Delay after an RCC peripheral clock enabling */ \
1203  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
1204  UNUSED(tmpreg); \
1205  } while(0)
1206 
1207 #if defined(FMAC)
1208 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \
1209  __IO uint32_t tmpreg; \
1210  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\
1211  /* Delay after an RCC peripheral clock enabling */ \
1212  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\
1213  UNUSED(tmpreg); \
1214  } while(0)
1215 #endif /* FMAC */
1216 
1217 #if defined(CORDIC)
1218 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \
1219  __IO uint32_t tmpreg; \
1220  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
1221  /* Delay after an RCC peripheral clock enabling */ \
1222  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
1223  UNUSED(tmpreg); \
1224  } while(0)
1225 #endif /* CORDIC */
1226 
1227 #if defined(RCC_AHB2ENR_D2SRAM1EN)
1228 #define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \
1229  __IO uint32_t tmpreg; \
1230  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
1231  /* Delay after an RCC peripheral clock enabling */ \
1232  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
1233  UNUSED(tmpreg); \
1234  } while(0)
1235 #else
1236 #define __HAL_RCC_AHBSRAM1_CLK_ENABLE() do { \
1237  __IO uint32_t tmpreg; \
1238  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
1239  /* Delay after an RCC peripheral clock enabling */ \
1240  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
1241  UNUSED(tmpreg); \
1242  } while(0)
1243 #endif /* RCC_AHB2ENR_D2SRAM1EN */
1244 
1245 #if defined(RCC_AHB2ENR_D2SRAM2EN)
1246 #define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \
1247  __IO uint32_t tmpreg; \
1248  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
1249  /* Delay after an RCC peripheral clock enabling */ \
1250  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
1251  UNUSED(tmpreg); \
1252  } while(0)
1253 #else
1254 #define __HAL_RCC_AHBSRAM2_CLK_ENABLE() do { \
1255  __IO uint32_t tmpreg; \
1256  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
1257  /* Delay after an RCC peripheral clock enabling */ \
1258  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
1259  UNUSED(tmpreg); \
1260  } while(0)
1261 #endif /* RCC_AHB2ENR_D2SRAM2EN */
1262 
1263 #if defined(RCC_AHB2ENR_D2SRAM3EN)
1264 #define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \
1265  __IO uint32_t tmpreg; \
1266  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
1267  /* Delay after an RCC peripheral clock enabling */ \
1268  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
1269  UNUSED(tmpreg); \
1270  } while(0)
1271 #endif
1272 
1273 #if defined(RCC_AHB2ENR_HSEMEN)
1274 #define __HAL_RCC_HSEM_CLK_ENABLE() do { \
1275  __IO uint32_t tmpreg; \
1276  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
1277  /* Delay after an RCC peripheral clock enabling */ \
1278  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
1279  UNUSED(tmpreg); \
1280  } while(0)
1281 #endif /* RCC_AHB2ENR_HSEMEN */
1282 
1283 #if defined(BDMA1)
1284 #define __HAL_RCC_BDMA1_CLK_ENABLE() do { \
1285  __IO uint32_t tmpreg; \
1286  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
1287  /* Delay after an RCC peripheral clock enabling */ \
1288  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
1289  UNUSED(tmpreg); \
1290  } while(0)
1291 #endif /* BDMA1 */
1292 
1293 #if defined(DCMI) && defined(PSSI)
1294 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
1295 #define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/
1296 #else
1297 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
1298 #endif /* DCMI && PSSI */
1299 #if defined(CRYP)
1300 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
1301 #endif /* CRYP */
1302 #if defined(HASH)
1303 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
1304 #endif /* HASH */
1305 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
1306 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
1307 #if defined(FMAC)
1308 #define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN))
1309 #endif /* FMAC */
1310 #if defined(CORDIC)
1311 #define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN))
1312 #endif /* CORDIC */
1313 #if defined(RCC_AHB2ENR_D2SRAM1EN)
1314 #define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
1315 #else
1316 #define __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
1317 #endif /* RCC_AHB2ENR_D2SRAM1EN */
1318 #if defined(RCC_AHB2ENR_D2SRAM2EN)
1319 #define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
1320 #else
1321 #define __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
1322 #endif /* RCC_AHB2ENR_D2SRAM2EN */
1323 #if defined(RCC_AHB2ENR_D2SRAM3EN)
1324 #define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
1325 #endif
1326 #if defined(RCC_AHB2ENR_HSEMEN)
1327 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
1328 #endif
1329 #if defined(BDMA1)
1330 #define __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
1331 #endif
1332 
1339 #if defined(DCMI) && defined(PSSI)
1340 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U)
1341 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/
1342 #else
1343 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)
1344 #endif /* DCMI && PSSI */
1345 #if defined(CRYP)
1346 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)
1347 #endif /* CRYP */
1348 #if defined(HASH)
1349 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)
1350 #endif /* HASH */
1351 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)
1352 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)
1353 #if defined(FMAC)
1354 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U)
1355 #endif /* FMAC */
1356 #if defined(CORDIC)
1357 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U)
1358 #endif /* CORDIC */
1359 #if defined(RCC_AHB2ENR_D2SRAM1EN)
1360 #define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
1361 #else
1362 #define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
1363 #endif /* RCC_AHB2ENR_D2SRAM1EN */
1364 #if defined(RCC_AHB2ENR_D2SRAM2EN)
1365 #define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)
1366 #else
1367 #define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
1368 #endif /* RCC_AHB2ENR_D2SRAM2EN */
1369 #if defined(RCC_AHB2ENR_D2SRAM3EN)
1370 #define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)
1371 #endif
1372 #if defined(RCC_AHB2ENR_HSEMEN)
1373 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U)
1374 #endif
1375 #if defined(BDMA1)
1376 #define __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U)
1377 #endif
1378 
1379 #if defined(DCMI) && defined(PSSI)
1380 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U)
1381 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/
1382 #else
1383 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U)
1384 #endif /* DCMI && PSSI */
1385 #if defined(CRYP)
1386 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)
1387 #endif /* CRYP */
1388 #if defined(HASH)
1389 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)
1390 #endif /* HASH */
1391 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)
1392 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)
1393 #if defined(FMAC)
1394 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U)
1395 #endif /* FMAC */
1396 #if defined(CORDIC)
1397 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U)
1398 #endif /* CORDIC */
1399 #if defined(RCC_AHB2ENR_D2SRAM1EN)
1400 #define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
1401 #else
1402 #define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
1403 #endif /* RCC_AHB2ENR_D2SRAM1EN */
1404 #if defined(RCC_AHB2ENR_D2SRAM2EN)
1405 #define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)
1406 #else
1407 #define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
1408 #endif /* RCC_AHB2ENR_D2SRAM2EN */
1409 #if defined(RCC_AHB2ENR_D2SRAM3EN)
1410 #define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)
1411 #endif
1412 #if defined(RCC_AHB2ENR_HSEMEN)
1413 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U)
1414 #endif
1415 #if defined(BDMA1)
1416 #define __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U)
1417 #endif
1418 
1425 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
1426  __IO uint32_t tmpreg; \
1427  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
1428  /* Delay after an RCC peripheral clock enabling */ \
1429  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
1430  UNUSED(tmpreg); \
1431  } while(0)
1432 
1433 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
1434  __IO uint32_t tmpreg; \
1435  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
1436  /* Delay after an RCC peripheral clock enabling */ \
1437  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
1438  UNUSED(tmpreg); \
1439  } while(0)
1440 
1441 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
1442  __IO uint32_t tmpreg; \
1443  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
1444  /* Delay after an RCC peripheral clock enabling */ \
1445  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
1446  UNUSED(tmpreg); \
1447  } while(0)
1448 
1449 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
1450  __IO uint32_t tmpreg; \
1451  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
1452  /* Delay after an RCC peripheral clock enabling */ \
1453  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
1454  UNUSED(tmpreg); \
1455  } while(0)
1456 
1457 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1458  __IO uint32_t tmpreg; \
1459  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
1460  /* Delay after an RCC peripheral clock enabling */ \
1461  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
1462  UNUSED(tmpreg); \
1463  } while(0)
1464 
1465 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1466  __IO uint32_t tmpreg; \
1467  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
1468  /* Delay after an RCC peripheral clock enabling */ \
1469  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
1470  UNUSED(tmpreg); \
1471  } while(0)
1472 
1473 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1474  __IO uint32_t tmpreg; \
1475  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
1476  /* Delay after an RCC peripheral clock enabling */ \
1477  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
1478  UNUSED(tmpreg); \
1479  } while(0)
1480 
1481 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
1482  __IO uint32_t tmpreg; \
1483  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
1484  /* Delay after an RCC peripheral clock enabling */ \
1485  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
1486  UNUSED(tmpreg); \
1487  } while(0)
1488 
1489 #if defined(GPIOI)
1490 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
1491  __IO uint32_t tmpreg; \
1492  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
1493  /* Delay after an RCC peripheral clock enabling */ \
1494  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
1495  UNUSED(tmpreg); \
1496  } while(0)
1497 #endif /* GPIOI */
1498 
1499 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
1500  __IO uint32_t tmpreg; \
1501  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
1502  /* Delay after an RCC peripheral clock enabling */ \
1503  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
1504  UNUSED(tmpreg); \
1505  } while(0)
1506 
1507 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
1508  __IO uint32_t tmpreg; \
1509  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
1510  /* Delay after an RCC peripheral clock enabling */ \
1511  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
1512  UNUSED(tmpreg); \
1513  } while(0)
1514 
1515 #if defined(RCC_AHB4ENR_CRCEN)
1516 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
1517  __IO uint32_t tmpreg; \
1518  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
1519  /* Delay after an RCC peripheral clock enabling */ \
1520  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
1521  UNUSED(tmpreg); \
1522  } while(0)
1523 #endif
1524 
1525 #if defined(BDMA2)
1526 #define __HAL_RCC_BDMA2_CLK_ENABLE() do { \
1527  __IO uint32_t tmpreg; \
1528  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
1529  /* Delay after an RCC peripheral clock enabling */ \
1530  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
1531  UNUSED(tmpreg); \
1532  } while(0)
1533 
1534 #define __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/
1535 #else
1536 #define __HAL_RCC_BDMA_CLK_ENABLE() do { \
1537  __IO uint32_t tmpreg; \
1538  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
1539  /* Delay after an RCC peripheral clock enabling */ \
1540  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
1541  UNUSED(tmpreg); \
1542  } while(0)
1543 #endif
1544 
1545 #if defined(ADC3)
1546 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1547  __IO uint32_t tmpreg; \
1548  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
1549  /* Delay after an RCC peripheral clock enabling */ \
1550  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
1551  UNUSED(tmpreg); \
1552  } while(0)
1553 #endif
1554 
1555 #if defined(RCC_AHB4ENR_HSEMEN)
1556 #define __HAL_RCC_HSEM_CLK_ENABLE() do { \
1557  __IO uint32_t tmpreg; \
1558  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
1559  /* Delay after an RCC peripheral clock enabling */ \
1560  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
1561  UNUSED(tmpreg); \
1562  } while(0)
1563 #endif
1564 
1565 #if defined(RCC_AHB4ENR_SRDSRAMEN)
1566 #define __HAL_RCC_SRDSRAM_CLK_ENABLE() do { \
1567  __IO uint32_t tmpreg; \
1568  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
1569  /* Delay after an RCC peripheral clock enabling */ \
1570  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
1571  UNUSED(tmpreg); \
1572  } while(0)
1573 #endif
1574 
1575 #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \
1576  __IO uint32_t tmpreg; \
1577  SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
1578  /* Delay after an RCC peripheral clock enabling */ \
1579  tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
1580  UNUSED(tmpreg); \
1581  } while(0)
1582 
1583 
1584 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
1585 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
1586 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
1587 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
1588 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
1589 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
1590 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
1591 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
1592 #if defined(GPIOI)
1593 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
1594 #endif /* GPIOI */
1595 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
1596 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
1597 #if defined(RCC_AHB4ENR_CRCEN)
1598 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
1599 #endif
1600 #if defined(BDMA2)
1601 #define __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
1602 #define __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/
1603 #else
1604 #define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
1605 #endif
1606 #if defined(ADC3)
1607 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
1608 #endif
1609 #if defined(RCC_AHB4ENR_HSEMEN)
1610 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
1611 #endif
1612 #if defined(RCC_AHB4ENR_SRDSRAMEN)
1613 #define __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
1614 #endif
1615 #define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
1616 
1617 
1624 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)
1625 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)
1626 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)
1627 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)
1628 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)
1629 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)
1630 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)
1631 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)
1632 #if defined(GPIOI)
1633 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U)
1634 #endif /* GPIOI */
1635 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)
1636 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)
1637 #if defined(RCC_AHB4ENR_CRCEN)
1638 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U)
1639 #endif
1640 #if defined(BDMA2)
1641 #define __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U)
1642 #define __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/
1643 #else
1644 #define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U)
1645 #endif
1646 #if defined(ADC3)
1647 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U)
1648 #endif
1649 #if defined(RCC_AHB4ENR_HSEMEN)
1650 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U)
1651 #endif
1652 #if defined(RCC_AHB4ENR_SRDSRAMEN)
1653 #define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
1654 #endif
1655 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
1656 
1657 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)
1658 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)
1659 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)
1660 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)
1661 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)
1662 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)
1663 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)
1664 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)
1665 #if defined(GPIOI)
1666 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U)
1667 #endif /* GPIOI */
1668 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)
1669 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)
1670 
1671 #if defined(RCC_AHB4ENR_CRCEN)
1672 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U)
1673 #endif
1674 #if defined(BDMA2)
1675 #define __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U)
1676 #define __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/
1677 #else
1678 #define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U)
1679 #endif
1680 #if defined(ADC3)
1681 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U)
1682 #endif
1683 #if defined(RCC_AHB4ENR_HSEMEN)
1684 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U)
1685 #endif
1686 #if defined(RCC_AHB4ENR_SRDSRAMEN)
1687 #define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U)
1688 #endif
1689 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
1690 
1691 
1698 #if defined(LTDC)
1699 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
1700  __IO uint32_t tmpreg; \
1701  SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
1702  /* Delay after an RCC peripheral clock enabling */ \
1703  tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
1704  UNUSED(tmpreg); \
1705  } while(0)
1706 #endif /* LTDC */
1707 
1708 #if defined(DSI)
1709 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
1710  __IO uint32_t tmpreg; \
1711  SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
1712  /* Delay after an RCC peripheral clock enabling */ \
1713  tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
1714  UNUSED(tmpreg); \
1715  } while(0)
1716 #endif /*DSI*/
1717 
1718 #define __HAL_RCC_WWDG1_CLK_ENABLE() do { \
1719  __IO uint32_t tmpreg; \
1720  SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
1721  /* Delay after an RCC peripheral clock enabling */ \
1722  tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
1723  UNUSED(tmpreg); \
1724  } while(0)
1725 
1726 #if defined(LTDC)
1727 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
1728 #endif /* LTDC */
1729 #if defined(DSI)
1730 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
1731 #endif /*DSI*/
1732 #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
1733 
1740 #if defined(LTDC)
1741 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U)
1742 #endif /* LTDC */
1743 #if defined(DSI)
1744 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U)
1745 #endif /*DSI*/
1746 #define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
1747 #if defined(LTDC)
1748 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U)
1749 #endif /* LTDC */
1750 #if defined(DSI)
1751 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U)
1752 #endif /*DSI*/
1753 #define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
1754 
1755 
1762 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
1763  __IO uint32_t tmpreg; \
1764  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
1765  /* Delay after an RCC peripheral clock enabling */ \
1766  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
1767  UNUSED(tmpreg); \
1768  } while(0)
1769 
1770 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
1771  __IO uint32_t tmpreg; \
1772  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
1773  /* Delay after an RCC peripheral clock enabling */ \
1774  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
1775  UNUSED(tmpreg); \
1776  } while(0)
1777 
1778 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
1779  __IO uint32_t tmpreg; \
1780  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
1781  /* Delay after an RCC peripheral clock enabling */ \
1782  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
1783  UNUSED(tmpreg); \
1784  } while(0)
1785 
1786 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
1787  __IO uint32_t tmpreg; \
1788  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
1789  /* Delay after an RCC peripheral clock enabling */ \
1790  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
1791  UNUSED(tmpreg); \
1792  } while(0)
1793 
1794 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
1795  __IO uint32_t tmpreg; \
1796  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
1797  /* Delay after an RCC peripheral clock enabling */ \
1798  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
1799  UNUSED(tmpreg); \
1800  } while(0)
1801 
1802 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
1803  __IO uint32_t tmpreg; \
1804  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
1805  /* Delay after an RCC peripheral clock enabling */ \
1806  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
1807  UNUSED(tmpreg); \
1808  } while(0)
1809 
1810 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
1811  __IO uint32_t tmpreg; \
1812  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
1813  /* Delay after an RCC peripheral clock enabling */ \
1814  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
1815  UNUSED(tmpreg); \
1816  } while(0)
1817 
1818 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
1819  __IO uint32_t tmpreg; \
1820  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
1821  /* Delay after an RCC peripheral clock enabling */ \
1822  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
1823  UNUSED(tmpreg); \
1824  } while(0)
1825 
1826 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1827  __IO uint32_t tmpreg; \
1828  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
1829  /* Delay after an RCC peripheral clock enabling */ \
1830  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
1831  UNUSED(tmpreg); \
1832  } while(0)
1833 
1834 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
1835  __IO uint32_t tmpreg; \
1836  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
1837  /* Delay after an RCC peripheral clock enabling */ \
1838  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
1839  UNUSED(tmpreg); \
1840  } while(0)
1841 
1842 #if defined(DUAL_CORE)
1843 #define __HAL_RCC_WWDG2_CLK_ENABLE() do { \
1844  __IO uint32_t tmpreg; \
1845  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
1846  /* Delay after an RCC peripheral clock enabling */ \
1847  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
1848  UNUSED(tmpreg); \
1849  } while(0)
1850 #endif /*DUAL_CORE*/
1851 
1852 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
1853  __IO uint32_t tmpreg; \
1854  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
1855  /* Delay after an RCC peripheral clock enabling */ \
1856  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
1857  UNUSED(tmpreg); \
1858  } while(0)
1859 
1860 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
1861  __IO uint32_t tmpreg; \
1862  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
1863  /* Delay after an RCC peripheral clock enabling */ \
1864  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
1865  UNUSED(tmpreg); \
1866  } while(0)
1867 
1868 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
1869  __IO uint32_t tmpreg; \
1870  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
1871  /* Delay after an RCC peripheral clock enabling */ \
1872  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
1873  UNUSED(tmpreg); \
1874  } while(0)
1875 
1876 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
1877  __IO uint32_t tmpreg; \
1878  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
1879  /* Delay after an RCC peripheral clock enabling */ \
1880  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
1881  UNUSED(tmpreg); \
1882  } while(0)
1883 
1884 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
1885  __IO uint32_t tmpreg; \
1886  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
1887  /* Delay after an RCC peripheral clock enabling */ \
1888  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
1889  UNUSED(tmpreg); \
1890  } while(0)
1891 
1892 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
1893  __IO uint32_t tmpreg; \
1894  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
1895  /* Delay after an RCC peripheral clock enabling */ \
1896  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
1897  UNUSED(tmpreg); \
1898  } while(0)
1899 
1900 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1901  __IO uint32_t tmpreg; \
1902  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
1903  /* Delay after an RCC peripheral clock enabling */ \
1904  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
1905  UNUSED(tmpreg); \
1906  } while(0)
1907 
1908 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
1909  __IO uint32_t tmpreg; \
1910  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
1911  /* Delay after an RCC peripheral clock enabling */ \
1912  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
1913  UNUSED(tmpreg); \
1914  } while(0)
1915 
1916 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
1917  __IO uint32_t tmpreg; \
1918  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
1919  /* Delay after an RCC peripheral clock enabling */ \
1920  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
1921  UNUSED(tmpreg); \
1922  } while(0)
1923 
1924 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1925  __IO uint32_t tmpreg; \
1926  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
1927  /* Delay after an RCC peripheral clock enabling */ \
1928  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
1929  UNUSED(tmpreg); \
1930  } while(0)
1931 
1932 #if defined(I2C5)
1933 #define __HAL_RCC_I2C5_CLK_ENABLE() do { \
1934  __IO uint32_t tmpreg; \
1935  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\
1936  /* Delay after an RCC peripheral clock enabling */ \
1937  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\
1938  UNUSED(tmpreg); \
1939  } while(0)
1940 #endif /* I2C5 */
1941 
1942 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
1943  __IO uint32_t tmpreg; \
1944  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
1945  /* Delay after an RCC peripheral clock enabling */ \
1946  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
1947  UNUSED(tmpreg); \
1948  } while(0)
1949 
1950 #define __HAL_RCC_DAC12_CLK_ENABLE() do { \
1951  __IO uint32_t tmpreg; \
1952  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
1953  /* Delay after an RCC peripheral clock enabling */ \
1954  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
1955  UNUSED(tmpreg); \
1956  } while(0)
1957 
1958 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
1959  __IO uint32_t tmpreg; \
1960  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
1961  /* Delay after an RCC peripheral clock enabling */ \
1962  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
1963  UNUSED(tmpreg); \
1964  } while(0)
1965 
1966 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
1967  __IO uint32_t tmpreg; \
1968  SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
1969  /* Delay after an RCC peripheral clock enabling */ \
1970  tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
1971  UNUSED(tmpreg); \
1972  } while(0)
1973 
1974 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
1975  __IO uint32_t tmpreg; \
1976  SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
1977  /* Delay after an RCC peripheral clock enabling */ \
1978  tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
1979  UNUSED(tmpreg); \
1980  } while(0)
1981 
1982 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
1983  __IO uint32_t tmpreg; \
1984  SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
1985  /* Delay after an RCC peripheral clock enabling */ \
1986  tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
1987  UNUSED(tmpreg); \
1988  } while(0)
1989 
1990 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
1991  __IO uint32_t tmpreg; \
1992  SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
1993  /* Delay after an RCC peripheral clock enabling */ \
1994  tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
1995  UNUSED(tmpreg); \
1996  } while(0)
1997 
1998 #define __HAL_RCC_MDIOS_CLK_ENABLE() do { \
1999  __IO uint32_t tmpreg; \
2000  SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
2001  /* Delay after an RCC peripheral clock enabling */ \
2002  tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
2003  UNUSED(tmpreg); \
2004  } while(0)
2005 
2006 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
2007  __IO uint32_t tmpreg; \
2008  SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
2009  /* Delay after an RCC peripheral clock enabling */ \
2010  tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
2011  UNUSED(tmpreg); \
2012  } while(0)
2013 
2014 #if defined(TIM23)
2015 #define __HAL_RCC_TIM23_CLK_ENABLE() do { \
2016  __IO uint32_t tmpreg; \
2017  SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\
2018  /* Delay after an RCC peripheral clock enabling */ \
2019  tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\
2020  UNUSED(tmpreg); \
2021  } while(0)
2022 #endif /* TIM23 */
2023 
2024 #if defined(TIM24)
2025 #define __HAL_RCC_TIM24_CLK_ENABLE() do { \
2026  __IO uint32_t tmpreg; \
2027  SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\
2028  /* Delay after an RCC peripheral clock enabling */ \
2029  tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\
2030  UNUSED(tmpreg); \
2031  } while(0)
2032 #endif /* TIM24 */
2033 
2034 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
2035 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
2036 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
2037 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
2038 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
2039 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
2040 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
2041 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
2042 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
2043 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
2044 
2045 #if defined(DUAL_CORE)
2046 #define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
2047 #endif /*DUAL_CORE*/
2048 
2049 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
2050 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
2051 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
2052 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
2053 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
2054 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
2055 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
2056 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
2057 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
2058 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
2059 #if defined(I2C5)
2060 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN)
2061 #endif /* I2C5 */
2062 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
2063 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
2064 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
2065 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
2066 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
2067 #define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
2068 #define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
2069 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
2070 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
2071 #if defined(TIM23)
2072 #define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN)
2073 #endif /* TIM23 */
2074 #if defined(TIM24)
2075 #define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN)
2076 #endif /* TIM24 */
2077 
2078 
2085 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)
2086 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)
2087 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)
2088 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)
2089 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)
2090 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)
2091 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)
2092 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)
2093 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)
2094 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)
2095 #if defined(DUAL_CORE)
2096 #define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U)
2097 #endif /*DUAL_CORE*/
2098 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)
2099 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)
2100 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
2101 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)
2102 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)
2103 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)
2104 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)
2105 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)
2106 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)
2107 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)
2108 #if defined(I2C5)
2109 #define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U)
2110 #endif /* I2C5 */
2111 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)
2112 #define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)
2113 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)
2114 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)
2115 #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)
2116 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)
2117 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)
2118 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)
2119 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)
2120 #if defined(TIM23)
2121 #define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U)
2122 #endif /* TIM23 */
2123 #if defined(TIM24)
2124 #define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U)
2125 #endif /* TIM24 */
2126 
2127 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)
2128 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)
2129 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)
2130 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)
2131 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)
2132 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)
2133 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)
2134 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)
2135 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)
2136 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)
2137 #if defined(DUAL_CORE)
2138 #define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U)
2139 #endif /*DUAL_CORE*/
2140 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)
2141 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)
2142 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
2143 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)
2144 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)
2145 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)
2146 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)
2147 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)
2148 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)
2149 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)
2150 #if defined(I2C5)
2151 #define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U)
2152 #endif /* I2C5 */
2153 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)
2154 #define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)
2155 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)
2156 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)
2157 #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)
2158 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)
2159 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)
2160 #define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)
2161 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)
2162 #if defined(TIM23)
2163 #define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U)
2164 #endif /* TIM23 */
2165 #if defined(TIM24)
2166 #define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U)
2167 #endif /* TIM24 */
2168 
2169 
2176 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
2177  __IO uint32_t tmpreg; \
2178  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
2179  /* Delay after an RCC peripheral clock enabling */ \
2180  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
2181  UNUSED(tmpreg); \
2182  } while(0)
2183 
2184 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
2185  __IO uint32_t tmpreg; \
2186  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2187  /* Delay after an RCC peripheral clock enabling */ \
2188  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2189  UNUSED(tmpreg); \
2190  } while(0)
2191 
2192 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
2193  __IO uint32_t tmpreg; \
2194  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
2195  /* Delay after an RCC peripheral clock enabling */ \
2196  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
2197  UNUSED(tmpreg); \
2198  } while(0)
2199 
2200 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
2201  __IO uint32_t tmpreg; \
2202  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
2203  /* Delay after an RCC peripheral clock enabling */ \
2204  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
2205  UNUSED(tmpreg); \
2206  } while(0)
2207 
2208 #if defined(UART9)
2209 #define __HAL_RCC_UART9_CLK_ENABLE() do { \
2210  __IO uint32_t tmpreg; \
2211  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
2212  /* Delay after an RCC peripheral clock enabling */ \
2213  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
2214  UNUSED(tmpreg); \
2215  } while(0)
2216 #endif /*UART9*/
2217 
2218 #if defined(USART10)
2219 #define __HAL_RCC_USART10_CLK_ENABLE() do { \
2220  __IO uint32_t tmpreg; \
2221  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
2222  /* Delay after an RCC peripheral clock enabling */ \
2223  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
2224  UNUSED(tmpreg); \
2225  } while(0)
2226 #endif /*USART10*/
2227 
2228 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
2229  __IO uint32_t tmpreg; \
2230  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2231  /* Delay after an RCC peripheral clock enabling */ \
2232  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2233  UNUSED(tmpreg); \
2234  } while(0)
2235 
2236 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
2237  __IO uint32_t tmpreg; \
2238  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2239  /* Delay after an RCC peripheral clock enabling */ \
2240  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2241  UNUSED(tmpreg); \
2242  } while(0)
2243 
2244 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
2245  __IO uint32_t tmpreg; \
2246  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
2247  /* Delay after an RCC peripheral clock enabling */ \
2248  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
2249  UNUSED(tmpreg); \
2250  } while(0)
2251 
2252 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
2253  __IO uint32_t tmpreg; \
2254  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
2255  /* Delay after an RCC peripheral clock enabling */ \
2256  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
2257  UNUSED(tmpreg); \
2258  } while(0)
2259 
2260 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
2261  __IO uint32_t tmpreg; \
2262  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
2263  /* Delay after an RCC peripheral clock enabling */ \
2264  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
2265  UNUSED(tmpreg); \
2266  } while(0)
2267 
2268 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
2269  __IO uint32_t tmpreg; \
2270  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
2271  /* Delay after an RCC peripheral clock enabling */ \
2272  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
2273  UNUSED(tmpreg); \
2274  } while(0)
2275 
2276 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
2277  __IO uint32_t tmpreg; \
2278  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
2279  /* Delay after an RCC peripheral clock enabling */ \
2280  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
2281  UNUSED(tmpreg); \
2282  } while(0)
2283 
2284 #if defined(SAI2)
2285 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
2286  __IO uint32_t tmpreg; \
2287  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
2288  /* Delay after an RCC peripheral clock enabling */ \
2289  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
2290  UNUSED(tmpreg); \
2291  } while(0)
2292 #endif /*SAI2*/
2293 
2294 #if defined(SAI3)
2295 #define __HAL_RCC_SAI3_CLK_ENABLE() do { \
2296  __IO uint32_t tmpreg; \
2297  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
2298  /* Delay after an RCC peripheral clock enabling */ \
2299  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
2300  UNUSED(tmpreg); \
2301  } while(0)
2302 #endif /*SAI3*/
2303 
2304 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
2305  __IO uint32_t tmpreg; \
2306  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
2307  /* Delay after an RCC peripheral clock enabling */ \
2308  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
2309  UNUSED(tmpreg); \
2310  } while(0)
2311 
2312 #if defined(HRTIM1)
2313 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
2314  __IO uint32_t tmpreg; \
2315  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
2316  /* Delay after an RCC peripheral clock enabling */ \
2317  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
2318  UNUSED(tmpreg); \
2319  } while(0)
2320 #endif /*HRTIM1*/
2321 
2322 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
2323 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
2324 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
2325 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
2326 #if defined(UART9)
2327 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
2328 #endif /*UART9*/
2329 #if defined(USART10)
2330 #define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
2331 #endif /*USART10*/
2332 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
2333 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
2334 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
2335 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
2336 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
2337 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
2338 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
2339 #if defined(SAI2)
2340 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
2341 #endif /*SAI2*/
2342 #if defined(SAI3)
2343 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
2344 #endif /*SAI3*/
2345 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
2346 #if defined(HRTIM1)
2347 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
2348 #endif /*HRTIM*/
2349 
2356 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)
2357 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)
2358 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
2359 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
2360 #if defined(UART9)
2361 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
2362 #endif /*UART9*/
2363 #if defined(USART10)
2364 #define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
2365 #endif /*USART10*/
2366 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)
2367 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)
2368 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)
2369 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)
2370 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)
2371 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)
2372 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)
2373 #if defined(SAI2)
2374 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)
2375 #endif /*SAI2*/
2376 #if defined(SAI3)
2377 #define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U)
2378 #endif /* SAI3 */
2379 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
2380 #if defined(HRTIM1)
2381 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U)
2382 #endif /*HRTIM1*/
2383 
2384 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)
2385 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)
2386 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
2387 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
2388 #if defined(UART9)
2389 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
2390 #endif /*UART9*/
2391 #if defined(USART10)
2392 #define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
2393 #endif /*USART10*/
2394 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)
2395 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)
2396 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)
2397 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)
2398 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)
2399 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)
2400 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)
2401 #if defined(SAI2)
2402 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)
2403 #endif /*SAI2*/
2404 #if defined(SAI3)
2405 #define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U)
2406 #endif /*SAI3*/
2407 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
2408 #if defined(HRTIM1)
2409 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U)
2410 #endif /*HRTIM1*/
2411 
2418 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
2419  __IO uint32_t tmpreg; \
2420  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
2421  /* Delay after an RCC peripheral clock enabling */ \
2422  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
2423  UNUSED(tmpreg); \
2424  } while(0)
2425 
2426 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
2427  __IO uint32_t tmpreg; \
2428  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
2429  /* Delay after an RCC peripheral clock enabling */ \
2430  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
2431  UNUSED(tmpreg); \
2432  } while(0)
2433 
2434 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
2435  __IO uint32_t tmpreg; \
2436  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
2437  /* Delay after an RCC peripheral clock enabling */ \
2438  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
2439  UNUSED(tmpreg); \
2440  } while(0)
2441 
2442 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
2443  __IO uint32_t tmpreg; \
2444  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
2445  /* Delay after an RCC peripheral clock enabling */ \
2446  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
2447  UNUSED(tmpreg); \
2448  } while(0)
2449 
2450 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
2451  __IO uint32_t tmpreg; \
2452  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
2453  /* Delay after an RCC peripheral clock enabling */ \
2454  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
2455  UNUSED(tmpreg); \
2456  } while(0)
2457 
2458 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \
2459  __IO uint32_t tmpreg; \
2460  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
2461  /* Delay after an RCC peripheral clock enabling */ \
2462  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
2463  UNUSED(tmpreg); \
2464  } while(0)
2465 
2466 #if defined(LPTIM4)
2467 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \
2468  __IO uint32_t tmpreg; \
2469  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
2470  /* Delay after an RCC peripheral clock enabling */ \
2471  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
2472  UNUSED(tmpreg); \
2473  } while(0)
2474 #endif /* LPTIM4 */
2475 
2476 #if defined(LPTIM5)
2477 #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \
2478  __IO uint32_t tmpreg; \
2479  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
2480  /* Delay after an RCC peripheral clock enabling */ \
2481  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
2482  UNUSED(tmpreg); \
2483  } while(0)
2484 #endif /* LPTIM5 */
2485 
2486 #if defined(DAC2)
2487 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \
2488  __IO uint32_t tmpreg; \
2489  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
2490  /* Delay after an RCC peripheral clock enabling */ \
2491  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
2492  UNUSED(tmpreg); \
2493  } while(0)
2494 #endif /* DAC2 */
2495 
2496 #define __HAL_RCC_COMP12_CLK_ENABLE() do { \
2497  __IO uint32_t tmpreg; \
2498  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
2499  /* Delay after an RCC peripheral clock enabling */ \
2500  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
2501  UNUSED(tmpreg); \
2502  } while(0)
2503 
2504 #define __HAL_RCC_VREF_CLK_ENABLE() do { \
2505  __IO uint32_t tmpreg; \
2506  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
2507  /* Delay after an RCC peripheral clock enabling */ \
2508  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
2509  UNUSED(tmpreg); \
2510  } while(0)
2511 
2512 #if defined(SAI4)
2513 #define __HAL_RCC_SAI4_CLK_ENABLE() do { \
2514  __IO uint32_t tmpreg; \
2515  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
2516  /* Delay after an RCC peripheral clock enabling */ \
2517  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
2518  UNUSED(tmpreg); \
2519  } while(0)
2520 #endif /* SAI4 */
2521 
2522 #define __HAL_RCC_RTC_CLK_ENABLE() do { \
2523  __IO uint32_t tmpreg; \
2524  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
2525  /* Delay after an RCC peripheral clock enabling */ \
2526  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
2527  UNUSED(tmpreg); \
2528  } while(0)
2529 
2530 #if defined(DTS)
2531 #define __HAL_RCC_DTS_CLK_ENABLE() do { \
2532  __IO uint32_t tmpreg; \
2533  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
2534  /* Delay after an RCC peripheral clock enabling */ \
2535  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
2536  UNUSED(tmpreg); \
2537  } while(0)
2538 #endif /*DTS*/
2539 
2540 #if defined(DFSDM2_BASE)
2541 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
2542  __IO uint32_t tmpreg; \
2543  SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
2544  /* Delay after an RCC peripheral clock enabling */ \
2545  tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
2546  UNUSED(tmpreg); \
2547  } while(0)
2548 #endif /*DFSDM2*/
2549 
2550 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
2551 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
2552 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
2553 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
2554 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
2555 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
2556 #if defined(LPTIM4)
2557 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
2558 #endif /*LPTIM4*/
2559 #if defined(LPTIM5)
2560 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
2561 #endif /*LPTIM5*/
2562 #if defined(DAC2)
2563 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
2564 #endif /*DAC2*/
2565 #define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
2566 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
2567 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
2568 #if defined(SAI4)
2569 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
2570 #endif /*SAI4*/
2571 #if defined(DTS)
2572 #define __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
2573 #endif /*DTS*/
2574 #if defined(DFSDM2_BASE)
2575 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
2576 #endif /*DFSDM2*/
2577 
2584 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)
2585 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
2586 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)
2587 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)
2588 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)
2589 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)
2590 #if defined(LPTIM4)
2591 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U)
2592 #endif /*LPTIM4*/
2593 #if defined(LPTIM5)
2594 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U)
2595 #endif /*LPTIM5*/
2596 #if defined(DAC2)
2597 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U)
2598 #endif /*DAC2*/
2599 #define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)
2600 #define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)
2601 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)
2602 #if defined(SAI4)
2603 #define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U)
2604 #endif /*SAI4*/
2605 #if defined(DTS)
2606 #define __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U)
2607 #endif /*DTS*/
2608 #if defined(DFSDM2_BASE)
2609 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U)
2610 #endif /*DFSDM2*/
2611 
2612 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)
2613 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
2614 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)
2615 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)
2616 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)
2617 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)
2618 #if defined(LPTIM4)
2619 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U)
2620 #endif /*LPTIM4*/
2621 #if defined(LPTIM5)
2622 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U)
2623 #endif /*LPTIM5*/
2624 #if defined(DAC2)
2625 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U)
2626 #endif /*DAC2*/
2627 #define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)
2628 #define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)
2629 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)
2630 #if defined(SAI4)
2631 #define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U)
2632 #endif /*SAI4*/
2633 #if defined(DTS)
2634 #define __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U)
2635 #endif /*DTS*/
2636 #if defined(DFSDM2_BASE)
2637 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U)
2638 #endif /*DFSDM2*/
2639 
2640 #if defined(DUAL_CORE)
2641 
2642 /* Exported macros for RCC_C1 -------------------------------------------------*/
2643 
2650 #define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \
2651  __IO uint32_t tmpreg; \
2652  SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
2653  /* Delay after an RCC peripheral clock enabling */ \
2654  tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
2655  UNUSED(tmpreg); \
2656  } while(0)
2657 
2658 #define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \
2659  __IO uint32_t tmpreg; \
2660  SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
2661  /* Delay after an RCC peripheral clock enabling */ \
2662  tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
2663  UNUSED(tmpreg); \
2664  } while(0)
2665 
2666 #define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \
2667  __IO uint32_t tmpreg; \
2668  SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
2669  /* Delay after an RCC peripheral clock enabling */ \
2670  tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
2671  UNUSED(tmpreg); \
2672  } while(0)
2673 
2674 
2675 #define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \
2676  __IO uint32_t tmpreg; \
2677  SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
2678  /* Delay after an RCC peripheral clock enabling */ \
2679  tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
2680  UNUSED(tmpreg); \
2681  } while(0)
2682 
2683 #define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \
2684  __IO uint32_t tmpreg; \
2685  SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
2686  /* Delay after an RCC peripheral clock enabling */ \
2687  tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
2688  UNUSED(tmpreg); \
2689  } while(0)
2690 
2691 #define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \
2692  __IO uint32_t tmpreg; \
2693  SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
2694  /* Delay after an RCC peripheral clock enabling */ \
2695  tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
2696  UNUSED(tmpreg); \
2697  } while(0)
2698 
2699 
2700 
2701 
2702 #define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
2703 #define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
2704 #define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
2705 #define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
2706 #define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
2707 #define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
2708 
2709 
2710 
2711 
2718 #define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \
2719  __IO uint32_t tmpreg; \
2720  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
2721  /* Delay after an RCC peripheral clock enabling */ \
2722  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
2723  UNUSED(tmpreg); \
2724  } while(0)
2725 
2726 #define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \
2727  __IO uint32_t tmpreg; \
2728  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
2729  /* Delay after an RCC peripheral clock enabling */ \
2730  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
2731  UNUSED(tmpreg); \
2732  } while(0)
2733 
2734 #define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \
2735  __IO uint32_t tmpreg; \
2736  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
2737  /* Delay after an RCC peripheral clock enabling */ \
2738  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
2739  UNUSED(tmpreg); \
2740  } while(0)
2741 
2742 #define __HAL_RCC_C1_ART_CLK_ENABLE() do { \
2743  __IO uint32_t tmpreg; \
2744  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
2745  /* Delay after an RCC peripheral clock enabling */ \
2746  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
2747  UNUSED(tmpreg); \
2748  } while(0)
2749 
2750 #define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \
2751  __IO uint32_t tmpreg; \
2752  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
2753  /* Delay after an RCC peripheral clock enabling */ \
2754  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
2755  UNUSED(tmpreg); \
2756  } while(0)
2757 
2758 #define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \
2759  __IO uint32_t tmpreg; \
2760  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
2761  /* Delay after an RCC peripheral clock enabling */ \
2762  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
2763  UNUSED(tmpreg); \
2764  } while(0)
2765 
2766 #define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \
2767  __IO uint32_t tmpreg; \
2768  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
2769  /* Delay after an RCC peripheral clock enabling */ \
2770  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
2771  UNUSED(tmpreg); \
2772  } while(0)
2773 
2774 
2775 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \
2776  __IO uint32_t tmpreg; \
2777  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
2778  /* Delay after an RCC peripheral clock enabling */ \
2779  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
2780  UNUSED(tmpreg); \
2781  } while(0)
2782 
2783 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
2784  __IO uint32_t tmpreg; \
2785  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
2786  /* Delay after an RCC peripheral clock enabling */ \
2787  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
2788  UNUSED(tmpreg); \
2789  } while(0)
2790 
2791 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \
2792  __IO uint32_t tmpreg; \
2793  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
2794  /* Delay after an RCC peripheral clock enabling */ \
2795  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
2796  UNUSED(tmpreg); \
2797  } while(0)
2798 
2799 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
2800  __IO uint32_t tmpreg; \
2801  SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
2802  /* Delay after an RCC peripheral clock enabling */ \
2803  tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
2804  UNUSED(tmpreg); \
2805  } while(0)
2806 
2807 #define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
2808 #define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
2809 #define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
2810 #define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
2811 #define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
2812 #define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
2813 #define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
2814 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
2815 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
2816 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
2817 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
2818 
2825 #define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \
2826  __IO uint32_t tmpreg; \
2827  SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2828  /* Delay after an RCC peripheral clock enabling */ \
2829  tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2830  UNUSED(tmpreg); \
2831  } while(0)
2832 #if defined(CRYP)
2833 #define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \
2834  __IO uint32_t tmpreg; \
2835  SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2836  /* Delay after an RCC peripheral clock enabling */ \
2837  tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2838  UNUSED(tmpreg); \
2839  } while(0)
2840 #endif /* CRYP */
2841 
2842 #if defined(HASH)
2843 #define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \
2844  __IO uint32_t tmpreg; \
2845  SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2846  /* Delay after an RCC peripheral clock enabling */ \
2847  tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2848  UNUSED(tmpreg); \
2849  } while(0)
2850 #endif /* HASH */
2851 
2852 #define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \
2853  __IO uint32_t tmpreg; \
2854  SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2855  /* Delay after an RCC peripheral clock enabling */ \
2856  tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2857  UNUSED(tmpreg); \
2858  } while(0)
2859 
2860 #define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \
2861  __IO uint32_t tmpreg; \
2862  SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
2863  /* Delay after an RCC peripheral clock enabling */ \
2864  tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
2865  UNUSED(tmpreg); \
2866  } while(0)
2867 
2868 #define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \
2869  __IO uint32_t tmpreg; \
2870  SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
2871  /* Delay after an RCC peripheral clock enabling */ \
2872  tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
2873  UNUSED(tmpreg); \
2874  } while(0)
2875 
2876 #define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \
2877  __IO uint32_t tmpreg; \
2878  SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
2879  /* Delay after an RCC peripheral clock enabling */ \
2880  tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
2881  UNUSED(tmpreg); \
2882  } while(0)
2883 
2884 #define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \
2885  __IO uint32_t tmpreg; \
2886  SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
2887  /* Delay after an RCC peripheral clock enabling */ \
2888  tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
2889  UNUSED(tmpreg); \
2890  } while(0)
2891 
2892 #define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
2893 #if defined(CRYP)
2894 #define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
2895 #endif /* CRYP */
2896 #if defined(HASH)
2897 #define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
2898 #endif /* HASH */
2899 #define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
2900 #define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
2901 #define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
2902 #define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
2903 #define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
2904 
2911 #define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \
2912  __IO uint32_t tmpreg; \
2913  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
2914  /* Delay after an RCC peripheral clock enabling */ \
2915  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
2916  UNUSED(tmpreg); \
2917  } while(0)
2918 
2919 #define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \
2920  __IO uint32_t tmpreg; \
2921  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
2922  /* Delay after an RCC peripheral clock enabling */ \
2923  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
2924  UNUSED(tmpreg); \
2925  } while(0)
2926 
2927 #define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \
2928  __IO uint32_t tmpreg; \
2929  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
2930  /* Delay after an RCC peripheral clock enabling */ \
2931  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
2932  UNUSED(tmpreg); \
2933  } while(0)
2934 
2935 #define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \
2936  __IO uint32_t tmpreg; \
2937  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
2938  /* Delay after an RCC peripheral clock enabling */ \
2939  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
2940  UNUSED(tmpreg); \
2941  } while(0)
2942 
2943 #define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \
2944  __IO uint32_t tmpreg; \
2945  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
2946  /* Delay after an RCC peripheral clock enabling */ \
2947  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
2948  UNUSED(tmpreg); \
2949  } while(0)
2950 
2951 #define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \
2952  __IO uint32_t tmpreg; \
2953  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
2954  /* Delay after an RCC peripheral clock enabling */ \
2955  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
2956  UNUSED(tmpreg); \
2957  } while(0)
2958 
2959 #define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \
2960  __IO uint32_t tmpreg; \
2961  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
2962  /* Delay after an RCC peripheral clock enabling */ \
2963  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
2964  UNUSED(tmpreg); \
2965  } while(0)
2966 
2967 #define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \
2968  __IO uint32_t tmpreg; \
2969  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
2970  /* Delay after an RCC peripheral clock enabling */ \
2971  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
2972  UNUSED(tmpreg); \
2973  } while(0)
2974 
2975 #define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \
2976  __IO uint32_t tmpreg; \
2977  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
2978  /* Delay after an RCC peripheral clock enabling */ \
2979  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
2980  UNUSED(tmpreg); \
2981  } while(0)
2982 
2983 #define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \
2984  __IO uint32_t tmpreg; \
2985  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
2986  /* Delay after an RCC peripheral clock enabling */ \
2987  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
2988  UNUSED(tmpreg); \
2989  } while(0)
2990 
2991 #define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \
2992  __IO uint32_t tmpreg; \
2993  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
2994  /* Delay after an RCC peripheral clock enabling */ \
2995  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
2996  UNUSED(tmpreg); \
2997  } while(0)
2998 
2999 #define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \
3000  __IO uint32_t tmpreg; \
3001  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
3002  /* Delay after an RCC peripheral clock enabling */ \
3003  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
3004  UNUSED(tmpreg); \
3005  } while(0)
3006 
3007 #define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \
3008  __IO uint32_t tmpreg; \
3009  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
3010  /* Delay after an RCC peripheral clock enabling */ \
3011  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
3012  UNUSED(tmpreg); \
3013  } while(0)
3014 
3015 #define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \
3016  __IO uint32_t tmpreg; \
3017  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
3018  /* Delay after an RCC peripheral clock enabling */ \
3019  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
3020  UNUSED(tmpreg); \
3021  } while(0)
3022 
3023 #define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \
3024  __IO uint32_t tmpreg; \
3025  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
3026  /* Delay after an RCC peripheral clock enabling */ \
3027  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
3028  UNUSED(tmpreg); \
3029  } while(0)
3030 
3031 #define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \
3032  __IO uint32_t tmpreg; \
3033  SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
3034  /* Delay after an RCC peripheral clock enabling */ \
3035  tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
3036  UNUSED(tmpreg); \
3037  } while(0)
3038 
3039 
3040 #define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
3041 #define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
3042 #define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
3043 #define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
3044 #define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
3045 #define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
3046 #define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
3047 #define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
3048 #define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
3049 #define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
3050 #define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
3051 #define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
3052 #define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
3053 #define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
3054 #define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
3055 #define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
3056 
3057 
3064 #define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \
3065  __IO uint32_t tmpreg; \
3066  SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
3067  /* Delay after an RCC peripheral clock enabling */ \
3068  tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
3069  UNUSED(tmpreg); \
3070  } while(0)
3071 
3072 #define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \
3073  __IO uint32_t tmpreg; \
3074  SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
3075  /* Delay after an RCC peripheral clock enabling */ \
3076  tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
3077  UNUSED(tmpreg); \
3078  } while(0)
3079 
3080 #define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \
3081  __IO uint32_t tmpreg; \
3082  SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
3083  /* Delay after an RCC peripheral clock enabling */ \
3084  tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
3085  UNUSED(tmpreg); \
3086  } while(0)
3087 
3088 #define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
3089 #define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
3090 #define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
3091 
3098 #define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \
3099  __IO uint32_t tmpreg; \
3100  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
3101  /* Delay after an RCC peripheral clock enabling */ \
3102  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
3103  UNUSED(tmpreg); \
3104  } while(0)
3105 
3106 #define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \
3107  __IO uint32_t tmpreg; \
3108  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
3109  /* Delay after an RCC peripheral clock enabling */ \
3110  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
3111  UNUSED(tmpreg); \
3112  } while(0)
3113 
3114 #define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \
3115  __IO uint32_t tmpreg; \
3116  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
3117  /* Delay after an RCC peripheral clock enabling */ \
3118  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
3119  UNUSED(tmpreg); \
3120  } while(0)
3121 
3122 #define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \
3123  __IO uint32_t tmpreg; \
3124  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
3125  /* Delay after an RCC peripheral clock enabling */ \
3126  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
3127  UNUSED(tmpreg); \
3128  } while(0)
3129 
3130 #define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \
3131  __IO uint32_t tmpreg; \
3132  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
3133  /* Delay after an RCC peripheral clock enabling */ \
3134  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
3135  UNUSED(tmpreg); \
3136  } while(0)
3137 
3138 #define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \
3139  __IO uint32_t tmpreg; \
3140  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
3141  /* Delay after an RCC peripheral clock enabling */ \
3142  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
3143  UNUSED(tmpreg); \
3144  } while(0)
3145 
3146 #define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \
3147  __IO uint32_t tmpreg; \
3148  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
3149  /* Delay after an RCC peripheral clock enabling */ \
3150  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
3151  UNUSED(tmpreg); \
3152  } while(0)
3153 
3154 #define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \
3155  __IO uint32_t tmpreg; \
3156  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
3157  /* Delay after an RCC peripheral clock enabling */ \
3158  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
3159  UNUSED(tmpreg); \
3160  } while(0)
3161 
3162 #define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \
3163  __IO uint32_t tmpreg; \
3164  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
3165  /* Delay after an RCC peripheral clock enabling */ \
3166  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
3167  UNUSED(tmpreg); \
3168  } while(0)
3169 
3170 #define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \
3171  __IO uint32_t tmpreg; \
3172  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
3173  /* Delay after an RCC peripheral clock enabling */ \
3174  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
3175  UNUSED(tmpreg); \
3176  } while(0)
3177 
3178 #define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \
3179  __IO uint32_t tmpreg; \
3180  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
3181  /* Delay after an RCC peripheral clock enabling */ \
3182  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
3183  UNUSED(tmpreg); \
3184  } while(0)
3185 
3186 #define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \
3187  __IO uint32_t tmpreg; \
3188  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
3189  /* Delay after an RCC peripheral clock enabling */ \
3190  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
3191  UNUSED(tmpreg); \
3192  } while(0)
3193 
3194 #define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \
3195  __IO uint32_t tmpreg; \
3196  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
3197  /* Delay after an RCC peripheral clock enabling */ \
3198  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
3199  UNUSED(tmpreg); \
3200  } while(0)
3201 
3202 #define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \
3203  __IO uint32_t tmpreg; \
3204  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
3205  /* Delay after an RCC peripheral clock enabling */ \
3206  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
3207  UNUSED(tmpreg); \
3208  } while(0)
3209 
3210 #define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \
3211  __IO uint32_t tmpreg; \
3212  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
3213  /* Delay after an RCC peripheral clock enabling */ \
3214  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
3215  UNUSED(tmpreg); \
3216  } while(0)
3217 
3218 #define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \
3219  __IO uint32_t tmpreg; \
3220  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
3221  /* Delay after an RCC peripheral clock enabling */ \
3222  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
3223  UNUSED(tmpreg); \
3224  } while(0)
3225 
3226 #define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \
3227  __IO uint32_t tmpreg; \
3228  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
3229  /* Delay after an RCC peripheral clock enabling */ \
3230  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
3231  UNUSED(tmpreg); \
3232  } while(0)
3233 
3234 #define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \
3235  __IO uint32_t tmpreg; \
3236  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
3237  /* Delay after an RCC peripheral clock enabling */ \
3238  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
3239  UNUSED(tmpreg); \
3240  } while(0)
3241 
3242 #define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \
3243  __IO uint32_t tmpreg; \
3244  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
3245  /* Delay after an RCC peripheral clock enabling */ \
3246  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
3247  UNUSED(tmpreg); \
3248  } while(0)
3249 
3250 #define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \
3251  __IO uint32_t tmpreg; \
3252  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
3253  /* Delay after an RCC peripheral clock enabling */ \
3254  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
3255  UNUSED(tmpreg); \
3256  } while(0)
3257 
3258 #define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \
3259  __IO uint32_t tmpreg; \
3260  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
3261  /* Delay after an RCC peripheral clock enabling */ \
3262  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
3263  UNUSED(tmpreg); \
3264  } while(0)
3265 
3266 #define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \
3267  __IO uint32_t tmpreg; \
3268  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
3269  /* Delay after an RCC peripheral clock enabling */ \
3270  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
3271  UNUSED(tmpreg); \
3272  } while(0)
3273 
3274 #define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \
3275  __IO uint32_t tmpreg; \
3276  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
3277  /* Delay after an RCC peripheral clock enabling */ \
3278  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
3279  UNUSED(tmpreg); \
3280  } while(0)
3281 
3282 #define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \
3283  __IO uint32_t tmpreg; \
3284  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
3285  /* Delay after an RCC peripheral clock enabling */ \
3286  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
3287  UNUSED(tmpreg); \
3288  } while(0)
3289 
3290 #define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \
3291  __IO uint32_t tmpreg; \
3292  SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
3293  /* Delay after an RCC peripheral clock enabling */ \
3294  tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
3295  UNUSED(tmpreg); \
3296  } while(0)
3297 
3298 #define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \
3299  __IO uint32_t tmpreg; \
3300  SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
3301  /* Delay after an RCC peripheral clock enabling */ \
3302  tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
3303  UNUSED(tmpreg); \
3304  } while(0)
3305 
3306 #define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \
3307  __IO uint32_t tmpreg; \
3308  SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
3309  /* Delay after an RCC peripheral clock enabling */ \
3310  tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
3311  UNUSED(tmpreg); \
3312  } while(0)
3313 
3314 #define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \
3315  __IO uint32_t tmpreg; \
3316  SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
3317  /* Delay after an RCC peripheral clock enabling */ \
3318  tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
3319  UNUSED(tmpreg); \
3320  } while(0)
3321 
3322 #define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \
3323  __IO uint32_t tmpreg; \
3324  SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
3325  /* Delay after an RCC peripheral clock enabling */ \
3326  tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
3327  UNUSED(tmpreg); \
3328  } while(0)
3329 
3330 #define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \
3331  __IO uint32_t tmpreg; \
3332  SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
3333  /* Delay after an RCC peripheral clock enabling */ \
3334  tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
3335  UNUSED(tmpreg); \
3336  } while(0)
3337 
3338 
3339 #define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
3340 #define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
3341 #define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
3342 #define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
3343 #define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
3344 #define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
3345 #define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
3346 #define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
3347 #define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
3348 #define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
3349 #define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
3350 #define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
3351 #define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
3352 #define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
3353 #define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
3354 #define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
3355 #define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
3356 #define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
3357 #define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
3358 #define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
3359 #define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
3360 #define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
3361 #define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
3362 #define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
3363 #define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
3364 #define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
3365 #define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
3366 #define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
3367 #define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
3368 #define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
3369 
3376 #define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \
3377  __IO uint32_t tmpreg; \
3378  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
3379  /* Delay after an RCC peripheral clock enabling */ \
3380  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
3381  UNUSED(tmpreg); \
3382  } while(0)
3383 
3384 #define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \
3385  __IO uint32_t tmpreg; \
3386  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
3387  /* Delay after an RCC peripheral clock enabling */ \
3388  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
3389  UNUSED(tmpreg); \
3390  } while(0)
3391 
3392 #define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \
3393  __IO uint32_t tmpreg; \
3394  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
3395  /* Delay after an RCC peripheral clock enabling */ \
3396  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
3397  UNUSED(tmpreg); \
3398  } while(0)
3399 
3400 #define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \
3401  __IO uint32_t tmpreg; \
3402  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
3403  /* Delay after an RCC peripheral clock enabling */ \
3404  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
3405  UNUSED(tmpreg); \
3406  } while(0)
3407 
3408 #define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \
3409  __IO uint32_t tmpreg; \
3410  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
3411  /* Delay after an RCC peripheral clock enabling */ \
3412  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
3413  UNUSED(tmpreg); \
3414  } while(0)
3415 
3416 #define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \
3417  __IO uint32_t tmpreg; \
3418  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
3419  /* Delay after an RCC peripheral clock enabling */ \
3420  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
3421  UNUSED(tmpreg); \
3422  } while(0)
3423 
3424 #define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \
3425  __IO uint32_t tmpreg; \
3426  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
3427  /* Delay after an RCC peripheral clock enabling */ \
3428  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
3429  UNUSED(tmpreg); \
3430  } while(0)
3431 
3432 #define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \
3433  __IO uint32_t tmpreg; \
3434  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
3435  /* Delay after an RCC peripheral clock enabling */ \
3436  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
3437  UNUSED(tmpreg); \
3438  } while(0)
3439 
3440 #define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \
3441  __IO uint32_t tmpreg; \
3442  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
3443  /* Delay after an RCC peripheral clock enabling */ \
3444  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
3445  UNUSED(tmpreg); \
3446  } while(0)
3447 
3448 #define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \
3449  __IO uint32_t tmpreg; \
3450  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
3451  /* Delay after an RCC peripheral clock enabling */ \
3452  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
3453  UNUSED(tmpreg); \
3454  } while(0)
3455 
3456 #define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \
3457  __IO uint32_t tmpreg; \
3458  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
3459  /* Delay after an RCC peripheral clock enabling */ \
3460  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
3461  UNUSED(tmpreg); \
3462  } while(0)
3463 
3464 #define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \
3465  __IO uint32_t tmpreg; \
3466  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
3467  /* Delay after an RCC peripheral clock enabling */ \
3468  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
3469  UNUSED(tmpreg); \
3470  } while(0)
3471 
3472 #define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \
3473  __IO uint32_t tmpreg; \
3474  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
3475  /* Delay after an RCC peripheral clock enabling */ \
3476  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
3477  UNUSED(tmpreg); \
3478  } while(0)
3479 
3480 #define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \
3481  __IO uint32_t tmpreg; \
3482  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
3483  /* Delay after an RCC peripheral clock enabling */ \
3484  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
3485  UNUSED(tmpreg); \
3486  } while(0)
3487 
3488 #define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \
3489  __IO uint32_t tmpreg; \
3490  SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
3491  /* Delay after an RCC peripheral clock enabling */ \
3492  tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
3493  UNUSED(tmpreg); \
3494  } while(0)
3495 
3496 #define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
3497 #define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
3498 #define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
3499 #define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
3500 #define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
3501 #define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
3502 #define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
3503 #define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
3504 #define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
3505 #define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
3506 #define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
3507 #define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
3508 #define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
3509 #define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
3510 #define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
3511 
3518 #define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \
3519  __IO uint32_t tmpreg; \
3520  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
3521  /* Delay after an RCC peripheral clock enabling */ \
3522  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
3523  UNUSED(tmpreg); \
3524  } while(0)
3525 
3526 #define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \
3527  __IO uint32_t tmpreg; \
3528  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
3529  /* Delay after an RCC peripheral clock enabling */ \
3530  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
3531  UNUSED(tmpreg); \
3532  } while(0)
3533 
3534 #define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \
3535  __IO uint32_t tmpreg; \
3536  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
3537  /* Delay after an RCC peripheral clock enabling */ \
3538  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
3539  UNUSED(tmpreg); \
3540  } while(0)
3541 
3542 #define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \
3543  __IO uint32_t tmpreg; \
3544  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
3545  /* Delay after an RCC peripheral clock enabling */ \
3546  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
3547  UNUSED(tmpreg); \
3548  } while(0)
3549 
3550 #define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \
3551  __IO uint32_t tmpreg; \
3552  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
3553  /* Delay after an RCC peripheral clock enabling */ \
3554  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
3555  UNUSED(tmpreg); \
3556  } while(0)
3557 
3558 #define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \
3559  __IO uint32_t tmpreg; \
3560  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
3561  /* Delay after an RCC peripheral clock enabling */ \
3562  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
3563  UNUSED(tmpreg); \
3564  } while(0)
3565 
3566 #define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \
3567  __IO uint32_t tmpreg; \
3568  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
3569  /* Delay after an RCC peripheral clock enabling */ \
3570  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
3571  UNUSED(tmpreg); \
3572  } while(0)
3573 
3574 #define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \
3575  __IO uint32_t tmpreg; \
3576  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
3577  /* Delay after an RCC peripheral clock enabling */ \
3578  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
3579  UNUSED(tmpreg); \
3580  } while(0)
3581 
3582 #define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \
3583  __IO uint32_t tmpreg; \
3584  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
3585  /* Delay after an RCC peripheral clock enabling */ \
3586  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
3587  UNUSED(tmpreg); \
3588  } while(0)
3589 
3590 
3591 #define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \
3592  __IO uint32_t tmpreg; \
3593  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
3594  /* Delay after an RCC peripheral clock enabling */ \
3595  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
3596  UNUSED(tmpreg); \
3597  } while(0)
3598 
3599 #define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \
3600  __IO uint32_t tmpreg; \
3601  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
3602  /* Delay after an RCC peripheral clock enabling */ \
3603  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
3604  UNUSED(tmpreg); \
3605  } while(0)
3606 
3607 #define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \
3608  __IO uint32_t tmpreg; \
3609  SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
3610  /* Delay after an RCC peripheral clock enabling */ \
3611  tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
3612  UNUSED(tmpreg); \
3613  } while(0)
3614 
3615 
3616 #define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
3617 #define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
3618 #define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
3619 #define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
3620 #define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
3621 #define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
3622 #define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
3623 #define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
3624 #define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
3625 #define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
3626 #define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
3627 #define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
3628 
3629 /* Exported macros for RCC_C2 -------------------------------------------------*/
3630 
3638 #define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \
3639  __IO uint32_t tmpreg; \
3640  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
3641  /* Delay after an RCC peripheral clock enabling */ \
3642  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
3643  UNUSED(tmpreg); \
3644  } while(0)
3645 
3646 #define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \
3647  __IO uint32_t tmpreg; \
3648  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
3649  /* Delay after an RCC peripheral clock enabling */ \
3650  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
3651  UNUSED(tmpreg); \
3652  } while(0)
3653 
3654 #define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \
3655  __IO uint32_t tmpreg; \
3656  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
3657  /* Delay after an RCC peripheral clock enabling */ \
3658  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
3659  UNUSED(tmpreg); \
3660  } while(0)
3661 
3662 #define __HAL_RCC_FLASH_C2_ALLOCATE() do { \
3663  __IO uint32_t tmpreg; \
3664  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
3665  /* Delay after an RCC peripheral clock enabling */ \
3666  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
3667  UNUSED(tmpreg); \
3668  } while(0)
3669 
3670 #define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \
3671  __IO uint32_t tmpreg; \
3672  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
3673  /* Delay after an RCC peripheral clock enabling */ \
3674  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
3675  UNUSED(tmpreg); \
3676  } while(0)
3677 
3678 #define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \
3679  __IO uint32_t tmpreg; \
3680  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
3681  /* Delay after an RCC peripheral clock enabling */ \
3682  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
3683  UNUSED(tmpreg); \
3684  } while(0)
3685 
3686 #define __HAL_RCC_ITCM_C2_ALLOCATE() do { \
3687  __IO uint32_t tmpreg; \
3688  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
3689  /* Delay after an RCC peripheral clock enabling */ \
3690  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
3691  UNUSED(tmpreg); \
3692  } while(0)
3693 
3694 #define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \
3695  __IO uint32_t tmpreg; \
3696  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
3697  /* Delay after an RCC peripheral clock enabling */ \
3698  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
3699  UNUSED(tmpreg); \
3700  } while(0)
3701 
3702 #define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \
3703  __IO uint32_t tmpreg; \
3704  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
3705  /* Delay after an RCC peripheral clock enabling */ \
3706  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
3707  UNUSED(tmpreg); \
3708  } while(0)
3709 
3710 #define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \
3711  __IO uint32_t tmpreg; \
3712  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
3713  /* Delay after an RCC peripheral clock enabling */ \
3714  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
3715  UNUSED(tmpreg); \
3716  } while(0)
3717 
3718 #define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \
3719  __IO uint32_t tmpreg; \
3720  SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
3721  /* Delay after an RCC peripheral clock enabling */ \
3722  tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
3723  UNUSED(tmpreg); \
3724  } while(0)
3725 
3726 
3727 
3728 
3729 #define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
3730 #define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
3731 #define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
3732 #define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
3733 #define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
3734 #define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
3735 #define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
3736 #define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))
3737 #define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))
3738 #define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))
3739 #define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))
3740 
3747 #define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \
3748  __IO uint32_t tmpreg; \
3749  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
3750  /* Delay after an RCC peripheral clock enabling */ \
3751  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
3752  UNUSED(tmpreg); \
3753  } while(0)
3754 
3755 #define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \
3756  __IO uint32_t tmpreg; \
3757  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
3758  /* Delay after an RCC peripheral clock enabling */ \
3759  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
3760  UNUSED(tmpreg); \
3761  } while(0)
3762 
3763 #define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \
3764  __IO uint32_t tmpreg; \
3765  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
3766  /* Delay after an RCC peripheral clock enabling */ \
3767  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
3768  UNUSED(tmpreg); \
3769  } while(0)
3770 
3771 #define __HAL_RCC_C2_ART_CLK_ENABLE() do { \
3772  __IO uint32_t tmpreg; \
3773  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
3774  /* Delay after an RCC peripheral clock enabling */ \
3775  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
3776  UNUSED(tmpreg); \
3777  } while(0)
3778 
3779 #define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \
3780  __IO uint32_t tmpreg; \
3781  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
3782  /* Delay after an RCC peripheral clock enabling */ \
3783  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
3784  UNUSED(tmpreg); \
3785  } while(0)
3786 
3787 #define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \
3788  __IO uint32_t tmpreg; \
3789  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
3790  /* Delay after an RCC peripheral clock enabling */ \
3791  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
3792  UNUSED(tmpreg); \
3793  } while(0)
3794 
3795 #define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \
3796  __IO uint32_t tmpreg; \
3797  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
3798  /* Delay after an RCC peripheral clock enabling */ \
3799  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
3800  UNUSED(tmpreg); \
3801  } while(0)
3802 
3803 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \
3804  __IO uint32_t tmpreg; \
3805  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
3806  /* Delay after an RCC peripheral clock enabling */ \
3807  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
3808  UNUSED(tmpreg); \
3809  } while(0)
3810 
3811 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
3812  __IO uint32_t tmpreg; \
3813  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
3814  /* Delay after an RCC peripheral clock enabling */ \
3815  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
3816  UNUSED(tmpreg); \
3817  } while(0)
3818 
3819 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \
3820  __IO uint32_t tmpreg; \
3821  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
3822  /* Delay after an RCC peripheral clock enabling */ \
3823  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
3824  UNUSED(tmpreg); \
3825  } while(0)
3826 
3827 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
3828  __IO uint32_t tmpreg; \
3829  SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
3830  /* Delay after an RCC peripheral clock enabling */ \
3831  tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
3832  UNUSED(tmpreg); \
3833  } while(0)
3834 
3835 
3836 #define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
3837 #define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
3838 #define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
3839 #define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
3840 #define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
3841 #define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
3842 #define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
3843 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
3844 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
3845 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
3846 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
3847 
3854 #define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \
3855  __IO uint32_t tmpreg; \
3856  SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
3857  /* Delay after an RCC peripheral clock enabling */ \
3858  tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
3859  UNUSED(tmpreg); \
3860  } while(0)
3861 
3862 #if defined(CRYP)
3863 #define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \
3864  __IO uint32_t tmpreg; \
3865  SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
3866  /* Delay after an RCC peripheral clock enabling */ \
3867  tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
3868  UNUSED(tmpreg); \
3869  } while(0)
3870 #endif /* CRYP */
3871 
3872 #if defined(HASH)
3873 #define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \
3874  __IO uint32_t tmpreg; \
3875  SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
3876  /* Delay after an RCC peripheral clock enabling */ \
3877  tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
3878  UNUSED(tmpreg); \
3879  } while(0)
3880 #endif /* HASH */
3881 
3882 #define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \
3883  __IO uint32_t tmpreg; \
3884  SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
3885  /* Delay after an RCC peripheral clock enabling */ \
3886  tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
3887  UNUSED(tmpreg); \
3888  } while(0)
3889 
3890 #define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \
3891  __IO uint32_t tmpreg; \
3892  SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
3893  /* Delay after an RCC peripheral clock enabling */ \
3894  tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
3895  UNUSED(tmpreg); \
3896  } while(0)
3897 
3898 #define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \
3899  __IO uint32_t tmpreg; \
3900  SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
3901  /* Delay after an RCC peripheral clock enabling */ \
3902  tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
3903  UNUSED(tmpreg); \
3904  } while(0)
3905 
3906 #define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \
3907  __IO uint32_t tmpreg; \
3908  SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
3909  /* Delay after an RCC peripheral clock enabling */ \
3910  tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
3911  UNUSED(tmpreg); \
3912  } while(0)
3913 
3914 #define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \
3915  __IO uint32_t tmpreg; \
3916  SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
3917  /* Delay after an RCC peripheral clock enabling */ \
3918  tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
3919  UNUSED(tmpreg); \
3920  } while(0)
3921 
3922 #define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
3923 #if defined(CRYP)
3924 #define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
3925 #endif /* CRYP */
3926 #if defined(HASH)
3927 #define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
3928 #endif /* HASH */
3929 #define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
3930 #define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
3931 #define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
3932 #define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
3933 #define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
3934 
3941 #define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \
3942  __IO uint32_t tmpreg; \
3943  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
3944  /* Delay after an RCC peripheral clock enabling */ \
3945  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
3946  UNUSED(tmpreg); \
3947  } while(0)
3948 
3949 #define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \
3950  __IO uint32_t tmpreg; \
3951  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
3952  /* Delay after an RCC peripheral clock enabling */ \
3953  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
3954  UNUSED(tmpreg); \
3955  } while(0)
3956 
3957 #define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \
3958  __IO uint32_t tmpreg; \
3959  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
3960  /* Delay after an RCC peripheral clock enabling */ \
3961  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
3962  UNUSED(tmpreg); \
3963  } while(0)
3964 
3965 #define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \
3966  __IO uint32_t tmpreg; \
3967  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
3968  /* Delay after an RCC peripheral clock enabling */ \
3969  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
3970  UNUSED(tmpreg); \
3971  } while(0)
3972 
3973 #define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \
3974  __IO uint32_t tmpreg; \
3975  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
3976  /* Delay after an RCC peripheral clock enabling */ \
3977  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
3978  UNUSED(tmpreg); \
3979  } while(0)
3980 
3981 #define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \
3982  __IO uint32_t tmpreg; \
3983  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
3984  /* Delay after an RCC peripheral clock enabling */ \
3985  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
3986  UNUSED(tmpreg); \
3987  } while(0)
3988 
3989 #define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \
3990  __IO uint32_t tmpreg; \
3991  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
3992  /* Delay after an RCC peripheral clock enabling */ \
3993  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
3994  UNUSED(tmpreg); \
3995  } while(0)
3996 
3997 #define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \
3998  __IO uint32_t tmpreg; \
3999  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
4000  /* Delay after an RCC peripheral clock enabling */ \
4001  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
4002  UNUSED(tmpreg); \
4003  } while(0)
4004 
4005 #define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \
4006  __IO uint32_t tmpreg; \
4007  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
4008  /* Delay after an RCC peripheral clock enabling */ \
4009  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
4010  UNUSED(tmpreg); \
4011  } while(0)
4012 
4013 #define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \
4014  __IO uint32_t tmpreg; \
4015  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
4016  /* Delay after an RCC peripheral clock enabling */ \
4017  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
4018  UNUSED(tmpreg); \
4019  } while(0)
4020 
4021 #define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \
4022  __IO uint32_t tmpreg; \
4023  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
4024  /* Delay after an RCC peripheral clock enabling */ \
4025  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
4026  UNUSED(tmpreg); \
4027  } while(0)
4028 
4029 #define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \
4030  __IO uint32_t tmpreg; \
4031  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
4032  /* Delay after an RCC peripheral clock enabling */ \
4033  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
4034  UNUSED(tmpreg); \
4035  } while(0)
4036 
4037 #define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \
4038  __IO uint32_t tmpreg; \
4039  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
4040  /* Delay after an RCC peripheral clock enabling */ \
4041  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
4042  UNUSED(tmpreg); \
4043  } while(0)
4044 
4045 #define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \
4046  __IO uint32_t tmpreg; \
4047  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
4048  /* Delay after an RCC peripheral clock enabling */ \
4049  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
4050  UNUSED(tmpreg); \
4051  } while(0)
4052 
4053 #define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \
4054  __IO uint32_t tmpreg; \
4055  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
4056  /* Delay after an RCC peripheral clock enabling */ \
4057  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
4058  UNUSED(tmpreg); \
4059  } while(0)
4060 
4061 #define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \
4062  __IO uint32_t tmpreg; \
4063  SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
4064  /* Delay after an RCC peripheral clock enabling */ \
4065  tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
4066  UNUSED(tmpreg); \
4067  } while(0)
4068 
4069 
4070 #define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
4071 #define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
4072 #define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
4073 #define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
4074 #define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
4075 #define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
4076 #define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
4077 #define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
4078 #define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
4079 #define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
4080 #define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
4081 #define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
4082 #define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
4083 #define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
4084 #define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
4085 #define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
4086 
4087 
4094 #define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \
4095  __IO uint32_t tmpreg; \
4096  SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
4097  /* Delay after an RCC peripheral clock enabling */ \
4098  tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
4099  UNUSED(tmpreg); \
4100  } while(0)
4101 
4102 #define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \
4103  __IO uint32_t tmpreg; \
4104  SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
4105  /* Delay after an RCC peripheral clock enabling */ \
4106  tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
4107  UNUSED(tmpreg); \
4108  } while(0)
4109 
4110 #define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \
4111  __IO uint32_t tmpreg; \
4112  SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
4113  /* Delay after an RCC peripheral clock enabling */ \
4114  tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
4115  UNUSED(tmpreg); \
4116  } while(0)
4117 
4118 #define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
4119 #define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
4120 #define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
4121 
4128 #define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \
4129  __IO uint32_t tmpreg; \
4130  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
4131  /* Delay after an RCC peripheral clock enabling */ \
4132  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
4133  UNUSED(tmpreg); \
4134  } while(0)
4135 
4136 #define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \
4137  __IO uint32_t tmpreg; \
4138  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
4139  /* Delay after an RCC peripheral clock enabling */ \
4140  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
4141  UNUSED(tmpreg); \
4142  } while(0)
4143 
4144 #define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \
4145  __IO uint32_t tmpreg; \
4146  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
4147  /* Delay after an RCC peripheral clock enabling */ \
4148  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
4149  UNUSED(tmpreg); \
4150  } while(0)
4151 
4152 #define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \
4153  __IO uint32_t tmpreg; \
4154  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
4155  /* Delay after an RCC peripheral clock enabling */ \
4156  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
4157  UNUSED(tmpreg); \
4158  } while(0)
4159 
4160 #define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \
4161  __IO uint32_t tmpreg; \
4162  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
4163  /* Delay after an RCC peripheral clock enabling */ \
4164  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
4165  UNUSED(tmpreg); \
4166  } while(0)
4167 
4168 #define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \
4169  __IO uint32_t tmpreg; \
4170  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
4171  /* Delay after an RCC peripheral clock enabling */ \
4172  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
4173  UNUSED(tmpreg); \
4174  } while(0)
4175 
4176 #define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \
4177  __IO uint32_t tmpreg; \
4178  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
4179  /* Delay after an RCC peripheral clock enabling */ \
4180  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
4181  UNUSED(tmpreg); \
4182  } while(0)
4183 
4184 #define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \
4185  __IO uint32_t tmpreg; \
4186  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
4187  /* Delay after an RCC peripheral clock enabling */ \
4188  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
4189  UNUSED(tmpreg); \
4190  } while(0)
4191 
4192 #define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \
4193  __IO uint32_t tmpreg; \
4194  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
4195  /* Delay after an RCC peripheral clock enabling */ \
4196  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
4197  UNUSED(tmpreg); \
4198  } while(0)
4199 
4200 #define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \
4201  __IO uint32_t tmpreg; \
4202  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
4203  /* Delay after an RCC peripheral clock enabling */ \
4204  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
4205  UNUSED(tmpreg); \
4206  } while(0)
4207 
4208 #define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \
4209  __IO uint32_t tmpreg; \
4210  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
4211  /* Delay after an RCC peripheral clock enabling */ \
4212  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
4213  UNUSED(tmpreg); \
4214  } while(0)
4215 
4216 #define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \
4217  __IO uint32_t tmpreg; \
4218  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
4219  /* Delay after an RCC peripheral clock enabling */ \
4220  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
4221  UNUSED(tmpreg); \
4222  } while(0)
4223 
4224 #define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \
4225  __IO uint32_t tmpreg; \
4226  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
4227  /* Delay after an RCC peripheral clock enabling */ \
4228  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
4229  UNUSED(tmpreg); \
4230  } while(0)
4231 
4232 #define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \
4233  __IO uint32_t tmpreg; \
4234  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
4235  /* Delay after an RCC peripheral clock enabling */ \
4236  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
4237  UNUSED(tmpreg); \
4238  } while(0)
4239 
4240 #define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \
4241  __IO uint32_t tmpreg; \
4242  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
4243  /* Delay after an RCC peripheral clock enabling */ \
4244  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
4245  UNUSED(tmpreg); \
4246  } while(0)
4247 
4248 #define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \
4249  __IO uint32_t tmpreg; \
4250  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
4251  /* Delay after an RCC peripheral clock enabling */ \
4252  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
4253  UNUSED(tmpreg); \
4254  } while(0)
4255 
4256 #define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \
4257  __IO uint32_t tmpreg; \
4258  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
4259  /* Delay after an RCC peripheral clock enabling */ \
4260  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
4261  UNUSED(tmpreg); \
4262  } while(0)
4263 
4264 #define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \
4265  __IO uint32_t tmpreg; \
4266  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
4267  /* Delay after an RCC peripheral clock enabling */ \
4268  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
4269  UNUSED(tmpreg); \
4270  } while(0)
4271 
4272 #define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \
4273  __IO uint32_t tmpreg; \
4274  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
4275  /* Delay after an RCC peripheral clock enabling */ \
4276  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
4277  UNUSED(tmpreg); \
4278  } while(0)
4279 
4280 #define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \
4281  __IO uint32_t tmpreg; \
4282  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
4283  /* Delay after an RCC peripheral clock enabling */ \
4284  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
4285  UNUSED(tmpreg); \
4286  } while(0)
4287 
4288 #define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \
4289  __IO uint32_t tmpreg; \
4290  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
4291  /* Delay after an RCC peripheral clock enabling */ \
4292  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
4293  UNUSED(tmpreg); \
4294  } while(0)
4295 
4296 #define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \
4297  __IO uint32_t tmpreg; \
4298  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
4299  /* Delay after an RCC peripheral clock enabling */ \
4300  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
4301  UNUSED(tmpreg); \
4302  } while(0)
4303 
4304 #define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \
4305  __IO uint32_t tmpreg; \
4306  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
4307  /* Delay after an RCC peripheral clock enabling */ \
4308  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
4309  UNUSED(tmpreg); \
4310  } while(0)
4311 
4312 #define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \
4313  __IO uint32_t tmpreg; \
4314  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
4315  /* Delay after an RCC peripheral clock enabling */ \
4316  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
4317  UNUSED(tmpreg); \
4318  } while(0)
4319 
4320 #define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \
4321  __IO uint32_t tmpreg; \
4322  SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
4323  /* Delay after an RCC peripheral clock enabling */ \
4324  tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
4325  UNUSED(tmpreg); \
4326  } while(0)
4327 
4328 #define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \
4329  __IO uint32_t tmpreg; \
4330  SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
4331  /* Delay after an RCC peripheral clock enabling */ \
4332  tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
4333  UNUSED(tmpreg); \
4334  } while(0)
4335 
4336 #define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \
4337  __IO uint32_t tmpreg; \
4338  SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
4339  /* Delay after an RCC peripheral clock enabling */ \
4340  tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
4341  UNUSED(tmpreg); \
4342  } while(0)
4343 
4344 #define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \
4345  __IO uint32_t tmpreg; \
4346  SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
4347  /* Delay after an RCC peripheral clock enabling */ \
4348  tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
4349  UNUSED(tmpreg); \
4350  } while(0)
4351 
4352 #define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \
4353  __IO uint32_t tmpreg; \
4354  SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
4355  /* Delay after an RCC peripheral clock enabling */ \
4356  tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
4357  UNUSED(tmpreg); \
4358  } while(0)
4359 
4360 #define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \
4361  __IO uint32_t tmpreg; \
4362  SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
4363  /* Delay after an RCC peripheral clock enabling */ \
4364  tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
4365  UNUSED(tmpreg); \
4366  } while(0)
4367 
4368 
4369 #define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
4370 #define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
4371 #define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
4372 #define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
4373 #define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
4374 #define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
4375 #define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
4376 #define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
4377 #define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
4378 #define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
4379 #define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
4380 #define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
4381 #define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
4382 #define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
4383 #define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
4384 #define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
4385 #define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
4386 #define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
4387 #define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
4388 #define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
4389 #define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
4390 #define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
4391 #define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
4392 #define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
4393 #define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
4394 #define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
4395 #define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
4396 #define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
4397 #define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
4398 #define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
4399 
4406 #define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \
4407  __IO uint32_t tmpreg; \
4408  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
4409  /* Delay after an RCC peripheral clock enabling */ \
4410  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
4411  UNUSED(tmpreg); \
4412  } while(0)
4413 
4414 #define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \
4415  __IO uint32_t tmpreg; \
4416  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
4417  /* Delay after an RCC peripheral clock enabling */ \
4418  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
4419  UNUSED(tmpreg); \
4420  } while(0)
4421 
4422 #define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \
4423  __IO uint32_t tmpreg; \
4424  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
4425  /* Delay after an RCC peripheral clock enabling */ \
4426  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
4427  UNUSED(tmpreg); \
4428  } while(0)
4429 
4430 #define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \
4431  __IO uint32_t tmpreg; \
4432  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
4433  /* Delay after an RCC peripheral clock enabling */ \
4434  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
4435  UNUSED(tmpreg); \
4436  } while(0)
4437 
4438 #define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \
4439  __IO uint32_t tmpreg; \
4440  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
4441  /* Delay after an RCC peripheral clock enabling */ \
4442  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
4443  UNUSED(tmpreg); \
4444  } while(0)
4445 
4446 #define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \
4447  __IO uint32_t tmpreg; \
4448  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
4449  /* Delay after an RCC peripheral clock enabling */ \
4450  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
4451  UNUSED(tmpreg); \
4452  } while(0)
4453 
4454 #define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \
4455  __IO uint32_t tmpreg; \
4456  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
4457  /* Delay after an RCC peripheral clock enabling */ \
4458  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
4459  UNUSED(tmpreg); \
4460  } while(0)
4461 
4462 #define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \
4463  __IO uint32_t tmpreg; \
4464  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
4465  /* Delay after an RCC peripheral clock enabling */ \
4466  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
4467  UNUSED(tmpreg); \
4468  } while(0)
4469 
4470 #define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \
4471  __IO uint32_t tmpreg; \
4472  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
4473  /* Delay after an RCC peripheral clock enabling */ \
4474  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
4475  UNUSED(tmpreg); \
4476  } while(0)
4477 
4478 #define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \
4479  __IO uint32_t tmpreg; \
4480  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
4481  /* Delay after an RCC peripheral clock enabling */ \
4482  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
4483  UNUSED(tmpreg); \
4484  } while(0)
4485 
4486 #define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \
4487  __IO uint32_t tmpreg; \
4488  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
4489  /* Delay after an RCC peripheral clock enabling */ \
4490  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
4491  UNUSED(tmpreg); \
4492  } while(0)
4493 
4494 #define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \
4495  __IO uint32_t tmpreg; \
4496  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
4497  /* Delay after an RCC peripheral clock enabling */ \
4498  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
4499  UNUSED(tmpreg); \
4500  } while(0)
4501 
4502 #define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \
4503  __IO uint32_t tmpreg; \
4504  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
4505  /* Delay after an RCC peripheral clock enabling */ \
4506  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
4507  UNUSED(tmpreg); \
4508  } while(0)
4509 
4510 #define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \
4511  __IO uint32_t tmpreg; \
4512  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
4513  /* Delay after an RCC peripheral clock enabling */ \
4514  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
4515  UNUSED(tmpreg); \
4516  } while(0)
4517 
4518 #define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \
4519  __IO uint32_t tmpreg; \
4520  SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
4521  /* Delay after an RCC peripheral clock enabling */ \
4522  tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
4523  UNUSED(tmpreg); \
4524  } while(0)
4525 
4526 #define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
4527 #define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
4528 #define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
4529 #define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
4530 #define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
4531 #define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
4532 #define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
4533 #define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
4534 #define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
4535 #define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
4536 #define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
4537 #define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
4538 #define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
4539 #define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
4540 #define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
4541 
4548 #define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \
4549  __IO uint32_t tmpreg; \
4550  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
4551  /* Delay after an RCC peripheral clock enabling */ \
4552  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
4553  UNUSED(tmpreg); \
4554  } while(0)
4555 
4556 #define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \
4557  __IO uint32_t tmpreg; \
4558  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
4559  /* Delay after an RCC peripheral clock enabling */ \
4560  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
4561  UNUSED(tmpreg); \
4562  } while(0)
4563 
4564 #define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \
4565  __IO uint32_t tmpreg; \
4566  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
4567  /* Delay after an RCC peripheral clock enabling */ \
4568  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
4569  UNUSED(tmpreg); \
4570  } while(0)
4571 
4572 #define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \
4573  __IO uint32_t tmpreg; \
4574  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
4575  /* Delay after an RCC peripheral clock enabling */ \
4576  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
4577  UNUSED(tmpreg); \
4578  } while(0)
4579 
4580 #define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \
4581  __IO uint32_t tmpreg; \
4582  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
4583  /* Delay after an RCC peripheral clock enabling */ \
4584  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
4585  UNUSED(tmpreg); \
4586  } while(0)
4587 
4588 #define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \
4589  __IO uint32_t tmpreg; \
4590  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
4591  /* Delay after an RCC peripheral clock enabling */ \
4592  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
4593  UNUSED(tmpreg); \
4594  } while(0)
4595 
4596 #define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \
4597  __IO uint32_t tmpreg; \
4598  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
4599  /* Delay after an RCC peripheral clock enabling */ \
4600  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
4601  UNUSED(tmpreg); \
4602  } while(0)
4603 
4604 #define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \
4605  __IO uint32_t tmpreg; \
4606  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
4607  /* Delay after an RCC peripheral clock enabling */ \
4608  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
4609  UNUSED(tmpreg); \
4610  } while(0)
4611 
4612 #define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \
4613  __IO uint32_t tmpreg; \
4614  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
4615  /* Delay after an RCC peripheral clock enabling */ \
4616  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
4617  UNUSED(tmpreg); \
4618  } while(0)
4619 
4620 #define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \
4621  __IO uint32_t tmpreg; \
4622  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
4623  /* Delay after an RCC peripheral clock enabling */ \
4624  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
4625  UNUSED(tmpreg); \
4626  } while(0)
4627 
4628 #define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \
4629  __IO uint32_t tmpreg; \
4630  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
4631  /* Delay after an RCC peripheral clock enabling */ \
4632  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
4633  UNUSED(tmpreg); \
4634  } while(0)
4635 
4636 #define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \
4637  __IO uint32_t tmpreg; \
4638  SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
4639  /* Delay after an RCC peripheral clock enabling */ \
4640  tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
4641  UNUSED(tmpreg); \
4642  } while(0)
4643 
4644 
4645 
4646 #define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
4647 #define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
4648 #define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
4649 #define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
4650 #define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
4651 #define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
4652 #define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
4653 #define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
4654 #define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
4655 #define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
4656 #define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
4657 #define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
4658 
4659 #endif /*DUAL_CORE*/
4660 
4664 #if (STM32H7_DEV_ID == 0x450UL)
4665 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */
4666 #elif (STM32H7_DEV_ID == 0x480UL)
4667 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */
4668 #else
4669 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */
4670 #endif /* STM32H7_DEV_ID == 0x450UL */
4671 #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
4672 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
4673 #if defined(JPEG)
4674 #define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
4675 #endif /* JPEG */
4676 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
4677 #if defined(QUADSPI)
4678 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
4679 #endif /*QUADSPI*/
4680 #if defined(OCTOSPI1)
4681 #define __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
4682 #endif /*OCTOSPI1*/
4683 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
4684 #if defined(OCTOSPI2)
4685 #define __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
4686 #endif /*OCTOSPI2*/
4687 #if defined(OCTOSPIM)
4688 #define __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
4689 #endif /*OCTOSPIM*/
4690 #if defined(OTFDEC1)
4691 #define __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
4692 #endif /*OTFDEC1*/
4693 #if defined(OTFDEC2)
4694 #define __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
4695 #endif /*OTFDEC2*/
4696 #if defined(GFXMMU)
4697 #define __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
4698 #endif /*GFXMMU*/
4699 
4700 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
4701 #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
4702 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
4703 #if defined(JPEG)
4704 #define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
4705 #endif /* JPEG */
4706 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
4707 #if defined(QUADSPI)
4708 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
4709 #endif /*QUADSPI*/
4710 #if defined(OCTOSPI1)
4711 #define __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
4712 #endif /*OCTOSPI1*/
4713 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
4714 #if defined(OCTOSPI2)
4715 #define __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
4716 #endif /*OCTOSPI2*/
4717 #if defined(OCTOSPIM)
4718 #define __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
4719 #endif /*OCTOSPIM*/
4720 #if defined(OTFDEC1)
4721 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
4722 #endif /*OTFDEC1*/
4723 #if defined(OTFDEC2)
4724 #define __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
4725 #endif /*OTFDEC2*/
4726 #if defined(GFXMMU)
4727 #define __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
4728 #endif /*GFXMMU*/
4729 
4730 
4731 
4734 #if (STM32H7_DEV_ID == 0x450UL)
4735 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */
4736 #elif (STM32H7_DEV_ID == 0x480UL)
4737 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */
4738 #else
4739 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */
4740 #endif /* STM32H7_DEV_ID == 0x450UL */
4741 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
4742 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
4743 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
4744 #if defined(DUAL_CORE)
4745 #define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))
4746 #endif /*DUAL_CORE*/
4747 #if defined(RCC_AHB1RSTR_CRCRST)
4748 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
4749 #endif
4750 #if defined(ETH)
4751 #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
4752 #endif /*ETH*/
4753 #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
4754 #if defined(USB2_OTG_FS)
4755 #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
4756 #endif /*USB2_OTG_FS*/
4757 
4758 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
4759 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
4760 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
4761 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
4762 #if defined(DUAL_CORE)
4763 #define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))
4764 #endif /*DUAL_CORE*/
4765 #if defined(RCC_AHB1RSTR_CRCRST)
4766 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
4767 #endif
4768 #if defined(ETH)
4769 #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
4770 #endif /*ETH*/
4771 #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
4772 #if defined(USB2_OTG_FS)
4773 #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
4774 #endif /*USB2_OTG_FS*/
4775 
4778 #if (STM32H7_DEV_ID == 0x450UL)
4779 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */
4780 #elif (STM32H7_DEV_ID == 0x480UL)
4781 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */
4782 #else
4783 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */
4784 #endif /* STM32H7_DEV_ID == 0x450UL */
4785 #if defined(DCMI) && defined(PSSI)
4786 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
4787 #define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/
4788 #else
4789 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
4790 #endif /* DCMI && PSSI */
4791 #if defined(CRYP)
4792 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
4793 #endif /* CRYP */
4794 #if defined(HASH)
4795 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
4796 #endif /* HASH */
4797 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
4798 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
4799 #if defined(FMAC)
4800 #define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST))
4801 #endif /*FMAC*/
4802 #if defined(CORDIC)
4803 #define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST))
4804 #endif /*CORDIC*/
4805 #if defined(RCC_AHB2RSTR_HSEMRST)
4806 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
4807 #endif
4808 #if defined(BDMA1)
4809 #define __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
4810 #endif /*BDMA1*/
4811 
4812 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
4813 #if defined(DCMI) && defined(PSSI)
4814 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
4815 #define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/
4816 #else
4817 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
4818 #endif /* DCMI && PSSI */
4819 #if defined(CRYP)
4820 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
4821 #endif /* CRYP */
4822 #if defined(HASH)
4823 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
4824 #endif /* HASH */
4825 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
4826 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
4827 #if defined(FMAC)
4828 #define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST))
4829 #endif /*FMAC*/
4830 #if defined(CORDIC)
4831 #define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST))
4832 #endif /*CORDIC*/
4833 #if defined(RCC_AHB2RSTR_HSEMRST)
4834 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
4835 #endif
4836 #if defined(BDMA1)
4837 #define __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
4838 #endif /*BDMA1*/
4839 
4840 
4844 #if (STM32H7_DEV_ID == 0x450UL)
4845 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */
4846 #elif (STM32H7_DEV_ID == 0x480UL)
4847 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */
4848 #else
4849 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */
4850 #endif /* STM32H7_DEV_ID == 0x450UL */
4851 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
4852 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
4853 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
4854 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
4855 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
4856 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
4857 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
4858 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
4859 #if defined(GPIOI)
4860 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
4861 #endif /* GPIOI */
4862 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
4863 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
4864 #if defined(RCC_AHB4RSTR_CRCRST)
4865 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
4866 #endif
4867 #if defined(BDMA2)
4868 #define __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
4869 #define __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/
4870 #else
4871 #define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
4872 #endif /*BDMA2*/
4873 #if defined(ADC3)
4874 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
4875 #endif /*ADC3*/
4876 #if defined(RCC_AHB4RSTR_HSEMRST)
4877 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
4878 #endif
4879 
4880 #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U)
4881 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
4882 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
4883 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
4884 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
4885 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
4886 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
4887 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
4888 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
4889 #if defined(GPIOI)
4890 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
4891 #endif /* GPIOI */
4892 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
4893 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
4894 #if defined(RCC_AHB4RSTR_CRCRST)
4895 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
4896 #endif
4897 #if defined(BDMA2)
4898 #define __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
4899 #define __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/
4900 #else
4901 #define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
4902 #endif /*BDMA2*/
4903 #if defined(ADC3)
4904 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
4905 #endif /*ADC3*/
4906 #if defined(RCC_AHB4RSTR_HSEMRST)
4907 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
4908 #endif
4909 
4912 #if (STM32H7_DEV_ID == 0x450UL)
4913 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */
4914 #else
4915 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */
4916 #endif /* STM32H7_DEV_ID == 0x450UL */
4917 #if defined(LTDC)
4918 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
4919 #endif /* LTDC */
4920 #if defined(DSI)
4921 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)
4922 #endif /*DSI*/
4923 
4924 #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U)
4925 #if defined(LTDC)
4926 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
4927 #endif /* LTDC */
4928 #if defined(DSI)
4929 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)
4930 #endif /*DSI*/
4931 
4934 #if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
4935 #define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */
4936 #else
4937 #define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */
4938 #endif /* STM32H7_DEV_ID == 0x450UL */
4939 #if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
4940 #define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */
4941 #else
4942 #define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */
4943 #endif /* STM32H7_DEV_ID == 0x450UL */
4944 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
4945 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
4946 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
4947 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
4948 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
4949 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
4950 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
4951 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
4952 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
4953 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
4954 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
4955 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
4956 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
4957 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
4958 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
4959 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
4960 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
4961 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
4962 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
4963 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
4964 #if defined(I2C5)
4965 #define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST)
4966 #endif /* I2C5 */
4967 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
4968 #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
4969 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
4970 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
4971 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
4972 #define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
4973 #define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
4974 #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
4975 #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
4976 #if defined(TIM23)
4977 #define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST)
4978 #endif /* TIM23 */
4979 #if defined(TIM24)
4980 #define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST)
4981 #endif /* TIM24 */
4982 
4983 #define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)
4984 #define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)
4985 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
4986 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
4987 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
4988 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
4989 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
4990 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
4991 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
4992 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
4993 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
4994 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
4995 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
4996 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
4997 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
4998 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
4999 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
5000 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
5001 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
5002 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
5003 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
5004 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
5005 #if defined(I2C5)
5006 #define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST)
5007 #endif /* I2C5 */
5008 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
5009 #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
5010 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
5011 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
5012 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
5013 #define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
5014 #define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
5015 #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
5016 #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
5017 #if defined(TIM23)
5018 #define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST)
5019 #endif /* TIM23 */
5020 #if defined(TIM24)
5021 #define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST)
5022 #endif /* TIM24 */
5023 
5026 #if (STM32H7_DEV_ID == 0x450UL)
5027 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */
5028 #elif (STM32H7_DEV_ID == 0x480UL)
5029 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */
5030 #else
5031 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */
5032 #endif /* STM32H7_DEV_ID == 0x450UL */
5033 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
5034 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
5035 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
5036 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
5037 #if defined(UART9)
5038 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
5039 #endif /*UART9*/
5040 #if defined(USART10)
5041 #define __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
5042 #endif /*USART10*/
5043 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
5044 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
5045 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
5046 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
5047 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
5048 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
5049 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
5050 #if defined(SAI2)
5051 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
5052 #endif /* SAI2 */
5053 #if defined(SAI3)
5054 #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
5055 #endif /*SAI3*/
5056 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
5057 #if defined(HRTIM1)
5058 #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
5059 #endif /*HRTIM1*/
5060 
5061 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
5062 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
5063 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
5064 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
5065 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
5066 #if defined(UART9)
5067 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
5068 #endif /*UART9*/
5069 #if defined(USART10)
5070 #define __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
5071 #endif /*USART10*/
5072 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
5073 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
5074 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
5075 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
5076 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
5077 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
5078 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
5079 #if defined(SAI2)
5080 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
5081 #endif /* SAI2 */
5082 #if defined(SAI3)
5083 #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
5084 #endif /*SAI3*/
5085 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
5086 #if defined(HRTIM1)
5087 #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
5088 #endif /*HRTIM1*/
5089 
5093 #if (STM32H7_DEV_ID == 0x450UL)
5094 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */
5095 #elif (STM32H7_DEV_ID == 0x480UL)
5096 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */
5097 #else
5098 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */
5099 #endif /* STM32H7_DEV_ID == 0x450UL */
5100 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
5101 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
5102 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
5103 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
5104 #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
5105 #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
5106 #if defined(LPTIM4)
5107 #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
5108 #endif /*LPTIM4*/
5109 #if defined(LPTIM5)
5110 #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
5111 #endif /*LPTIM5*/
5112 #if defined(DAC2)
5113 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
5114 #endif /*DAC2*/
5115 #define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
5116 #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
5117 #if defined(SAI4)
5118 #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
5119 #endif /*SAI4*/
5120 #if defined(DTS)
5121 #define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
5122 #endif /*DTS*/
5123 #if defined(DFSDM2_BASE)
5124 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
5125 #endif /*DFSDM2*/
5126 
5127 #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U)
5128 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
5129 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
5130 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
5131 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
5132 #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
5133 #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
5134 #if defined(LPTIM4)
5135 #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
5136 #endif /*LPTIM4*/
5137 #if defined(LPTIM5)
5138 #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
5139 #endif /*LPTIM5*/
5140 #if defined(RCC_APB4RSTR_DAC2RST)
5141 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
5142 #endif
5143 #define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
5144 #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
5145 #if defined(SAI4)
5146 #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
5147 #endif /*SAI4*/
5148 #if defined(DTS)
5149 #define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
5150 #endif /*DTS*/
5151 #if defined(DFSDM2_BASE)
5152 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
5153 #endif /*DFSDM2*/
5154 
5163 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
5164 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
5165 #if defined(JPEG)
5166 #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
5167 #endif /* JPEG */
5168 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
5169 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
5170 #if defined(QUADSPI)
5171 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
5172 #endif /*QUADSPI*/
5173 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
5174 #if defined(OCTOSPI1)
5175 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
5176 #endif /*OCTOSPI1*/
5177 #if defined(OCTOSPI2)
5178 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
5179 #endif /*OCTOSPI2*/
5180 #if defined(OCTOSPIM)
5181 #define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
5182 #endif /*OCTOSPIM*/
5183 #if defined(OTFDEC1)
5184 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
5185 #endif /*OTFDEC1*/
5186 #if defined(OTFDEC2)
5187 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
5188 #endif /*OTFDEC2*/
5189 #if defined(GFXMMU)
5190 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
5191 #endif /*GFXMMU*/
5192 #if defined(CD_AXISRAM2_BASE)
5193 #define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
5194 #endif
5195 #if defined(CD_AXISRAM3_BASE)
5196 #define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
5197 #endif
5198 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
5199 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
5200 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
5201 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
5202 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
5203 #define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
5204 #else
5205 #define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))
5206 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */
5207 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
5208 
5209 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
5210 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
5211 #if defined(JPEG)
5212 #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
5213 #endif /* JPEG */
5214 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
5215 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
5216 #if defined(QUADSPI)
5217 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
5218 #endif /*QUADSPI*/
5219 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
5220 #if defined(OCTOSPI1)
5221 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
5222 #endif /*OCTOSPI1*/
5223 #if defined(OCTOSPI2)
5224 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
5225 #endif /*OCTOSPI2*/
5226 #if defined(OCTOSPIM)
5227 #define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
5228 #endif /*OCTOSPIM*/
5229 #if defined(OTFDEC1)
5230 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
5231 #endif /*OTFDEC1*/
5232 #if defined(OTFDEC2)
5233 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
5234 #endif /*OTFDEC2*/
5235 #if defined(GFXMMU)
5236 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
5237 #endif /*GFXMMU*/
5238 #if defined(CD_AXISRAM2_BASE)
5239 #define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
5240 #endif
5241 #if defined(CD_AXISRAM3_BASE)
5242 #define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
5243 #endif
5244 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
5245 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
5246 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
5247 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
5248 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
5249 #define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
5250 #else
5251 #define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))
5252 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */
5253 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
5254 
5262 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)
5263 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)
5264 #if defined(JPEG)
5265 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U)
5266 #endif /* JPEG */
5267 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)
5268 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)
5269 #if defined(QUADSPI)
5270 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U)
5271 #endif /*QUADSPI*/
5272 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)
5273 #if defined(OCTOSPI1)
5274 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U)
5275 #endif /*OCTOSPI1*/
5276 #if defined(OCTOSPI2)
5277 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U)
5278 #endif /*OCTOSPI2*/
5279 #if defined(OCTOSPIM)
5280 #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U)
5281 #endif /*OCTOSPIM*/
5282 #if defined(OTFDEC1)
5283 #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
5284 #endif /*OTFDEC1*/
5285 #if defined(OTFDEC2)
5286 #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
5287 #endif /*OTFDEC2*/
5288 #if defined(GFXMMU)
5289 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U)
5290 #endif /*GFXMMU*/
5291 #if defined(CD_AXISRAM2_BASE)
5292 #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U)
5293 #endif
5294 #if defined(CD_AXISRAM3_BASE)
5295 #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U)
5296 #endif
5297 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)
5298 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)
5299 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)
5300 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
5301 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
5302 #else
5303 #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)
5304 #endif
5305 
5306 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)
5307 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)
5308 #if defined(JPEG)
5309 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U)
5310 #endif /* JPEG */
5311 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)
5312 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)
5313 #if defined(QUADSPI)
5314 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U)
5315 #endif /*QUADSPI*/
5316 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)
5317 #if defined(OCTOSPI1)
5318 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U)
5319 #endif /*OCTOSPI1*/
5320 #if defined(OCTOSPI2)
5321 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U)
5322 #endif /*OCTOSPI2*/
5323 #if defined(OCTOSPIM)
5324 #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
5325 #endif /*OCTOSPIM*/
5326 #if defined(OTFDEC1)
5327 #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U)
5328 #endif /*OTFDEC1*/
5329 #if defined(OTFDEC2)
5330 #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U)
5331 #endif /*OTFDEC2*/
5332 #if defined(GFXMMU)
5333 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U)
5334 #endif /*GFXMMU*/
5335 #if defined(CD_AXISRAM2_BASE)
5336 #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U)
5337 #endif
5338 #if defined(CD_AXISRAM3_BASE)
5339 #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U)
5340 #endif
5341 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)
5342 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)
5343 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)
5344 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
5345 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
5346 #else
5347 #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)
5348 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
5349 
5357 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
5358 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
5359 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
5360 #if defined(RCC_AHB1LPENR_CRCLPEN)
5361 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
5362 #endif
5363 #if defined(ETH)
5364 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
5365 #endif /*ETH*/
5366 #if defined(DUAL_CORE)
5367 #define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))
5368 #endif /*DUAL_CORE*/
5369 #if defined(ETH)
5370 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
5371 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
5372 #endif /*ETH*/
5373 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
5374 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
5375 #if defined(USB2_OTG_FS)
5376 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
5377 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
5378 #endif /* USB2_OTG_FS */
5379 
5380 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
5381 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
5382 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
5383 #if defined(RCC_AHB1LPENR_CRCLPEN)
5384 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
5385 #endif
5386 #if defined(ETH)
5387 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
5388 #endif /*ETH*/
5389 #if defined(DUAL_CORE)
5390 #define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))
5391 #endif /*DUAL_CORE*/
5392 #if defined(ETH)
5393 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
5394 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
5395 #endif /*ETH*/
5396 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
5397 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
5398 #if defined(USB2_OTG_FS)
5399 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
5400 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
5401 #endif /* USB2_OTG_FS */
5402 
5410 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)
5411 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)
5412 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)
5413 #if defined(RCC_AHB1LPENR_CRCLPEN)
5414 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U)
5415 #endif
5416 #if defined(ETH)
5417 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U)
5418 #endif /*ETH*/
5419 #if defined(DUAL_CORE)
5420 #define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U)
5421 #endif /*DUAL_CORE*/
5422 #if defined(ETH)
5423 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U)
5424 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U)
5425 #endif /*ETH*/
5426 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)
5427 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
5428 #if defined(USB2_OTG_FS)
5429 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U)
5430 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)
5431 #endif /* USB2_OTG_FS */
5432 
5433 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)
5434 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)
5435 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)
5436 #if defined(RCC_AHB1LPENR_CRCLPEN)
5437 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U)
5438 #endif
5439 #if defined(ETH)
5440 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U)
5441 #endif /* ETH */
5442 #if defined(DUAL_CORE)
5443 #define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U)
5444 #endif /*DUAL_CORE*/
5445 #if defined(ETH)
5446 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U)
5447 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U)
5448 #endif /* ETH */
5449 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)
5450 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
5451 #if defined(USB2_OTG_FS)
5452 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U)
5453 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)
5454 #endif /* USB2_OTG_FS */
5455 
5456 
5464 #if defined(DCMI) && defined(PSSI)
5465 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
5466 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/
5467 #else
5468 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
5469 #endif /* DCMI && PSSI */
5470 #if defined(CRYP)
5471 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
5472 #endif /* CRYP */
5473 #if defined(HASH)
5474 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
5475 #endif /* HASH */
5476 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
5477 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
5478 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
5479 #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
5480 #endif
5481 #if defined(FMAC)
5482 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN))
5483 #endif /* FMAC */
5484 #if defined(CORDIC)
5485 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN))
5486 #endif /* CORDIC */
5487 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
5488 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
5489 #else
5490 #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
5491 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
5492 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
5493 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
5494 #else
5495 #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
5496 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
5497 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
5498 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
5499 #endif
5500 
5501 #if defined(DCMI) && defined(PSSI)
5502 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
5503 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/
5504 #else
5505 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
5506 #endif /* DCMI && PSSI */
5507 #if defined(CRYP)
5508 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
5509 #endif /* CRYP */
5510 #if defined(HASH)
5511 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
5512 #endif /* HASH */
5513 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
5514 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
5515 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
5516 #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
5517 #endif
5518 #if defined(FMAC)
5519 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN))
5520 #endif /* FMAC */
5521 #if defined(CORDIC)
5522 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN))
5523 #endif /* CORDIC */
5524 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
5525 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
5526 #else
5527 #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
5528 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
5529 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
5530 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
5531 #else
5532 #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
5533 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
5534 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
5535 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
5536 #endif
5537 
5545 #if defined(DCMI) && defined(PSSI)
5546 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U)
5547 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/
5548 #else
5549 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)
5550 #endif /* DCMI && PSSI */
5551 #if defined(CRYP)
5552 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)
5553 #endif /* CRYP */
5554 #if defined(HASH)
5555 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)
5556 #endif /* HASH */
5557 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)
5558 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)
5559 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
5560 #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
5561 #endif
5562 #if defined(FMAC)
5563 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U)
5564 #endif /* FMAC */
5565 #if defined(CORDIC)
5566 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U)
5567 #endif /* CORDIC */
5568 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
5569 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
5570 #else
5571 #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
5572 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
5573 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
5574 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)
5575 #else
5576 #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
5577 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
5578 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
5579 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)
5580 #endif /* RCC_AHB2LPENR_D2SRAM3LPEN */
5581 
5582 #if defined(DCMI) && defined(PSSI)
5583 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U)
5584 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/
5585 #else
5586 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U)
5587 #endif /* DCMI && PSSI */
5588 #if defined(CRYP)
5589 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)
5590 #endif /* CRYP */
5591 #if defined(HASH)
5592 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)
5593 #endif /* HASH */
5594 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)
5595 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
5596 #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
5597 #endif
5598 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)
5599 #if defined(FMAC)
5600 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U)
5601 #endif /* FMAC */
5602 #if defined(CORDIC)
5603 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U)
5604 #endif /* CORDIC */
5605 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
5606 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
5607 #else
5608 #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
5609 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
5610 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
5611 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)
5612 #else
5613 #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
5614 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
5615 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
5616 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)
5617 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/
5618 
5619 
5627 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
5628 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
5629 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
5630 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
5631 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
5632 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
5633 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
5634 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
5635 #if defined(GPIOI)
5636 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
5637 #endif /* GPIOI */
5638 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
5639 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
5640 #if defined(RCC_AHB4LPENR_CRCLPEN)
5641 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
5642 #endif
5643 #if defined(BDMA2)
5644 #define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
5645 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
5646 #else
5647 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
5648 #endif /* BDMA2 */
5649 #if defined(ADC3)
5650 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
5651 #endif /* ADC3 */
5652 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
5653 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
5654 #define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN))
5655 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
5656 #else
5657 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
5658 #endif /* RCC_AHB4LPENR_SRDSRAMLPEN */
5659 
5660 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
5661 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
5662 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
5663 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
5664 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
5665 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
5666 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
5667 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
5668 #if defined(GPIOI)
5669 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
5670 #endif /* GPIOI */
5671 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
5672 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
5673 #if defined(RCC_AHB4LPENR_CRCLPEN)
5674 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
5675 #endif
5676 #if defined(BDMA2)
5677 #define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
5678 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/
5679 #else
5680 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
5681 #endif /*BDMA2*/
5682 #if defined(ADC3)
5683 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
5684 #endif /*ADC3*/
5685 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
5686 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
5687 #define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
5688 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
5689 #else
5690 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
5691 #endif
5692 
5693 
5701 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)
5702 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)
5703 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)
5704 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)
5705 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)
5706 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)
5707 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)
5708 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)
5709 #if defined(GPIOI)
5710 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U)
5711 #endif /* GPIOI */
5712 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)
5713 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)
5714 #if defined(RCC_AHB4LPENR_CRCLPEN)
5715 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U)
5716 #endif
5717 #if defined(BDMA2)
5718 #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U)
5719 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/
5720 #else
5721 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U)
5722 #endif /*BDMA2*/
5723 #if defined(ADC3)
5724 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U)
5725 #endif /*ADC3*/
5726 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)
5727 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
5728 #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
5729 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/
5730 #else
5731 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)
5732 #endif
5733 
5734 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)
5735 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)
5736 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)
5737 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)
5738 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)
5739 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)
5740 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)
5741 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)
5742 #if defined(GPIOI)
5743 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U)
5744 #endif /* GPIOI */
5745 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)
5746 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)
5747 #if defined(RCC_AHB4LPENR_CRCLPEN)
5748 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U)
5749 #endif
5750 #if defined(BDMA2)
5751 #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U)
5752 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/
5753 #else
5754 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U)
5755 #endif /*BDMA2*/
5756 #if defined(ADC3)
5757 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U)
5758 #endif /*ADC3*/
5759 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)
5760 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
5761 #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
5762 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/
5763 #else
5764 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)
5765 #endif
5766 
5767 
5775 #if defined(LTDC)
5776 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
5777 #endif /* LTDC */
5778 #if defined(DSI)
5779 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
5780 #endif /*DSI*/
5781 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
5782 
5783 #if defined(LTDC)
5784 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
5785 #endif /* LTDC */
5786 #if defined(DSI)
5787 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
5788 #endif /*DSI*/
5789 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
5790 
5791 
5799 #if defined(LTDC)
5800 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U)
5801 #endif /* LTDC */
5802 #if defined(DSI)
5803 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U)
5804 #endif /*DSI*/
5805 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
5806 
5807 #if defined(LTDC)
5808 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U)
5809 #endif /* LTDC */
5810 #if defined(DSI)
5811 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U)
5812 #endif /*DSI*/
5813 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
5814 
5815 
5823 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
5824 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
5825 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
5826 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
5827 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
5828 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
5829 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
5830 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
5831 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
5832 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
5833 
5834 #if defined(DUAL_CORE)
5835 #define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
5836 #endif /*DUAL_CORE*/
5837 
5838 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
5839 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
5840 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
5841 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
5842 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
5843 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
5844 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
5845 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
5846 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
5847 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
5848 #if defined(I2C5)
5849 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN)
5850 #endif /* I2C5 */
5851 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
5852 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
5853 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
5854 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
5855 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
5856 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
5857 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
5858 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
5859 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
5860 #if defined(TIM23)
5861 #define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN)
5862 #endif /* TIM23 */
5863 #if defined(TIM24)
5864 #define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN)
5865 #endif /* TIM24 */
5866 
5867 
5868 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
5869 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
5870 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
5871 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
5872 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
5873 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
5874 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
5875 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
5876 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
5877 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
5878 
5879 #if defined(DUAL_CORE)
5880 #define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
5881 #endif /*DUAL_CORE*/
5882 
5883 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
5884 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
5885 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
5886 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
5887 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
5888 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
5889 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
5890 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
5891 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
5892 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
5893 #if defined(I2C5)
5894 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN)
5895 #endif /* I2C5 */
5896 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
5897 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
5898 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
5899 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
5900 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
5901 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
5902 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
5903 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
5904 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
5905 #if defined(TIM23)
5906 #define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN)
5907 #endif /* TIM23 */
5908 #if defined(TIM24)
5909 #define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN)
5910 #endif /* TIM24 */
5911 
5912 
5920 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)
5921 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)
5922 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)
5923 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)
5924 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)
5925 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)
5926 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)
5927 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)
5928 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)
5929 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)
5930 #if defined(DUAL_CORE)
5931 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U)
5932 #endif /*DUAL_CORE*/
5933 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)
5934 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)
5935 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
5936 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)
5937 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)
5938 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)
5939 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)
5940 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)
5941 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)
5942 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)
5943 #if defined(I2C5)
5944 #define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U)
5945 #endif /* I2C5 */
5946 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)
5947 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)
5948 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)
5949 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)
5950 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)
5951 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)
5952 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)
5953 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)
5954 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)
5955 #if defined(TIM23)
5956 #define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U)
5957 #endif /* TIM23 */
5958 #if defined(TIM24)
5959 #define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U)
5960 #endif /* TIM24 */
5961 
5962 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)
5963 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)
5964 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)
5965 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)
5966 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)
5967 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)
5968 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)
5969 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)
5970 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)
5971 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)
5972 #if defined(DUAL_CORE)
5973 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U)
5974 #endif /*DUAL_CORE*/
5975 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)
5976 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)
5977 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
5978 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)
5979 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)
5980 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)
5981 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)
5982 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)
5983 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)
5984 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)
5985 #if defined(I2C5)
5986 #define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U)
5987 #endif /* I2C5 */
5988 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)
5989 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)
5990 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)
5991 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)
5992 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)
5993 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)
5994 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)
5995 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)
5996 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)
5997 #if defined(TIM23)
5998 #define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U)
5999 #endif /* TIM23 */
6000 #if defined(TIM24)
6001 #define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U)
6002 #endif /* TIM24 */
6003 
6004 
6012 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
6013 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
6014 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
6015 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
6016 #if defined(UART9)
6017 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
6018 #endif /*UART9*/
6019 #if defined(USART10)
6020 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
6021 #endif /*USART10*/
6022 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
6023 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
6024 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
6025 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
6026 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
6027 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
6028 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
6029 #if defined(SAI2)
6030 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
6031 #endif /* SAI2 */
6032 #if defined(SAI3)
6033 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
6034 #endif /*SAI3*/
6035 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
6036 #if defined(HRTIM1)
6037 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
6038 #endif /*HRTIM1*/
6039 
6040 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
6041 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
6042 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
6043 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
6044 #if defined(UART9)
6045 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
6046 #endif /*UART9*/
6047 #if defined(USART10)
6048 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
6049 #endif /*USART10*/
6050 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
6051 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
6052 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
6053 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
6054 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
6055 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
6056 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
6057 #if defined(SAI2)
6058 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
6059 #endif /* SAI2 */
6060 #if defined(SAI3)
6061 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
6062 #endif /*SAI3*/
6063 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
6064 #if defined(HRTIM1)
6065 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
6066 #endif /*HRTIM1*/
6067 
6068 
6076 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)
6077 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)
6078 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
6079 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
6080 #if defined(UART9)
6081 #define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
6082 #endif /*UART9*/
6083 #if defined(USART10)
6084 #define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
6085 #endif /*USART10*/
6086 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
6087 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)
6088 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)
6089 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)
6090 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)
6091 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)
6092 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)
6093 #if defined(SAI2)
6094 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U)
6095 #endif /* SAI2 */
6096 #if defined(SAI3)
6097 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U)
6098 #endif /*SAI3*/
6099 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
6100 #if defined(HRTIM1)
6101 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U)
6102 #endif /*HRTIM1*/
6103 
6104 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)
6105 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)
6106 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
6107 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
6108 #if defined(UART9)
6109 #define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
6110 #endif /*UART9*/
6111 #if defined(USART10)
6112 #define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
6113 #endif /*USART10*/
6114 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
6115 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)
6116 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)
6117 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)
6118 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)
6119 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)
6120 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)
6121 #if defined(SAI2)
6122 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U)
6123 #endif /* SAI2 */
6124 #if defined(SAI3)
6125 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U)
6126 #endif /*SAI3*/
6127 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
6128 #if defined(HRTIM1)
6129 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U)
6130 #endif /*HRTIM1*/
6131 
6139 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
6140 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
6141 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
6142 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
6143 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
6144 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
6145 #if defined(LPTIM4)
6146 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
6147 #endif /*LPTIM4*/
6148 #if defined(LPTIM5)
6149 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
6150 #endif /*LPTIM5*/
6151 #if defined(DAC2)
6152 #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
6153 #endif /*DAC2*/
6154 #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
6155 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
6156 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
6157 #if defined(SAI4)
6158 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
6159 #endif /*SAI4*/
6160 #if defined(DTS)
6161 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
6162 #endif /*DTS*/
6163 #if defined(DFSDM2_BASE)
6164 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
6165 #endif /*DFSDM2*/
6166 
6167 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
6168 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
6169 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
6170 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
6171 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
6172 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
6173 #if defined(LPTIM4)
6174 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
6175 #endif /*LPTIM4*/
6176 #if defined(LPTIM5)
6177 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
6178 #endif /*LPTIM5*/
6179 #if defined(DAC2)
6180 #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
6181 #endif /*DAC2*/
6182 #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
6183 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
6184 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
6185 #if defined(SAI4)
6186 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
6187 #endif /*SAI4*/
6188 #if defined(DTS)
6189 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
6190 #endif /*DTS*/
6191 #if defined(DFSDM2_BASE)
6192 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
6193 #endif /*DFSDM2*/
6194 
6195 
6203 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)
6204 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
6205 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)
6206 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)
6207 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)
6208 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)
6209 #if defined(LPTIM4)
6210 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U)
6211 #endif /*LPTIM4*/
6212 #if defined(LPTIM5)
6213 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U)
6214 #endif /*LPTIM5*/
6215 #if defined(DAC2)
6216 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U)
6217 #endif /*DAC2*/
6218 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)
6219 #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)
6220 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)
6221 #if defined(SAI4)
6222 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U)
6223 #endif /*SAI4*/
6224 #if defined(DTS)
6225 #define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U)
6226 #endif /*DTS*/
6227 #if defined(DFSDM2_BASE)
6228 #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
6229 #endif /*DFSDM2*/
6230 
6231 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)
6232 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
6233 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)
6234 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)
6235 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)
6236 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)
6237 #if defined(LPTIM4)
6238 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U)
6239 #endif /*LPTIM4*/
6240 #if defined(LPTIM5)
6241 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U)
6242 #endif /*LPTIM5*/
6243 #if defined(DAC2)
6244 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U)
6245 #endif /*DAC2*/
6246 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)
6247 #define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)
6248 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)
6249 #if defined(SAI4)
6250 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U)
6251 #endif /*SAI4*/
6252 #if defined(DTS)
6253 #define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U)
6254 #endif /*DTS*/
6255 #if defined(DFSDM2_BASE)
6256 #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
6257 #endif /*DFSDM2*/
6258 
6259 
6260 #if defined(DUAL_CORE)
6261 
6268 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
6269 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
6270 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
6271 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
6272 #define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
6273 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
6274 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
6275 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
6276 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
6277 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
6278 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
6279 
6280 
6281 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
6282 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
6283 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
6284 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
6285 #define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
6286 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
6287 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
6288 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
6289 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
6290 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
6291 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
6292 
6293 
6294 
6302 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
6303 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
6304 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
6305 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
6306 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
6307 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
6308 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
6309 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
6310 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
6311 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
6312 
6313 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
6314 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
6315 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
6316 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
6317 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
6318 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
6319 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
6320 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
6321 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
6322 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
6323 
6331 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
6332 #if defined(CRYP)
6333 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
6334 #endif /* CRYP */
6335 #if defined(HASH)
6336 #define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
6337 #endif /* HASH */
6338 #define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
6339 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
6340 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
6341 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
6342 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
6343 
6344 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
6345 #if defined(CRYP)
6346 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
6347 #endif /* CRYP */
6348 #if defined(HASH)
6349 #define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
6350 #endif /* HASH */
6351 #define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
6352 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
6353 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
6354 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
6355 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
6356 
6364 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
6365 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
6366 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
6367 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
6368 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
6369 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
6370 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
6371 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
6372 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
6373 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
6374 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
6375 #define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
6376 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
6377 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
6378 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
6379 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
6380 
6381 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
6382 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
6383 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
6384 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
6385 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
6386 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
6387 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
6388 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
6389 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
6390 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
6391 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
6392 #define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
6393 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
6394 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
6395 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
6396 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
6397 
6405 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
6406 #define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
6407 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
6408 
6409 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
6410 #define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
6411 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
6412 
6420 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
6421 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
6422 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
6423 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
6424 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
6425 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
6426 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
6427 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
6428 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
6429 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
6430 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
6431 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
6432 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
6433 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
6434 #define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
6435 #define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
6436 #define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
6437 #define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
6438 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
6439 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
6440 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
6441 #define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
6442 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
6443 #define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
6444 #define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
6445 #define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
6446 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
6447 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
6448 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
6449 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
6450 
6451 
6452 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
6453 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
6454 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
6455 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
6456 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
6457 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
6458 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
6459 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
6460 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
6461 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
6462 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
6463 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
6464 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
6465 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
6466 #define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
6467 #define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
6468 #define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
6469 #define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
6470 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
6471 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
6472 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
6473 #define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
6474 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
6475 #define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
6476 #define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
6477 #define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
6478 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
6479 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
6480 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
6481 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
6482 
6490 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
6491 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
6492 #define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
6493 #define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
6494 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
6495 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
6496 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
6497 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
6498 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
6499 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
6500 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
6501 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
6502 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
6503 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
6504 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
6505 
6506 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
6507 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
6508 #define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
6509 #define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
6510 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
6511 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
6512 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
6513 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
6514 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
6515 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
6516 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
6517 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
6518 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
6519 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
6520 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
6521 
6529 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
6530 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
6531 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
6532 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
6533 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
6534 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
6535 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
6536 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
6537 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
6538 #define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
6539 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
6540 #define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
6541 
6542 
6543 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
6544 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
6545 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
6546 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
6547 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
6548 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
6549 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
6550 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
6551 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
6552 #define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
6553 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
6554 #define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
6555 
6564 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
6565 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
6566 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
6567 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
6568 #define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
6569 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
6570 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
6571 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
6572 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
6573 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
6574 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
6575 
6576 
6577 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
6578 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
6579 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
6580 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
6581 #define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
6582 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
6583 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
6584 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
6585 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
6586 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
6587 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
6588 
6589 
6590 
6598 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
6599 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
6600 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
6601 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
6602 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
6603 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
6604 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
6605 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
6606 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
6607 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
6608 
6609 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
6610 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
6611 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
6612 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
6613 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
6614 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
6615 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
6616 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
6617 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
6618 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
6619 
6627 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
6628 #if defined(CRYP)
6629 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
6630 #endif /* CRYP */
6631 #if defined(HASH)
6632 #define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
6633 #endif /* HASH */
6634 #define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
6635 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
6636 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
6637 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
6638 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
6639 
6640 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
6641 #if defined(CRYP)
6642 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
6643 #endif /* CRYP */
6644 #if defined(HASH)
6645 #define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
6646 #endif /* HASH */
6647 #define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
6648 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
6649 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
6650 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
6651 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
6652 
6660 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
6661 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
6662 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
6663 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
6664 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
6665 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
6666 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
6667 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
6668 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
6669 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
6670 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
6671 #define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
6672 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
6673 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
6674 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
6675 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
6676 
6677 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
6678 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
6679 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
6680 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
6681 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
6682 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
6683 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
6684 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
6685 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
6686 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
6687 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
6688 #define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
6689 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
6690 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
6691 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
6692 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
6693 
6701 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
6702 #define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
6703 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
6704 
6705 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
6706 #define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
6707 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
6708 
6716 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
6717 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
6718 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
6719 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
6720 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
6721 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
6722 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
6723 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
6724 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
6725 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
6726 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
6727 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
6728 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
6729 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
6730 #define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
6731 #define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
6732 #define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
6733 #define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
6734 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
6735 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
6736 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
6737 #define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
6738 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
6739 #define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
6740 #define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
6741 #define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
6742 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
6743 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
6744 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
6745 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
6746 
6747 
6748 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
6749 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
6750 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
6751 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
6752 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
6753 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
6754 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
6755 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
6756 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
6757 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
6758 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
6759 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
6760 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
6761 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
6762 #define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
6763 #define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
6764 #define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
6765 #define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
6766 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
6767 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
6768 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
6769 #define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
6770 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
6771 #define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
6772 #define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
6773 #define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
6774 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
6775 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
6776 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
6777 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
6778 
6786 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
6787 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
6788 #define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
6789 #define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
6790 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
6791 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
6792 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
6793 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
6794 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
6795 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
6796 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
6797 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
6798 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
6799 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
6800 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
6801 
6802 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
6803 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
6804 #define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
6805 #define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
6806 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
6807 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
6808 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
6809 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
6810 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
6811 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
6812 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
6813 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
6814 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
6815 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
6816 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
6817 
6825 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
6826 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
6827 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
6828 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
6829 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
6830 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
6831 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
6832 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
6833 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
6834 #define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
6835 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
6836 #define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
6837 
6838 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
6839 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
6840 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
6841 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
6842 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
6843 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
6844 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
6845 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
6846 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
6847 #define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
6848 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
6849 #define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
6850 
6851 #endif /*DUAL_CORE*/
6852 
6853 #if defined(DUAL_CORE)
6854 
6857 #else
6858 
6861 #endif /*DUAL_CORE*/
6862 
6863 #if defined(RCC_D3AMR_BDMAAMEN)
6864 #define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
6865 #endif
6866 #if defined(RCC_D3AMR_LPUART1AMEN)
6867 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
6868 #endif
6869 #if defined(RCC_D3AMR_SPI6AMEN)
6870 #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
6871 #endif
6872 #if defined(RCC_D3AMR_I2C4AMEN)
6873 #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
6874 #endif
6875 #if defined(RCC_D3AMR_LPTIM2AMEN)
6876 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
6877 #endif
6878 #if defined(RCC_D3AMR_LPTIM3AMEN)
6879 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
6880 #endif
6881 #if defined(LPTIM4)
6882 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
6883 #endif
6884 #if defined(LPTIM5)
6885 #define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
6886 #endif
6887 #if defined(RCC_D3AMR_COMP12AMEN)
6888 #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
6889 #endif
6890 #if defined(RCC_D3AMR_VREFAMEN)
6891 #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
6892 #endif
6893 #if defined(RCC_D3AMR_RTCAMEN)
6894 #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
6895 #endif
6896 #if defined(RCC_D3AMR_CRCAMEN)
6897 #define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
6898 #endif
6899 #if defined(SAI4)
6900 #define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
6901 #endif
6902 #if defined(ADC3)
6903 #define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
6904 #endif
6905 #if defined(RCC_D3AMR_DTSAMEN)
6906 #define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN)
6907 #endif
6908 #if defined(RCC_D3AMR_BKPRAMAMEN)
6909 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
6910 #endif
6911 #if defined(RCC_D3AMR_SRAM4AMEN)
6912 #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
6913 #endif
6914 
6915 #if defined(BDMA2)
6916 #define __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
6917 #endif
6918 #if defined(RCC_SRDAMR_GPIOAMEN)
6919 #define __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
6920 #endif
6921 #if defined(RCC_SRDAMR_LPUART1AMEN)
6922 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
6923 #endif
6924 #if defined(RCC_SRDAMR_SPI6AMEN)
6925 #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
6926 #endif
6927 #if defined(RCC_SRDAMR_I2C4AMEN)
6928 #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
6929 #endif
6930 #if defined(RCC_SRDAMR_LPTIM2AMEN)
6931 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
6932 #endif
6933 #if defined(RCC_SRDAMR_LPTIM3AMEN)
6934 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
6935 #endif
6936 #if defined(DAC2)
6937 #define __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
6938 #endif
6939 #if defined(RCC_SRDAMR_COMP12AMEN)
6940 #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
6941 #endif
6942 #if defined(RCC_SRDAMR_VREFAMEN)
6943 #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
6944 #endif
6945 #if defined(RCC_SRDAMR_RTCAMEN)
6946 #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
6947 #endif
6948 #if defined(RCC_SRDAMR_DTSAMEN)
6949 #define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
6950 #endif
6951 #if defined(DFSDM2_BASE)
6952 #define __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
6953 #endif
6954 #if defined(RCC_SRDAMR_BKPRAMAMEN)
6955 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
6956 #endif
6957 #if defined(RCC_SRDAMR_SRDSRAMAMEN)
6958 #define __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
6959 #endif
6960 
6961 #if defined(RCC_D3AMR_BDMAAMEN)
6962 #define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
6963 #endif
6964 #if defined(RCC_D3AMR_LPUART1AMEN)
6965 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
6966 #endif
6967 #if defined(RCC_D3AMR_SPI6AMEN)
6968 #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
6969 #endif
6970 #if defined(RCC_D3AMR_I2C4AMEN)
6971 #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
6972 #endif
6973 #if defined(RCC_D3AMR_LPTIM2AMEN)
6974 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
6975 #endif
6976 #if defined(RCC_D3AMR_LPTIM3AMEN)
6977 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
6978 #endif
6979 #if defined(LPTIM4)
6980 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
6981 #endif
6982 #if defined(LPTIM5)
6983 #define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
6984 #endif
6985 #if defined(RCC_D3AMR_COMP12AMEN)
6986 #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
6987 #endif
6988 #if defined(RCC_D3AMR_VREFAMEN)
6989 #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
6990 #endif
6991 #if defined(RCC_D3AMR_RTCAMEN)
6992 #define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)
6993 #endif
6994 #if defined(RCC_D3AMR_CRCAMEN)
6995 #define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)
6996 #endif
6997 #if defined(SAI4)
6998 #define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)
6999 #endif
7000 #if defined(ADC3)
7001 #define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)
7002 #endif
7003 #if defined(RCC_D3AMR_DTSAMEN)
7004 #define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN)
7005 #endif
7006 #if defined(RCC_D3AMR_BKPRAMAMEN)
7007 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
7008 #endif
7009 #if defined(RCC_D3AMR_SRAM4AMEN)
7010 #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
7011 #endif
7012 
7013 #if defined(BDMA2)
7014 #define __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
7015 #endif
7016 #if defined(RCC_SRDAMR_GPIOAMEN)
7017 #define __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
7018 #endif
7019 #if defined(RCC_SRDAMR_LPUART1AMEN)
7020 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
7021 #endif
7022 #if defined(RCC_SRDAMR_SPI6AMEN)
7023 #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
7024 #endif
7025 #if defined(RCC_SRDAMR_I2C4AMEN)
7026 #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
7027 #endif
7028 #if defined(RCC_SRDAMR_LPTIM2AMEN)
7029 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
7030 #endif
7031 #if defined(RCC_SRDAMR_LPTIM3AMEN)
7032 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
7033 #endif
7034 #if defined(RCC_SRDAMR_DAC2AMEN)
7035 #define __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
7036 #endif
7037 #if defined(RCC_SRDAMR_COMP12AMEN)
7038 #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
7039 #endif
7040 #if defined(RCC_SRDAMR_VREFAMEN)
7041 #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
7042 #endif
7043 #if defined(RCC_SRDAMR_RTCAMEN)
7044 #define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
7045 #endif
7046 #if defined(RCC_SRDAMR_DTSAMEN)
7047 #define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
7048 #endif
7049 #if defined(DFSDM2_BASE)
7050 #define __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
7051 #endif
7052 #if defined(RCC_SRDAMR_BKPRAMAMEN)
7053 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
7054 #endif
7055 #if defined(RCC_SRDAMR_SRDSRAMAMEN)
7056 #define __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
7057 #endif
7058 
7059 
7060 #if defined(RCC_CKGAENR_AXICKG)
7061 
7064 #define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
7065 #define __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
7066 #define __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
7067 #define __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
7068 #define __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
7069 #define __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
7070 #define __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
7071 #define __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
7072 #define __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
7073 #define __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
7074 #define __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
7075 #define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
7076 #define __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
7077 #define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
7078 #define __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
7079 #define __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
7080 #define __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
7081 #define __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
7082 #define __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
7083 #define __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
7084 #define __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
7085 
7086 
7087 #define __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
7088 #define __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
7089 #define __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
7090 #define __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
7091 #define __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
7092 #define __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
7093 #define __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
7094 #define __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
7095 #define __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
7096 #define __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
7097 #define __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
7098 #define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
7099 #define __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
7100 #define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
7101 #define __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
7102 #define __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
7103 #define __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
7104 #define __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
7105 #define __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
7106 #define __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
7107 #define __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
7108 
7109 #endif /* RCC_CKGAENR_AXICKG */
7110 
7111 
7112 
7113 
7133 #define __HAL_RCC_HSI_CONFIG(__STATE__) \
7134  MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
7135 
7136 
7145 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
7146 
7162 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
7163 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
7164 
7165 
7172 #if defined(RCC_VER_X)
7173 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
7174  do { \
7175  if(HAL_GetREVID() <= REV_ID_Y) \
7176  { \
7177  if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \
7178  { \
7179  MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \
7180  } \
7181  else \
7182  { \
7183  MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \
7184  } \
7185  } \
7186  else \
7187  { \
7188  MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \
7189  } \
7190  } while(0)
7191 
7192 #else
7193 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
7194  MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
7195 #endif /*RCC_VER_X*/
7196 
7205 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
7206 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
7207 
7208 
7216 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
7217 
7218 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
7219 
7236 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
7237 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
7238 
7245 #if defined(RCC_VER_X)
7246 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \
7247  do { \
7248  if(HAL_GetREVID() <= REV_ID_Y) \
7249  { \
7250  if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \
7251  { \
7252  MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \
7253  } \
7254  else \
7255  { \
7256  MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \
7257  } \
7258  } \
7259  else \
7260  { \
7261  MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \
7262  } \
7263  } while(0)
7264 
7265 #else
7266 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \
7267  do { \
7268  MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \
7269  } while(0)
7270 
7271 #endif /*RCC_VER_X*/
7272 
7281 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
7282 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
7283 
7284 
7293 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
7294 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
7295 
7315 #if defined(RCC_CR_HSEEXT)
7316 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
7317  do { \
7318  if ((__STATE__) == RCC_HSE_ON) \
7319  { \
7320  SET_BIT(RCC->CR, RCC_CR_HSEON); \
7321  } \
7322  else if ((__STATE__) == RCC_HSE_OFF) \
7323  { \
7324  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
7325  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
7326  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
7327  } \
7328  else if ((__STATE__) == RCC_HSE_BYPASS) \
7329  { \
7330  SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
7331  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
7332  SET_BIT(RCC->CR, RCC_CR_HSEON); \
7333  } \
7334  else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \
7335  { \
7336  SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
7337  SET_BIT(RCC->CR, RCC_CR_HSEEXT); \
7338  SET_BIT(RCC->CR, RCC_CR_HSEON); \
7339  } \
7340  else \
7341  { \
7342  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
7343  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
7344  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
7345  } \
7346  } while(0)
7347 #else
7348 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
7349  do { \
7350  if ((__STATE__) == RCC_HSE_ON) \
7351  { \
7352  SET_BIT(RCC->CR, RCC_CR_HSEON); \
7353  } \
7354  else if ((__STATE__) == RCC_HSE_OFF) \
7355  { \
7356  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
7357  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
7358  } \
7359  else if ((__STATE__) == RCC_HSE_BYPASS) \
7360  { \
7361  SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
7362  SET_BIT(RCC->CR, RCC_CR_HSEON); \
7363  } \
7364  else \
7365  { \
7366  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
7367  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
7368  } \
7369  } while(0)
7370 #endif /* RCC_CR_HSEEXT */
7371 
7400 #if defined(RCC_BDCR_LSEEXT)
7401 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
7402  do { \
7403  if((__STATE__) == RCC_LSE_ON) \
7404  { \
7405  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7406  } \
7407  else if((__STATE__) == RCC_LSE_OFF) \
7408  { \
7409  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7410  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
7411  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7412  } \
7413  else if((__STATE__) == RCC_LSE_BYPASS) \
7414  { \
7415  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7416  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
7417  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7418  } \
7419  else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \
7420  { \
7421  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7422  SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
7423  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7424  } \
7425  else \
7426  { \
7427  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7428  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7429  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
7430  } \
7431  } while(0)
7432 #else
7433 
7434 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
7435  do { \
7436  if((__STATE__) == RCC_LSE_ON) \
7437  { \
7438  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7439  } \
7440  else if((__STATE__) == RCC_LSE_OFF) \
7441  { \
7442  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7443  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7444  } \
7445  else if((__STATE__) == RCC_LSE_BYPASS) \
7446  { \
7447  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7448  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7449  } \
7450  else \
7451  { \
7452  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7453  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7454  } \
7455  } while(0)
7456 
7457 #endif /* RCC_BDCR_LSEEXT */
7458 
7465 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
7466 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
7467 
7489 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
7490  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
7491 
7492 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
7493  RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
7494  } while (0)
7495 
7496 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
7497 
7498 
7504 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
7505 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
7506 
7514 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
7515 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
7516 
7534 #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
7535 
7536 #define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
7537 
7538 
7544 #define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
7545 
7546 #define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
7547 
7548 
7590 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
7591  do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \
7592  WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
7593  ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
7594  } while(0)
7595 
7596 
7606 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
7607 
7608 
7625  #define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
7626 
7627 
7637 #define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
7638  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
7639 
7640 
7651 #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
7652  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
7653 
7654 
7655 
7664 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
7665 
7666 
7676 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
7677 
7686 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
7687 
7704 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
7705  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
7706 
7720 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
7721  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
7722 
7742 #if defined(RCC_VER_X)
7743 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
7744  do{ \
7745  if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \
7746  { \
7747  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \
7748  } \
7749  else \
7750  { \
7751  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \
7752  } \
7753  } while(0)
7754 #else
7755 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
7756  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
7757 #endif /*RCC_VER_X*/
7758 
7766 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
7767  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
7768 
7777 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
7778  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
7779 
7798 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
7799 
7814 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
7815 
7831 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
7832 
7849 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
7850 
7853 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
7854 
7855 #if defined(DUAL_CORE)
7856 #define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)
7857 
7858 #define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)
7859 #endif /*DUAL_CORE*/
7860 
7861 #if defined(DUAL_CORE)
7862 
7895 #define RCC_FLAG_MASK ((uint8_t)0x1F)
7896 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
7897 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
7898 
7899 #define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
7900 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
7901 
7902 #define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
7903 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
7904 
7905 #else
7906 
7941 #define RCC_FLAG_MASK ((uint8_t)0x1F)
7942 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
7943 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
7944 #endif /*DUAL_CORE*/
7945 
7950 #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
7951 
7956 /* Include RCC HAL Extension module */
7957 #include "stm32h7xx_hal_rcc_ex.h"
7958 
7959 /* Exported functions --------------------------------------------------------*/
7967 /* Initialization and de-initialization functions ******************************/
7968 HAL_StatusTypeDef HAL_RCC_DeInit(void);
7969 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
7970 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
7971 
7979 /* Peripheral Control functions ************************************************/
7980 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
7981 void HAL_RCC_EnableCSS(void);
7982 void HAL_RCC_DisableCSS(void);
7983 uint32_t HAL_RCC_GetSysClockFreq(void);
7984 uint32_t HAL_RCC_GetHCLKFreq(void);
7985 uint32_t HAL_RCC_GetPCLK1Freq(void);
7986 uint32_t HAL_RCC_GetPCLK2Freq(void);
7987 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
7988 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
7989 /* CSS NMI IRQ handler */
7990 void HAL_RCC_NMI_IRQHandler(void);
7991 /* User Callbacks in non blocking mode (IT mode) */
7992 void HAL_RCC_CCSCallback(void);
7993 
8002 /* Private types -------------------------------------------------------------*/
8003 /* Private variables ---------------------------------------------------------*/
8004 /* Private constants ---------------------------------------------------------*/
8009 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
8010 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms */
8011 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */
8012 #define CSI_TIMEOUT_VALUE (2U) /* 2 ms */
8013 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms */
8014 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms */
8015 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
8016 #define RCC_DBP_TIMEOUT_VALUE (100U)
8017 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
8018 
8023 /* Private macros ------------------------------------------------------------*/
8032 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
8033  (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
8034  (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
8035  (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
8036  (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
8037  (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
8038  (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
8039 
8040 #if defined(RCC_CR_HSEEXT)
8041 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
8042  ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))
8043 #else
8044 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
8045  ((HSE) == RCC_HSE_BYPASS))
8046 #endif /* RCC_CR_HSEEXT */
8047 
8048 #if defined(RCC_BDCR_LSEEXT)
8049 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
8050  ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))
8051 #else
8052 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
8053  ((LSE) == RCC_LSE_BYPASS))
8054 #endif /* RCC_BDCR_LSEEXT */
8055 
8056 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \
8057  ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
8058  ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
8059 
8060 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
8061 
8062 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
8063 
8064 #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
8065 
8066 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
8067  ((PLL) == RCC_PLL_ON))
8068 
8069 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \
8070  ((SOURCE) == RCC_PLLSOURCE_HSI) || \
8071  ((SOURCE) == RCC_PLLSOURCE_NONE) || \
8072  ((SOURCE) == RCC_PLLSOURCE_HSE))
8073 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
8074 #if !defined(RCC_VER_2_0)
8075 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
8076 #else
8077 #define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
8078 #endif /* !RCC_VER_2_0 */
8079 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
8080 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
8081 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
8082 
8083 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
8084  ((VALUE) == RCC_PLL1_DIVQ) || \
8085  ((VALUE) == RCC_PLL1_DIVR))
8086 
8087 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
8088 
8089 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
8090  ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
8091  ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
8092  ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
8093 
8094 #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \
8095  ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \
8096  ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \
8097  ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
8098  ((SYSCLK) == RCC_SYSCLK_DIV512))
8099 
8100 
8101 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \
8102  ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \
8103  ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \
8104  ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
8105  ((HCLK) == RCC_HCLK_DIV512))
8106 
8107 #define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
8108  ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
8109  ((CDPCLK1) == RCC_APB3_DIV16))
8110 
8111 #define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */
8112 
8113 #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
8114  ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
8115  ((PCLK1) == RCC_APB1_DIV16))
8116 
8117 #define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
8118  ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
8119  ((PCLK2) == RCC_APB2_DIV16))
8120 
8121 #define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
8122  ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \
8123  ((SRDPCLK1) == RCC_APB4_DIV16))
8124 
8125 #define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
8126 
8127 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
8128  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
8129  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
8130  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
8131  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
8132  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
8133  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
8134  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
8135  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
8136  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
8137  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
8138  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
8139  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
8140  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
8141  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
8142  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
8143  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
8144  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
8145  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
8146  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
8147  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
8148  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
8149  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
8150  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
8151  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
8152  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
8153  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
8154  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
8155  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
8156  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
8157  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
8158  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
8159 
8160 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
8161 
8162 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
8163  ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \
8164  ((SOURCE) == RCC_MCO1SOURCE_HSI48))
8165 
8166 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
8167  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \
8168  ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
8169 
8170 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
8171  ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
8172  ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \
8173  ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \
8174  ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \
8175  ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \
8176  ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \
8177  ((DIV) == RCC_MCODIV_15))
8178 
8179 #if defined(DUAL_CORE)
8180 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
8181  ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
8182  ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \
8183  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
8184  ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
8185  ((FLAG) == RCC_FLAG_LSIRDY) || \
8186  ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \
8187  ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \
8188  ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \
8189  ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \
8190  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
8191  ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
8192  ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
8193  ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV))
8194 
8195 #else
8196 
8197 #if defined(RCC_CR_D2CKRDY)
8198 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
8199  ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
8200  ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \
8201  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
8202  ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
8203  ((FLAG) == RCC_FLAG_LSIRDY) || \
8204  ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \
8205  ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \
8206  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
8207  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
8208  ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
8209  ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV ))
8210 #else
8211 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
8212  ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
8213  ((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \
8214  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
8215  ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
8216  ((FLAG) == RCC_FLAG_LSIRDY) || \
8217  ((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \
8218  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
8219  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
8220  ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
8221  ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV ))
8222 #endif /* RCC_CR_D2CKRDY */
8223 
8224 #endif /*DUAL_CORE*/
8225 
8226 #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
8227 #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
8228 
8229 #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
8230  ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
8231 
8232 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
8233  ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
8234 
8249 #ifdef __cplusplus
8250 }
8251 #endif
8252 
8253 #endif /* STM32H7xx_HAL_RCC_H */
8254 
8255 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:77
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:47
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:51
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
HAL_RCC_NMI_IRQHandler
void HAL_RCC_NMI_IRQHandler(void)
HAL_RCC_DeInit
HAL_StatusTypeDef HAL_RCC_DeInit(void)
stm32h7xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_RCC_DisableCSS
void HAL_RCC_DisableCSS(void)
HAL_RCC_MCOConfig
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
HAL_RCC_CCSCallback
void HAL_RCC_CCSCallback(void)
HAL_RCC_EnableCSS
void HAL_RCC_EnableCSS(void)

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:55