Collaboration diagram for LSE Configuration:
Macros | |
| #define | __HAL_RCC_LSE_CONFIG(__STATE__) |
| Macro to configure the External Low Speed oscillator (LSE). More... | |
| #define | __HAL_RCC_LSE_CONFIG(__STATE__) |
| Macro to configure the External Low Speed oscillator (LSE). More... | |
| #define | __HAL_RCC_LSE_CONFIG(__STATE__) |
| Macro to configure the External Low Speed oscillator (LSE). More... | |
| #define | __HAL_RCC_LSE_CONFIG(__STATE__) |
| Macro to configure the External Low Speed oscillator (LSE). More... | |
| #define | __HAL_RCC_LSE_CONFIG(__STATE__) |
| Macro to configure the External Low Speed oscillator (LSE). More... | |
| #define | __HAL_RCC_LSE_CONFIG(__STATE__) |
| Macro to configure the External Low Speed oscillator (LSE). More... | |
Detailed Description
Macro Definition Documentation
◆ __HAL_RCC_LSE_CONFIG [1/6]
| #define __HAL_RCC_LSE_CONFIG | ( | __STATE__ | ) |
Value:
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_OFF) \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0)
Macro to configure the External Low Speed oscillator (LSE).
- Note
- Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
-
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
- After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
- Parameters
-
<strong>STATE</strong> specifies the new state of the LSE. This parameter can be one of the following values: - RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
- RCC_LSE_ON: turn ON the LSE oscillator.
- RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Definition at line 781 of file stm32f7xx_hal_rcc.h.
◆ __HAL_RCC_LSE_CONFIG [2/6]
| #define __HAL_RCC_LSE_CONFIG | ( | __STATE__ | ) |
Value:
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0U)
Macro to configure the External Low Speed oscillator (LSE).
- Note
- Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
- As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
- After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
- Parameters
-
<strong>STATE</strong> specifies the new state of the LSE. This parameter can be one of the following values: - RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
- RCC_LSE_ON: turn ON the LSE oscillator.
- RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Definition at line 938 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_LSE_CONFIG [3/6]
| #define __HAL_RCC_LSE_CONFIG | ( | __STATE__ | ) |
Value:
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0U)
Macro to configure the External Low Speed oscillator (LSE).
- Note
- Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
- As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
- After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
- Parameters
-
<strong>STATE</strong> specifies the new state of the LSE. This parameter can be one of the following values: - RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
- RCC_LSE_ON: turn ON the LSE oscillator.
- RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Definition at line 938 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_LSE_CONFIG [4/6]
| #define __HAL_RCC_LSE_CONFIG | ( | __STATE__ | ) |
Value:
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0U)
Macro to configure the External Low Speed oscillator (LSE).
- Note
- Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
- As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
- After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
- Parameters
-
<strong>STATE</strong> specifies the new state of the LSE. This parameter can be one of the following values: - RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
- RCC_LSE_ON: turn ON the LSE oscillator.
- RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Definition at line 938 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.
◆ __HAL_RCC_LSE_CONFIG [5/6]
| #define __HAL_RCC_LSE_CONFIG | ( | __STATE__ | ) |
Value:
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_OFF) \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0)
Macro to configure the External Low Speed oscillator (LSE).
- Note
- Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
- The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). A duty cycle close to 50% is recommended.
- As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
- After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
- If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
- Parameters
-
<strong>STATE</strong> specifies the new state of the LSE. This parameter can be one of the following values: - RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
- RCC_LSE_ON: turn ON the LSE oscillator.
- RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
- RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)
Definition at line 7434 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h.
◆ __HAL_RCC_LSE_CONFIG [6/6]
| #define __HAL_RCC_LSE_CONFIG | ( | __STATE__ | ) |
Value:
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_OFF) \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0)
Macro to configure the External Low Speed oscillator (LSE).
- Note
- Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
- The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). A duty cycle close to 50% is recommended.
- As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
- After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
- If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
- Parameters
-
<strong>STATE</strong> specifies the new state of the LSE. This parameter can be one of the following values: - RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
- RCC_LSE_ON: turn ON the LSE oscillator.
- RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
- RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)
Definition at line 7437 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h.