stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
Go to the documentation of this file.
1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_HAL_RCC_EX_H
22 #define __STM32F4xx_HAL_RCC_EX_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t PLLState;
52  uint32_t PLLSource;
55  uint32_t PLLM;
58  uint32_t PLLN;
62  uint32_t PLLP;
65  uint32_t PLLQ;
67 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
68  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
69  defined(STM32F413xx) || defined(STM32F423xx)
70  uint32_t PLLR;
74 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
75 }RCC_PLLInitTypeDef;
76 
77 #if defined(STM32F446xx)
78 
81 typedef struct
82 {
83  uint32_t PLLI2SM;
86  uint32_t PLLI2SN;
89  uint32_t PLLI2SP;
92  uint32_t PLLI2SQ;
96  uint32_t PLLI2SR;
99 }RCC_PLLI2SInitTypeDef;
100 
104 typedef struct
105 {
106  uint32_t PLLSAIM;
109  uint32_t PLLSAIN;
112  uint32_t PLLSAIP;
115  uint32_t PLLSAIQ;
118 }RCC_PLLSAIInitTypeDef;
119 
123 typedef struct
124 {
125  uint32_t PeriphClockSelection;
128  RCC_PLLI2SInitTypeDef PLLI2S;
131  RCC_PLLSAIInitTypeDef PLLSAI;
134  uint32_t PLLI2SDivQ;
138  uint32_t PLLSAIDivQ;
142  uint32_t Sai1ClockSelection;
145  uint32_t Sai2ClockSelection;
148  uint32_t I2sApb1ClockSelection;
151  uint32_t I2sApb2ClockSelection;
154  uint32_t RTCClockSelection;
157  uint32_t SdioClockSelection;
160  uint32_t CecClockSelection;
163  uint32_t Fmpi2c1ClockSelection;
166  uint32_t SpdifClockSelection;
169  uint32_t Clk48ClockSelection;
172  uint8_t TIMPresSelection;
174 }RCC_PeriphCLKInitTypeDef;
175 #endif /* STM32F446xx */
176 
177 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
178 
181 typedef struct
182 {
183  uint32_t PeriphClockSelection;
186  uint32_t I2SClockSelection;
189  uint32_t RTCClockSelection;
192  uint32_t Lptim1ClockSelection;
195  uint32_t Fmpi2c1ClockSelection;
198  uint8_t TIMPresSelection;
200 }RCC_PeriphCLKInitTypeDef;
201 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
202 
203 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
204 
207 typedef struct
208 {
209  uint32_t PLLI2SM;
212  uint32_t PLLI2SN;
215  uint32_t PLLI2SQ;
219  uint32_t PLLI2SR;
222 }RCC_PLLI2SInitTypeDef;
223 
227 typedef struct
228 {
229  uint32_t PeriphClockSelection;
232  RCC_PLLI2SInitTypeDef PLLI2S;
235 #if defined(STM32F413xx) || defined(STM32F423xx)
236  uint32_t PLLDivR;
240  uint32_t PLLI2SDivR;
243 #endif /* STM32F413xx || STM32F423xx */
244 
245  uint32_t I2sApb1ClockSelection;
248  uint32_t I2sApb2ClockSelection;
251  uint32_t RTCClockSelection;
254  uint32_t SdioClockSelection;
257  uint32_t Fmpi2c1ClockSelection;
260  uint32_t Clk48ClockSelection;
263  uint32_t Dfsdm1ClockSelection;
266  uint32_t Dfsdm1AudioClockSelection;
269 #if defined(STM32F413xx) || defined(STM32F423xx)
270  uint32_t Dfsdm2ClockSelection;
273  uint32_t Dfsdm2AudioClockSelection;
276  uint32_t Lptim1ClockSelection;
279  uint32_t SaiAClockSelection;
282  uint32_t SaiBClockSelection;
284 #endif /* STM32F413xx || STM32F423xx */
285 
286  uint32_t PLLI2SSelection;
289  uint8_t TIMPresSelection;
291 }RCC_PeriphCLKInitTypeDef;
292 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
293 
294 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
295 
299 typedef struct
300 {
301  uint32_t PLLI2SN;
305  uint32_t PLLI2SR;
309  uint32_t PLLI2SQ;
312 }RCC_PLLI2SInitTypeDef;
313 
317 typedef struct
318 {
319  uint32_t PLLSAIN;
322 #if defined(STM32F469xx) || defined(STM32F479xx)
323  uint32_t PLLSAIP;
326 #endif /* STM32F469xx || STM32F479xx */
327 
328  uint32_t PLLSAIQ;
332  uint32_t PLLSAIR;
336 }RCC_PLLSAIInitTypeDef;
337 
341 typedef struct
342 {
343  uint32_t PeriphClockSelection;
346  RCC_PLLI2SInitTypeDef PLLI2S;
349  RCC_PLLSAIInitTypeDef PLLSAI;
352  uint32_t PLLI2SDivQ;
356  uint32_t PLLSAIDivQ;
360  uint32_t PLLSAIDivR;
363  uint32_t RTCClockSelection;
366  uint8_t TIMPresSelection;
368 #if defined(STM32F469xx) || defined(STM32F479xx)
369  uint32_t Clk48ClockSelection;
372  uint32_t SdioClockSelection;
374 #endif /* STM32F469xx || STM32F479xx */
375 }RCC_PeriphCLKInitTypeDef;
376 
377 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
378 
379 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
380  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
381 
384 typedef struct
385 {
386 #if defined(STM32F411xE)
387  uint32_t PLLI2SM;
389 #endif /* STM32F411xE */
390 
391  uint32_t PLLI2SN;
396  uint32_t PLLI2SR;
400 }RCC_PLLI2SInitTypeDef;
401 
405 typedef struct
406 {
407  uint32_t PeriphClockSelection;
410  RCC_PLLI2SInitTypeDef PLLI2S;
413  uint32_t RTCClockSelection;
415 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
416  uint8_t TIMPresSelection;
418 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
419 }RCC_PeriphCLKInitTypeDef;
420 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
421 
425 /* Exported constants --------------------------------------------------------*/
433 /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
434 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
435  defined(STM32F413xx) || defined(STM32F423xx)
436 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U
437 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U
438 #define RCC_PERIPHCLK_TIM 0x00000004U
439 #define RCC_PERIPHCLK_RTC 0x00000008U
440 #define RCC_PERIPHCLK_FMPI2C1 0x00000010U
441 #define RCC_PERIPHCLK_CLK48 0x00000020U
442 #define RCC_PERIPHCLK_SDIO 0x00000040U
443 #define RCC_PERIPHCLK_PLLI2S 0x00000080U
444 #define RCC_PERIPHCLK_DFSDM1 0x00000100U
445 #define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
446 #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
447 #if defined(STM32F413xx) || defined(STM32F423xx)
448 #define RCC_PERIPHCLK_DFSDM2 0x00000400U
449 #define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
450 #define RCC_PERIPHCLK_LPTIM1 0x00001000U
451 #define RCC_PERIPHCLK_SAIA 0x00002000U
452 #define RCC_PERIPHCLK_SAIB 0x00004000U
453 #endif /* STM32F413xx || STM32F423xx */
454 /*----------------------------------------------------------------------------*/
455 
456 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/
457 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
458 #define RCC_PERIPHCLK_I2S 0x00000001U
459 #define RCC_PERIPHCLK_TIM 0x00000002U
460 #define RCC_PERIPHCLK_RTC 0x00000004U
461 #define RCC_PERIPHCLK_FMPI2C1 0x00000008U
462 #define RCC_PERIPHCLK_LPTIM1 0x00000010U
463 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
464 /*----------------------------------------------------------------------------*/
465 
466 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/
467 #if defined(STM32F446xx)
468 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U
469 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U
470 #define RCC_PERIPHCLK_SAI1 0x00000004U
471 #define RCC_PERIPHCLK_SAI2 0x00000008U
472 #define RCC_PERIPHCLK_TIM 0x00000010U
473 #define RCC_PERIPHCLK_RTC 0x00000020U
474 #define RCC_PERIPHCLK_CEC 0x00000040U
475 #define RCC_PERIPHCLK_FMPI2C1 0x00000080U
476 #define RCC_PERIPHCLK_CLK48 0x00000100U
477 #define RCC_PERIPHCLK_SDIO 0x00000200U
478 #define RCC_PERIPHCLK_SPDIFRX 0x00000400U
479 #define RCC_PERIPHCLK_PLLI2S 0x00000800U
480 #endif /* STM32F446xx */
481 /*-----------------------------------------------------------------------------*/
482 
483 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
484 #if defined(STM32F469xx) || defined(STM32F479xx)
485 #define RCC_PERIPHCLK_I2S 0x00000001U
486 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
487 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
488 #define RCC_PERIPHCLK_LTDC 0x00000008U
489 #define RCC_PERIPHCLK_TIM 0x00000010U
490 #define RCC_PERIPHCLK_RTC 0x00000020U
491 #define RCC_PERIPHCLK_PLLI2S 0x00000040U
492 #define RCC_PERIPHCLK_CLK48 0x00000080U
493 #define RCC_PERIPHCLK_SDIO 0x00000100U
494 #endif /* STM32F469xx || STM32F479xx */
495 /*----------------------------------------------------------------------------*/
496 
497 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
498 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
499 #define RCC_PERIPHCLK_I2S 0x00000001U
500 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
501 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
502 #define RCC_PERIPHCLK_LTDC 0x00000008U
503 #define RCC_PERIPHCLK_TIM 0x00000010U
504 #define RCC_PERIPHCLK_RTC 0x00000020U
505 #define RCC_PERIPHCLK_PLLI2S 0x00000040U
506 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
507 /*----------------------------------------------------------------------------*/
508 
509 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
510 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
511  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
512 #define RCC_PERIPHCLK_I2S 0x00000001U
513 #define RCC_PERIPHCLK_RTC 0x00000002U
514 #define RCC_PERIPHCLK_PLLI2S 0x00000004U
515 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
516 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
517 #define RCC_PERIPHCLK_TIM 0x00000008U
518 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
519 /*----------------------------------------------------------------------------*/
523 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
524  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
525  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
526  defined(STM32F479xx)
527 
530 #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
531 #define RCC_I2SCLKSOURCE_EXT 0x00000001U
532 
535 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
536  STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
537 
541 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
542  defined(STM32F469xx) || defined(STM32F479xx)
543 #define RCC_PLLSAIDIVR_2 0x00000000U
544 #define RCC_PLLSAIDIVR_4 0x00010000U
545 #define RCC_PLLSAIDIVR_8 0x00020000U
546 #define RCC_PLLSAIDIVR_16 0x00030000U
547 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
548 
555 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
556  defined(STM32F412Rx) || defined(STM32F412Cx)
557 #define RCC_PLLI2SP_DIV2 0x00000002U
558 #define RCC_PLLI2SP_DIV4 0x00000004U
559 #define RCC_PLLI2SP_DIV6 0x00000006U
560 #define RCC_PLLI2SP_DIV8 0x00000008U
561 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
562 
569 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
570 #define RCC_PLLSAIP_DIV2 0x00000002U
571 #define RCC_PLLSAIP_DIV4 0x00000004U
572 #define RCC_PLLSAIP_DIV6 0x00000006U
573 #define RCC_PLLSAIP_DIV8 0x00000008U
574 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
575 
579 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
580 
583 #define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
584 #define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
585 #define RCC_SAIACLKSOURCE_EXT 0x00200000U
586 
593 #define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
594 #define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
595 #define RCC_SAIBCLKSOURCE_EXT 0x00800000U
596 
599 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
600 
601 #if defined(STM32F469xx) || defined(STM32F479xx)
602 
605 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
606 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
607 
614 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
615 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
616 
623 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
624 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
625 
628 #endif /* STM32F469xx || STM32F479xx */
629 
630 #if defined(STM32F446xx)
631 
634 #define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
635 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
636 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
637 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
638 
645 #define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
646 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
647 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
648 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
649 
656 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
657 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
658 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
659 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
660 
667 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
668 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
669 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
670 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
671 
678 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
679 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
680 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
681 
688 #define RCC_CECCLKSOURCE_HSI 0x00000000U
689 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
690 
697 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
698 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
699 
706 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
707 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
708 
715 #define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
716 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
717 
721 #endif /* STM32F446xx */
722 
723 #if defined(STM32F413xx) || defined(STM32F423xx)
724 
727 #define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
728 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
729 #define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
730 #define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
731 
738 #define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
739 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
740 #define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
741 #define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
742 
749 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
750 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
751 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
752 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
753 
761 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
762 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
763 
770 #define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
771 #define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
772 
776 #endif /* STM32F413xx || STM32F423xx */
777 
778 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
779 
782 #define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
783 #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
784 
791 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
792 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
793 
800 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
801 #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
802 
809 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
810 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
811 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
812 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
813 
820 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
821 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
822 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
823 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
824 
831 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
832 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
833 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
834 
841 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
842 #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
843 
850 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
851 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
852 
855 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
856 
857 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
858 
862 #define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
863 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
864 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
865 
872 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
873 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
874 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
875 
882 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
883 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
884 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
885 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
886 
889 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
890 
891 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
892  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
893  defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
894  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
895  defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
896 
899 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
900 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
901 
904 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
905  STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
906  STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
907 
908 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
909  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
910  defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
911  defined(STM32F423xx)
912 
915 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
916 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
917 
920 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
921  STM32F412Rx || STM32F412Cx */
922 
923 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
924  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
925  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
926  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
927  defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
928 
931 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U
932 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
933 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
934 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
935 
938 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
939  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
940  STM32F412Rx || STM32F413xx | STM32F423xx */
941 
942 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
943 
946 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U
947 #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
948 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
949 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
950 
953 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
954 
959 /* Exported macro ------------------------------------------------------------*/
963 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
964 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
965 
972 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
973  __IO uint32_t tmpreg = 0x00U; \
974  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
975  /* Delay after an RCC peripheral clock enabling */ \
976  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
977  UNUSED(tmpreg); \
978  } while(0U)
979 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
980  __IO uint32_t tmpreg = 0x00U; \
981  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
982  /* Delay after an RCC peripheral clock enabling */ \
983  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
984  UNUSED(tmpreg); \
985  } while(0U)
986 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
987  __IO uint32_t tmpreg = 0x00U; \
988  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
989  /* Delay after an RCC peripheral clock enabling */ \
990  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
991  UNUSED(tmpreg); \
992  } while(0U)
993 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
994  __IO uint32_t tmpreg = 0x00U; \
995  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
996  /* Delay after an RCC peripheral clock enabling */ \
997  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
998  UNUSED(tmpreg); \
999  } while(0U)
1000 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1001  __IO uint32_t tmpreg = 0x00U; \
1002  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
1003  /* Delay after an RCC peripheral clock enabling */ \
1004  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
1005  UNUSED(tmpreg); \
1006  } while(0U)
1007 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
1008  __IO uint32_t tmpreg = 0x00U; \
1009  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
1010  /* Delay after an RCC peripheral clock enabling */ \
1011  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
1012  UNUSED(tmpreg); \
1013  } while(0U)
1014 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1015  __IO uint32_t tmpreg = 0x00U; \
1016  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
1017  /* Delay after an RCC peripheral clock enabling */ \
1018  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
1019  UNUSED(tmpreg); \
1020  } while(0U)
1021 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1022  __IO uint32_t tmpreg = 0x00U; \
1023  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
1024  /* Delay after an RCC peripheral clock enabling */ \
1025  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
1026  UNUSED(tmpreg); \
1027  } while(0U)
1028 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
1029  __IO uint32_t tmpreg = 0x00U; \
1030  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
1031  /* Delay after an RCC peripheral clock enabling */ \
1032  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
1033  UNUSED(tmpreg); \
1034  } while(0U)
1035 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
1036  __IO uint32_t tmpreg = 0x00U; \
1037  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
1038  /* Delay after an RCC peripheral clock enabling */ \
1039  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
1040  UNUSED(tmpreg); \
1041  } while(0U)
1042 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
1043  __IO uint32_t tmpreg = 0x00U; \
1044  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
1045  /* Delay after an RCC peripheral clock enabling */ \
1046  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
1047  UNUSED(tmpreg); \
1048  } while(0U)
1049 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
1050  __IO uint32_t tmpreg = 0x00U; \
1051  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
1052  /* Delay after an RCC peripheral clock enabling */ \
1053  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
1054  UNUSED(tmpreg); \
1055  } while(0U)
1056 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
1057  __IO uint32_t tmpreg = 0x00U; \
1058  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
1059  /* Delay after an RCC peripheral clock enabling */ \
1060  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
1061  UNUSED(tmpreg); \
1062  } while(0U)
1063 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
1064  __IO uint32_t tmpreg = 0x00U; \
1065  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
1066  /* Delay after an RCC peripheral clock enabling */ \
1067  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
1068  UNUSED(tmpreg); \
1069  } while(0U)
1070 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
1071  __IO uint32_t tmpreg = 0x00U; \
1072  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
1073  /* Delay after an RCC peripheral clock enabling */ \
1074  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
1075  UNUSED(tmpreg); \
1076  } while(0U)
1077 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
1078  __IO uint32_t tmpreg = 0x00U; \
1079  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
1080  /* Delay after an RCC peripheral clock enabling */ \
1081  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
1082  UNUSED(tmpreg); \
1083  } while(0U)
1084 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
1085  __IO uint32_t tmpreg = 0x00U; \
1086  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
1087  /* Delay after an RCC peripheral clock enabling */ \
1088  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
1089  UNUSED(tmpreg); \
1090  } while(0U)
1091 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
1092 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
1093 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
1094 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
1095 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
1096 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
1097 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
1098 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
1099 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
1100 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
1101 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
1102 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
1103 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
1104 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
1105 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
1106 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
1107 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
1108 
1112 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
1113  __HAL_RCC_ETHMAC_CLK_ENABLE(); \
1114  __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
1115  __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
1116  } while(0U)
1117 
1120 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
1121  __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
1122  __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
1123  __HAL_RCC_ETHMAC_CLK_DISABLE(); \
1124  } while(0U)
1125 
1136 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
1137 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
1138 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
1139 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
1140 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
1141 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
1142 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
1143 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
1144 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
1145 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
1146 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
1147 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
1148 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
1149 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
1150 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
1151 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
1152 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
1153 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
1154  __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
1155  __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
1156 
1157 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
1158 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
1159 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
1160 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
1161 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
1162 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
1163 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
1164 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
1165 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
1166 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
1167 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
1168 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
1169 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
1170 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
1171 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
1172 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
1173 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
1174 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
1175  __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
1176  __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
1177 
1188  #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
1189  __IO uint32_t tmpreg = 0x00U; \
1190  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1191  /* Delay after an RCC peripheral clock enabling */ \
1192  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1193  UNUSED(tmpreg); \
1194  } while(0U)
1195 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
1196 
1197 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1198 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
1199  __IO uint32_t tmpreg = 0x00U; \
1200  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1201  /* Delay after an RCC peripheral clock enabling */ \
1202  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1203  UNUSED(tmpreg); \
1204  } while(0U)
1205 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
1206  __IO uint32_t tmpreg = 0x00U; \
1207  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1208  /* Delay after an RCC peripheral clock enabling */ \
1209  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1210  UNUSED(tmpreg); \
1211  } while(0U)
1212 
1213 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
1214 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
1215 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1216 
1217 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
1218  __HAL_RCC_SYSCFG_CLK_ENABLE();\
1219  }while(0U)
1220 
1221 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
1222 
1223 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
1224  __IO uint32_t tmpreg = 0x00U; \
1225  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1226  /* Delay after an RCC peripheral clock enabling */ \
1227  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1228  UNUSED(tmpreg); \
1229  } while(0U)
1230 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
1231 
1242 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
1243 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
1244 
1245 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1246 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
1247 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
1248 
1249 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
1250 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
1251 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1252 
1253 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
1254 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
1255 
1256 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
1257 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
1258 
1269 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
1270  __IO uint32_t tmpreg = 0x00U; \
1271  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1272  /* Delay after an RCC peripheral clock enabling */ \
1273  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1274  UNUSED(tmpreg); \
1275  } while(0U)
1276 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
1277 #if defined(STM32F469xx) || defined(STM32F479xx)
1278 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
1279  __IO uint32_t tmpreg = 0x00U; \
1280  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1281  /* Delay after an RCC peripheral clock enabling */ \
1282  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1283  UNUSED(tmpreg); \
1284  } while(0U)
1285 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
1286 #endif /* STM32F469xx || STM32F479xx */
1287 
1299 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1300 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
1301 #if defined(STM32F469xx) || defined(STM32F479xx)
1302 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1303 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
1304 #endif /* STM32F469xx || STM32F479xx */
1305 
1316 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
1317  __IO uint32_t tmpreg = 0x00U; \
1318  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
1319  /* Delay after an RCC peripheral clock enabling */ \
1320  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
1321  UNUSED(tmpreg); \
1322  } while(0U)
1323 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
1324  __IO uint32_t tmpreg = 0x00U; \
1325  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
1326  /* Delay after an RCC peripheral clock enabling */ \
1327  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
1328  UNUSED(tmpreg); \
1329  } while(0U)
1330 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
1331  __IO uint32_t tmpreg = 0x00U; \
1332  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1333  /* Delay after an RCC peripheral clock enabling */ \
1334  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1335  UNUSED(tmpreg); \
1336  } while(0U)
1337 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
1338  __IO uint32_t tmpreg = 0x00U; \
1339  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1340  /* Delay after an RCC peripheral clock enabling */ \
1341  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1342  UNUSED(tmpreg); \
1343  } while(0U)
1344 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1345  __IO uint32_t tmpreg = 0x00U; \
1346  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1347  /* Delay after an RCC peripheral clock enabling */ \
1348  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1349  UNUSED(tmpreg); \
1350  } while(0U)
1351 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1352  __IO uint32_t tmpreg = 0x00U; \
1353  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1354  /* Delay after an RCC peripheral clock enabling */ \
1355  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1356  UNUSED(tmpreg); \
1357  } while(0U)
1358 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
1359  __IO uint32_t tmpreg = 0x00U; \
1360  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1361  /* Delay after an RCC peripheral clock enabling */ \
1362  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1363  UNUSED(tmpreg); \
1364  } while(0U)
1365 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
1366  __IO uint32_t tmpreg = 0x00U; \
1367  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1368  /* Delay after an RCC peripheral clock enabling */ \
1369  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1370  UNUSED(tmpreg); \
1371  } while(0U)
1372 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1373  __IO uint32_t tmpreg = 0x00U; \
1374  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1375  /* Delay after an RCC peripheral clock enabling */ \
1376  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1377  UNUSED(tmpreg); \
1378  } while(0U)
1379 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
1380  __IO uint32_t tmpreg = 0x00U; \
1381  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1382  /* Delay after an RCC peripheral clock enabling */ \
1383  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1384  UNUSED(tmpreg); \
1385  } while(0U)
1386 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1387  __IO uint32_t tmpreg = 0x00U; \
1388  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1389  /* Delay after an RCC peripheral clock enabling */ \
1390  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1391  UNUSED(tmpreg); \
1392  } while(0U)
1393 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
1394  __IO uint32_t tmpreg = 0x00U; \
1395  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1396  /* Delay after an RCC peripheral clock enabling */ \
1397  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1398  UNUSED(tmpreg); \
1399  } while(0U)
1400 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
1401  __IO uint32_t tmpreg = 0x00U; \
1402  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1403  /* Delay after an RCC peripheral clock enabling */ \
1404  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1405  UNUSED(tmpreg); \
1406  } while(0U)
1407 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
1408  __IO uint32_t tmpreg = 0x00U; \
1409  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1410  /* Delay after an RCC peripheral clock enabling */ \
1411  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1412  UNUSED(tmpreg); \
1413  } while(0U)
1414 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
1415  __IO uint32_t tmpreg = 0x00U; \
1416  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
1417  /* Delay after an RCC peripheral clock enabling */ \
1418  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
1419  UNUSED(tmpreg); \
1420  } while(0U)
1421 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
1422  __IO uint32_t tmpreg = 0x00U; \
1423  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
1424  /* Delay after an RCC peripheral clock enabling */ \
1425  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
1426  UNUSED(tmpreg); \
1427  } while(0U)
1428 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
1429  __IO uint32_t tmpreg = 0x00U; \
1430  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
1431  /* Delay after an RCC peripheral clock enabling */ \
1432  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
1433  UNUSED(tmpreg); \
1434  } while(0U)
1435 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
1436  __IO uint32_t tmpreg = 0x00U; \
1437  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1438  /* Delay after an RCC peripheral clock enabling */ \
1439  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1440  UNUSED(tmpreg); \
1441  } while(0U)
1442 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1443  __IO uint32_t tmpreg = 0x00U; \
1444  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1445  /* Delay after an RCC peripheral clock enabling */ \
1446  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1447  UNUSED(tmpreg); \
1448  } while(0U)
1449 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1450 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
1451 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
1452 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1453 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
1454 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
1455 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
1456 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1457 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1458 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1459 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
1460 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
1461 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
1462 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
1463 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1464 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
1465 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
1466 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
1467 
1478 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1479 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
1480 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
1481 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1482 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
1483 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1484 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1485 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1486 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1487 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1488 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
1489 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1490 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1491 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
1492 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1493 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1494 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
1495 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
1496 
1497 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
1498 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
1499 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
1500 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1501 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
1502 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1503 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1504 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1505 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1506 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1507 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
1508 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1509 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1510 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
1511 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
1512 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1513 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
1514 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
1515 
1526 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1527  __IO uint32_t tmpreg = 0x00U; \
1528  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1529  /* Delay after an RCC peripheral clock enabling */ \
1530  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1531  UNUSED(tmpreg); \
1532  } while(0U)
1533 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
1534  __IO uint32_t tmpreg = 0x00U; \
1535  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1536  /* Delay after an RCC peripheral clock enabling */ \
1537  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1538  UNUSED(tmpreg); \
1539  } while(0U)
1540 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1541  __IO uint32_t tmpreg = 0x00U; \
1542  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1543  /* Delay after an RCC peripheral clock enabling */ \
1544  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1545  UNUSED(tmpreg); \
1546  } while(0U)
1547 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
1548  __IO uint32_t tmpreg = 0x00U; \
1549  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1550  /* Delay after an RCC peripheral clock enabling */ \
1551  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1552  UNUSED(tmpreg); \
1553  } while(0U)
1554 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
1555  __IO uint32_t tmpreg = 0x00U; \
1556  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1557  /* Delay after an RCC peripheral clock enabling */ \
1558  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1559  UNUSED(tmpreg); \
1560  } while(0U)
1561 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
1562  __IO uint32_t tmpreg = 0x00U; \
1563  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1564  /* Delay after an RCC peripheral clock enabling */ \
1565  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1566  UNUSED(tmpreg); \
1567  } while(0U)
1568 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
1569  __IO uint32_t tmpreg = 0x00U; \
1570  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
1571  /* Delay after an RCC peripheral clock enabling */ \
1572  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
1573  UNUSED(tmpreg); \
1574  } while(0U)
1575 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
1576  __IO uint32_t tmpreg = 0x00U; \
1577  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1578  /* Delay after an RCC peripheral clock enabling */ \
1579  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1580  UNUSED(tmpreg); \
1581  } while(0U)
1582 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
1583  __IO uint32_t tmpreg = 0x00U; \
1584  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1585  /* Delay after an RCC peripheral clock enabling */ \
1586  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1587  UNUSED(tmpreg); \
1588  } while(0U)
1589 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
1590 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
1591 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1592 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1593 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1594 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1595 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
1596 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
1597 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
1598 
1599 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1600 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
1601  __IO uint32_t tmpreg = 0x00U; \
1602  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1603  /* Delay after an RCC peripheral clock enabling */ \
1604  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1605  UNUSED(tmpreg); \
1606  } while(0U)
1607 
1608 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
1609 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1610 
1611 #if defined(STM32F469xx) || defined(STM32F479xx)
1612 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
1613  __IO uint32_t tmpreg = 0x00U; \
1614  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1615  /* Delay after an RCC peripheral clock enabling */ \
1616  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1617  UNUSED(tmpreg); \
1618  } while(0U)
1619 
1620 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
1621 #endif /* STM32F469xx || STM32F479xx */
1622 
1633 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
1634 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
1635 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
1636 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
1637 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
1638 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
1639 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
1640 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
1641 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
1642 
1643 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
1644 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
1645 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
1646 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
1647 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
1648 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
1649 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
1650 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
1651 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
1652 
1653 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1654 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
1655 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
1656 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1657 
1658 #if defined(STM32F469xx) || defined(STM32F479xx)
1659 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
1660 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
1661 #endif /* STM32F469xx || STM32F479xx */
1662 
1670 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
1671 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
1672 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
1673 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
1674 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
1675 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
1676 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
1677 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
1678 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
1679 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
1680 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
1681 
1682 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
1683 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
1684 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
1685 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
1686 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
1687 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
1688 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
1689 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
1690 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
1691 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
1692 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
1693 
1701 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
1702 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
1703 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
1704 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
1705 
1706 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
1707 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
1708 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
1709 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
1710 
1711 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1712 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
1713 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
1714 
1715 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
1716 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
1717 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1718 
1726 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
1727 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
1728 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
1729 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
1730 
1731 #if defined(STM32F469xx) || defined(STM32F479xx)
1732 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
1733 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
1734 #endif /* STM32F469xx || STM32F479xx */
1735 
1743 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1744 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1745 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1746 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1747 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1748 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1749 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1750 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1751 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1752 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1753 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1754 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
1755 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
1756 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1757 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
1758 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1759 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1760 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
1761 
1762 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1763 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
1764 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1765 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1766 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
1767 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1768 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1769 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1770 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1771 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1772 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1773 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1774 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1775 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1776 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1777 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1778 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
1779 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
1780 
1788 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1789 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
1790 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
1791 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
1792 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
1793 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
1794 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1795 
1796 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
1797 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
1798 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1799 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1800 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
1801 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
1802 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
1803 
1804 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1805 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
1806 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
1807 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
1808 
1809 #if defined(STM32F469xx) || defined(STM32F479xx)
1810 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
1811 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
1812 #endif /* STM32F469xx || STM32F479xx */
1813 
1825 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
1826 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
1827 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
1828 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
1829 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
1830 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
1831 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
1832 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
1833 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
1834 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
1835 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
1836 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
1837 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
1838 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
1839 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
1840 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
1841 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
1842 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
1843 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
1844 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
1845 
1846 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
1847 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
1848 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
1849 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
1850 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
1851 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
1852 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
1853 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
1854 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
1855 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
1856 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
1857 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
1858 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
1859 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
1860 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
1861 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
1862 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
1863 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
1864 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
1865 
1877 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
1878 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
1879 
1880 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
1881 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
1882 
1883 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
1884 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
1885 
1886 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1887 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
1888 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
1889 
1890 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
1891 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
1892 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1893 
1905 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
1906 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
1907 
1908 #if defined(STM32F469xx) || defined(STM32F479xx)
1909 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
1910 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
1911 #endif /* STM32F469xx || STM32F479xx */
1912 
1924 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
1925 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
1926 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
1927 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
1928 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
1929 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
1930 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
1931 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
1932 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
1933 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
1934 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
1935 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
1936 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
1937 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
1938 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
1939 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
1940 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
1941 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
1942 
1943 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
1944 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
1945 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
1946 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
1947 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
1948 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
1949 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
1950 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
1951 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
1952 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
1953 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
1954 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
1955 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
1956 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
1957 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
1958 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
1959 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
1960 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
1961 
1973 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
1974 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
1975 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
1976 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
1977 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
1978 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
1979 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
1980 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
1981 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
1982 
1983 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
1984 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
1985 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
1986 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
1987 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
1988 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
1989 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
1990 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
1991 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
1992 
1993 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1994 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
1995 
1996 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
1997 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1998 
1999 #if defined(STM32F469xx) || defined(STM32F479xx)
2000 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
2001 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
2002 #endif /* STM32F469xx || STM32F479xx */
2003 
2006 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
2007 /*----------------------------------------------------------------------------*/
2008 
2009 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
2010 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
2011 
2018 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
2019  __IO uint32_t tmpreg = 0x00U; \
2020  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
2021  /* Delay after an RCC peripheral clock enabling */ \
2022  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
2023  UNUSED(tmpreg); \
2024  } while(0U)
2025 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
2026  __IO uint32_t tmpreg = 0x00U; \
2027  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2028  /* Delay after an RCC peripheral clock enabling */ \
2029  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2030  UNUSED(tmpreg); \
2031  } while(0U)
2032 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
2033  __IO uint32_t tmpreg = 0x00U; \
2034  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2035  /* Delay after an RCC peripheral clock enabling */ \
2036  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2037  UNUSED(tmpreg); \
2038  } while(0U)
2039 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
2040  __IO uint32_t tmpreg = 0x00U; \
2041  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2042  /* Delay after an RCC peripheral clock enabling */ \
2043  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2044  UNUSED(tmpreg); \
2045  } while(0U)
2046 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
2047  __IO uint32_t tmpreg = 0x00U; \
2048  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2049  /* Delay after an RCC peripheral clock enabling */ \
2050  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2051  UNUSED(tmpreg); \
2052  } while(0U)
2053 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
2054  __IO uint32_t tmpreg = 0x00U; \
2055  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
2056  /* Delay after an RCC peripheral clock enabling */ \
2057  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
2058  UNUSED(tmpreg); \
2059  } while(0U)
2060 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
2061  __IO uint32_t tmpreg = 0x00U; \
2062  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
2063  /* Delay after an RCC peripheral clock enabling */ \
2064  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
2065  UNUSED(tmpreg); \
2066  } while(0U)
2067 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
2068  __IO uint32_t tmpreg = 0x00U; \
2069  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
2070  /* Delay after an RCC peripheral clock enabling */ \
2071  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
2072  UNUSED(tmpreg); \
2073  } while(0U)
2074 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
2075  __IO uint32_t tmpreg = 0x00U; \
2076  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
2077  /* Delay after an RCC peripheral clock enabling */ \
2078  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
2079  UNUSED(tmpreg); \
2080  } while(0U)
2081 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
2082  __IO uint32_t tmpreg = 0x00U; \
2083  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
2084  /* Delay after an RCC peripheral clock enabling */ \
2085  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
2086  UNUSED(tmpreg); \
2087  } while(0U)
2088 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
2089 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
2090 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
2091 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
2092 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
2093 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
2094 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
2095 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
2096 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
2097 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
2098 #if defined(STM32F407xx)|| defined(STM32F417xx)
2099 
2102 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
2103  __IO uint32_t tmpreg = 0x00U; \
2104  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
2105  /* Delay after an RCC peripheral clock enabling */ \
2106  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
2107  UNUSED(tmpreg); \
2108  } while(0U)
2109 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
2110  __IO uint32_t tmpreg = 0x00U; \
2111  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
2112  /* Delay after an RCC peripheral clock enabling */ \
2113  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
2114  UNUSED(tmpreg); \
2115  } while(0U)
2116 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
2117  __IO uint32_t tmpreg = 0x00U; \
2118  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
2119  /* Delay after an RCC peripheral clock enabling */ \
2120  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
2121  UNUSED(tmpreg); \
2122  } while(0U)
2123 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
2124  __IO uint32_t tmpreg = 0x00U; \
2125  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
2126  /* Delay after an RCC peripheral clock enabling */ \
2127  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
2128  UNUSED(tmpreg); \
2129  } while(0U)
2130 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
2131  __HAL_RCC_ETHMAC_CLK_ENABLE(); \
2132  __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
2133  __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
2134  } while(0U)
2135 
2139 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
2140 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
2141 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
2142 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
2143 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
2144  __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
2145  __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
2146  __HAL_RCC_ETHMAC_CLK_DISABLE(); \
2147  } while(0U)
2148 #endif /* STM32F407xx || STM32F417xx */
2149 
2160 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
2161 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
2162 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
2163 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
2164 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
2165 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
2166 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
2167 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
2168 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
2169 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
2170 
2171 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
2172 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
2173 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
2174 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
2175 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
2176 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
2177 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
2178 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
2179 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
2180 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
2181 #if defined(STM32F407xx)|| defined(STM32F417xx)
2182 
2185 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
2186 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
2187 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
2188 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
2189 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
2190  __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
2191  __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
2192 
2195 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
2196 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
2197 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
2198 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
2199 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
2200  __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
2201  __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
2202 #endif /* STM32F407xx || STM32F417xx */
2203 
2214 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
2215  __HAL_RCC_SYSCFG_CLK_ENABLE();\
2216  }while(0U)
2217 
2218 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
2219 
2220 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
2221  __IO uint32_t tmpreg = 0x00U; \
2222  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2223  /* Delay after an RCC peripheral clock enabling */ \
2224  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2225  UNUSED(tmpreg); \
2226  } while(0U)
2227 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
2228 
2229 #if defined(STM32F407xx)|| defined(STM32F417xx)
2230 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
2231  __IO uint32_t tmpreg = 0x00U; \
2232  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2233  /* Delay after an RCC peripheral clock enabling */ \
2234  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2235  UNUSED(tmpreg); \
2236  } while(0U)
2237 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
2238 #endif /* STM32F407xx || STM32F417xx */
2239 
2240 #if defined(STM32F415xx) || defined(STM32F417xx)
2241 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
2242  __IO uint32_t tmpreg = 0x00U; \
2243  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2244  /* Delay after an RCC peripheral clock enabling */ \
2245  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2246  UNUSED(tmpreg); \
2247  } while(0U)
2248 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
2249  __IO uint32_t tmpreg = 0x00U; \
2250  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2251  /* Delay after an RCC peripheral clock enabling */ \
2252  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2253  UNUSED(tmpreg); \
2254  } while(0U)
2255 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
2256 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
2257 #endif /* STM32F415xx || STM32F417xx */
2258 
2270 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
2271 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
2272 
2273 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
2274 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
2275 
2276 #if defined(STM32F407xx)|| defined(STM32F417xx)
2277 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
2278 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
2279 #endif /* STM32F407xx || STM32F417xx */
2280 
2281 #if defined(STM32F415xx) || defined(STM32F417xx)
2282 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
2283 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
2284 
2285 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
2286 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
2287 #endif /* STM32F415xx || STM32F417xx */
2288 
2299 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
2300  __IO uint32_t tmpreg = 0x00U; \
2301  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
2302  /* Delay after an RCC peripheral clock enabling */ \
2303  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
2304  UNUSED(tmpreg); \
2305  } while(0U)
2306 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
2307 
2318 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
2319 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
2320 
2331 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
2332  __IO uint32_t tmpreg = 0x00U; \
2333  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
2334  /* Delay after an RCC peripheral clock enabling */ \
2335  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
2336  UNUSED(tmpreg); \
2337  } while(0U)
2338 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
2339  __IO uint32_t tmpreg = 0x00U; \
2340  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
2341  /* Delay after an RCC peripheral clock enabling */ \
2342  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
2343  UNUSED(tmpreg); \
2344  } while(0U)
2345 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
2346  __IO uint32_t tmpreg = 0x00U; \
2347  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
2348  /* Delay after an RCC peripheral clock enabling */ \
2349  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
2350  UNUSED(tmpreg); \
2351  } while(0U)
2352 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
2353  __IO uint32_t tmpreg = 0x00U; \
2354  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
2355  /* Delay after an RCC peripheral clock enabling */ \
2356  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
2357  UNUSED(tmpreg); \
2358  } while(0U)
2359 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
2360  __IO uint32_t tmpreg = 0x00U; \
2361  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
2362  /* Delay after an RCC peripheral clock enabling */ \
2363  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
2364  UNUSED(tmpreg); \
2365  } while(0U)
2366 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
2367  __IO uint32_t tmpreg = 0x00U; \
2368  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
2369  /* Delay after an RCC peripheral clock enabling */ \
2370  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
2371  UNUSED(tmpreg); \
2372  } while(0U)
2373 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
2374  __IO uint32_t tmpreg = 0x00U; \
2375  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
2376  /* Delay after an RCC peripheral clock enabling */ \
2377  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
2378  UNUSED(tmpreg); \
2379  } while(0U)
2380 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
2381  __IO uint32_t tmpreg = 0x00U; \
2382  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
2383  /* Delay after an RCC peripheral clock enabling */ \
2384  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
2385  UNUSED(tmpreg); \
2386  } while(0U)
2387 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
2388  __IO uint32_t tmpreg = 0x00U; \
2389  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
2390  /* Delay after an RCC peripheral clock enabling */ \
2391  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
2392  UNUSED(tmpreg); \
2393  } while(0U)
2394 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
2395  __IO uint32_t tmpreg = 0x00U; \
2396  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
2397  /* Delay after an RCC peripheral clock enabling */ \
2398  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
2399  UNUSED(tmpreg); \
2400  } while(0U)
2401 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
2402  __IO uint32_t tmpreg = 0x00U; \
2403  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
2404  /* Delay after an RCC peripheral clock enabling */ \
2405  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
2406  UNUSED(tmpreg); \
2407  } while(0U)
2408 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
2409  __IO uint32_t tmpreg = 0x00U; \
2410  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2411  /* Delay after an RCC peripheral clock enabling */ \
2412  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2413  UNUSED(tmpreg); \
2414  } while(0U)
2415 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
2416  __IO uint32_t tmpreg = 0x00U; \
2417  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2418  /* Delay after an RCC peripheral clock enabling */ \
2419  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2420  UNUSED(tmpreg); \
2421  } while(0U)
2422 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
2423  __IO uint32_t tmpreg = 0x00U; \
2424  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2425  /* Delay after an RCC peripheral clock enabling */ \
2426  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2427  UNUSED(tmpreg); \
2428  } while(0U)
2429 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
2430  __IO uint32_t tmpreg = 0x00U; \
2431  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2432  /* Delay after an RCC peripheral clock enabling */ \
2433  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2434  UNUSED(tmpreg); \
2435  } while(0U)
2436 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
2437  __IO uint32_t tmpreg = 0x00U; \
2438  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2439  /* Delay after an RCC peripheral clock enabling */ \
2440  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2441  UNUSED(tmpreg); \
2442  } while(0U)
2443 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
2444 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2445 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
2446 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2447 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2448 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
2449 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
2450 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
2451 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
2452 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
2453 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
2454 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
2455 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
2456 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
2457 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
2458 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
2459 
2470 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
2471 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
2472 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
2473 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
2474 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2475 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
2476 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
2477 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
2478 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
2479 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
2480 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
2481 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
2482 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
2483 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
2484 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
2485 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
2486 
2487 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
2488 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
2489 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
2490 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
2491 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
2492 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
2493 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
2494 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
2495 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
2496 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
2497 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
2498 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
2499 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
2500 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
2501 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
2502 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
2503 
2514 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
2515  __IO uint32_t tmpreg = 0x00U; \
2516  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2517  /* Delay after an RCC peripheral clock enabling */ \
2518  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2519  UNUSED(tmpreg); \
2520  } while(0U)
2521 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
2522  __IO uint32_t tmpreg = 0x00U; \
2523  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
2524  /* Delay after an RCC peripheral clock enabling */ \
2525  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
2526  UNUSED(tmpreg); \
2527  } while(0U)
2528 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
2529  __IO uint32_t tmpreg = 0x00U; \
2530  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
2531  /* Delay after an RCC peripheral clock enabling */ \
2532  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
2533  UNUSED(tmpreg); \
2534  } while(0U)
2535 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
2536  __IO uint32_t tmpreg = 0x00U; \
2537  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
2538  /* Delay after an RCC peripheral clock enabling */ \
2539  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
2540  UNUSED(tmpreg); \
2541  } while(0U)
2542 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
2543  __IO uint32_t tmpreg = 0x00U; \
2544  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2545  /* Delay after an RCC peripheral clock enabling */ \
2546  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2547  UNUSED(tmpreg); \
2548  } while(0U)
2549 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
2550  __IO uint32_t tmpreg = 0x00U; \
2551  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
2552  /* Delay after an RCC peripheral clock enabling */ \
2553  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
2554  UNUSED(tmpreg); \
2555  } while(0U)
2556 
2557 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
2558 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
2559 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
2560 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
2561 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
2562 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
2563 
2574 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
2575 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
2576 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
2577 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
2578 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
2579 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
2580 
2581 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
2582 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
2583 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
2584 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
2585 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
2586 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
2587 
2595 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
2596 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
2597 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
2598 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
2599 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
2600 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
2601 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
2602 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
2603 
2604 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
2605 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
2606 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
2607 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
2608 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
2609 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
2610 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
2611 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
2612 
2620 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
2621 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
2622 
2623 #if defined(STM32F407xx)|| defined(STM32F417xx)
2624 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
2625 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
2626 #endif /* STM32F407xx || STM32F417xx */
2627 
2628 #if defined(STM32F415xx) || defined(STM32F417xx)
2629 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
2630 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
2631 
2632 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
2633 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
2634 #endif /* STM32F415xx || STM32F417xx */
2635 
2636 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
2637 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
2638 
2639 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
2640 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
2641 
2649 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
2650 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
2651 
2652 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
2653 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
2654 
2662 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
2663 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
2664 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
2665 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
2666 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
2667 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
2668 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
2669 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
2670 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
2671 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
2672 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
2673 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
2674 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2675 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
2676 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2677 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
2678 
2679 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
2680 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2681 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
2682 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2683 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
2684 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
2685 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
2686 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
2687 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
2688 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
2689 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
2690 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
2691 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
2692 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
2693 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
2694 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
2695 
2703 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
2704 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
2705 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
2706 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
2707 
2708 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
2709 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
2710 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
2711 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
2712 
2724 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
2725 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
2726 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
2727 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
2728 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
2729 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
2730 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
2731 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
2732 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
2733 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
2734 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
2735 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
2736 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
2737 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
2738 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
2739 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
2740 
2741 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
2742 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
2743 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
2744 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
2745 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
2746 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
2747 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
2748 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
2749 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
2750 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
2751 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
2752 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
2753 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
2754 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
2755 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
2756 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
2757 
2769 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
2770 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
2771 
2772 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
2773 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
2774 
2775 #if defined(STM32F407xx)|| defined(STM32F417xx)
2776 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
2777 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
2778 #endif /* STM32F407xx || STM32F417xx */
2779 
2780 #if defined(STM32F415xx) || defined(STM32F417xx)
2781 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
2782 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
2783 
2784 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
2785 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
2786 #endif /* STM32F415xx || STM32F417xx */
2787 
2799 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
2800 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
2801 
2813 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
2814 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
2815 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
2816 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
2817 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
2818 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
2819 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
2820 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
2821 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
2822 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
2823 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
2824 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
2825 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
2826 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
2827 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
2828 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
2829 
2830 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
2831 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
2832 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
2833 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
2834 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
2835 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
2836 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
2837 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
2838 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
2839 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
2840 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
2841 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
2842 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
2843 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
2844 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
2845 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
2846 
2858 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
2859 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
2860 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
2861 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
2862 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
2863 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
2864 
2865 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
2866 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
2867 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
2868 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
2869 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
2870 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
2871 
2874 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
2875 /*----------------------------------------------------------------------------*/
2876 
2877 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/
2878 #if defined(STM32F401xC) || defined(STM32F401xE)
2879 
2886 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
2887  __IO uint32_t tmpreg = 0x00U; \
2888  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2889  /* Delay after an RCC peripheral clock enabling */ \
2890  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2891  UNUSED(tmpreg); \
2892  } while(0U)
2893 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
2894  __IO uint32_t tmpreg = 0x00U; \
2895  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2896  /* Delay after an RCC peripheral clock enabling */ \
2897  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2898  UNUSED(tmpreg); \
2899  } while(0U)
2900 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
2901  __IO uint32_t tmpreg = 0x00U; \
2902  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2903  /* Delay after an RCC peripheral clock enabling */ \
2904  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2905  UNUSED(tmpreg); \
2906  } while(0U)
2907 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
2908  __IO uint32_t tmpreg = 0x00U; \
2909  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2910  /* Delay after an RCC peripheral clock enabling */ \
2911  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2912  UNUSED(tmpreg); \
2913  } while(0U)
2914 
2915 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
2916 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
2917 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
2918 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
2919 
2930 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
2931 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
2932 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
2933 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
2934 
2935 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
2936 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
2937 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
2938 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
2939 
2950 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
2951  __HAL_RCC_SYSCFG_CLK_ENABLE();\
2952  }while(0U)
2953 
2954 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
2955 
2966 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
2967 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
2968 
2979 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
2980  __IO uint32_t tmpreg = 0x00U; \
2981  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2982  /* Delay after an RCC peripheral clock enabling */ \
2983  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2984  UNUSED(tmpreg); \
2985  } while(0U)
2986 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
2987  __IO uint32_t tmpreg = 0x00U; \
2988  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2989  /* Delay after an RCC peripheral clock enabling */ \
2990  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2991  UNUSED(tmpreg); \
2992  } while(0U)
2993 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
2994  __IO uint32_t tmpreg = 0x00U; \
2995  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2996  /* Delay after an RCC peripheral clock enabling */ \
2997  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2998  UNUSED(tmpreg); \
2999  } while(0U)
3000 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
3001  __IO uint32_t tmpreg = 0x00U; \
3002  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3003  /* Delay after an RCC peripheral clock enabling */ \
3004  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3005  UNUSED(tmpreg); \
3006  } while(0U)
3007 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
3008  __IO uint32_t tmpreg = 0x00U; \
3009  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3010  /* Delay after an RCC peripheral clock enabling */ \
3011  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3012  UNUSED(tmpreg); \
3013  } while(0U)
3014 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
3015 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
3016 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
3017 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
3018 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
3019 
3030 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
3031 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
3032 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
3033 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
3034 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
3035 
3036 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
3037 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
3038 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
3039 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
3040 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
3041 
3052 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
3053  __IO uint32_t tmpreg = 0x00U; \
3054  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3055  /* Delay after an RCC peripheral clock enabling */ \
3056  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3057  UNUSED(tmpreg); \
3058  } while(0U)
3059 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
3060  __IO uint32_t tmpreg = 0x00U; \
3061  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3062  /* Delay after an RCC peripheral clock enabling */ \
3063  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3064  UNUSED(tmpreg); \
3065  } while(0U)
3066 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
3067  __IO uint32_t tmpreg = 0x00U; \
3068  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3069  /* Delay after an RCC peripheral clock enabling */ \
3070  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3071  UNUSED(tmpreg); \
3072  } while(0U)
3073 
3074 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
3075 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
3076 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
3077 
3088 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
3089 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
3090 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
3091 
3092 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
3093 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
3094 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
3095 
3102 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
3103 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
3104 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
3105 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3106 
3107 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
3108 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
3109 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
3110 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3111 
3119 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
3120 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
3121 
3122 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
3123 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
3124 
3132 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
3133 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
3134 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
3135 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
3136 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
3137 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
3138 
3139 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
3140 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
3141 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
3142 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
3143 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
3144 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
3145 
3153 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
3154 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
3155 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
3156 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
3157 
3158 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
3159 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
3160 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
3161 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
3162 
3170 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
3171 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
3172 
3184 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
3185 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
3186 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3187 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3188 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3189 
3190 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
3191 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
3192 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3193 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3194 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3195 
3207 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
3208 
3209 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
3210 
3222 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
3223 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
3224 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
3225 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
3226 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
3227 
3228 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
3229 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
3230 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
3231 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
3232 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
3233 
3245 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
3246 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
3247 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
3248 
3249 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
3250 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
3251 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
3252 
3255 #endif /* STM32F401xC || STM32F401xE*/
3256 /*----------------------------------------------------------------------------*/
3257 
3258 /*-------------------------------- STM32F410xx -------------------------------*/
3259 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
3260 
3267 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3268  __IO uint32_t tmpreg = 0x00U; \
3269  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3270  /* Delay after an RCC peripheral clock enabling */ \
3271  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3272  UNUSED(tmpreg); \
3273  } while(0U)
3274 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
3275  __IO uint32_t tmpreg = 0x00U; \
3276  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
3277  /* Delay after an RCC peripheral clock enabling */ \
3278  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
3279  UNUSED(tmpreg); \
3280  } while(0U)
3281 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
3282 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
3283 
3294 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
3295 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
3296 
3297 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
3298 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
3299 
3307 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
3308  __IO uint32_t tmpreg = 0x00U; \
3309  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
3310  /* Delay after an RCC peripheral clock enabling */ \
3311  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
3312  UNUSED(tmpreg); \
3313  } while(0U)
3314 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
3315  __IO uint32_t tmpreg = 0x00U; \
3316  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
3317  /* Delay after an RCC peripheral clock enabling */ \
3318  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
3319  UNUSED(tmpreg); \
3320  } while(0U)
3321 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
3322  __IO uint32_t tmpreg = 0x00U; \
3323  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
3324  /* Delay after an RCC peripheral clock enabling */ \
3325  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
3326  UNUSED(tmpreg); \
3327  } while(0U)
3328 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
3329  __IO uint32_t tmpreg = 0x00U; \
3330  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
3331  /* Delay after an RCC peripheral clock enabling */ \
3332  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
3333  UNUSED(tmpreg); \
3334  } while(0U)
3335 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
3336  __IO uint32_t tmpreg = 0x00U; \
3337  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
3338  /* Delay after an RCC peripheral clock enabling */ \
3339  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
3340  UNUSED(tmpreg); \
3341  } while(0U)
3342 
3343 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
3344 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
3345 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
3346 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
3347 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
3348 
3359 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
3360 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
3361 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
3362 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
3363 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
3364 
3365 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
3366 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
3367 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
3368 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
3369 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
3370 
3378 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
3379  __IO uint32_t tmpreg = 0x00U; \
3380  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3381  /* Delay after an RCC peripheral clock enabling */ \
3382  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3383  UNUSED(tmpreg); \
3384  } while(0U)
3385 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
3386  __IO uint32_t tmpreg = 0x00U; \
3387  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
3388  /* Delay after an RCC peripheral clock enabling */ \
3389  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
3390  UNUSED(tmpreg); \
3391  } while(0U)
3392 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
3393 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
3394 
3405 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
3406 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
3407 
3408 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
3409 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
3410 
3418 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3419 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
3420 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3421 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
3422 
3430 #define __HAL_RCC_AHB2_FORCE_RESET()
3431 #define __HAL_RCC_AHB2_RELEASE_RESET()
3432 
3440 #define __HAL_RCC_AHB3_FORCE_RESET()
3441 #define __HAL_RCC_AHB3_RELEASE_RESET()
3442 
3450 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
3451 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
3452 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
3453 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
3454 
3455 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
3456 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
3457 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
3458 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
3459 
3467 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
3468 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
3469 
3481 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
3482 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3483 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3484 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3485 
3486 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
3487 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3488 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3489 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3490 
3498 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
3499 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
3500 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
3501 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
3502 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
3503 
3504 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
3505 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
3506 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
3507 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
3508 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
3509 
3517 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
3518 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
3519 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
3520 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
3521 
3525 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
3526 /*----------------------------------------------------------------------------*/
3527 
3528 /*-------------------------------- STM32F411xx -------------------------------*/
3529 #if defined(STM32F411xE)
3530 
3537 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
3538  __IO uint32_t tmpreg = 0x00U; \
3539  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3540  /* Delay after an RCC peripheral clock enabling */ \
3541  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3542  UNUSED(tmpreg); \
3543  } while(0U)
3544 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
3545  __IO uint32_t tmpreg = 0x00U; \
3546  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3547  /* Delay after an RCC peripheral clock enabling */ \
3548  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3549  UNUSED(tmpreg); \
3550  } while(0U)
3551 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
3552  __IO uint32_t tmpreg = 0x00U; \
3553  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3554  /* Delay after an RCC peripheral clock enabling */ \
3555  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3556  UNUSED(tmpreg); \
3557  } while(0U)
3558 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3559  __IO uint32_t tmpreg = 0x00U; \
3560  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3561  /* Delay after an RCC peripheral clock enabling */ \
3562  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3563  UNUSED(tmpreg); \
3564  } while(0U)
3565 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
3566 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
3567 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
3568 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
3569 
3580 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
3581 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
3582 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
3583 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
3584 
3585 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
3586 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
3587 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
3588 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
3589 
3600 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
3601  __HAL_RCC_SYSCFG_CLK_ENABLE();\
3602  }while(0U)
3603 
3604 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
3605 
3616 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
3617 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
3618 
3629 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
3630  __IO uint32_t tmpreg = 0x00U; \
3631  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
3632  /* Delay after an RCC peripheral clock enabling */ \
3633  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
3634  UNUSED(tmpreg); \
3635  } while(0U)
3636 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
3637  __IO uint32_t tmpreg = 0x00U; \
3638  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
3639  /* Delay after an RCC peripheral clock enabling */ \
3640  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
3641  UNUSED(tmpreg); \
3642  } while(0U)
3643 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
3644  __IO uint32_t tmpreg = 0x00U; \
3645  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
3646  /* Delay after an RCC peripheral clock enabling */ \
3647  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
3648  UNUSED(tmpreg); \
3649  } while(0U)
3650 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
3651  __IO uint32_t tmpreg = 0x00U; \
3652  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3653  /* Delay after an RCC peripheral clock enabling */ \
3654  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3655  UNUSED(tmpreg); \
3656  } while(0U)
3657 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
3658  __IO uint32_t tmpreg = 0x00U; \
3659  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3660  /* Delay after an RCC peripheral clock enabling */ \
3661  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3662  UNUSED(tmpreg); \
3663  } while(0U)
3664 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
3665 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
3666 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
3667 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
3668 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
3669 
3680 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
3681 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
3682 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
3683 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
3684 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
3685 
3686 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
3687 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
3688 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
3689 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
3690 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
3691 
3699 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
3700  __IO uint32_t tmpreg = 0x00U; \
3701  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3702  /* Delay after an RCC peripheral clock enabling */ \
3703  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3704  UNUSED(tmpreg); \
3705  } while(0U)
3706 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
3707  __IO uint32_t tmpreg = 0x00U; \
3708  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3709  /* Delay after an RCC peripheral clock enabling */ \
3710  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3711  UNUSED(tmpreg); \
3712  } while(0U)
3713 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
3714  __IO uint32_t tmpreg = 0x00U; \
3715  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3716  /* Delay after an RCC peripheral clock enabling */ \
3717  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3718  UNUSED(tmpreg); \
3719  } while(0U)
3720 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
3721  __IO uint32_t tmpreg = 0x00U; \
3722  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3723  /* Delay after an RCC peripheral clock enabling */ \
3724  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3725  UNUSED(tmpreg); \
3726  } while(0U)
3727 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
3728 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
3729 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
3730 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
3731 
3742 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
3743 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
3744 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
3745 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
3746 
3747 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
3748 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
3749 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
3750 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
3751 
3759 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
3760 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
3761 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3762 
3763 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
3764 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
3765 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3766 
3774 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
3775 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
3776 
3777 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
3778 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
3779 
3787 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
3788 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
3789 
3797 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
3798 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
3799 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
3800 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
3801 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
3802 
3803 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
3804 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
3805 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
3806 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
3807 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
3808 
3816 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
3817 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
3818 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
3819 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
3820 
3821 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
3822 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
3823 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
3824 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
3825 
3837 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
3838 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
3839 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3840 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3841 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3842 
3843 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
3844 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
3845 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3846 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3847 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3848 
3860 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
3861 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
3862 
3870 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
3871 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
3872 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
3873 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
3874 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
3875 
3876 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
3877 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
3878 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
3879 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
3880 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
3881 
3889 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
3890 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
3891 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
3892 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
3893 
3894 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
3895 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
3896 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
3897 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
3898 
3901 #endif /* STM32F411xE */
3902 /*----------------------------------------------------------------------------*/
3903 
3904 /*---------------------------------- STM32F446xx -----------------------------*/
3905 #if defined(STM32F446xx)
3906 
3913 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
3914  __IO uint32_t tmpreg = 0x00U; \
3915  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
3916  /* Delay after an RCC peripheral clock enabling */ \
3917  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
3918  UNUSED(tmpreg); \
3919  } while(0U)
3920 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
3921  __IO uint32_t tmpreg = 0x00U; \
3922  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3923  /* Delay after an RCC peripheral clock enabling */ \
3924  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3925  UNUSED(tmpreg); \
3926  } while(0U)
3927 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3928  __IO uint32_t tmpreg = 0x00U; \
3929  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3930  /* Delay after an RCC peripheral clock enabling */ \
3931  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3932  UNUSED(tmpreg); \
3933  } while(0U)
3934 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
3935  __IO uint32_t tmpreg = 0x00U; \
3936  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3937  /* Delay after an RCC peripheral clock enabling */ \
3938  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3939  UNUSED(tmpreg); \
3940  } while(0U)
3941 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
3942  __IO uint32_t tmpreg = 0x00U; \
3943  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3944  /* Delay after an RCC peripheral clock enabling */ \
3945  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3946  UNUSED(tmpreg); \
3947  } while(0U)
3948 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
3949  __IO uint32_t tmpreg = 0x00U; \
3950  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
3951  /* Delay after an RCC peripheral clock enabling */ \
3952  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
3953  UNUSED(tmpreg); \
3954  } while(0U)
3955 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
3956  __IO uint32_t tmpreg = 0x00U; \
3957  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
3958  /* Delay after an RCC peripheral clock enabling */ \
3959  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
3960  UNUSED(tmpreg); \
3961  } while(0U)
3962 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
3963  __IO uint32_t tmpreg = 0x00U; \
3964  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
3965  /* Delay after an RCC peripheral clock enabling */ \
3966  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
3967  UNUSED(tmpreg); \
3968  } while(0U)
3969 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
3970  __IO uint32_t tmpreg = 0x00U; \
3971  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
3972  /* Delay after an RCC peripheral clock enabling */ \
3973  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
3974  UNUSED(tmpreg); \
3975  } while(0U)
3976 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
3977 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
3978 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
3979 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
3980 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
3981 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
3982 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
3983 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
3984 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
3985 
3996 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
3997 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
3998 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
3999 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
4000 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
4001 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
4002 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
4003 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
4004 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
4005 
4006 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
4007 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
4008 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
4009 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
4010 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
4011 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
4012 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
4013 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
4014 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
4015 
4026 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
4027  __IO uint32_t tmpreg = 0x00U; \
4028  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
4029  /* Delay after an RCC peripheral clock enabling */ \
4030  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
4031  UNUSED(tmpreg); \
4032  } while(0U)
4033 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
4034 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
4035  __HAL_RCC_SYSCFG_CLK_ENABLE();\
4036  }while(0U)
4037 
4038 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
4039 
4040 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
4041  __IO uint32_t tmpreg = 0x00U; \
4042  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4043  /* Delay after an RCC peripheral clock enabling */ \
4044  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4045  UNUSED(tmpreg); \
4046  } while(0U)
4047 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
4048 
4059 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
4060 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
4061 
4062 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
4063 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
4064 
4065 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
4066 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
4067 
4078 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
4079  __IO uint32_t tmpreg = 0x00U; \
4080  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
4081  /* Delay after an RCC peripheral clock enabling */ \
4082  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
4083  UNUSED(tmpreg); \
4084  } while(0U)
4085 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
4086  __IO uint32_t tmpreg = 0x00U; \
4087  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4088  /* Delay after an RCC peripheral clock enabling */ \
4089  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4090  UNUSED(tmpreg); \
4091  } while(0U)
4092 
4093 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
4094 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
4095 
4106 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
4107 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
4108 
4109 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
4110 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
4111 
4122 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
4123  __IO uint32_t tmpreg = 0x00U; \
4124  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4125  /* Delay after an RCC peripheral clock enabling */ \
4126  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4127  UNUSED(tmpreg); \
4128  } while(0U)
4129 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
4130  __IO uint32_t tmpreg = 0x00U; \
4131  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4132  /* Delay after an RCC peripheral clock enabling */ \
4133  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4134  UNUSED(tmpreg); \
4135  } while(0U)
4136 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
4137  __IO uint32_t tmpreg = 0x00U; \
4138  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4139  /* Delay after an RCC peripheral clock enabling */ \
4140  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4141  UNUSED(tmpreg); \
4142  } while(0U)
4143 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
4144  __IO uint32_t tmpreg = 0x00U; \
4145  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4146  /* Delay after an RCC peripheral clock enabling */ \
4147  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4148  UNUSED(tmpreg); \
4149  } while(0U)
4150 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
4151  __IO uint32_t tmpreg = 0x00U; \
4152  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4153  /* Delay after an RCC peripheral clock enabling */ \
4154  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4155  UNUSED(tmpreg); \
4156  } while(0U)
4157 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
4158  __IO uint32_t tmpreg = 0x00U; \
4159  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
4160  /* Delay after an RCC peripheral clock enabling */ \
4161  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
4162  UNUSED(tmpreg); \
4163  } while(0U)
4164 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
4165  __IO uint32_t tmpreg = 0x00U; \
4166  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4167  /* Delay after an RCC peripheral clock enabling */ \
4168  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4169  UNUSED(tmpreg); \
4170  } while(0U)
4171 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
4172  __IO uint32_t tmpreg = 0x00U; \
4173  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4174  /* Delay after an RCC peripheral clock enabling */ \
4175  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4176  UNUSED(tmpreg); \
4177  } while(0U)
4178 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
4179  __IO uint32_t tmpreg = 0x00U; \
4180  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4181  /* Delay after an RCC peripheral clock enabling */ \
4182  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4183  UNUSED(tmpreg); \
4184  } while(0U)
4185 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
4186  __IO uint32_t tmpreg = 0x00U; \
4187  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4188  /* Delay after an RCC peripheral clock enabling */ \
4189  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4190  UNUSED(tmpreg); \
4191  } while(0U)
4192 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
4193  __IO uint32_t tmpreg = 0x00U; \
4194  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
4195  /* Delay after an RCC peripheral clock enabling */ \
4196  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
4197  UNUSED(tmpreg); \
4198  } while(0U)
4199 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
4200  __IO uint32_t tmpreg = 0x00U; \
4201  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
4202  /* Delay after an RCC peripheral clock enabling */ \
4203  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
4204  UNUSED(tmpreg); \
4205  } while(0U)
4206 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
4207  __IO uint32_t tmpreg = 0x00U; \
4208  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
4209  /* Delay after an RCC peripheral clock enabling */ \
4210  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
4211  UNUSED(tmpreg); \
4212  } while(0U)
4213 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
4214  __IO uint32_t tmpreg = 0x00U; \
4215  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
4216  /* Delay after an RCC peripheral clock enabling */ \
4217  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
4218  UNUSED(tmpreg); \
4219  } while(0U)
4220 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
4221  __IO uint32_t tmpreg = 0x00U; \
4222  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
4223  /* Delay after an RCC peripheral clock enabling */ \
4224  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
4225  UNUSED(tmpreg); \
4226  } while(0U)
4227 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
4228  __IO uint32_t tmpreg = 0x00U; \
4229  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
4230  /* Delay after an RCC peripheral clock enabling */ \
4231  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
4232  UNUSED(tmpreg); \
4233  } while(0U)
4234 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
4235  __IO uint32_t tmpreg = 0x00U; \
4236  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
4237  /* Delay after an RCC peripheral clock enabling */ \
4238  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
4239  UNUSED(tmpreg); \
4240  } while(0U)
4241 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
4242  __IO uint32_t tmpreg = 0x00U; \
4243  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
4244  /* Delay after an RCC peripheral clock enabling */ \
4245  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
4246  UNUSED(tmpreg); \
4247  } while(0U)
4248 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
4249  __IO uint32_t tmpreg = 0x00U; \
4250  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
4251  /* Delay after an RCC peripheral clock enabling */ \
4252  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
4253  UNUSED(tmpreg); \
4254  } while(0U)
4255 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
4256 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
4257 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
4258 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
4259 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
4260 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
4261 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
4262 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
4263 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
4264 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
4265 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
4266 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
4267 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
4268 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
4269 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
4270 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
4271 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
4272 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
4273 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
4274 
4285 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
4286 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
4287 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
4288 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
4289 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
4290 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
4291 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
4292 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
4293 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
4294 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
4295 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
4296 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
4297 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
4298 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
4299 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
4300 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
4301 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
4302 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
4303 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
4304 
4305 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
4306 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
4307 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
4308 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
4309 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
4310 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
4311 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
4312 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
4313 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
4314 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
4315 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
4316 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
4317 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
4318 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
4319 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
4320 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
4321 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
4322 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
4323 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
4324 
4335 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
4336  __IO uint32_t tmpreg = 0x00U; \
4337  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
4338  /* Delay after an RCC peripheral clock enabling */ \
4339  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
4340  UNUSED(tmpreg); \
4341  } while(0U)
4342 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
4343  __IO uint32_t tmpreg = 0x00U; \
4344  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
4345  /* Delay after an RCC peripheral clock enabling */ \
4346  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
4347  UNUSED(tmpreg); \
4348  } while(0U)
4349 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
4350  __IO uint32_t tmpreg = 0x00U; \
4351  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
4352  /* Delay after an RCC peripheral clock enabling */ \
4353  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
4354  UNUSED(tmpreg); \
4355  } while(0U)
4356 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
4357  __IO uint32_t tmpreg = 0x00U; \
4358  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
4359  /* Delay after an RCC peripheral clock enabling */ \
4360  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
4361  UNUSED(tmpreg); \
4362  } while(0U)
4363 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
4364  __IO uint32_t tmpreg = 0x00U; \
4365  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
4366  /* Delay after an RCC peripheral clock enabling */ \
4367  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
4368  UNUSED(tmpreg); \
4369  } while(0U)
4370 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
4371  __IO uint32_t tmpreg = 0x00U; \
4372  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
4373  /* Delay after an RCC peripheral clock enabling */ \
4374  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
4375  UNUSED(tmpreg); \
4376  } while(0U)
4377 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
4378  __IO uint32_t tmpreg = 0x00U; \
4379  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
4380  /* Delay after an RCC peripheral clock enabling */ \
4381  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
4382  UNUSED(tmpreg); \
4383  } while(0U)
4384 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
4385  __IO uint32_t tmpreg = 0x00U; \
4386  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
4387  /* Delay after an RCC peripheral clock enabling */ \
4388  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
4389  UNUSED(tmpreg); \
4390  } while(0U)
4391 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
4392 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
4393 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
4394 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
4395 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
4396 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
4397 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
4398 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
4399 
4410 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
4411 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
4412 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
4413 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
4414 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
4415 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
4416 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
4417 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
4418 
4419 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
4420 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
4421 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
4422 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
4423 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
4424 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
4425 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
4426 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
4427 
4435 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
4436 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
4437 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
4438 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
4439 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
4440 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
4441 
4442 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
4443 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
4444 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
4445 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
4446 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
4447 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
4448 
4456 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
4457 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
4458 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
4459 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
4460 
4461 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
4462 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
4463 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
4464 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
4465 
4473 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
4474 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
4475 
4476 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
4477 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
4478 
4479 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
4480 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
4481 
4489 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
4490 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
4491 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
4492 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
4493 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
4494 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
4495 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
4496 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
4497 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
4498 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
4499 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
4500 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
4501 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
4502 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
4503 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
4504 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
4505 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
4506 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
4507 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
4508 
4509 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
4510 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
4511 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
4512 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
4513 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
4514 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
4515 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
4516 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
4517 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
4518 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
4519 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
4520 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
4521 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
4522 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
4523 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
4524 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
4525 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
4526 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
4527 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
4528 
4536 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
4537 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
4538 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
4539 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
4540 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
4541 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
4542 
4543 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
4544 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
4545 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
4546 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
4547 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
4548 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
4549 
4561 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
4562 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
4563 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
4564 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
4565 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
4566 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
4567 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
4568 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
4569 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
4570 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
4571 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
4572 
4573 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
4574 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
4575 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
4576 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
4577 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
4578 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
4579 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
4580 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
4581 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
4582 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
4583 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
4584 
4596 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
4597 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
4598 
4599 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
4600 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
4601 
4602 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
4603 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
4604 
4616 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
4617 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
4618 
4619 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
4620 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
4621 
4633 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
4634 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
4635 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
4636 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
4637 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
4638 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
4639 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
4640 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
4641 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
4642 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
4643 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
4644 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
4645 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
4646 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
4647 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
4648 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
4649 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
4650 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
4651 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
4652 
4653 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
4654 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
4655 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
4656 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
4657 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
4658 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
4659 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
4660 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
4661 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
4662 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
4663 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
4664 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
4665 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
4666 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
4667 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
4668 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
4669 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
4670 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
4671 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
4672 
4684 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
4685 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
4686 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
4687 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
4688 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
4689 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
4690 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
4691 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
4692 
4693 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
4694 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
4695 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
4696 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
4697 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
4698 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
4699 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
4700 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
4701 
4705 #endif /* STM32F446xx */
4706 /*----------------------------------------------------------------------------*/
4707 
4708 /*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/
4709 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
4710 
4717 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4718 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
4719  __IO uint32_t tmpreg = 0x00U; \
4720  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
4721  /* Delay after an RCC peripheral clock enabling */ \
4722  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
4723  UNUSED(tmpreg); \
4724  } while(0U)
4725 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
4726 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4727 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
4728  __IO uint32_t tmpreg = 0x00U; \
4729  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
4730  /* Delay after an RCC peripheral clock enabling */ \
4731  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
4732  UNUSED(tmpreg); \
4733  } while(0U)
4734 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
4735 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4736 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
4737  __IO uint32_t tmpreg = 0x00U; \
4738  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
4739  /* Delay after an RCC peripheral clock enabling */ \
4740  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
4741  UNUSED(tmpreg); \
4742  } while(0U)
4743 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
4744  __IO uint32_t tmpreg = 0x00U; \
4745  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
4746  /* Delay after an RCC peripheral clock enabling */ \
4747  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
4748  UNUSED(tmpreg); \
4749  } while(0U)
4750 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
4751 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
4752  __IO uint32_t tmpreg = 0x00U; \
4753  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
4754  /* Delay after an RCC peripheral clock enabling */ \
4755  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
4756  UNUSED(tmpreg); \
4757  } while(0U)
4758 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4759 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
4760 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
4761 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4762 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
4763 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
4764 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4765 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
4766 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
4767 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
4768 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
4769 
4780 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4781 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
4782 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
4783 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4784 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
4785 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
4786 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4787 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
4788 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
4789 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
4790 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
4791 
4792 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4793 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
4794 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
4795 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4796 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
4797 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
4798 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
4799 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
4800 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
4801 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
4802 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
4803 
4814 #if defined(STM32F423xx)
4815 #define __HAL_RCC_AES_CLK_ENABLE() do { \
4816  __IO uint32_t tmpreg = 0x00U; \
4817  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
4818  /* Delay after an RCC peripheral clock enabling */ \
4819  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
4820  UNUSED(tmpreg); \
4821  } while(0U)
4822 
4823 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
4824 #endif /* STM32F423xx */
4825 
4826 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
4827  __IO uint32_t tmpreg = 0x00U; \
4828  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4829  /* Delay after an RCC peripheral clock enabling */ \
4830  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4831  UNUSED(tmpreg); \
4832  } while(0U)
4833 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
4834 
4835 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
4836  __HAL_RCC_SYSCFG_CLK_ENABLE();\
4837  }while(0U)
4838 
4839 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
4840 
4851 #if defined(STM32F423xx)
4852 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
4853 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
4854 #endif /* STM32F423xx */
4855 
4856 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
4857 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
4858 
4859 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
4860 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
4861 
4872 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
4873 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
4874  __IO uint32_t tmpreg = 0x00U; \
4875  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
4876  /* Delay after an RCC peripheral clock enabling */ \
4877  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
4878  UNUSED(tmpreg); \
4879  } while(0U)
4880 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
4881  __IO uint32_t tmpreg = 0x00U; \
4882  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4883  /* Delay after an RCC peripheral clock enabling */ \
4884  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4885  UNUSED(tmpreg); \
4886  } while(0U)
4887 
4888 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
4889 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
4890 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
4891 
4902 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
4903 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
4904 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
4905 
4906 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
4907 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
4908 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
4909 
4921 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
4922  __IO uint32_t tmpreg = 0x00U; \
4923  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4924  /* Delay after an RCC peripheral clock enabling */ \
4925  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4926  UNUSED(tmpreg); \
4927  } while(0U)
4928 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
4929  __IO uint32_t tmpreg = 0x00U; \
4930  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4931  /* Delay after an RCC peripheral clock enabling */ \
4932  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4933  UNUSED(tmpreg); \
4934  } while(0U)
4935 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
4936  __IO uint32_t tmpreg = 0x00U; \
4937  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4938  /* Delay after an RCC peripheral clock enabling */ \
4939  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4940  UNUSED(tmpreg); \
4941  } while(0U)
4942 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
4943  __IO uint32_t tmpreg = 0x00U; \
4944  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4945  /* Delay after an RCC peripheral clock enabling */ \
4946  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4947  UNUSED(tmpreg); \
4948  } while(0U)
4949 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
4950  __IO uint32_t tmpreg = 0x00U; \
4951  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4952  /* Delay after an RCC peripheral clock enabling */ \
4953  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4954  UNUSED(tmpreg); \
4955  } while(0U)
4956 #if defined(STM32F413xx) || defined(STM32F423xx)
4957 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
4958  __IO uint32_t tmpreg = 0x00U; \
4959  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
4960  /* Delay after an RCC peripheral clock enabling */ \
4961  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
4962  UNUSED(tmpreg); \
4963  } while(0U)
4964 #endif /* STM32F413xx || STM32F423xx */
4965 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
4966  __IO uint32_t tmpreg = 0x00U; \
4967  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
4968  /* Delay after an RCC peripheral clock enabling */ \
4969  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
4970  UNUSED(tmpreg); \
4971  } while(0U)
4972 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
4973 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
4974  __IO uint32_t tmpreg = 0x00U; \
4975  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4976  /* Delay after an RCC peripheral clock enabling */ \
4977  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4978  UNUSED(tmpreg); \
4979  } while(0U)
4980 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
4981 
4982 #if defined(STM32F413xx) || defined(STM32F423xx)
4983 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
4984  __IO uint32_t tmpreg = 0x00U; \
4985  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4986  /* Delay after an RCC peripheral clock enabling */ \
4987  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4988  UNUSED(tmpreg); \
4989  } while(0U)
4990 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
4991  __IO uint32_t tmpreg = 0x00U; \
4992  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4993  /* Delay after an RCC peripheral clock enabling */ \
4994  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4995  UNUSED(tmpreg); \
4996  } while(0U)
4997 #endif /* STM32F413xx || STM32F423xx */
4998 
4999 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
5000  __IO uint32_t tmpreg = 0x00U; \
5001  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
5002  /* Delay after an RCC peripheral clock enabling */ \
5003  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
5004  UNUSED(tmpreg); \
5005  } while(0U)
5006 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
5007  __IO uint32_t tmpreg = 0x00U; \
5008  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
5009  /* Delay after an RCC peripheral clock enabling */ \
5010  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
5011  UNUSED(tmpreg); \
5012  } while(0U)
5013 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
5014  __IO uint32_t tmpreg = 0x00U; \
5015  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
5016  /* Delay after an RCC peripheral clock enabling */ \
5017  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
5018  UNUSED(tmpreg); \
5019  } while(0U)
5020 #if defined(STM32F413xx) || defined(STM32F423xx)
5021 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \
5022  __IO uint32_t tmpreg = 0x00U; \
5023  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
5024  /* Delay after an RCC peripheral clock enabling */ \
5025  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
5026  UNUSED(tmpreg); \
5027  } while(0U)
5028 #endif /* STM32F413xx || STM32F423xx */
5029 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
5030  __IO uint32_t tmpreg = 0x00U; \
5031  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
5032  /* Delay after an RCC peripheral clock enabling */ \
5033  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
5034  UNUSED(tmpreg); \
5035  } while(0U)
5036 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
5037  __IO uint32_t tmpreg = 0x00U; \
5038  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
5039  /* Delay after an RCC peripheral clock enabling */ \
5040  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
5041  UNUSED(tmpreg); \
5042  } while(0U)
5043 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
5044  __IO uint32_t tmpreg = 0x00U; \
5045  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
5046  /* Delay after an RCC peripheral clock enabling */ \
5047  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
5048  UNUSED(tmpreg); \
5049  } while(0U)
5050 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
5051  __IO uint32_t tmpreg = 0x00U; \
5052  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
5053  /* Delay after an RCC peripheral clock enabling */ \
5054  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
5055  UNUSED(tmpreg); \
5056  } while(0U)
5057 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
5058  __IO uint32_t tmpreg = 0x00U; \
5059  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
5060  /* Delay after an RCC peripheral clock enabling */ \
5061  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
5062  UNUSED(tmpreg); \
5063  } while(0U)
5064 #if defined(STM32F413xx) || defined(STM32F423xx)
5065 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
5066  __IO uint32_t tmpreg = 0x00U; \
5067  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
5068  /* Delay after an RCC peripheral clock enabling */ \
5069  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
5070  UNUSED(tmpreg); \
5071  } while(0U)
5072 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
5073  __IO uint32_t tmpreg = 0x00U; \
5074  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
5075  /* Delay after an RCC peripheral clock enabling */ \
5076  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
5077  UNUSED(tmpreg); \
5078  } while(0U)
5079 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
5080  __IO uint32_t tmpreg = 0x00U; \
5081  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
5082  /* Delay after an RCC peripheral clock enabling */ \
5083  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
5084  UNUSED(tmpreg); \
5085  } while(0U)
5086 #endif /* STM32F413xx || STM32F423xx */
5087 
5088 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
5089 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
5090 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
5091 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
5092 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
5093 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
5094 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
5095 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
5096 #if defined(STM32F413xx) || defined(STM32F423xx)
5097 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
5098 #endif /* STM32F413xx || STM32F423xx */
5099 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
5100 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
5101 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5102 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
5103 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5104 #if defined(STM32F413xx) || defined(STM32F423xx)
5105 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
5106 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
5107 #endif /* STM32F413xx || STM32F423xx */
5108 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
5109 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
5110 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
5111 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
5112 #if defined(STM32F413xx) || defined(STM32F423xx)
5113 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
5114 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
5115 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
5116 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
5117 #endif /* STM32F413xx || STM32F423xx */
5118 
5130 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
5131 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
5132 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
5133 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
5134 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
5135 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
5136 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
5137 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
5138 #if defined(STM32F413xx) || defined(STM32F423xx)
5139 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
5140 #endif /* STM32F413xx || STM32F423xx */
5141 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
5142 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
5143 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5144 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
5145 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
5146 #if defined(STM32F413xx) || defined(STM32F423xx)
5147 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
5148 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
5149 #endif /* STM32F413xx || STM32F423xx */
5150 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
5151 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
5152 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
5153 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
5154 #if defined(STM32F413xx) || defined(STM32F423xx)
5155 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
5156 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
5157 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
5158 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
5159 #endif /* STM32F413xx || STM32F423xx */
5160 
5161 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
5162 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
5163 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
5164 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
5165 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
5166 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
5167 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
5168 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
5169 #if defined(STM32F413xx) || defined(STM32F423xx)
5170 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
5171 #endif /* STM32F413xx || STM32F423xx */
5172 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
5173 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
5174 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5175 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
5176 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
5177 #if defined(STM32F413xx) || defined(STM32F423xx)
5178 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
5179 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
5180 #endif /* STM32F413xx || STM32F423xx */
5181 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
5182 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
5183 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
5184 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
5185 #if defined(STM32F413xx) || defined(STM32F423xx)
5186 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
5187 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
5188 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
5189 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
5190 #endif /* STM32F413xx || STM32F423xx */
5191 
5201 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
5202  __IO uint32_t tmpreg = 0x00U; \
5203  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
5204  /* Delay after an RCC peripheral clock enabling */ \
5205  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
5206  UNUSED(tmpreg); \
5207  } while(0U)
5208 #if defined(STM32F413xx) || defined(STM32F423xx)
5209 #define __HAL_RCC_UART9_CLK_ENABLE() do { \
5210  __IO uint32_t tmpreg = 0x00U; \
5211  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
5212  /* Delay after an RCC peripheral clock enabling */ \
5213  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
5214  UNUSED(tmpreg); \
5215  } while(0U)
5216 #define __HAL_RCC_UART10_CLK_ENABLE() do { \
5217  __IO uint32_t tmpreg = 0x00U; \
5218  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
5219  /* Delay after an RCC peripheral clock enabling */ \
5220  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
5221  UNUSED(tmpreg); \
5222  } while(0U)
5223 #endif /* STM32F413xx || STM32F423xx */
5224 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
5225  __IO uint32_t tmpreg = 0x00U; \
5226  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
5227  /* Delay after an RCC peripheral clock enabling */ \
5228  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
5229  UNUSED(tmpreg); \
5230  } while(0U)
5231 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
5232  __IO uint32_t tmpreg = 0x00U; \
5233  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
5234  /* Delay after an RCC peripheral clock enabling */ \
5235  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
5236  UNUSED(tmpreg); \
5237  } while(0U)
5238 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
5239  __IO uint32_t tmpreg = 0x00U; \
5240  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
5241  /* Delay after an RCC peripheral clock enabling */ \
5242  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
5243  UNUSED(tmpreg); \
5244  } while(0U)
5245 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
5246  __IO uint32_t tmpreg = 0x00U; \
5247  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
5248  /* Delay after an RCC peripheral clock enabling */ \
5249  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
5250  UNUSED(tmpreg); \
5251  } while(0U)
5252 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
5253  __IO uint32_t tmpreg = 0x00U; \
5254  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
5255  /* Delay after an RCC peripheral clock enabling */ \
5256  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
5257  UNUSED(tmpreg); \
5258  } while(0U)
5259 #if defined(STM32F413xx) || defined(STM32F423xx)
5260 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
5261  __IO uint32_t tmpreg = 0x00U; \
5262  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
5263  /* Delay after an RCC peripheral clock enabling */ \
5264  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
5265  UNUSED(tmpreg); \
5266  } while(0U)
5267 #endif /* STM32F413xx || STM32F423xx */
5268 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
5269  __IO uint32_t tmpreg = 0x00U; \
5270  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
5271  /* Delay after an RCC peripheral clock enabling */ \
5272  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
5273  UNUSED(tmpreg); \
5274  } while(0U)
5275 #if defined(STM32F413xx) || defined(STM32F423xx)
5276 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
5277  __IO uint32_t tmpreg = 0x00U; \
5278  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
5279  /* Delay after an RCC peripheral clock enabling */ \
5280  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
5281  UNUSED(tmpreg); \
5282  } while(0U)
5283 #endif /* STM32F413xx || STM32F423xx */
5284 
5285 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
5286 #if defined(STM32F413xx) || defined(STM32F423xx)
5287 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
5288 #define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
5289 #endif /* STM32F413xx || STM32F423xx */
5290 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
5291 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
5292 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
5293 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
5294 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
5295 #if defined(STM32F413xx) || defined(STM32F423xx)
5296 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
5297 #endif /* STM32F413xx || STM32F423xx */
5298 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
5299 #if defined(STM32F413xx) || defined(STM32F423xx)
5300 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
5301 #endif /* STM32F413xx || STM32F423xx */
5302 
5313 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
5314 #if defined(STM32F413xx) || defined(STM32F423xx)
5315 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
5316 #define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
5317 #endif /* STM32F413xx || STM32F423xx */
5318 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
5319 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
5320 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
5321 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
5322 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
5323 #if defined(STM32F413xx) || defined(STM32F423xx)
5324 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
5325 #endif /* STM32F413xx || STM32F423xx */
5326 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
5327 #if defined(STM32F413xx) || defined(STM32F423xx)
5328 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
5329 #endif /* STM32F413xx || STM32F423xx */
5330 
5331 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
5332 #if defined(STM32F413xx) || defined(STM32F423xx)
5333 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
5334 #define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
5335 #endif /* STM32F413xx || STM32F423xx */
5336 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
5337 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
5338 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
5339 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
5340 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
5341 #if defined(STM32F413xx) || defined(STM32F423xx)
5342 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
5343 #endif /* STM32F413xx || STM32F423xx */
5344 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
5345 #if defined(STM32F413xx) || defined(STM32F423xx)
5346 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
5347 #endif /* STM32F413xx || STM32F423xx */
5348 
5356 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
5357 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
5358 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
5359 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
5360 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
5361 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
5362 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
5363 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
5364 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
5365 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
5366 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
5367 
5368 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
5369 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
5370 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
5371 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
5372 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
5373 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
5374 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
5375 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
5376 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
5377 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
5378 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
5379 
5387 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
5388 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
5389 
5390 #if defined(STM32F423xx)
5391 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
5392 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
5393 #endif /* STM32F423xx */
5394 
5395 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
5396 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
5397 
5398 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
5399 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
5400 
5408 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5409 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
5410 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
5411 
5412 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
5413 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
5414 
5415 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
5416 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
5417 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5418 #if defined(STM32F412Cx)
5419 #define __HAL_RCC_AHB3_FORCE_RESET()
5420 #define __HAL_RCC_AHB3_RELEASE_RESET()
5421 
5422 #define __HAL_RCC_FSMC_FORCE_RESET()
5423 #define __HAL_RCC_QSPI_FORCE_RESET()
5424 
5425 #define __HAL_RCC_FSMC_RELEASE_RESET()
5426 #define __HAL_RCC_QSPI_RELEASE_RESET()
5427 #endif /* STM32F412Cx */
5428 
5436 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
5437 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
5438 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
5439 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
5440 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
5441 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
5442 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
5443 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
5444 #if defined(STM32F413xx) || defined(STM32F423xx)
5445 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
5446 #endif /* STM32F413xx || STM32F423xx */
5447 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
5448 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5449 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
5450 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5451 #if defined(STM32F413xx) || defined(STM32F423xx)
5452 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
5453 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
5454 #endif /* STM32F413xx || STM32F423xx */
5455 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
5456 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
5457 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
5458 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
5459 #if defined(STM32F413xx) || defined(STM32F423xx)
5460 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
5461 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
5462 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
5463 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
5464 #endif /* STM32F413xx || STM32F423xx */
5465 
5466 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
5467 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
5468 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
5469 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
5470 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
5471 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
5472 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
5473 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
5474 #if defined(STM32F413xx) || defined(STM32F423xx)
5475 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
5476 #endif /* STM32F413xx || STM32F423xx */
5477 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
5478 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5479 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
5480 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5481 #if defined(STM32F413xx) || defined(STM32F423xx)
5482 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
5483 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
5484 #endif /* STM32F413xx || STM32F423xx */
5485 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
5486 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
5487 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
5488 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
5489 #if defined(STM32F413xx) || defined(STM32F423xx)
5490 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
5491 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
5492 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
5493 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
5494 #endif /* STM32F413xx || STM32F423xx */
5495 
5503 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
5504 #if defined(STM32F413xx) || defined(STM32F423xx)
5505 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST))
5506 #define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST))
5507 #endif /* STM32F413xx || STM32F423xx */
5508 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
5509 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
5510 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
5511 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
5512 #if defined(STM32F413xx) || defined(STM32F423xx)
5513 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
5514 #endif /* STM32F413xx || STM32F423xx */
5515 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
5516 #if defined(STM32F413xx) || defined(STM32F423xx)
5517 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST))
5518 #endif /* STM32F413xx || STM32F423xx */
5519 
5520 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
5521 #if defined(STM32F413xx) || defined(STM32F423xx)
5522 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
5523 #define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
5524 #endif /* STM32F413xx || STM32F423xx */
5525 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
5526 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
5527 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
5528 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
5529 #if defined(STM32F413xx) || defined(STM32F423xx)
5530 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
5531 #endif /* STM32F413xx || STM32F423xx */
5532 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
5533 #if defined(STM32F413xx) || defined(STM32F423xx)
5534 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
5535 #endif /* STM32F413xx || STM32F423xx */
5536 
5548 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
5549 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
5550 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
5551 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
5552 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
5553 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
5554 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
5555 #if defined(STM32F413xx) || defined(STM32F423xx)
5556 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
5557 #endif /* STM32F413xx || STM32F423xx */
5558 
5559 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
5560 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
5561 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
5562 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
5563 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
5564 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
5565 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
5566 #if defined(STM32F413xx) || defined(STM32F423xx)
5567 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
5568 #endif /* STM32F413xx || STM32F423xx */
5569 
5581 #if defined(STM32F423xx)
5582 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))
5583 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
5584 #endif /* STM32F423xx */
5585 
5586 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
5587 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
5588 
5589 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
5590 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
5591 
5603 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5604 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
5605 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
5606 
5607 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
5608 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
5609 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5610 
5623 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
5624 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
5625 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
5626 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
5627 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
5628 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
5629 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
5630 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
5631 #if defined(STM32F413xx) || defined(STM32F423xx)
5632 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
5633 #endif /* STM32F413xx || STM32F423xx */
5634 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
5635 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
5636 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5637 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
5638 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5639 #if defined(STM32F413xx) || defined(STM32F423xx)
5640 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
5641 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
5642 #endif /* STM32F413xx || STM32F423xx */
5643 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
5644 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
5645 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
5646 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
5647 #if defined(STM32F413xx) || defined(STM32F423xx)
5648 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
5649 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
5650 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
5651 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
5652 #endif /* STM32F413xx || STM32F423xx */
5653 
5654 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
5655 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
5656 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
5657 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
5658 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
5659 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
5660 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
5661 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
5662 #if defined(STM32F413xx) || defined(STM32F423xx)
5663 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
5664 #endif /* STM32F413xx || STM32F423xx */
5665 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
5666 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
5667 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
5668 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
5669 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
5670 #if defined(STM32F413xx) || defined(STM32F423xx)
5671 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
5672 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
5673 #endif /* STM32F413xx || STM32F423xx */
5674 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
5675 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
5676 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
5677 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
5678 #if defined(STM32F413xx) || defined(STM32F423xx)
5679 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
5680 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
5681 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
5682 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
5683 #endif /* STM32F413xx || STM32F423xx */
5684 
5696 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
5697 #if defined(STM32F413xx) || defined(STM32F423xx)
5698 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN))
5699 #define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN))
5700 #endif /* STM32F413xx || STM32F423xx */
5701 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
5702 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
5703 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
5704 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
5705 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
5706 #if defined(STM32F413xx) || defined(STM32F423xx)
5707 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
5708 #endif /* STM32F413xx || STM32F423xx */
5709 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
5710 #if defined(STM32F413xx) || defined(STM32F423xx)
5711 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN))
5712 #endif /* STM32F413xx || STM32F423xx */
5713 
5714 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
5715 #if defined(STM32F413xx) || defined(STM32F423xx)
5716 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
5717 #define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
5718 #endif /* STM32F413xx || STM32F423xx */
5719 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
5720 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
5721 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
5722 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
5723 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
5724 #if defined(STM32F413xx) || defined(STM32F423xx)
5725 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
5726 #endif /* STM32F413xx || STM32F423xx */
5727 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
5728 #if defined(STM32F413xx) || defined(STM32F423xx)
5729 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
5730 #endif /* STM32F413xx || STM32F423xx */
5731 
5734 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
5735 /*----------------------------------------------------------------------------*/
5736 
5737 /*------------------------------- PLL Configuration --------------------------*/
5738 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
5739  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
5740  defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
5741 
5774 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
5775  (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
5776  ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
5777  ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
5778  ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \
5779  ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
5780 #else
5781 
5810 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
5811  (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
5812  ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
5813  ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
5814  ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
5815  #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
5816 /*----------------------------------------------------------------------------*/
5817 
5818 /*----------------------------PLLI2S Configuration ---------------------------*/
5819 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
5820  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
5821  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
5822  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
5823  defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
5824 
5828 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
5829 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
5830 
5831 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
5832  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
5833  STM32F412Rx || STM32F412Cx */
5834 #if defined(STM32F446xx)
5835 
5862 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
5863  (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5864  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
5865  ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
5866  ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
5867  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
5868 #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
5869  defined(STM32F413xx) || defined(STM32F423xx)
5870 
5893 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
5894  (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5895  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
5896  ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
5897  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
5898 #else
5899 
5914 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
5915  (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
5916  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
5917 #endif /* STM32F446xx */
5918 
5919 #if defined(STM32F411xE)
5920 
5940 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5941  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
5942  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
5943 #endif /* STM32F411xE */
5944 
5945 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
5946 
5963 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\
5964  ((__PLLI2SQ__) << 24U) |\
5965  ((__PLLI2SR__) << 28U))
5966 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
5967 /*----------------------------------------------------------------------------*/
5968 
5969 /*------------------------------ PLLSAI Configuration ------------------------*/
5970 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
5971 
5975 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
5976 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
5977 
5978 #if defined(STM32F446xx)
5979 
6004 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
6005  (RCC->PLLSAICFGR = ((__PLLSAIM__) | \
6006  ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \
6007  ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \
6008  ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))
6009 #endif /* STM32F446xx */
6010 
6011 #if defined(STM32F469xx) || defined(STM32F479xx)
6012 
6028 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
6029  (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
6030  ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
6031  ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\
6032  ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
6033 #endif /* STM32F469xx || STM32F479xx */
6034 
6035 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
6036 
6050 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
6051  (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \
6052  ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \
6053  ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
6054 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
6055 
6056 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6057 /*----------------------------------------------------------------------------*/
6058 
6059 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
6060 #if defined(STM32F413xx) || defined(STM32F423xx)
6061 
6067 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
6068 
6074 #define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
6075 #endif /* STM32F413xx || STM32F423xx */
6076 
6077 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
6078  defined(STM32F469xx) || defined(STM32F479xx)
6079 
6085 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
6086 
6093 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
6094 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6095 
6096 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
6097 
6105 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
6106 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
6107 /*----------------------------------------------------------------------------*/
6108 
6109 /*------------------------- Peripheral Clock selection -----------------------*/
6110 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
6111  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6112  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
6113  defined(STM32F479xx)
6114 
6122 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
6123 
6124 
6131 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
6132 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
6133 
6134 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
6135 
6149 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
6150 
6164 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
6165 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
6166 
6167 #if defined(STM32F446xx)
6168 
6179 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
6180 
6189 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
6190 
6202 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
6203 
6212 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
6213 
6223 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
6224 
6232 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
6233 
6243 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
6244 
6252 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
6253 
6260 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
6261 
6267 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
6268 
6276 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
6277 
6284 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
6285 
6292 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
6293 
6299 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
6300 
6307 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
6308 
6314 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
6315 
6322 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
6323 
6329 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
6330 #endif /* STM32F446xx */
6331 
6332 #if defined(STM32F469xx) || defined(STM32F479xx)
6333 
6340 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
6341 
6347 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
6348 
6355 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
6356 
6362 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
6363 
6370 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
6371 
6377 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
6378 
6379 #endif /* STM32F469xx || STM32F479xx */
6380 
6381 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
6382  defined(STM32F413xx) || defined(STM32F423xx)
6383 
6390 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
6391 
6397 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
6398 
6407 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
6408 
6416 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
6417 
6418 #if defined(STM32F413xx) || defined(STM32F423xx)
6419 
6426 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
6427 
6433 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
6434 
6442 #define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
6443 
6450 #define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
6451 
6463 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
6464 
6473 #define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
6474 
6486 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
6487 
6496 #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
6497 
6506 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
6507 
6515 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
6516 #endif /* STM32F413xx || STM32F423xx */
6517 
6526 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
6527 
6535 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
6536 
6545 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
6546 
6554 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
6555 
6564 #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
6565 
6573 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
6574 
6581 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
6582 
6589 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
6590 
6596 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
6597 
6604 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
6605 
6611 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
6612 
6613 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6614 
6615 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6616 
6623 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
6624 
6631 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
6632 
6640 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
6641 
6648 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
6649 
6658 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
6659 
6667 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
6668 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6669 
6670 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6671  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
6672  defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
6673  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
6674  defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
6675 
6688 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
6689 
6690 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
6691  STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\
6692  STM32F423xx */
6693 
6694 /*----------------------------------------------------------------------------*/
6695 
6696 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6697 
6699 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
6700 
6703 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
6704 
6707 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
6708 
6712 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
6713 
6717 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
6718 
6719 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6720 
6721 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6722 
6724 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
6725 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
6726 
6729 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
6730 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
6731 
6732 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6733 
6738 /* Exported functions --------------------------------------------------------*/
6746 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
6747 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
6748 
6749 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
6750 
6751 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
6752  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
6753  defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
6754  defined(STM32F423xx)
6755 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
6756 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
6757 #if defined(RCC_PLLI2S_SUPPORT)
6758 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
6759 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
6760 #endif /* RCC_PLLI2S_SUPPORT */
6761 #if defined(RCC_PLLSAI_SUPPORT)
6762 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);
6763 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
6764 #endif /* RCC_PLLSAI_SUPPORT */
6765 
6772 /* Private types -------------------------------------------------------------*/
6773 /* Private variables ---------------------------------------------------------*/
6774 /* Private constants ---------------------------------------------------------*/
6783 /* --- CR Register ---*/
6784 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6785  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6786 /* Alias word address of PLLSAION bit */
6787 #define RCC_PLLSAION_BIT_NUMBER 0x1CU
6788 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
6789 
6790 #define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
6791 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6792 
6793 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
6794  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
6795  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
6796  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
6797  defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
6798 /* Alias word address of PLLI2SON bit */
6799 #define RCC_PLLI2SON_BIT_NUMBER 0x1AU
6800 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
6801 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
6802  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
6803  STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
6804 
6805 /* --- DCKCFGR Register ---*/
6806 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6807  defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
6808  defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
6809  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
6810  defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
6811 /* Alias word address of TIMPRE bit */
6812 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
6813 #define RCC_TIMPRE_BIT_NUMBER 0x18U
6814 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
6815 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
6816  STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
6817  STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
6818 
6819 /* --- CFGR Register ---*/
6820 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
6821 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
6822  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
6823  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
6824  defined(STM32F469xx) || defined(STM32F479xx)
6825 /* Alias word address of I2SSRC bit */
6826 #define RCC_I2SSRC_BIT_NUMBER 0x17U
6827 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
6828 
6829 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
6830 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
6831  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
6832 
6833 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
6834  defined(STM32F413xx) || defined(STM32F423xx)
6835 /* --- PLLI2SCFGR Register ---*/
6836 #define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
6837 /* Alias word address of PLLI2SSRC bit */
6838 #define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
6839 #define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
6840 
6841 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
6842 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */
6843 
6844 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6845 /* Alias word address of MCO1EN bit */
6846 #define RCC_MCO1EN_BIT_NUMBER 0x8U
6847 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
6848 
6849 /* Alias word address of MCO2EN bit */
6850 #define RCC_MCO2EN_BIT_NUMBER 0x9U
6851 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
6852 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6853 
6854 #define PLL_TIMEOUT_VALUE 2U /* 2 ms */
6855 
6863 /* Private macros ------------------------------------------------------------*/
6870 #if defined(STM32F411xE)
6871 #define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
6872 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
6873 #else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
6874  STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx ||
6875  STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx ||
6876  STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
6877 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6878 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6879 #endif /* STM32F411xE */
6880 
6881 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
6882 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
6883 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
6884 
6885 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
6886 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
6887 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
6888 
6889 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
6890 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
6891 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
6892 
6893 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6894 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
6895 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6896 
6897 #if defined(STM32F446xx)
6898 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
6899 #endif /* STM32F446xx */
6900 
6901 #if defined(STM32F469xx) || defined(STM32F479xx)
6902 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
6903 #endif /* STM32F469xx || STM32F479xx */
6904 
6905 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
6906 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
6907 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6908 
6909 #if defined(STM32F413xx) || defined(STM32F423xx)
6910 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
6911 #endif /* STM32F413xx || STM32F423xx */
6912 
6913 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6914 
6915 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
6916  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6917 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
6918 
6919 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6920 
6921 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
6922 
6923 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6924 
6925 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
6926 
6927 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
6928 
6929 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
6930  ((VALUE) == RCC_PLLSAIDIVR_4) ||\
6931  ((VALUE) == RCC_PLLSAIDIVR_8) ||\
6932  ((VALUE) == RCC_PLLSAIDIVR_16))
6933 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6934 
6935 #if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
6936  defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
6937 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
6938 
6939 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
6940  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
6941 #endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
6942 
6943 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6944 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6945 
6946 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
6947  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
6948 
6949 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
6950  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
6951  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
6952 
6953 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
6954  ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
6955  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
6956  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
6957 
6958 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\
6959  ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\
6960  ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
6961 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6962 
6963 #if defined(STM32F446xx)
6964 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6965 
6966 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
6967  ((VALUE) == RCC_PLLI2SP_DIV4) ||\
6968  ((VALUE) == RCC_PLLI2SP_DIV6) ||\
6969  ((VALUE) == RCC_PLLI2SP_DIV8))
6970 
6971 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
6972 
6973 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
6974  ((VALUE) == RCC_PLLSAIP_DIV4) ||\
6975  ((VALUE) == RCC_PLLSAIP_DIV6) ||\
6976  ((VALUE) == RCC_PLLSAIP_DIV8))
6977 
6978 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
6979  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
6980  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\
6981  ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
6982 
6983 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
6984  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
6985  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\
6986  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
6987 
6988 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
6989  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
6990  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
6991  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
6992 
6993  #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
6994  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
6995  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
6996  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
6997 
6998 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
6999  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
7000  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
7001 
7002 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\
7003  ((SOURCE) == RCC_CECCLKSOURCE_LSE))
7004 
7005 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
7006  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
7007 
7008 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
7009  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
7010 
7011 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
7012  ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
7013 #endif /* STM32F446xx */
7014 
7015 #if defined(STM32F469xx) || defined(STM32F479xx)
7016 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
7017 
7018 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
7019  ((VALUE) == RCC_PLLSAIP_DIV4) ||\
7020  ((VALUE) == RCC_PLLSAIP_DIV6) ||\
7021  ((VALUE) == RCC_PLLSAIP_DIV8))
7022 
7023 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
7024  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
7025 
7026 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
7027  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
7028 
7029 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
7030  ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
7031 
7032 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
7033  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
7034 #endif /* STM32F469xx || STM32F479xx */
7035 
7036 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
7037  defined(STM32F413xx) || defined(STM32F423xx)
7038 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
7039 
7040 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
7041 
7042 #define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
7043  ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
7044 
7045 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
7046  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
7047  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
7048  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
7049 
7050  #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
7051  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
7052  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
7053  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
7054 
7055 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
7056  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
7057  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
7058 
7059 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
7060  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
7061 
7062 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
7063  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
7064 
7065 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
7066  ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
7067 
7068 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \
7069  ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
7070 
7071 #if defined(STM32F413xx) || defined(STM32F423xx)
7072 #define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \
7073  ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
7074 
7075 #define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \
7076  ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
7077 
7078 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
7079  ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
7080  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
7081  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
7082 
7083 #define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\
7084  ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\
7085  ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\
7086  ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
7087 
7088 #define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\
7089  ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\
7090  ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\
7091  ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
7092 
7093 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
7094 
7095 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
7096 
7097 #endif /* STM32F413xx || STM32F423xx */
7098 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
7099 
7100 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
7101  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
7102  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
7103  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
7104  defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
7105 
7106 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
7107  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
7108 
7109 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
7110  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
7111  STM32F412Rx */
7112 
7113 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
7114 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
7115  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
7116 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
7117 
7132 #ifdef __cplusplus
7133 }
7134 #endif
7135 
7136 #endif /* __STM32F4xx_HAL_RCC_EX_H */
7137 
7138 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_PLLInitTypeDef::PLLQ
uint32_t PLLQ
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:65
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
RCC_PLLInitTypeDef::PLLState
uint32_t PLLState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:49
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
RCC_PLLInitTypeDef::PLLP
uint32_t PLLP
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:62
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:47
RCC_PLLInitTypeDef::PLLM
uint32_t PLLM
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:55
HAL_RCCEx_DisablePLLI2S
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
HAL_RCCEx_DisablePLLSAI
HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
RCC_PLLInitTypeDef::PLLSource
uint32_t PLLSource
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:52
RCC_PLLI2SInitTypeDef
PLLI2S Clock structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:76
RCC_PLLSAIInitTypeDef
PLLSAI Clock structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:101
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
HAL_RCCEx_EnablePLLI2S
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:126
RCC_PLLInitTypeDef::PLLN
uint32_t PLLN
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:58
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745
HAL_RCCEx_EnablePLLSAI
HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:52