stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_HAL_RCC_H
22 #define __STM32F4xx_HAL_RCC_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx_hal_def.h"
30 
31 /* Include RCC HAL Extended module */
32 /* (include on top of file since RCC structures are defined in extended file) */
33 #include "stm32f4xx_hal_rcc_ex.h"
34 
43 /* Exported types ------------------------------------------------------------*/
51 typedef struct
52 {
53  uint32_t OscillatorType;
56  uint32_t HSEState;
59  uint32_t LSEState;
62  uint32_t HSIState;
65  uint32_t HSICalibrationValue;
68  uint32_t LSIState;
71  RCC_PLLInitTypeDef PLL;
72 }RCC_OscInitTypeDef;
73 
77 typedef struct
78 {
79  uint32_t ClockType;
82  uint32_t SYSCLKSource;
85  uint32_t AHBCLKDivider;
88  uint32_t APB1CLKDivider;
91  uint32_t APB2CLKDivider;
94 }RCC_ClkInitTypeDef;
95 
100 /* Exported constants --------------------------------------------------------*/
108 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
109 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
110 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
111 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
112 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
113 
120 #define RCC_HSE_OFF 0x00000000U
121 #define RCC_HSE_ON RCC_CR_HSEON
122 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
123 
130 #define RCC_LSE_OFF 0x00000000U
131 #define RCC_LSE_ON RCC_BDCR_LSEON
132 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
133 
140 #define RCC_HSI_OFF ((uint8_t)0x00)
141 #define RCC_HSI_ON ((uint8_t)0x01)
142 
143 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
144 
151 #define RCC_LSI_OFF ((uint8_t)0x00)
152 #define RCC_LSI_ON ((uint8_t)0x01)
153 
160 #define RCC_PLL_NONE ((uint8_t)0x00)
161 #define RCC_PLL_OFF ((uint8_t)0x01)
162 #define RCC_PLL_ON ((uint8_t)0x02)
163 
170 #define RCC_PLLP_DIV2 0x00000002U
171 #define RCC_PLLP_DIV4 0x00000004U
172 #define RCC_PLLP_DIV6 0x00000006U
173 #define RCC_PLLP_DIV8 0x00000008U
174 
181 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
182 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
183 
190 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
191 #define RCC_CLOCKTYPE_HCLK 0x00000002U
192 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
193 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
194 
203 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
204 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
205 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
206 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
207 
216 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
217 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
218 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
219 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))
227 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
228 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
229 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
230 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
231 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
232 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
233 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
234 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
235 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
236 
243 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
244 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
245 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
246 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
247 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
248 
255 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
256 #define RCC_RTCCLKSOURCE_LSE 0x00000100U
257 #define RCC_RTCCLKSOURCE_LSI 0x00000200U
258 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
259 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
260 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
261 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
262 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
263 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
264 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
265 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
266 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
267 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
268 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
269 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
270 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
271 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
272 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
273 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
274 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
275 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
276 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
277 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
278 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
279 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
280 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
281 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
282 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
283 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
284 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
285 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
286 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
287 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
288 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
289 
296 #define RCC_MCO1 0x00000000U
297 #define RCC_MCO2 0x00000001U
298 
305 #define RCC_MCO1SOURCE_HSI 0x00000000U
306 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
307 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
308 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
309 
316 #define RCC_MCODIV_1 0x00000000U
317 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
318 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
319 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
320 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
321 
328 #define RCC_IT_LSIRDY ((uint8_t)0x01)
329 #define RCC_IT_LSERDY ((uint8_t)0x02)
330 #define RCC_IT_HSIRDY ((uint8_t)0x04)
331 #define RCC_IT_HSERDY ((uint8_t)0x08)
332 #define RCC_IT_PLLRDY ((uint8_t)0x10)
333 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
334 #define RCC_IT_CSS ((uint8_t)0x80)
335 
348 /* Flags in the CR register */
349 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
350 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
351 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
352 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
353 
354 /* Flags in the BDCR register */
355 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
356 
357 /* Flags in the CSR register */
358 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
359 #define RCC_FLAG_BORRST ((uint8_t)0x79)
360 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
361 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
362 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
363 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
364 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
365 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
366 
374 /* Exported macro ------------------------------------------------------------*/
386 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
387  __IO uint32_t tmpreg = 0x00U; \
388  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
389  /* Delay after an RCC peripheral clock enabling */ \
390  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
391  UNUSED(tmpreg); \
392  } while(0U)
393 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
394  __IO uint32_t tmpreg = 0x00U; \
395  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
396  /* Delay after an RCC peripheral clock enabling */ \
397  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
398  UNUSED(tmpreg); \
399  } while(0U)
400 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
401  __IO uint32_t tmpreg = 0x00U; \
402  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
403  /* Delay after an RCC peripheral clock enabling */ \
404  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
405  UNUSED(tmpreg); \
406  } while(0U)
407 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
408  __IO uint32_t tmpreg = 0x00U; \
409  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
410  /* Delay after an RCC peripheral clock enabling */ \
411  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
412  UNUSED(tmpreg); \
413  } while(0U)
414 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
415  __IO uint32_t tmpreg = 0x00U; \
416  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
417  /* Delay after an RCC peripheral clock enabling */ \
418  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
419  UNUSED(tmpreg); \
420  } while(0U)
421 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
422  __IO uint32_t tmpreg = 0x00U; \
423  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
424  /* Delay after an RCC peripheral clock enabling */ \
425  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
426  UNUSED(tmpreg); \
427  } while(0U)
428 
429 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
430 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
431 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
432 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
433 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
434 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
435 
446 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
447 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
448 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
449 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
450 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
451 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
452 
453 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
454 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
455 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
456 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
457 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
458 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
459 
470 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
471  __IO uint32_t tmpreg = 0x00U; \
472  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
473  /* Delay after an RCC peripheral clock enabling */ \
474  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
475  UNUSED(tmpreg); \
476  } while(0U)
477 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
478  __IO uint32_t tmpreg = 0x00U; \
479  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
480  /* Delay after an RCC peripheral clock enabling */ \
481  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
482  UNUSED(tmpreg); \
483  } while(0U)
484 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
485  __IO uint32_t tmpreg = 0x00U; \
486  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
487  /* Delay after an RCC peripheral clock enabling */ \
488  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
489  UNUSED(tmpreg); \
490  } while(0U)
491 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
492  __IO uint32_t tmpreg = 0x00U; \
493  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
494  /* Delay after an RCC peripheral clock enabling */ \
495  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
496  UNUSED(tmpreg); \
497  } while(0U)
498 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
499  __IO uint32_t tmpreg = 0x00U; \
500  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
501  /* Delay after an RCC peripheral clock enabling */ \
502  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
503  UNUSED(tmpreg); \
504  } while(0U)
505 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
506  __IO uint32_t tmpreg = 0x00U; \
507  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
508  /* Delay after an RCC peripheral clock enabling */ \
509  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
510  UNUSED(tmpreg); \
511  } while(0U)
512 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
513  __IO uint32_t tmpreg = 0x00U; \
514  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
515  /* Delay after an RCC peripheral clock enabling */ \
516  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
517  UNUSED(tmpreg); \
518  } while(0U)
519 
520 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
521 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
522 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
523 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
524 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
525 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
526 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
527 
538 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
539 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
540 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
541 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
542 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
543 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
544 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
545 
546 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
547 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
548 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
549 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
550 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
551 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
552 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
553 
564 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
565  __IO uint32_t tmpreg = 0x00U; \
566  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
567  /* Delay after an RCC peripheral clock enabling */ \
568  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
569  UNUSED(tmpreg); \
570  } while(0U)
571 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
572  __IO uint32_t tmpreg = 0x00U; \
573  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
574  /* Delay after an RCC peripheral clock enabling */ \
575  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
576  UNUSED(tmpreg); \
577  } while(0U)
578 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
579  __IO uint32_t tmpreg = 0x00U; \
580  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
581  /* Delay after an RCC peripheral clock enabling */ \
582  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
583  UNUSED(tmpreg); \
584  } while(0U)
585 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
586  __IO uint32_t tmpreg = 0x00U; \
587  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
588  /* Delay after an RCC peripheral clock enabling */ \
589  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
590  UNUSED(tmpreg); \
591  } while(0U)
592 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
593  __IO uint32_t tmpreg = 0x00U; \
594  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
595  /* Delay after an RCC peripheral clock enabling */ \
596  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
597  UNUSED(tmpreg); \
598  } while(0U)
599 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
600  __IO uint32_t tmpreg = 0x00U; \
601  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
602  /* Delay after an RCC peripheral clock enabling */ \
603  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
604  UNUSED(tmpreg); \
605  } while(0U)
606 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
607  __IO uint32_t tmpreg = 0x00U; \
608  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
609  /* Delay after an RCC peripheral clock enabling */ \
610  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
611  UNUSED(tmpreg); \
612  } while(0U)
613 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
614  __IO uint32_t tmpreg = 0x00U; \
615  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
616  /* Delay after an RCC peripheral clock enabling */ \
617  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
618  UNUSED(tmpreg); \
619  } while(0U)
620 
621 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
622 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
623 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
624 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
625 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
626 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
627 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
628 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
629 
640 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
641 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
642 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
643 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
644 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
645 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
646 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
647 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
648 
649 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
650 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
651 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
652 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
653 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
654 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
655 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
656 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
657 
665 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
666 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
667 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
668 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
669 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
670 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
671 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
672 
673 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
674 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
675 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
676 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
677 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
678 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
679 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
680 
688 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
689 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
690 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
691 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
692 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
693 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
694 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
695 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
696 
697 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
698 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
699 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
700 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
701 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
702 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
703 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
704 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
705 
713 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
714 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
715 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
716 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
717 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
718 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
719 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
720 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
721 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
722 
723 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
724 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
725 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
726 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
727 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
728 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
729 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
730 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
731 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
732 
744 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
745 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
746 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
747 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
748 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
749 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
750 
751 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
752 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
753 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
754 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
755 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
756 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
757 
769 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
770 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
771 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
772 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
773 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
774 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
775 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
776 
777 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
778 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
779 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
780 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
781 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
782 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
783 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
784 
796 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
797 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
798 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
799 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
800 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
801 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
802 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
803 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
804 
805 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
806 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
807 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
808 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
809 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
810 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
811 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
812 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
813 
836 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
837 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
838 
846 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
847  RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
848 
864 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
865 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
866 
895 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
896  do { \
897  if ((__STATE__) == RCC_HSE_ON) \
898  { \
899  SET_BIT(RCC->CR, RCC_CR_HSEON); \
900  } \
901  else if ((__STATE__) == RCC_HSE_BYPASS) \
902  { \
903  SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
904  SET_BIT(RCC->CR, RCC_CR_HSEON); \
905  } \
906  else \
907  { \
908  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
909  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
910  } \
911  } while(0U)
912 
938 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
939  do { \
940  if((__STATE__) == RCC_LSE_ON) \
941  { \
942  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
943  } \
944  else if((__STATE__) == RCC_LSE_BYPASS) \
945  { \
946  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
947  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
948  } \
949  else \
950  { \
951  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
952  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
953  } \
954  } while(0U)
955 
966 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
967 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
968 
991 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
992  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
993 
994 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
995  RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
996  } while(0U)
997 
1005 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1006 
1013 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
1014 
1020 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1021 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1022 
1037 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
1038 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
1039 
1048 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
1049 
1059 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
1060 
1077 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
1078 
1088 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
1089 
1096 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
1097 
1120 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1121  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1122 
1141 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1142  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
1143 
1163 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1164 
1176 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1177 
1190 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1191 
1204 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1205 
1209 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1210 
1229 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
1230 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
1231 
1240 /* Exported functions --------------------------------------------------------*/
1248 /* Initialization and de-initialization functions ******************************/
1249 HAL_StatusTypeDef HAL_RCC_DeInit(void);
1250 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1251 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1259 /* Peripheral Control functions ************************************************/
1260 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1261 void HAL_RCC_EnableCSS(void);
1262 void HAL_RCC_DisableCSS(void);
1263 uint32_t HAL_RCC_GetSysClockFreq(void);
1264 uint32_t HAL_RCC_GetHCLKFreq(void);
1265 uint32_t HAL_RCC_GetPCLK1Freq(void);
1266 uint32_t HAL_RCC_GetPCLK2Freq(void);
1267 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1268 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1269 
1270 /* CSS NMI IRQ handler */
1271 void HAL_RCC_NMI_IRQHandler(void);
1272 
1273 /* User Callbacks in non blocking mode (IT mode) */
1274 void HAL_RCC_CSSCallback(void);
1275 
1284 /* Private types -------------------------------------------------------------*/
1285 /* Private variables ---------------------------------------------------------*/
1286 /* Private constants ---------------------------------------------------------*/
1295 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1296 /* --- CR Register --- */
1297 /* Alias word address of HSION bit */
1298 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
1299 #define RCC_HSION_BIT_NUMBER 0x00U
1300 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
1301 /* Alias word address of CSSON bit */
1302 #define RCC_CSSON_BIT_NUMBER 0x13U
1303 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
1304 /* Alias word address of PLLON bit */
1305 #define RCC_PLLON_BIT_NUMBER 0x18U
1306 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
1307 
1308 /* --- BDCR Register --- */
1309 /* Alias word address of RTCEN bit */
1310 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
1311 #define RCC_RTCEN_BIT_NUMBER 0x0FU
1312 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
1313 /* Alias word address of BDRST bit */
1314 #define RCC_BDRST_BIT_NUMBER 0x10U
1315 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
1316 
1317 /* --- CSR Register --- */
1318 /* Alias word address of LSION bit */
1319 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
1320 #define RCC_LSION_BIT_NUMBER 0x00U
1321 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
1322 
1323 /* CR register byte 3 (Bits[23:16]) base address */
1324 #define RCC_CR_BYTE2_ADDRESS 0x40023802U
1325 
1326 /* CIR register byte 2 (Bits[15:8]) base address */
1327 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
1328 
1329 /* CIR register byte 3 (Bits[23:16]) base address */
1330 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
1331 
1332 /* BDCR register base address */
1333 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
1334 
1335 #define RCC_DBP_TIMEOUT_VALUE 2U
1336 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1337 
1338 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1339 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */
1340 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */
1341 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
1342 
1351 /* Private macros ------------------------------------------------------------*/
1359 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
1360 
1361 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1362  ((HSE) == RCC_HSE_BYPASS))
1363 
1364 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1365  ((LSE) == RCC_LSE_BYPASS))
1366 
1367 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1368 
1369 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1370 
1371 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1372 
1373 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1374  ((SOURCE) == RCC_PLLSOURCE_HSE))
1375 
1376 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1377  ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1378  ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
1379  ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
1380 
1381 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
1382  ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
1383  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
1384  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
1385  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
1386  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
1387  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
1388  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
1389  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
1390  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
1391  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
1392  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
1393  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
1394  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
1395  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
1396  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
1397  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
1398  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
1399  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
1400  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
1401  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
1402  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
1403  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
1404  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
1405  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
1406  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
1407  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
1408  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
1409  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
1410  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
1411  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
1412  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
1413 
1414 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
1415 
1416 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
1417 
1418 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
1419 
1420 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
1421  ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
1422  ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
1423  ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
1424  ((HCLK) == RCC_SYSCLK_DIV512))
1425 
1426 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
1427 
1428 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
1429  ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
1430  ((PCLK) == RCC_HCLK_DIV16))
1431 
1432 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
1433 
1434 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
1435  ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1436 
1437 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
1438  ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1439  ((DIV) == RCC_MCODIV_5))
1440 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
1441 
1458 #ifdef __cplusplus
1459 }
1460 #endif
1461 
1462 #endif /* __STM32F4xx_HAL_RCC_H */
1463 
1464 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_RCC_CSSCallback
void HAL_RCC_CSSCallback(void)
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:77
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:47
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:51
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:65
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:91
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:59
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
HAL_RCC_NMI_IRQHandler
void HAL_RCC_NMI_IRQHandler(void)
HAL_RCC_DeInit
HAL_StatusTypeDef HAL_RCC_DeInit(void)
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:62
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:85
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:71
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:79
HAL_RCC_DisableCSS
void HAL_RCC_DisableCSS(void)
HAL_RCC_MCOConfig
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:68
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:82
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:56
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:53
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:88
HAL_RCC_EnableCSS
void HAL_RCC_EnableCSS(void)
stm32f4xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:52