Macros
APB2 Peripheral Clock Enable Disable
STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCC » RCC Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Collaboration diagram for APB2 Peripheral Clock Enable Disable:

Macros

#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 
#define __HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 
#define __HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 
#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 
#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
#define __HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
#define __HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.


Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Enable or disable the High Speed APB (APB2) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

◆ __HAL_RCC_ADC1_CLK_DISABLE [1/3]

#define __HAL_RCC_ADC1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 624 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_ADC1_CLK_DISABLE [2/3]

#define __HAL_RCC_ADC1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 624 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_ADC1_CLK_DISABLE [3/3]

#define __HAL_RCC_ADC1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 624 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_ADC1_CLK_ENABLE [1/3]

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 585 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_ADC1_CLK_ENABLE [2/3]

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 585 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_ADC1_CLK_ENABLE [3/3]

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 585 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI1_CLK_DISABLE [1/3]

#define __HAL_RCC_SPI1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 625 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI1_CLK_DISABLE [2/3]

#define __HAL_RCC_SPI1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 625 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI1_CLK_DISABLE [3/3]

#define __HAL_RCC_SPI1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 625 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI1_CLK_ENABLE [1/3]

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 592 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI1_CLK_ENABLE [2/3]

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 592 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI1_CLK_ENABLE [3/3]

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 592 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_DISABLE [1/4]

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 476 of file stm32f7xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_DISABLE [2/4]

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 626 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_DISABLE [3/4]

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 626 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_DISABLE [4/4]

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 626 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_ENABLE [1/4]

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 468 of file stm32f7xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_ENABLE [2/4]

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 599 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_ENABLE [3/4]

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 599 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_ENABLE [4/4]

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 599 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM11_CLK_DISABLE [1/3]

#define __HAL_RCC_TIM11_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Definition at line 628 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM11_CLK_DISABLE [2/3]

#define __HAL_RCC_TIM11_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Definition at line 628 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM11_CLK_DISABLE [3/3]

#define __HAL_RCC_TIM11_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Definition at line 628 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM11_CLK_ENABLE [1/3]

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 613 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM11_CLK_ENABLE [2/3]

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 613 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM11_CLK_ENABLE [3/3]

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 613 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM1_CLK_DISABLE [1/3]

#define __HAL_RCC_TIM1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 621 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM1_CLK_DISABLE [2/3]

#define __HAL_RCC_TIM1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 621 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM1_CLK_DISABLE [3/3]

#define __HAL_RCC_TIM1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 621 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM1_CLK_ENABLE [1/3]

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 564 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM1_CLK_ENABLE [2/3]

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 564 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM1_CLK_ENABLE [3/3]

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 564 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM9_CLK_DISABLE [1/3]

#define __HAL_RCC_TIM9_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

Definition at line 627 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM9_CLK_DISABLE [2/3]

#define __HAL_RCC_TIM9_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

Definition at line 627 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM9_CLK_DISABLE [3/3]

#define __HAL_RCC_TIM9_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

Definition at line 627 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM9_CLK_ENABLE [1/3]

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 606 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM9_CLK_ENABLE [2/3]

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 606 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM9_CLK_ENABLE [3/3]

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 606 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART1_CLK_DISABLE [1/3]

#define __HAL_RCC_USART1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 622 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART1_CLK_DISABLE [2/3]

#define __HAL_RCC_USART1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 622 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART1_CLK_DISABLE [3/3]

#define __HAL_RCC_USART1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 622 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART1_CLK_ENABLE [1/3]

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 571 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART1_CLK_ENABLE [2/3]

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 571 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART1_CLK_ENABLE [3/3]

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 571 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART6_CLK_DISABLE [1/3]

#define __HAL_RCC_USART6_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

Definition at line 623 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART6_CLK_DISABLE [2/3]

#define __HAL_RCC_USART6_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

Definition at line 623 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART6_CLK_DISABLE [3/3]

#define __HAL_RCC_USART6_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

Definition at line 623 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART6_CLK_ENABLE [1/3]

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 578 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART6_CLK_ENABLE [2/3]

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 578 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART6_CLK_ENABLE [3/3]

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 578 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

RCC_APB2ENR_SPI1EN
#define RCC_APB2ENR_SPI1EN
Definition: stm32f407xx.h:10061
RCC_APB2ENR_ADC1EN
#define RCC_APB2ENR_ADC1EN
Definition: stm32f407xx.h:10049
RCC_APB2ENR_TIM11EN
#define RCC_APB2ENR_TIM11EN
Definition: stm32f407xx.h:10073
RCC_APB2ENR_USART6EN
#define RCC_APB2ENR_USART6EN
Definition: stm32f407xx.h:10046
RCC_APB2ENR_USART1EN
#define RCC_APB2ENR_USART1EN
Definition: stm32f407xx.h:10043
RCC_APB2ENR_TIM9EN
#define RCC_APB2ENR_TIM9EN
Definition: stm32f407xx.h:10067
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:216
RCC_APB2ENR_TIM1EN
#define RCC_APB2ENR_TIM1EN
Definition: stm32f407xx.h:10037
RCC_APB2ENR_SYSCFGEN
#define RCC_APB2ENR_SYSCFGEN
Definition: stm32f407xx.h:10064
RCC
#define RCC
Definition: stm32f407xx.h:1113

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:06